Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a preparation method of the semiconductor device, the semiconductor device comprising a bit line structure, the bit line structure comprising a bit line and a bit line sidewall protection layer, the bit line comprising a first semiconductor layer, a metal wire layer and a bit line cover layer, the bit line sidewall protection layer covering two sidewalls of the bit line; a contact plug, the contact plug being located between adjacent bit line structures; a bonding pad, the bonding pad being located on the contact plug and connected with the contact plug, the bonding pad covering a top surface of part of the bit line structure and being broken on the top surface of the bit line structure; wherein the bonding pad comprises a first metal material layer and a second metal material layer, the second metal material layer being located on the first metal material layer, and the first metal material layer having an L-shaped cross section. The adjacent bonding pads can be disconnected from each other to prevent the bonding pads from forming a short circuit, and meanwhile the second metal material layer will not be reduced too much to cause the resistance of the bonding pad to be too large or even cause the bonding pad to be broken.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] Due to the development of electronic technology, the miniaturization of semiconductor devices is developing rapidly, the design rules of semiconductor devices are being reduced, and the preparation process of transistors has entered the 10-nanometer level or even the 3-nanometer level.

[0003] However, as the size of semiconductor devices shrinks, the size of contact plugs continues to decrease and the distance between adjacent contacts also continues to shrink. During the manufacturing process, the risk of forming open circuits and short circuits increases, and higher requirements are placed on the semiconductor manufacturing process. Summary of the Invention

[0004] Based on this, the embodiments of the present application provide a semiconductor device and a method for manufacturing a semiconductor device, which can increase the window of the contact plug manufacturing process and reduce the risk of contact short circuit or open circuit, etc.

[0005] In a first aspect, the present application provides a semiconductor device according to some embodiments, including:

[0006] A plurality of bit line structures are provided on the substrate, each of the plurality of bit line structures comprises a bit line and a bit line sidewall protection layer, the bit line comprises a first semiconductor layer, a metal wire layer and a bit line capping layer, and the bit line sidewall protection layer covers two sidewalls of the bit line;

[0007] a plurality of contact plugs disposed on the substrate, the plurality of contact plugs being located between adjacent bit line structures, the height of the contact plugs in a direction perpendicular to the substrate being lower than the height of the bit line structures in the direction perpendicular to the substrate;

[0008] a plurality of bonding pads, the plurality of bonding pads being located on the plurality of contact plugs and correspondingly connected to the plurality of contact plugs, the plurality of bonding pads having a height in a direction perpendicular to the substrate being higher than the height of the bit line structure in the direction perpendicular to the substrate, the bonding pads covering a portion of a top surface of the bit line structure and being disconnected on the top surface of the bit line structure;

[0009] The bonding pad includes a first metal material layer and a second metal material layer, the second metal material layer is located on the first metal material layer, and the first metal material layer has an L-shaped cross section.

[0010] In some embodiments, the second metal material layer includes a first portion and a second portion, wherein the height of the first portion in a direction perpendicular to the substrate is less than the height of the bit line structure in a direction perpendicular to the substrate, the height of the second portion in a direction perpendicular to the substrate is greater than the height of the bit line structure in a direction perpendicular to the substrate, and the curvature of the first portion is different from the curvature of the second portion.

[0011] In some embodiments, the semiconductor device further includes:

[0012] A metal silicide layer is disposed between the contact plug and the bonding pad.

[0013] In some embodiments, a height of the metal silicide in a direction perpendicular to the substrate is higher than a height of the metal wire layer in a direction perpendicular to the substrate.

[0014] In some embodiments, the semiconductor device further includes:

[0015] An insulating structure is provided, where the insulating structure fills between the plurality of bonding pads, and a height of the insulating structure in a direction perpendicular to the substrate is equal to a height of the bonding pads in the direction perpendicular to the substrate.

[0016] In a second aspect, the present application further provides a method for manufacturing a semiconductor device according to some embodiments, comprising:

[0017] forming a plurality of bit line structures on a substrate, each of the plurality of bit line structures comprising a bit line and a bit line sidewall protection layer, the bit line comprising a first semiconductor layer, a metal wire layer and a bit line capping layer, the bit line sidewall protection layer covering two sidewalls of the bit line;

[0018] forming a plurality of contact plugs on the substrate, wherein the plurality of contact plugs are located between adjacent bit line structures, and a height of the contact plugs in a direction perpendicular to the substrate is lower than a height of the bit line structures in the direction perpendicular to the substrate;

[0019] forming a plurality of bonding pads on the plurality of contact plugs, the plurality of bonding pads being located on the plurality of contact plugs and correspondingly connected to the plurality of contact plugs, the plurality of bonding pads having a height in a direction perpendicular to the substrate being higher than the height of the bit line structure in the direction perpendicular to the substrate, the bonding pads covering a portion of a top surface of the bit line structure and being disconnected on the top surface of the bit line structure;

[0020] The bonding pad includes a first metal material layer and a second metal material layer, the second metal material layer is located on the first metal material layer, and the first metal material layer has an L-shaped cross section.

[0021] In some embodiments, providing a first semiconductor structure includes:

[0022] The forming of a plurality of contact plugs on the substrate comprises:

[0023] A contact plug material layer is deposited between the plurality of bit line structures, and the contact plug material layer is etched back to form the contact plug, wherein the height of the contact plug in a direction perpendicular to the substrate is lower than the height of the bit line in the direction perpendicular to the substrate.

[0024] In some embodiments, forming a plurality of bonding pads on the plurality of contact plugs includes:

[0025] Depositing an initial first metal material layer on the contact plug and the bit line structure, wherein the initial first metal material layer covers surfaces of the contact plug and the bit line structure;

[0026] Depositing an initial second metal material layer on the surface of the initial first metal material layer, wherein the height of the initial second metal material layer in a direction perpendicular to the substrate is higher than the height of the bit line in the direction perpendicular to the substrate, and grinding and flattening the second metal material layer;

[0027] Etching the initial second metal material layer using a first etching method to expose the initial first metal material layer;

[0028] The initial first metal material layer is etched using a second etching method to form the first metal material layer having an L-shaped cross section.

[0029] In some embodiments, before forming a plurality of bonding pads on the plurality of contact plugs, the method further includes:

[0030] A metal silicide layer is formed on the contact plug, wherein a height of the metal silicide in a direction perpendicular to the substrate is higher than a height of the metal wire layer in the direction perpendicular to the substrate.

[0031] In some embodiments, after forming a plurality of bonding pads on the plurality of contact plugs, the method further includes:

[0032] cleaning the conjugate pad;

[0033] An insulating structure is filled between the plurality of bonding pads, wherein a height of the insulating structure in a direction perpendicular to the substrate is equal to a height of the bonding pads in the direction perpendicular to the substrate.

[0034] The semiconductor structure and the method for manufacturing the same provided by this application have at least the following beneficial effects:

[0035] The present application provides a semiconductor device and a method for preparing a semiconductor device. The bonding pad in the semiconductor device includes a first metal material layer and a second metal material layer. The second metal material layer is located on the first metal material layer. The first metal material layer has an L-shaped cross-section, which can disconnect adjacent bonding pads from each other to prevent the bonding pads from forming a short circuit. At the same time, the second metal material layer will not be reduced too much to cause the resistance of the bonding pad to be too large or even cause the bonding pad to be broken. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0038] Figure 2 、 Figure 3 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0039] Figure 4-Figure 9 A schematic diagram of a cross-sectional view of a method for forming a semiconductor device provided in an embodiment of the present application; Description of the accompanying drawings:

[0040] 1: bit line structure; 10: bit line; 101: first semiconductor layer; 102: metal wire layer; 103: bit line cap layer; 104: bit line sidewall protection layer; 201: contact plug; 301: metal silicide layer; 40: bonding pad; 401: first metal material layer; 402: second metal material layer; 4021: first portion; 4022: second portion; 403: initial first metal material layer; 404: initial second metal material layer; 501: insulating structure; 601: patterned mask layer; T0: bonding pad groove; T1: first groove; T2: second groove; S1: first curved surface; S2: second curved surface. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent," or "connected to," it can be directly on, adjacent, or connected to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present application, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0044] Spatially relative terms such as "on..." may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented "under" the other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0045] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes as a result, for example, of manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the present invention.

[0047] Figure 1 A schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present application. In some embodiments, the semiconductor device includes a plurality of bit line structures 1, which are disposed on a substrate (not shown), each of the plurality of bit line structures 1 including a bit line 10 and a bit line sidewall protection layer 104, the bit line 10 including a first semiconductor layer 101, a metal wire layer 102, and a bit line capping layer 103, the first semiconductor layer 101, the metal wire layer 102, and the bit line capping layer 103 being stacked sequentially on the substrate, the bit line sidewall protection layer 104 covering both sidewalls of the bit line 10; a plurality of contact plugs 201, which are disposed on the substrate (not shown), the plurality of contact plugs 201 being located between adjacent bit line structures 1, the contact plugs 201 being perpendicular to the substrate. The upward height is lower than the height of the bit line 10 in the direction perpendicular to the substrate; a plurality of bonding pads 40 are located on the plurality of contact plugs 201 and are connected to the plurality of contact plugs 201 in a one-to-one correspondence; the height of the plurality of bonding pads 40 in the direction perpendicular to the substrate is higher than the height of the bit line 100 in the direction perpendicular to the substrate; the bonding pads 40 cover a portion of the top surface of the bit line structure 1 and are disconnected at the top surface of the bit line structure 1, wherein the bonding pads 40 include a first metal material layer 401 and a second metal material layer 402, the second metal material layer 402 being located on the first metal material layer 401, and the first metal material layer 401 having an L-shaped cross-section. The L-shaped cross-section of the first metal material layer 401 can disconnect adjacent bonding pads 40 from each other to prevent a short circuit; at the same time, the second metal material layer 402 will not be etched too much, resulting in excessive resistance of the bonding pad 40 or even over-etching, resulting in a disconnection of the bonding pad 40.

[0048] Continue to refer Figure 1In some embodiments of the present application, multiple bitline structures 1 extend along a first direction (e.g., the X direction) and are arranged in an alternating pattern along a second direction (e.g., the Y direction) on a substrate (not shown). Each of the multiple bitline structures 1 includes a bitline 10 and a bitline sidewall protection layer 104. The bitline 10 includes a first semiconductor layer 101, a metal wiring layer 102, and a bitline capping layer 103. The first semiconductor layer 101, the metal wiring layer 102, and the bitline capping layer 103 cover both sidewalls of the bitline 10. The substrate (not shown) can be a single crystal silicon wafer, a polycrystalline silicon wafer, a silicon germanium wafer, a sapphire wafer, a silicon carbide wafer, a silicon-on-insulator wafer, a germanium-on-insulator wafer, a glass wafer, a III-V compound wafer (e.g., silicon nitride or gallium arsenide), an oxide semiconductor wafer, or other wafers having semiconductor devices formed thereon. The substrate can also include an active region, a shallow trench isolation structure surrounding the active region, a buried wordline, and other structures. The first semiconductor layer 101 is located on the substrate and is directly connected to the substrate. The first semiconductor layer 101 is a material with conductive properties, for example, it can be at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, germanium silicon, doped germanium silicon, etc. The first semiconductor layer can be a single layer or multiple layers, and the concentration of the dopant can be a constant value or a variable value. The metal wire layer 102 is located on the first semiconductor layer and is directly connected to the first semiconductor layer. The metal wire layer 102 is a material with conductive properties, for example, it can be at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The metal wire layer 102 can be a single layer or multiple layers. The embodiment of the present invention uses a two-layer structure as an example. Since the metal wire layer has a low resistance, it can provide good conductivity. The bit line capping layer 103 is located on the metal wire layer 102 to protect the metal wire layer 102. The bit line capping layer 103 has good etching resistance and stability. The bit line capping layer 103 can be made of at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The bit line capping layer 103 can be a single layer or multiple layers. The bit line sidewall protection layer 104 covers the two sidewalls of the bit line 10 to protect the bit line 10 and prevent damage to the bit line 10 during subsequent processes. The bit line sidewall protection layer 104 can be made of at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The bit line cap layer 103 can be a single layer or multiple layers, including two layers or three layers. The material of each layer can be the same or different, and can also include an air gap structure to reduce the parasitic capacitance between adjacent bit line structures 1 or between the bit line structure 1 and the contact plug 201.

[0049] Continue to refer Figure 1 In some embodiments of the present application, a plurality of contact plugs 201 are provided on the substrate and are directly connected to the substrate. The plurality of contact plugs 201 are located between adjacent bit line structures 1. The height of the contact plugs 201 in a direction perpendicular to the substrate is lower than the height of the bit line structure 1 in a direction perpendicular to the substrate (for example, in the third direction, the Z direction). The contact plugs 201 are made of a conductive material, for example, at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, silicon germanium, doped silicon germanium, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The embodiment of the present invention takes doped polysilicon as an example for description. The height of the contact plug 201 in the direction perpendicular to the substrate is lower than the height of the bit line structure 1 in the direction perpendicular to the substrate (for example, the third direction, the Z direction), forming a bonding pad groove T0, which can provide space for the bonding pad 40, so that the transistor 6F 2 The structural transformation of the upper memory structure into an optimal hexagonal arrangement structure can improve the storage density of semiconductor devices.

[0050] Continue to refer Figure 1In some embodiments, a plurality of bonding pads 40 are located on the plurality of contact plugs 201, filling the bonding pad grooves T0, and connected to the plurality of contact plugs 201 in a one-to-one correspondence. The height of the plurality of bonding pads 40 in a direction perpendicular to the substrate is higher than the height of the bit line structure 1 in a direction perpendicular to the substrate (for example, the third direction, the Z direction). The bonding pads 40 cover a portion of the top surface of the bit line structure 1 and are disconnected on the top surface of the bit line structure 1. The bonding pads 40 are made of a conductive material, for example, at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, silicon germanium, doped silicon germanium, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The bonding pad 40 may include one or more layers of material. The embodiment of the present invention is described by taking two layers as an example. The height of the bonding pad 40 in the direction perpendicular to the substrate is higher than the height of the bit line structure 1 in the direction perpendicular to the substrate (for example, the third direction, the Z direction). The bonding pad 40 covers part of the top surface of the bit line structure 1, that is, the bonding pad 40 is rearranged above the top surface of the bit line structure 1 to form a hexagonally arranged contact pad, which can make the formed storage structure, such as a capacitor, a phase change storage structure, a ferroelectric storage structure, etc., more tightly arranged, thereby improving the storage density.

[0051] Continue to refer Figure 1 In some embodiments, the bonding pad 40 includes a first metal material layer 401 and a second metal material layer 402. The first metal material layer 401 is located at the bottom and surrounding sidewalls of the bonding pad recess T0, and the second metal material layer 402 is located on the sidewalls of the first metal material layer 401 away from the bonding pad recess T0 and completely fills the bonding pad recess T0. A portion of the first metal material layer 401 located on the surrounding sidewalls of the bonding pad recess T0 is removed to form a first metal material layer 401 having an L-shaped cross-section along a second direction (e.g., the Y direction). Because the first metal material layer 401 has an L-shaped cross-section along the second direction (e.g., the Y direction), adjacent first metal material layers 401 are disconnected from each other, that is, the bonding pads 40 are disconnected from each other, which can prevent adjacent bonding pads 40 from forming a short circuit and improve the yield of the semiconductor device.

[0052] Continue to refer Figure 1In some embodiments, the second metal material layer 402 includes a first portion 4021 whose height in the direction perpendicular to the substrate is lower than the height of the bit line structure 1 in the direction perpendicular to the substrate, and a second portion 4022 whose height in the direction perpendicular to the substrate is higher than the height of the bit line structure 1 in the direction perpendicular to the substrate. The first portion 4021 is located in the bonding pad groove T0. When a portion of the first metal material layer 401 is removed, the curvature of the first curved surface S1 of the exposed first portion 4021 is relatively large, so that more of the first portion 4021 can be retained, thereby preventing the first portion 4021 from being retained. The resistance of the bonding pad 40 is too large due to the relatively small number of 4021, and even the first part 4021 is broken to form a short circuit in the bonding pad 40, which affects the performance of the semiconductor device. The second part 4022 is located on the first part 4021 and the bit line structure 1, and is connected to the first part 4021. A large opening needs to be formed during the formation of the second part 4022, that is, the curvature of the second curved surface S2 of the exposed second part 4022 is relatively small, so that the adjacent second parts 4022 are completely disconnected, preventing short circuits between adjacent bonding pads 40, and at the same time providing a larger preparation process window for forming the first part 4021.

[0053] Continue to refer Figure 1 In some embodiments, a metal silicide layer 301 is further disposed between the contact plug 201 and the bonding pad 40. The metal silicide layer 301 is located above the contact plug 201 and below the first metal material layer 401, connecting the contact plug 201 and the first metal material layer 401, thereby reducing the contact resistance between the contact plug 201 and the first metal material layer 401. Furthermore, this prevents damage to the contact plug 201 or the substrate during subsequent processes. The material of the metal silicide layer 301 may be one or two of cobalt silicide, titanium silicide, nickel silicide, molybdenum silicide, and the like. The height of the metal silicide layer 301 in the direction perpendicular to the substrate is higher than the height of the metal wire layer 102 in the direction perpendicular to the substrate. This prevents the first metal material layer 401 from being etched into the bitline sidewall protection layer 104 and the bitline cap layer 103, thereby exposing or even etching the metal wire layer 102 and affecting the performance of the semiconductor device.

[0054] Continue to refer Figure 1In some embodiments, the semiconductor device structure further includes an insulating structure 501, which is filled between adjacent bonding pads 40 to isolate adjacent bonding pads 40 from each other. The upper surface of the bonding pad 40 is flush with the upper surface of the insulating structure 501, that is, the height of the insulating structure 501 in the direction perpendicular to the substrate is equal to the height of the bonding pad 40 in the direction perpendicular to the substrate. The insulating structure is an insulating material, for example, it can be at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc., and can also be one or more layers. In some embodiments, it can also include an air gap structure to reduce the parasitic capacitance between the bonding pads 40.

[0055] Figure 2 A flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application is provided. Figure 3 A partial flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application, Figure 4-Figure 9 A schematic diagram of a cross-sectional view of a manufacturing method for forming a semiconductor device provided in an embodiment of the present application.

[0056] refer to Figure 2 , the semiconductor device manufacturing method comprises at least the following steps:

[0057] S10: forming a plurality of bit line structures on the substrate, each of the plurality of bit line structures comprising a bit line and a bit line sidewall protection layer, the bit line comprising a first semiconductor layer, a metal wire layer and a bit line capping layer, the bit line sidewall protection layer covering two sidewalls of the bit line;

[0058] S20: forming a plurality of contact plugs on the substrate, wherein the plurality of contact plugs are located between adjacent bit line structures, and a height of the contact plugs in a direction perpendicular to the substrate is lower than a height of the bit lines in the direction perpendicular to the substrate;

[0059] S30: forming a plurality of bonding pads on the plurality of contact plugs, wherein the plurality of bonding pads are located on the plurality of contact plugs and are correspondingly connected to the plurality of contact plugs, wherein the height of the plurality of bonding pads in a direction perpendicular to the substrate is higher than the height of the bit line structure in a direction perpendicular to the substrate, and the bonding pads cover a portion of the top surface of the bit line structure and are disconnected on the top surface of the bit line structure; wherein the bonding pads include a first metal material layer and a second metal material layer, the second metal material layer is located on the first metal material layer, and the first metal material layer has an L-shaped cross-section.

[0060] It should be understood that Figure 2 The operations shown in the preparation methods are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in a different order than that shown in the figures. In addition, some operations may be performed simultaneously or in a different order than that shown in the figures.

[0061] In the method for preparing a semiconductor device provided in an embodiment of the present application, adjacent bonding pads can be disconnected from each other to prevent a short circuit, while the second metal material layer will not be reduced too much to cause the resistance of the bonding pad to be too high or even cause the bonding pad to be disconnected.

[0062] refer to Figure 2 and Figure 4 In some embodiments, a plurality of bit line structures 1 are formed on a substrate. The plurality of bit line structures 1 extend along a first direction (e.g., an X direction) and are arranged on the substrate at intervals along a second direction (e.g., a Y direction) (not shown). Each of the plurality of bit line structures 1 includes a bit line 10 and a bit line sidewall protection layer 104. The bit line 10 includes a first semiconductor layer 101, a metal wire layer 102, and a bit line capping layer 103. The first semiconductor layer 101, the metal wire layer 102, and the bit line capping layer 103 are stacked sequentially on the substrate. The bit line sidewall protection layer 104 covers the two sidewalls of the bit line 10. The substrate (not shown) can be a single crystal silicon wafer, a polycrystalline silicon wafer, a silicon germanium wafer, a sapphire wafer, a silicon carbide wafer, a silicon-on-insulator wafer, a germanium-on-insulator wafer, a glass wafer, a III-V compound wafer (e.g., silicon nitride or gallium arsenide), an oxide semiconductor wafer, or other wafers having semiconductor devices formed thereon. The substrate can also include an active region, a shallow trench isolation structure surrounding the active region, a buried wordline, and other structures. The first semiconductor layer 101 is located on and directly connected to the substrate. The first semiconductor layer 101 is a conductive material, such as at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, silicon germanium, or doped silicon germanium. The first semiconductor layer can be a single layer or multiple layers, and the concentration of the dopant can be a constant or a variable value. The metal wire layer 102 is located on the first semiconductor layer and is directly connected to the first semiconductor layer. The metal wire layer 102 is made of a conductive material, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The metal wire layer 102 can be a single layer or multiple layers. The embodiment of the present invention uses a two-layer structure as an example. Since the metal wire layer has a low resistance, it can provide good conductivity. The bit line capping layer 103 is located on the metal wire layer 102 to protect the metal wire layer 102. The bit line capping layer 103 has good etching resistance and stability. The bit line capping layer 103 can be made of at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The bit line capping layer 103 can be a single layer or multiple layers. The bit line sidewall protection layer 104 covers the two sidewalls of the bit line 10 to protect the bit line 10 and prevent damage to the bit line 10 during subsequent processes. The bit line sidewall protection layer 104 can be made of at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc. The bit line cap layer 103 can be a single layer or multiple layers, including two layers or three layers. The material of each layer can be the same or different, and can also include an air gap structure to reduce the parasitic capacitance between adjacent bit line structures 1 or between the bit line structure 1 and the contact plug 201.

[0063] refer to Figure 2 and Figure 5 In some embodiments, a plurality of contact plugs 201 are formed on the substrate. The plurality of contact plugs 201 are disposed on the substrate and are directly connected to the substrate. The plurality of contact plugs 201 are located between adjacent bit line structures 1. The height of the contact plugs 201 in a direction perpendicular to the substrate is lower than the height of the bit line structure 1 in a direction perpendicular to the substrate (e.g., a third direction, a Z direction). The contact plugs 201 are made of a conductive material, such as at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, silicon germanium, doped silicon germanium, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The embodiment of the present invention takes doped polysilicon as an example for explanation. The height of the contact plug 201 in the direction perpendicular to the substrate is lower than the height of the bit line structure 1 in the direction perpendicular to the substrate (for example, the third direction, the Z direction), forming a bonding pad groove T0, which can provide space for the bonding pad 40, so that the 6F 2The structural transformation of the upper hexagonal optimal arrangement structure can improve the storage density of semiconductor devices. Methods for forming contact plug 201 include but are not limited to chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, and flow deposition. First, doped polysilicon material is deposited to fill the gaps between the multiple bitline structures 1. The doped polysilicon material is then etched back to ensure that the height of the doped polysilicon material on the substrate is lower than the height of the bitline structure on the substrate, forming contact plug 201.

[0064] refer to Figure 2 and Figure 6 In some embodiments, an initial first metal material layer 403 and an initial second metal material layer 404 are deposited on the plurality of contact plugs 201. The initial first metal material layer 403 is deposited within the bonding pad recess T0, located at the bottom and surrounding sidewalls of the bonding pad recess T0. The initial second metal material layer 404 is deposited on the sidewalls of the initial first metal material layer 403 away from the bonding pad recess T0, filling the bonding pad recess T0. The initial second metal material layer 404 is also deposited on the bit line structure 1, such that the initial second metal material layer 404 is higher than the bit line structure in a direction perpendicular to the substrate, and then polished and flattened. Methods for depositing the initial first metal material layer 403 and the initial second metal material layer 404 include, but are not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, plasma-enhanced physical vapor deposition, sputtering, and the like. The deposition methods for the initial first metal material layer 403 and the initial second metal material layer 404 can be the same or different. The initial first metal material layer 403 and the initial second metal material layer 404 are made of conductive materials, for example, at least one of the following materials: single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, doped single crystal silicon, silicon germanium, doped silicon germanium, titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO x ), iridium (Ir), iridium oxide (IrO x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), metal silicide, etc. The materials of the initial first metal material layer 403 and the initial second metal material layer 404 can be the same or different. The embodiment of the present invention is described with the initial first metal material layer 403 being titanium nitride and the initial second metal material layer 404 being tungsten.

[0065] Continue to refer Figure 2 and Figure 6In some embodiments, before forming the plurality of bonding pads 40 on the plurality of contact plugs 201, the process further includes forming a metal silicide layer 301 on the contact plugs 201. A metal material may be deposited on the contact plugs 201 and then subjected to a high-temperature treatment to react with the polysilicon in the contact plugs 201 to form the metal silicide layer 301, and unreacted metal material is removed. The metal silicide layer 301 can reduce the contact resistance between the contact plugs 201 and the bonding pads 40, while also preventing damage to the contact plugs 201 or the substrate during subsequent processes. The material of the metal silicide layer 301 can be one or more of cobalt silicide, titanium silicide, nickel silicide, molybdenum silicide, and the like. The height of the metal silicide layer 301 in the direction perpendicular to the substrate is higher than the height of the metal wire layer 102 in the direction perpendicular to the substrate, so as to prevent the metal wire layer 102 from being exposed or even etched when the first metal material layer 401 is etched to the bit line sidewall protection layer 104 and the bit line cap layer 103, thereby affecting the performance of the semiconductor device.

[0066] Figure 3 A flowchart of etching to form bonding pads in a method for preparing a semiconductor device according to an embodiment of the present application is provided. Figure 3 The method for preparing the bonding pad 40 includes at least the following steps:

[0067] S301: etching the initial and second initial metal material layers using a first etching method;

[0068] S302: etching the initial first initial metal material layer using a second etching method;

[0069] S303: Cleaning the conjugate pad;

[0070] S304: Filling insulation structure.

[0071] It should be understood that Figure 3 The operations shown in the preparation methods are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in a different order than that shown in the figures. In addition, some operations may be performed simultaneously or in a different order than that shown in the figures.

[0072] refer to Figure 3 and Figure 7In some embodiments, a mask layer material layer is deposited on the surface of the initial second metal material layer 404, and the patterned mask layer material layer forms a patterned mask layer 601. The patterned mask layer 601 is used as a mask to etch the initial second metal material layer 404 using a first etching method to form a first groove T1. The first groove T1 exposes the initial first metal material layer 403. The first etching method can be dry etching or wet etching. The embodiment of the present invention is described using dry etching. The first etching method can be performed under conditions such as a temperature range of 40°C-90°C, a pressure range of 8-40 mTorr, a bias range of 70-200 eV, and nitrogen trifluoride as the main etching gas. This can make the initial second metal material layer 404 etched quickly, and the opening of the formed first groove T1 is relatively large, and the curvature of the second curved surface S2 of the side wall of the first groove T1 is relatively small, so that adjacent initial second metal material layers 404 are completely disconnected, preventing short circuits between adjacent initial second metal material layers 404, and at the same time providing a larger preparation process window for forming the second groove T2.

[0073] refer to Figure 3 and Figure 7 In some embodiments, the patterned mask layer 601 is continued as a mask, and a second etching method is used to etch the initial first metal material layer 403 at the bottom of the first groove T1. The initial first metal material layer 403 on the sidewall of the bonding pad groove T0 is partially removed, exposing the portion of the initial first metal material layer 403 at the bottom of the bonding pad groove T0, forming a second groove T2. The second groove T2 is connected to the first groove T1. Because the initial first metal material layer 403 on the sidewall of the bonding pad groove T0 is completely removed, adjacent bonding pads 40 can be disconnected from each other, preventing short circuits between adjacent bonding pads 40. The second etching method can be dry etching or wet etching. The embodiment of the present invention is described using dry etching. The first etching method can be performed under conditions such as a temperature range of 10°C to 40°C, a pressure range of 1-8 mTorr, a bias range of 10-70 eV, and chlorine as the primary etching gas. The second etching method primarily selectively etches the initial first metal material layer 403, resulting in a relatively narrow second groove T2 with a relatively small opening and a relatively large curvature of the first curved surface S1. Because the second etching method selectively etches the initial first metal material layer 403, the initial second metal material 404 is less etched, thereby preventing excessive etching of the initial second metal material 404 from causing excessive resistance of the bonding pad 40 or fracture of the bonding pad 40, thereby preventing the bonding pad 40 from being disconnected and affecting the performance of the semiconductor device.

[0074] refer to Figure 3 and Figure 8In some embodiments, the semiconductor device is cleaned to remove the patterned mask layer 601 and byproducts from the etching process. A cleaning medium with a stronger cleaning capability for the initial first metal material layer 403 can be selected, thereby better protecting the initial second metal material layer 404. First metal material layer 401 and second metal material layer 402 are formed, respectively. First metal material layer 401 has an L-shaped cross-section along a second direction (e.g., the Y direction). This disconnects adjacent first metal material layers 401, and thus disconnects bonding pads 40. This prevents short circuits between adjacent bonding pads 40, thereby improving the yield of the semiconductor device. The second metal material layer 402 includes a first portion 4021 formed after the second etching method and a second portion 4022 formed after the first etching method. The first portion 4021 is located within the bonding pad groove T0. When a portion of the first metal material layer 401 is removed, the first curved surface S1 of the exposed first portion 4021 has a relatively large curvature. This allows a relatively large amount of the first portion 4021 to be retained, preventing excessive resistance of the bonding pad 40 due to a relatively small amount of the retained first portion 4021, or even fracture of the first portion 4021, resulting in a short circuit of the bonding pad 40 and affecting the performance of the semiconductor device. The second portion 4022 is located on the first portion 4021 and the bit line structure 1 and is connected to the first portion 4021. During the formation of the second portion 4022, a large opening needs to be formed, that is, the curvature of the second curved surface S2 of the exposed second portion 4022 is relatively small. This allows adjacent second portions 4022 to be completely disconnected, preventing short circuits between adjacent bonding pads 40, while also providing a larger manufacturing process window for forming the first portion 4021.

[0075] refer to Figure 3 and Figure 1 In some embodiments, an insulating material is deposited in the first groove T1 and the second groove T2, and then polished and flattened to form an insulating structure 501. The method of depositing the insulating material includes but is not limited to chemical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, flow deposition, etc. The insulating structure is filled between adjacent bonding pads 40 to isolate adjacent bonding pads 40 from each other. The upper surface of the bonding pad 40 is flush with the upper surface of the insulating structure 501, that is, the height of the insulating structure 501 in the direction perpendicular to the substrate is equal to the height of the bonding pad 40 in the direction perpendicular to the substrate. The insulating structure is an insulating material, for example, it can be at least one of the following materials: silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, etc., and can also be one or more layers. In some embodiments, it can also include an air gap structure to reduce parasitic capacitance between the bonding pads 40.

[0076] By using two etching methods, selective etching forms bonding pads comprising a first metal material layer and a second metal material layer, wherein the first metal material layer has an L-shaped cross-section and the second metal material layer has a first portion and a second portion with different curvatures. This prevents adjacent bonding pads from shorting due to the connection of the first metal layer, and also prevents adjacent bonding pads from excessive resistance or disconnection due to over-etching of the second metal material layer. In addition, selective etching can speed up the process, shorten process time, and improve production capacity.

[0077] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A plurality of bit line structures are provided on the substrate, each of the plurality of bit line structures comprises a bit line and a bit line sidewall protection layer, the bit line comprises a first semiconductor layer, a metal wire layer and a bit line capping layer, and the bit line sidewall protection layer covers two sidewalls of the bit line; a plurality of contact plugs disposed on the substrate, the plurality of contact plugs being located between adjacent bit line structures, the height of the contact plugs in a direction perpendicular to the substrate being lower than the height of the bit line structures in the direction perpendicular to the substrate; a plurality of bonding pads, the plurality of bonding pads being located on the plurality of contact plugs and correspondingly connected to the plurality of contact plugs, the plurality of bonding pads having a height in a direction perpendicular to the substrate being higher than the height of the bit line structure in the direction perpendicular to the substrate, the bonding pads covering a portion of a top surface of the bit line structure and being disconnected on the top surface of the bit line structure; Wherein, the bonding pad comprises a first metal material layer and a second metal material layer, the second metal material layer is located on the first metal material layer, and the first metal material layer has an L-shaped cross section; The second metal material layer includes a first part and a second part, the height of the first part in the direction perpendicular to the substrate is less than the height of the bit line structure in the direction perpendicular to the substrate, the height of the second part in the direction perpendicular to the substrate is greater than the height of the bit line structure in the direction perpendicular to the substrate, and the curvature of the first part is greater than the curvature of the second part.

2. The semiconductor device according to claim 1, wherein Also includes, A metal silicide layer is disposed between the contact plug and the bonding pad.

3. The semiconductor device according to claim 2, wherein A height of the metal silicide in a direction perpendicular to the substrate is higher than a height of the metal wire layer in a direction perpendicular to the substrate.

4. The semiconductor device according to any one of claims 1 to 3, further comprising: An insulating structure is filled between the plurality of bonding pads, and a height of the insulating structure in a direction perpendicular to the substrate is equal to a height of the bonding pads in the direction perpendicular to the substrate.

5. A method for preparing a semiconductor device, characterized in that: forming a plurality of bit line structures on a substrate, each of the plurality of bit line structures comprising a bit line and a bit line sidewall protection layer, the bit line comprising a first semiconductor layer, a metal wire layer and a bit line capping layer, the bit line sidewall protection layer covering two sidewalls of the bit line; forming a plurality of contact plugs on the substrate, wherein the plurality of contact plugs are located between adjacent bit line structures, and a height of the contact plugs in a direction perpendicular to the substrate is lower than a height of the bit line structures in the direction perpendicular to the substrate; forming a plurality of bonding pads on the plurality of contact plugs, the plurality of bonding pads being located on the plurality of contact plugs and correspondingly connected to the plurality of contact plugs, the plurality of bonding pads having a height in a direction perpendicular to the substrate being higher than the height of the bit line structure in the direction perpendicular to the substrate, the bonding pads covering a portion of a top surface of the bit line structure and being disconnected on the top surface of the bit line structure; Wherein, the bonding pad comprises a first metal material layer and a second metal material layer, the second metal material layer is located on the first metal material layer, and the first metal material layer has an L-shaped cross section; The second metal material layer includes a first part and a second part, the height of the first part in the direction perpendicular to the substrate is less than the height of the bit line structure in the direction perpendicular to the substrate, the height of the second part in the direction perpendicular to the substrate is greater than the height of the bit line structure in the direction perpendicular to the substrate, and the curvature of the first part is greater than the curvature of the second part.

6. The method for preparing a semiconductor device according to claim 5, wherein: The forming of a plurality of contact plugs on the substrate comprises: A contact plug material layer is deposited between the plurality of bit line structures, and the contact plug material layer is etched back to form the contact plug, wherein the height of the contact plug in a direction perpendicular to the substrate is lower than the height of the bit line in the direction perpendicular to the substrate.

7. The method for manufacturing a semiconductor device according to claim 5, wherein forming a plurality of bonding pads on the plurality of contact plugs comprises: Depositing an initial first metal material layer on the contact plug and the bit line structure, wherein the initial first metal material layer covers surfaces of the contact plug and the bit line structure; Depositing an initial second metal material layer on the surface of the initial first metal material layer, wherein the height of the initial second metal material layer in a direction perpendicular to the substrate is higher than the height of the bit line in the direction perpendicular to the substrate, and grinding and flattening the initial second metal material layer; Etching the initial second metal material layer using a first etching method to expose the initial first metal material layer; The initial first metal material layer is etched using a second etching method to form the first metal material layer having an L-shaped cross section.

8. The method for manufacturing a semiconductor device according to any one of claims 5 to 7, further comprising: before forming a plurality of bonding pads on the plurality of contact plugs; A metal silicide layer is formed on the contact plug, wherein a height of the metal silicide in a direction perpendicular to the substrate is higher than a height of the metal wire layer in the direction perpendicular to the substrate.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising: after forming a plurality of bonding pads on the plurality of contact plugs; cleaning the conjugate pad; An insulating structure is filled between the plurality of bonding pads, wherein a height of the insulating structure in a direction perpendicular to the substrate is equal to a height of the bonding pads in the direction perpendicular to the substrate.

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