Three-dimensional dynamic memory and preparation method thereof

Abstract

The invention discloses a three-dimensional dynamic memory and a preparation method thereof, and relates to the field of memories, and the memory comprises a substrate, a first metal electrode layer, a second metal electrode layer, a third metal electrode layer, a dielectric layer, a functional layer and a capacitor dielectric layer. Wherein the first metal electrode layers and the dielectric layers are arranged in a staggered and stacked manner; the third metal electrode layer is of a T-shaped structure; the vertical section of the third metal electrode layer penetrates through the substrate from the dielectric layer on the topmost layer and extends into the substrate; the outer surface of the vertical section of the third metal electrode layer is coated with a second metal electrode layer; the outer surface of the second metal electrode layer is coated with a functional layer; each capacitor dielectric layer is of a hollow columnar structure with the corresponding third metal electrode layer as the center. And the capacitor dielectric layer penetrates from the dielectric layer at the topmost layer to the direction of the substrate and extends into the substrate. The second metal electrode layer is introduced, so that the data operation window of the three-dimensional dynamic memory is improved, and the bit error rate of the three-dimensional memory is reduced.

Description

Technical Field

[0001] The present application relates to the field of memory, and in particular to a three-dimensional dynamic memory and a preparation method thereof. Background Art

[0002] 3D 1S1C is considered to be a powerful alternative to DRAM in the face of the three-dimensional stacking dilemma because of its easy three-dimensional stacking, high density and performance close to DRAM (Dynamic Random Access Memory). However, it still has the problem of high bit error rate caused by a small operating window, which limits the further development of 3D 1S1C. Summary of the invention

[0003] The purpose of the present application is to provide a three-dimensional dynamic memory and a preparation method thereof, which can improve the data operation window of the 3D 1S1C memory and reduce the bit error rate of the memory.

[0004] To achieve the above objectives, this application provides the following solutions:

[0005] In a first aspect, the present application provides a three-dimensional dynamic memory, comprising: a substrate, a plurality of first metal electrode layers, at least one second metal electrode layer, at least one third metal electrode layer, a plurality of dielectric layers, at least one functional layer and at least one capacitor dielectric layer;

[0006] A plurality of the first metal electrode layers and a plurality of the dielectric layers are arranged in a staggered stacking manner; in the staggered stacking structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is arranged on the upper surface of the substrate;

[0007] Each of the third metal electrode layers is a T-shaped structure; the vertical section of each of the third metal electrode layers penetrates from the upper surface of the top dielectric layer toward the substrate and extends to the inside of the substrate; the horizontal section of each of the third metal electrode layers is arranged on the upper surface of the top dielectric layer;

[0008] The outer surface of each vertical segment of the third metal electrode layer is covered with the second metal electrode layer; the outer surface of each second metal electrode layer is covered with the functional layer;

[0009] The number of the capacitor dielectric layers and the number of the third metal electrode layers are the same and correspond one to one;

[0010] Each of the capacitor dielectric layers is a hollow columnar structure centered on the corresponding third metal electrode layer; each of the capacitor dielectric layers penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate.

[0011] In a second aspect, the present application provides a method for preparing a three-dimensional dynamic memory, comprising:

[0012] Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate;

[0013] At least one annular groove is formed on the substrate; each of the annular grooves penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate;

[0014] For each of the annular grooves, uniformly depositing a capacitor dielectric layer in the annular groove;

[0015] After filling the capacitor dielectric layer, a hole is formed at the center of each capacitor dielectric layer; each hole penetrates from the upper surface of the top dielectric layer toward the substrate and extends to the inside of the substrate;

[0016] For each of the holes, a functional layer and a second metal electrode layer are uniformly deposited on the inner wall of the hole in sequence;

[0017] After depositing the second metal electrode layer, the remaining space of the hole is filled with a third metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer.

[0018] In a third aspect, the present application provides a method for preparing a three-dimensional dynamic memory, comprising:

[0019] Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate;

[0020] forming at least one hole in the substrate;

[0021] Uniformly depositing a functional layer and a second metal electrode layer on the inner wall of each hole in sequence;

[0022] After depositing the second metal electrode layer, filling the remaining space of the hole with a third metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a predetermined area on the upper surface of the topmost dielectric layer;

[0023] After filling the third metal electrode layer, forming an annular groove on the substrate with each of the third metal electrode layers as the center; the annular groove penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the inside of the substrate;

[0024] For each of the annular grooves, a capacitor dielectric layer is uniformly deposited in the annular groove.

[0025] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0026] The present application provides a three-dimensional dynamic memory and a preparation method thereof, a substrate, a first metal electrode layer, a second metal electrode layer, a third metal electrode layer, a dielectric layer, a functional layer and a capacitor dielectric layer; wherein the first metal electrode layer and the dielectric layer are arranged in an alternating stack; each third metal electrode layer is a T-shaped structure; the vertical segment of each third metal electrode layer penetrates and extends from the upper surface of the top dielectric layer to the direction where the substrate is located to the inside of the substrate; the outer surface of the vertical segment of each third metal electrode layer is coated with the second metal electrode layer; the outer surface of each second metal electrode layer is coated with the functional layer; each capacitor dielectric layer is a hollow columnar structure centered on the corresponding third metal electrode layer; each capacitor dielectric layer penetrates and extends from the upper surface of the top dielectric layer to the direction where the substrate is located to the inside of the substrate. The present invention sets a second metal electrode layer between the third metal electrode layer and the functional layer, thereby improving the data operation window of the three-dimensional dynamic memory and reducing the bit error rate of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A schematic diagram of the structure of a three-dimensional dynamic memory provided in Example 1 of the present application;

[0029] Figure 2 A schematic flow chart of a method for preparing a three-dimensional dynamic memory provided in Example 2 of the present application;

[0030] Figure 3 A schematic diagram of a process for preparing a capacitor provided in Example 2 of the present application;

[0031] Figure 4 A schematic flow chart of the preparation process of the gating device provided in Example 2 of the present application.

[0032] Reference numerals:

[0033] 1-substrate; 2-first metal electrode layer; 3-dielectric layer; 4-third metal electrode layer; 5-second metal electrode layer; 6-functional layer; 7-capacitor dielectric layer; 8-first capacitor electrode layer; 9-second capacitor electrode layer. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0036] Example 1

[0037] like Figure 1 As shown, this embodiment provides a three-dimensional dynamic memory, including: a peripheral electrode layer in the horizontal direction, a functional layer 6 in the vertical direction and a capacitor dielectric layer 7. Specifically, the peripheral electrode layer includes a substrate 1, a plurality of first metal electrode layers 2 and a plurality of dielectric layers 3.

[0038] A plurality of the first metal electrode layers 2 and a plurality of the dielectric layers 3 are arranged in an interlaced and stacked manner; in the interlaced and stacked structure, the topmost layer is the dielectric layer 3 and the bottommost layer is the first metal electrode layer 2; the bottommost first metal electrode layer 2 is arranged on the upper surface of the substrate 1.

[0039] The peripheral electrode layer has at least one hole penetrating in the vertical direction, and the holes are arranged in an array according to a certain rule. The bottom of the hole extends at least to the substrate 1, and the inner wall of the hole is sequentially deposited with a functional layer 6, a second metal electrode layer 5 and a third metal electrode layer 4; the third metal electrode layer 4 extends all the way to the upper surface of the peripheral electrode layer. Figure 1 As shown, each of the third metal electrode layers 4 has a T-shaped structure; the vertical section of each of the third metal electrode layers 4 penetrates from the upper surface of the top dielectric layer 3 toward the direction of the substrate 1 and extends to the inside of the substrate 1; the horizontal section of each of the third metal electrode layers 4 is arranged on the upper surface of the top dielectric layer 3. The outer surface of the vertical section of each of the third metal electrode layers 4 is covered with the second metal electrode layer 5; the outer surface of each of the second metal electrode layers 5 is covered with the functional layer 6.

[0040] The resistance of the second metal electrode layer 5 is higher than the resistance of the third metal electrode layer 4 .

[0041] The bottoms of the functional layer 6 , the second metal electrode layer 5 , and the third metal electrode layer 4 are lower than the bottom first metal electrode layer 2 in the vertical direction, that is, the bottoms extend to the area where the substrate 1 is located.

[0042] There is an annular groove outside each hole, the hole is located at the center of the annular groove, the annular groove surrounds the hole and vertically cuts off the peripheral electrode layer, and the bottom of the annular groove at least extends to the substrate 1. The annular groove is evenly filled with a capacitor dielectric layer 7, and the area directly facing the third metal electrode layer 4 and the first metal electrode layer 2 constitutes a storage unit. Figure 1 As shown, the number of the capacitor dielectric layers 7 and the third metal electrode layers 4 is the same and corresponds to each other. Each of the capacitor dielectric layers 7 is a hollow columnar structure centered on the corresponding third metal electrode layer 4; each of the capacitor dielectric layers 7 penetrates from the upper surface of the topmost dielectric layer 3 toward the direction of the substrate 1 and extends to the inside of the substrate 1.

[0043] As an optional implementation, in the traditional 3D 1S1C preparation process, since it is necessary to consider the deep etching of the holes and the annular grooves, the first metal electrode layer 2 is required to be compatible with the high aspect ratio etching process, and the first metal electrode layer 2 is also used as the word line of the storage array, and it is required to meet the low resistance requirement, but usually the electrode material of the capacitor needs to have a good matching ability with the capacitor dielectric, including considerations such as energy band and work function. Therefore, after the annular groove is prepared, it is necessary to use a capacitor electrode material that matches the capacitor dielectric layer 7 to replace a part of the first metal electrode layer 2 to achieve the purpose of reducing the leakage current of the storage unit. And it is necessary to ensure that after the replacement is completed, the side wall of the annular groove can still be kept smooth to ensure the uniform distribution of the capacitor electric field. Therefore, the position where the first metal electrode layer 2 contacts the annular groove will be concave inward, and the inside will be filled with the capacitor electrode layer to keep the inner wall of the annular groove smooth. The capacitor electrode layer needs to be made of a material that can well limit the leakage current in the capacitor dielectric layer 7. Such as Figure 1 As shown, the three-dimensional dynamic memory further includes: a first capacitor electrode layer 8 and a second capacitor electrode layer 9.

[0044] The first capacitor electrode layer 8 is evenly arranged between the inner wall of each capacitor dielectric layer 7 of the hollow columnar structure and each layer of the first metal electrode layer 2 .

[0045] The second capacitor electrode layer 9 is evenly arranged between the outer wall of each capacitor dielectric layer 7 of the hollow columnar structure and each layer of the first metal electrode layer 2 .

[0046] As an optional implementation, the width of the first capacitor electrode layer 8 and the width of the second capacitor electrode layer 9 are the same as the width of the corresponding first metal electrode layer 2 .

[0047] The dielectric layer 3 and the first metal electrode layer 2 are alternately stacked and repeated periodically in the vertical direction as needed, and the number of repetitions is the same as the number of memory cell layers required by the three-dimensional 1S1C memory. That is, the first metal electrode layer 2 and the dielectric layer 3 have the same number of layers, and the number of layers is the same as the number of memory cell layers required by the three-dimensional dynamic memory.

[0048] In this embodiment, the purpose of the second metal electrode layer 5 is to adjust the holding voltage of the gating device, because the current 1S1C operation window difference is mainly caused by the low holding voltage during the high-speed operation of the gating device; and the functional layer 6 has two states: high resistance state and low resistance state. When the voltage across the functional layer 6 exceeds the threshold voltage Vth of the functional layer 6, the functional layer 6 switches from the high resistance state to the low resistance state. When the voltage across the functional layer 6 in the low resistance state is lower than the holding voltage Vhold of the functional layer 6, the functional layer 6 switches from the low resistance state to the high resistance state; the total holding voltage VHold of the functional layer 6 and the second metal electrode layer 5 = Vhold + Vhold * R / R_low, where R_low is the resistance of the functional layer 6 in the low resistance state, and R is the resistance of the second metal electrode layer 5, with a value range of 0≤R≤Rmax, where Rmax is the value of R when VHold is equal to Vth. By adjusting the resistance of the second metal electrode layer 5, the total holding voltage VHold of the gating device can be adjusted; by selecting a suitable material of the second metal electrode layer 5 with a larger resistance value, the 1S1C operation window can be increased. When operating the memory cell, since the resistance of the third metal electrode layer 4 is lower than that of the second metal electrode layer 5, the electrical signal is preferentially transmitted to the target memory cell position through the third metal electrode layer 4. When the memory device is then operated, the existence of the second metal electrode layer 5 will increase the operation window of the 1S1C memory.

[0049] If the second metal electrode layer 5 is eliminated, the purpose of increasing the 1S1C operating window can also be achieved by increasing the resistance of the third metal electrode layer 4. However, the third metal electrode layer 4 is not only the electrode of the storage device. When the number of storage unit stacking layers is higher, it also plays the role of connecting the lower storage device and the top bit line. The larger resistance of the third metal electrode layer 4 will cause the transmission speed of the read and write signals in the three-dimensional storage array to be greatly reduced, which is unacceptable for the 1S1C memory of the target DRAM scenario.

[0050] If the second metal electrode layer 5 is deposited first, then the functional layer 6 is deposited, and then the third metal electrode layer 4 is deposited, since the resistance of the second metal electrode layer 5 is only higher than that of the third metal electrode layer 4, 2However, its resistance value still cannot separate two adjacent cells in the vertical direction, which is equivalent to the same string of storage cells in the vertical direction sharing one selection device, thus losing the advantage of high density of 3D 1S1C memory.

[0051] If the second metal electrode layer 5 is placed in the annular groove, there will also be the problem of the same string of storage units sharing a selection device in the vertical direction. Therefore, depositing the functional layer 6, the second metal electrode layer 5, and the third metal electrode layer 4 in the hole in sequence is the only feasible solution.

[0052] The advantages of this embodiment are:

[0053] (1) The second metal electrode layer 5 is provided to improve the data operation window of the 3D 1S1C memory and reduce the bit error rate of the three-dimensional memory.

[0054] (2) In the 3D 1S1C memory, a portion of the first metal electrode layer 2 is replaced by a capacitor electrode layer (including a first capacitor electrode layer 8 and a second capacitor electrode layer 9), thereby optimizing the capacitor electrode preparation process and reducing the leakage current of the three-dimensional memory.

[0055] Example 2

[0056] This embodiment provides a method for preparing a three-dimensional dynamic memory, such as Figure 2 As shown, the method is to first carry out the preparation process of the capacitor, and then carry out the preparation process of the gating device on this basis. The method includes the following steps.

[0057] (a1) A first metal electrode layer 2 and a dielectric layer 3 are alternately stacked and grown on a substrate 1 to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer 3, and the bottommost layer is the first metal electrode layer 2; the bottommost first metal electrode layer 2 is arranged on the upper surface of the substrate 1.

[0058] (a2) at least one annular groove is formed on the substrate; each of the annular grooves penetrates from the upper surface of the topmost dielectric layer 3 toward the direction of the substrate 1 and extends to the interior of the substrate 1.

[0059] (a3) For each of the annular grooves, a capacitor dielectric layer 7 is uniformly deposited in the annular groove to fill the annular groove.

[0060] Steps (a1) to (a3) ​​are capacitor manufacturing processes and are Figure 2 and Figure 3 The preparation process consisting of (a), (b) and (e) is shown.

[0061] (a4) After filling the capacitor dielectric layer 7, a hole is formed at the center of each of the capacitor dielectric layers 7; each of the holes penetrates from the upper surface of the topmost dielectric layer 3 toward the direction of the substrate 1 and extends to the interior of the substrate 1.

[0062] (a5) For each of the holes, a functional layer 6 and a second metal electrode layer 5 are uniformly deposited on the inner wall of the hole in sequence.

[0063] (a6) After depositing the second metal electrode layer 5, the remaining space of the hole is filled with a third metal electrode layer 4; the third metal electrode layer 4 extends from the area of ​​the hole to a predetermined area on the upper surface of the top dielectric layer 3. Steps (a4) to (a6) are the preparation process of the gating device, corresponding to Figure 2 (f) to (i) of the Regulations.

[0064] As an optional implementation, Figure 3 As shown, before performing step (a3) ​​of "uniformly depositing a capacitor dielectric layer 7 in the annular groove", the method for preparing the three-dimensional dynamic memory further includes:

[0065] (1) A portion of each first metal electrode layer 2 on both sides of the annular groove is removed inwardly. This step corresponds to Figure 3 The preparation process of (c) in FIG.

[0066] (2) Fill the capacitor electrode layer at the position where the first metal electrode layer 2 is removed so that the inner wall of the annular groove remains smooth. This step corresponds to Figure 3 The preparation process of (d).

[0067] The following is a method for preparing a three-dimensional dynamic memory after introducing specific materials into each layer, and the preparation process of the capacitor is first performed, and then the preparation process of the gating device is performed. The specific preparation process flow is as follows:

[0068] like Figure 2 In part (a), a three-layer stack of 50nm W (tungsten) and 100nm SiO 2 (silicon dioxide), and the top layer is SiO 2 That is, the dielectric layer 3 is made of SiO 2 , the first metal electrode layer 2 is made of W.

[0069] like Figure 2 In part (b), a ring pattern is formed on the stack by photolithography, and ICP etching with good anisotropy is used. SF 6 +C 4 F 8 (sulfur hexafluoride + octafluorocyclobutane), the stack is etched to obtain an annular groove with a width of 50 nm.

[0070] like Figure 2 In part (c), HF (hydrofluoric acid) and HNO 3 (nitric acid) mixed solution selectively removes 20nm of exposed W.

[0071] like Figure 2 In part (d), W and SiO are treated by ALD process. 2 The precursor with selective growth ability uniformly grows a layer of TiN (tin) electrode on the W surface with a thickness of 20nm to keep the side wall of the annular groove flat. That is, the first capacitor electrode layer 8 and the second capacitor electrode layer 9 are made of TiN.

[0072] like Figure 2 In part (e), a 10nm thick Al layer is uniformly grown on the side wall of the annular groove through the ALD process. 2 O 3 (aluminum oxide); then grow a 15nm thick layer of ZrO 2 (zirconium dioxide); fill the annular groove.

[0073] like Figure 2 In part (f), a circular pattern is formed on the stack by photolithography at the center of the annular groove. ICP etching with good anisotropy is used, and SF 6 +C 4 F 8 , the stack is etched to obtain circular holes with a diameter of 100nm.

[0074] like Figure 2 In part (g), a 30nm GeTE layer is uniformly deposited on the sidewall of the hole. 9 Material, the chemical formula of the material is Ge:Te=1:9.

[0075] like Figure 2 In part (h), a layer of TiN is uniformly deposited on the side wall of the hole, and its resistivity is 3*10 -4 Ω·m.

[0076] like Figure 2 In part (i), a layer of W is uniformly deposited on the side wall of the hole, and its resistivity is 10 -6 Ω·m.

[0077] At this point, the preparation of the three-dimensional dynamic memory is completed.

[0078] Among them, when TiN is used as the capacitor electrode material, compared with the traditional use of W as the electrode material, the leakage current of the capacitor is reduced from 2×10 -6 A / cm 2 Down to 6×10-8 A / cm 2 , which greatly reduces the leakage current of the capacitor and improves the data retention time of the three-dimensional memory device.

[0079] By adding a layer of high-resistance TiN between the functional layer 6 and the third metal electrode layer 4, the holding voltage of the gate device is increased from 0.5V to 1V, and the corresponding operation window of the memory is also increased by 0.5V.

[0080] Example 3

[0081] This embodiment provides a method for preparing a three-dimensional dynamic memory. The method first performs a preparation process of a gate device, and then performs a preparation process of a capacitor. The method includes:

[0082] (b1) A first metal electrode layer 2 and a dielectric layer 3 are alternately stacked and grown on a substrate 1 to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer 3, and the bottommost layer is the first metal electrode layer 2; the bottommost first metal electrode layer 2 is arranged on the upper surface of the substrate 1.

[0083] (b2) forming at least one hole in the substrate.

[0084] (b3) The functional layer 6 and the second metal electrode layer 5 are uniformly deposited on the inner wall of each of the holes in sequence.

[0085] (b4) After depositing the second metal electrode layer 5, the remaining space of the hole is filled with the third metal electrode layer 4; the third metal electrode layer 4 extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer 3.

[0086] Steps (b1) to (b4) are the manufacturing process of the gating device, corresponding to Figure 4 (a) to (d) of the

[0087] (b5) After filling the third metal electrode layer 4, an annular groove is formed on the substrate with each of the third metal electrode layers 4 as the center; the annular groove penetrates from the upper surface of the topmost dielectric layer 3 toward the direction of the substrate 1 and extends to the interior of the substrate 1.

[0088] (b6) For each of the annular grooves, a capacitor dielectric layer 7 is uniformly deposited in the annular groove to fill the annular groove.

[0089] As an optional implementation, Figure 3 As shown, before performing step (b6) of "uniformly depositing a capacitor dielectric layer 7 in the annular groove", the method for preparing the three-dimensional dynamic memory further includes:

[0090] (1) A portion of each first metal electrode layer 2 on both sides of the annular groove is removed inwardly. This step corresponds to Figure 3 The preparation process of (c) in FIG.

[0091] (2) Fill the capacitor electrode layer at the position where the first metal electrode layer 2 is removed so that the inner wall of the annular groove remains smooth. This step corresponds to Figure 3 The preparation process of (d).

[0092] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A three-dimensional dynamic memory, characterized in that: The three-dimensional dynamic memory comprises: a substrate, a plurality of first metal electrode layers, at least one second metal electrode layer, at least one third metal electrode layer, a plurality of dielectric layers, at least one functional layer and at least one capacitor dielectric layer; A plurality of the first metal electrode layers and a plurality of the dielectric layers are arranged in a staggered stacking manner; in the staggered stacking structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is arranged on the upper surface of the substrate; Each of the third metal electrode layers is a T-shaped structure; the vertical section of each of the third metal electrode layers penetrates from the upper surface of the top dielectric layer toward the substrate and extends to the inside of the substrate; the horizontal section of each of the third metal electrode layers is arranged on the upper surface of the top dielectric layer; The outer surface of each vertical segment of the third metal electrode layer is covered with the second metal electrode layer; the outer surface of each second metal electrode layer is covered with the functional layer; The number of the capacitor dielectric layers and the number of the third metal electrode layers are the same and correspond one to one; Each of the capacitor dielectric layers is a hollow columnar structure centered on the corresponding third metal electrode layer; each of the capacitor dielectric layers penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate.

2. The three-dimensional dynamic memory according to claim 1, characterized in that: The three-dimensional dynamic memory further includes: a first capacitor electrode layer and a second capacitor electrode layer; The first capacitor electrode layer is evenly arranged between the inner wall of each capacitor dielectric layer of the hollow columnar structure and each layer of the first metal electrode layer; The second capacitor electrode layer is evenly arranged between the outer wall of each capacitor dielectric layer of the hollow columnar structure and each layer of the first metal electrode layer.

3. The three-dimensional dynamic memory according to claim 2, characterized in that: The width of the first capacitor electrode layer and the width of the second capacitor electrode layer are the same as the width of the corresponding first metal electrode layer.

4. The three-dimensional dynamic memory according to claim 2, characterized in that: The first capacitor electrode layer and the second capacitor electrode layer are made of a material that limits leakage current in the capacitor dielectric layer.

5. The three-dimensional dynamic memory according to claim 1, characterized in that: The resistance of the second metal electrode layer is higher than the resistance of the corresponding third metal electrode layer.

6. The three-dimensional dynamic memory according to claim 1, characterized in that: The bottom of the functional layer, the bottom of the second metal electrode layer and the bottom of the third metal electrode layer are all located in the region where the substrate is located.

7. The three-dimensional dynamic memory according to claim 1, characterized in that: The number of layers of the first metal electrode layer and the dielectric layer is the same, and the number of layers is the same as the number of memory cell layers required by the three-dimensional dynamic memory.

8. A method for preparing a three-dimensional dynamic memory, characterized in that: The preparation method of the three-dimensional dynamic memory comprises: Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate; At least one annular groove is formed on the substrate; each of the annular grooves penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the interior of the substrate; For each of the annular grooves, uniformly depositing a capacitor dielectric layer in the annular groove; After filling the capacitor dielectric layer, a hole is formed at the center of each capacitor dielectric layer; each hole penetrates from the upper surface of the top dielectric layer toward the substrate and extends to the inside of the substrate; For each of the holes, a functional layer and a second metal electrode layer are uniformly deposited on the inner wall of the hole in sequence; After depositing the second metal electrode layer, the remaining space of the hole is filled with a third metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a preset area on the upper surface of the topmost dielectric layer.

9. A method for preparing a three-dimensional dynamic memory, characterized in that: The preparation method of the three-dimensional dynamic memory comprises: Alternately stacking and growing a first metal electrode layer and a dielectric layer on a substrate to form a base sheet; in the staggered stacked structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is disposed on the upper surface of the substrate; forming at least one hole in the substrate; Uniformly depositing a functional layer and a second metal electrode layer on the inner wall of each hole in sequence; After depositing the second metal electrode layer, filling the remaining space of the hole with a third metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a predetermined area on the upper surface of the topmost dielectric layer; After filling the third metal electrode layer, an annular groove is formed on the substrate with each of the third metal electrode layers as the center; the annular groove penetrates from the upper surface of the topmost dielectric layer toward the substrate and extends to the inside of the substrate; For each of the annular grooves, a capacitor dielectric layer is uniformly deposited in the annular groove.

10. The method for preparing a three-dimensional dynamic memory according to claim 8 or 9, characterized in that: Before performing the step of "uniformly depositing a capacitor dielectric layer in the annular groove", the method for preparing the three-dimensional dynamic memory further includes: Removing a portion of each first metal electrode layer on both sides of the annular groove inwardly; A capacitor electrode layer is filled at the position where the first metal electrode layer is removed so as to keep the inner wall of the annular groove smooth.

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