Three-dimensional dynamic memory and method of manufacturing the same

Abstract

The application discloses a three-dimensional dynamic memory and a preparation method thereof, and relates to the field of memories.The memory comprises a substrate, a first metal electrode layer, a third metal electrode layer, a dielectric layer, a functional layer and a capacitor dielectric layer; the first metal electrode layer and the dielectric layer are arranged in an interlaced and laminated mode; the third metal electrode layer has a T-shaped structure; a vertical section of the third metal electrode layer penetrates and extends to the inside of the substrate from the direction of the dielectric layer at the topmost layer to the substrate; the outer surface of the vertical section of the third metal electrode layer is coated with a second metal electrode layer; the outer surface of the second metal electrode layer is coated with the functional layer; each capacitor dielectric layer has a hollow columnar structure with the corresponding third metal electrode layer as the center; and the capacitor dielectric layer penetrates and extends to the inside of the substrate from the direction of the dielectric layer at the topmost layer to the substrate. The second metal electrode layer is introduced, the data operation window of the three-dimensional dynamic memory is improved, and the bit error rate of the three-dimensional memory is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory, in particular to a three-dimensional dynamic memory and a preparation method thereof. BACKGROUND

[0002] 3D 1S1C is considered as a powerful substitute for DRAM (Dynamic Random Access Memory) when facing the dilemma of three-dimensional stacking because of its easy three-dimensional stacking, high density and performance close to DRAM, but it still has the problem of high error rate caused by small operation window, which limits the further development of 3D 1S1C. SUMMARY

[0003] The purpose of the present application is to provide a three-dimensional dynamic memory and a preparation method thereof, which can improve the data operation window of 3D 1S1C memory and reduce the error rate of the memory.

[0004] To achieve the above purpose, the present application provides the following solutions:

[0005] In a first aspect, the present application provides a three-dimensional dynamic memory, comprising: a substrate, a plurality of first metal electrode layers, at least one second metal electrode layer, at least one third metal electrode layer, a plurality of dielectric layers, at least one functional layer and at least one capacitor dielectric layer;

[0006] The plurality of first metal electrode layers and the plurality of dielectric layers adopt an interlaced layer stacking arrangement; in the interlaced layer stacking structure, the topmost layer is the dielectric layer, and the bottommost layer is the first metal electrode layer; the bottommost first metal electrode layer is arranged on the upper surface of the substrate;

[0007] Each of the third metal electrode layers is in a T-shaped structure; the vertical segment of each of the third metal electrode layers penetrates and extends to the inside of the substrate from the upper surface of the topmost dielectric layer in the direction of the substrate; the horizontal segment of each of the third metal electrode layers is arranged on the upper surface of the topmost dielectric layer;

[0008] The outer surface of the vertical segment of each of the third metal electrode layers is coated with the second metal electrode layer; the outer surface of each of the second metal electrode layers is coated with the functional layer;

[0009] The number of capacitor dielectric layers is the same as that of third metal electrode layers, and each capacitor dielectric layer corresponds to one third metal electrode layer;

[0010] Each of the capacitor dielectric layers is a hollow columnar structure with the corresponding third metal electrode layer as the center; each of the capacitor dielectric layers penetrates and extends to the inside of the substrate from the upper surface of the topmost dielectric layer in the direction of the substrate.

[0011] In a second aspect, the present application provides a method for preparing a three-dimensional dynamic memory, comprising:

[0012] forming a substrate by alternately stacking a first metal electrode layer and a dielectric layer on a substrate; in the alternately stacked structure, the top layer is the dielectric layer, and the bottom layer is the first metal electrode layer; the bottom layer of the first metal electrode layer is arranged on the upper surface of the substrate;

[0013] forming at least one annular groove on the substrate; each annular groove penetrates and extends to the interior of the substrate from the upper surface of the top layer of the dielectric layer to the direction of the substrate;

[0014] for each annular groove, uniformly depositing a capacitor dielectric layer in the annular groove;

[0015] after filling the capacitor dielectric layer, forming a hole in the center of each capacitor dielectric layer; each hole penetrates and extends to the interior of the substrate from the upper surface of the top layer of the dielectric layer to the direction of the substrate;

[0016] for each hole, sequentially and uniformly depositing a functional layer and a second metal electrode layer on the inner wall of the hole;

[0017] after depositing the second metal electrode layer, filling a third metal electrode layer in the remaining space of the hole; the third metal electrode layer extends from the area of the hole to the preset area of the upper surface of the top layer of the dielectric layer.

[0018] In a third aspect, the present application provides a method for preparing a three-dimensional dynamic memory, comprising:

[0019] forming a substrate by alternately stacking a first metal electrode layer and a dielectric layer on a substrate; in the alternately stacked structure, the top layer is the dielectric layer, and the bottom layer is the first metal electrode layer; the bottom layer of the first metal electrode layer is arranged on the upper surface of the substrate;

[0020] forming at least one hole on the substrate;

[0021] sequentially and uniformly depositing a functional layer and a second metal electrode layer on the inner wall of each hole;

[0022] after depositing the second metal electrode layer, filling a third metal electrode layer in the remaining space of the hole; the third metal electrode layer extends from the area of the hole to the preset area of the upper surface of the top layer of the dielectric layer.

[0023] After filling the third metal electrode layer, annular grooves are formed on the substrate with each third metal electrode layer as the center; the annular grooves penetrate and extend to the inside of the substrate from the upper surface of the topmost dielectric layer to the direction in which the substrate is located;

[0024] For each annular groove, a capacitor dielectric layer is uniformly deposited in the annular groove.

[0025] According to the specific embodiments provided in the present application, the following technical effects are disclosed:

[0026] The present application provides a three-dimensional dynamic memory and a preparation method thereof, a substrate, a first metal electrode layer, a second metal electrode layer, a third metal electrode layer, a dielectric layer, a functional layer, and a capacitor dielectric layer; wherein the first metal electrode layer and the dielectric layer are alternately and laminatedly arranged; each third metal electrode layer is a T-shaped structure; the vertical section of each third metal electrode layer penetrates and extends to the inside of the substrate from the upper surface of the topmost dielectric layer to the direction in which the substrate is located; the outer surface of the vertical section of each third metal electrode layer is coated with a second metal electrode layer; the outer surface of each second metal electrode layer is coated with a functional layer; each capacitor dielectric layer is a hollow columnar structure with the corresponding third metal electrode layer as the center; each capacitor dielectric layer penetrates and extends to the inside of the substrate from the upper surface of the topmost dielectric layer to the direction in which the substrate is located. The present application sets a second metal electrode layer between the third metal electrode layer and the functional layer, improves the data operation window of the three-dimensional dynamic memory, and reduces the bit error rate of the three-dimensional memory. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0028] Figure 1 A structure schematic diagram of a three-dimensional dynamic memory provided in Embodiment 1 of the present application;

[0029] Figure 2 A flowchart of a preparation method of a three-dimensional dynamic memory provided in Embodiment 2 of the present application;

[0030] Figure 3 A flowchart of a preparation process of a capacitor provided in Embodiment 2 of the present application;

[0031] Figure 4 A flowchart of a preparation process of a gating device provided in Embodiment 2 of the present application.

[0032] Figure label:

[0033] 1-Substrate; 2-First metal electrode layer; 3-Dielectric layer; 4-Third metal electrode layer; 5-Second metal electrode layer; 6-Functional layer; 7-Capacitor dielectric layer; 8-First capacitor electrode layer; 9-Second capacitor electrode layer. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1

[0037] like Figure 1 As shown, this embodiment provides a three-dimensional dynamic memory, including: a horizontal peripheral electrode layer, a vertical functional layer 6, and a capacitor dielectric layer 7, etc. Specifically, the peripheral electrode layer includes a substrate 1, a plurality of first metal electrode layers 2, and a plurality of dielectric layers 3.

[0038] The plurality of first metal electrode layers 2 and the plurality of dielectric layers 3 are arranged in an alternating stacked manner; in the alternating stacked structure, the top layer is the dielectric layer 3 and the bottom layer is the first metal electrode layer 2; the bottom first metal electrode layer 2 is disposed on the upper surface of the substrate 1.

[0039] The outer electrode layer has at least one through-hole in the vertical direction. The holes are arranged in an array according to a certain pattern, and the bottom of the holes extends at least to the substrate 1. The inner walls of the holes are sequentially deposited with a functional layer 6, a second metal electrode layer 5, and a third metal electrode layer 4; the third metal electrode layer 4 extends all the way to the upper surface of the outer electrode layer. Figure 1 As shown, each of the third metal electrode layers 4 has a T-shaped structure; the vertical segment of each third metal electrode layer 4 extends from the upper surface of the top dielectric layer 3 towards the substrate 1 and into the interior of the substrate 1; the horizontal segment of each third metal electrode layer 4 is disposed on the upper surface of the top dielectric layer 3. The outer surface of the vertical segment of each third metal electrode layer 4 is covered with the second metal electrode layer 5; the outer surface of each second metal electrode layer 5 is covered with the functional layer 6.

[0040] The resistance of the second metal electrode layer 5 is higher than that of the third metal electrode layer 4.

[0041] The bottom of the functional layer 6, the second metal electrode layer 5 and the third metal electrode layer 4 is lower than the bottom of the first metal electrode layer 2 in the vertical direction, i.e. the bottom extends to the area where the substrate 1 is located.

[0042] Each hole is located at the center of the annular groove, and the annular groove surrounds the hole and vertically cuts off the peripheral electrode layer. The bottom of the annular groove extends to at least the substrate 1. The annular groove is uniformly filled with a capacitor dielectric layer 7, and the area where the third metal electrode layer 4 and the first metal electrode layer 2 are opposite constitutes a storage unit. Figure 1 As shown in the figure, the number of the capacitor dielectric layer 7 and the third metal electrode layer 4 is the same and one-to-one correspondence. Each capacitor dielectric layer 7 is a hollow columnar structure with the corresponding third metal electrode layer 4 as the center. Each capacitor dielectric layer 7 penetrates and extends to the inside of the substrate 1 from the upper surface of the topmost dielectric layer 3 to the direction where the substrate 1 is located.

[0043] As an optional embodiment, in the traditional 3D 1S1C preparation process, since the deep etching of the hole and the annular groove needs to be considered, the first metal electrode layer 2 needs to be compatible with the high aspect ratio etching process, and the first metal electrode layer 2 also simultaneously serves as the word line of the storage array, which needs to meet the requirement of low resistance. However, the electrode material of the capacitor usually needs to have good matching ability with the capacitor dielectric, including the energy band and work function. Therefore, after the annular groove is prepared, the capacitor electrode material that matches the capacitor dielectric layer 7 is used to replace part of the first metal electrode layer 2, so as to achieve the purpose of reducing the leakage current of the storage unit. And it is necessary to ensure that after the replacement is completed, the side wall of the annular groove can still remain smooth to ensure the uniform distribution of the capacitor electric field. Therefore, the position of the first metal electrode layer 2 in contact with the annular groove is inwardly recessed, and the inside is filled with a capacitor electrode layer to keep the inside wall of the annular groove smooth. The capacitor electrode layer needs to be selected from a material that can well limit the leakage current of the capacitor dielectric layer 7. Figure 1 As shown in the figure, the three-dimensional dynamic memory further comprises a first capacitor electrode layer 8 and a second capacitor electrode layer 9.

[0044] The first capacitor electrode layer 8 is arranged between the inner wall of each hollow columnar structure of the capacitor dielectric layer 7 and each layer of the first metal electrode layer 2.

[0045] The second capacitor electrode layer 9 is arranged between the outer wall of each hollow columnar structure of the capacitor dielectric layer 7 and each layer of the first metal electrode layer 2.

[0046] As an optional embodiment, the width of the first capacitor electrode layer 8, the width of the second capacitor electrode layer 9 and the width of the corresponding first metal electrode layer 2 are the same.

[0047] The dielectric layer 3 and the first metal electrode layer 2 are alternately stacked in the vertical direction and periodically repeated according to needs, and the number of repetitions is the same as the number of layers of the storage unit required by the three-dimensional 1S1C memory. That is, the number of layers of the first metal electrode layer 2 and the dielectric layer 3 is the same, and the number of layers is the same as the number of layers of the storage unit required by the three-dimensional dynamic memory.

[0048] In this embodiment, the purpose of the second metal electrode layer 5 is to regulate the holding voltage of the gating device. The main reason for the poor 1S1C operation window is that the holding voltage is low during the high-speed operation of the gating device. The functional layer 6 has two states of high resistance and low resistance. When the voltage across the functional layer 6 exceeds the threshold voltage Vth of the functional layer 6, the functional layer 6 switches from the high resistance state to the low resistance state. When the voltage across the functional layer 6 in the low resistance state is lower than the holding voltage Vhold of the functional layer 6, the functional layer 6 switches from the low resistance state to the high resistance state. The total holding voltage VHold of the functional layer 6 and the second metal electrode layer 5 is VHold = Vhold + Vhold * R / R_low, where R_low is the resistance value of the functional layer 6 in the low resistance state, and R is the resistance of the second metal electrode layer 5, and the value range is 0 ≤ R ≤ Rmax, where Rmax is the value of R when VHold is equal to Vth. By adjusting the resistance value of the second metal electrode layer 5, the total holding voltage VHold of the gating device can be adjusted. By selecting a second metal electrode layer 5 material with a suitable large resistance value, the 1S1C operation window can be increased. When operating the storage unit, the resistance value of the third metal electrode layer 4 is lower than that of the second metal electrode layer 5, and the electrical signal is transmitted to the target storage unit position through the third metal electrode layer 4 first, and then the storage device is operated. The existence of the second metal electrode layer 5 can increase the operation window of the 1S1C memory.

[0049] If the second metal electrode layer 5 is cancelled, the 1S1C operation window can also be increased by increasing the resistance of the third metal electrode layer 4. However, the third metal electrode layer 4 is not only an electrode of the storage device, but also serves as a connection between the lower storage device and the top bit line when the number of stacked layers of the storage unit is high. A large resistance of the third metal electrode layer 4 will greatly reduce the transmission speed of the read and write signals in the three-dimensional memory array, which is unacceptable for the 1S1C memory in the target DRAM scenario.

[0050] If the second metal electrode layer 5 is deposited first, then the functional layer 6 is deposited, and then the third metal electrode layer 4 is deposited, the resistance of the second metal electrode layer 5 is only higher than that of the third metal electrode layer 4, which is 10 2Although the resistance is on the order of Ω, it is still insufficient to separate two adjacent cells in the vertical direction. This is equivalent to the same string of memory cells in the vertical direction sharing a single gating device, thus losing the high-density advantage of 3D 1S1C memory.

[0051] If the second metal electrode layer 5 is placed in the annular groove, the same problem will exist where the same string of memory cells in the vertical direction shares a single gate device. Therefore, depositing the functional layer 6, the second metal electrode layer 5, and the third metal electrode layer 4 sequentially in the hole is the only feasible solution.

[0052] The advantage of this embodiment is that:

[0053] (1) The second metal electrode layer 5 was set up, which improved the data operation window of the 3D 1S1C memory and reduced the bit error rate of the three-dimensional memory.

[0054] (2) In the 3D 1S1C memory, a portion of the first metal electrode layer 2 is replaced by a capacitor electrode layer (including the first capacitor electrode layer 8 and the second capacitor electrode layer 9), which optimizes the electrode fabrication process of the capacitor and reduces the leakage current of the three-dimensional memory.

[0055] Example 2

[0056] This embodiment provides a method for fabricating a three-dimensional dynamic memory, such as... Figure 2 As shown, this method involves first fabricating the capacitor, and then fabricating the gating device based on that. The method includes the following steps.

[0057] (a1) A first metal electrode layer 2 and a dielectric layer 3 are alternately stacked and grown on a substrate 1 to form a substrate; in the staggered stacked structure, the top layer is the dielectric layer 3 and the bottom layer is the first metal electrode layer 2; the bottom layer of the first metal electrode layer 2 is disposed on the upper surface of the substrate 1.

[0058] (a2) At least one annular groove is formed on the substrate; each annular groove extends from the upper surface of the top dielectric layer 3 toward the substrate 1 and into the interior of the substrate 1.

[0059] (a3) For each of the annular grooves, a capacitor dielectric layer 7 is uniformly deposited in the annular groove to fill the annular groove.

[0060] Steps (a1) to (a3) ​​constitute the capacitor fabrication process, and are... Figure 2 and Figure 3 The preparation process shown in (a), (b) and (e) is as follows.

[0061] (a4) After filling the capacitor dielectric layer 7, a hole is formed at the center of each capacitor dielectric layer 7; each hole extends from the upper surface of the top dielectric layer 3 toward the substrate 1 and into the interior of the substrate 1.

[0062] (a5) For each of the holes, a functional layer 6 and a second metal electrode layer 5 are deposited uniformly on the inner wall of the hole in sequence.

[0063] (a6) After depositing the second metal electrode layer 5, the remaining space in the hole is filled with a third metal electrode layer 4; the third metal electrode layer 4 extends from the region of the hole to a predetermined region on the upper surface of the top dielectric layer 3. Steps (a4) to (a6) constitute the fabrication process of the gating device, corresponding to... Figure 2 The (f) to (i) parts in the text.

[0064] As an optional implementation method, such as Figure 3 As shown, before performing step (a3) ​​"uniformly depositing the capacitor dielectric layer 7 within the annular groove", the fabrication method of the three-dimensional dynamic memory further includes:

[0065] (1) Remove a portion of each of the first metal electrode layers 2 on both sides of the annular groove inwards. This step corresponds to... Figure 3 The preparation process of (c) in the text.

[0066] (2) Fill the location where the first metal electrode layer 2 has been removed with a capacitor electrode layer to keep the inner wall of the annular groove smooth. This step corresponds to... Figure 3 The preparation process of (d) in the text.

[0067] The following describes the fabrication method of the three-dimensional dynamic memory after introducing specific materials into each layer. The process involves first fabricating the capacitors, followed by the fabrication of the gating devices. The specific fabrication process flow is as follows:

[0068] like Figure 2 In part (a), a three-layer stack of 50nm W (tungsten) and 100nm SiO2 (silicon dioxide) is first prepared on substrate 1, with the top layer being SiO2. That is, the dielectric layer 3 uses SiO2, and the first metal electrode layer 2 uses W.

[0069] like Figure 2 In part (b), an annular pattern is formed on the stack by photolithography, and ICP etching with good anisotropy is used. The etching gas is SF6+C4F8 (sulfur hexafluoride + octafluorocyclobutane) to etch the stack, and the resulting annular groove has a ring width of 50nm.

[0070] like Figure 2Part (c) in the above, using HF (hydrofluoric acid) and HNO3 (nitric acid) mixture to selectively remove 20 nm exposed W.

[0071] As Figure 2 Part (d) in the above, through ALD process, using the precursor with selective growth ability for W and SiO2, to grow a layer of TiN (tin) electrode on the surface of W, with thickness of 20 nm, to keep the side wall of the ring-shaped groove smooth. That is, the first capacitor electrode layer 8 and the second capacitor electrode layer 9 are made of TiN.

[0072] As Figure 2 Part (e) in the above, through ALD process, to grow a layer of 10 nm thick Al2O3 (aluminum oxide) on the side wall of the ring-shaped groove; and then to grow a layer of 15 nm thick ZrO2 (zirconium dioxide) on the side wall of the ring-shaped groove; to fill the ring-shaped groove.

[0073] As Figure 2 Part (f) in the above, to form a circular pattern above the stack through photolithography in the center of the ring-shaped groove; to use ICP etching with good anisotropic etching, and to select SF6+C4F8 as the etching gas, to etch the stack, to obtain a circular hole with diameter of 100 nm.

[0074] As Figure 2 Part (g) in the above, to uniformly deposit a layer of 30 nm GeTE9 material on the side wall of the hole, and the chemical formula of the material is Ge:Te=1:9.

[0075] As Figure 2 Part (h) in the above, to continue to uniformly deposit a layer of TiN on the side wall of the hole, and the resistivity of the TiN is 3*10 -4 Ω·m.

[0076] As Figure 2 Part (i) in the above, to continue to uniformly deposit a layer of W on the side wall of the hole, and the resistivity of the W is 10 -6 Ω·m.

[0077] Thus, the preparation of the three-dimensional dynamic memory is completed.

[0078] Among them, when using TiN as the capacitor electrode material, compared with the traditional use of W as the electrode material, the leakage current of the capacitor is reduced from 2*10 -6 A / cm 2 to 6*10 -8 A / cm 2 , which greatly reduces the leakage current of the capacitor and improves the data retention time of the three-dimensional memory device.

[0079] By adding a high-resistance TiN layer between the functional layer 6 and the third metal electrode layer 4, the holding voltage of the gating device is increased from 0.5V to 1V, and the operating window of the corresponding memory is also increased by 0.5V.

[0080] Embodiment 3

[0081] The embodiment provides a preparation method of a three-dimensional dynamic memory. The method comprises the following steps of:

[0082] (b1) alternately stacking and growing the first metal electrode layer 2 and the dielectric layer 3 on the substrate 1 to form a substrate; in the alternately stacked structure, the top layer is the dielectric layer 3, and the bottom layer is the first metal electrode layer 2; the bottom layer of the first metal electrode layer 2 is arranged on the upper surface of the substrate 1.

[0083] (b2) forming at least one hole in the substrate.

[0084] (b3) sequentially and uniformly depositing the functional layer 6 and the second metal electrode layer 5 on the inner wall of each hole.

[0085] (b4) after the second metal electrode layer 5 is deposited, filling the third metal electrode layer 4 in the remaining space of the hole; the third metal electrode layer 4 extends from the area of the hole to a preset area on the upper surface of the top layer of the dielectric layer 3.

[0086] The steps (b1) to (b4) are the preparation process of the gating device, which corresponds to the parts (a) to (d) in the embodiment. Figure 4

[0087] (b5) after the third metal electrode layer 4 is filled, forming a ring-shaped groove in the substrate with each third metal electrode layer 4 as the center; the ring-shaped groove penetrates and extends to the inside of the substrate 1 from the upper surface of the top layer of the dielectric layer 3 to the direction of the substrate 1.

[0088] (b6) for each ring-shaped groove, uniformly depositing the capacitor dielectric layer 7 in the ring-shaped groove to fill the ring-shaped groove.

[0089] As an optional implementation, as shown in the embodiment, before the step (b6) “uniformly depositing the capacitor dielectric layer 7 in the ring-shaped groove” is performed, the preparation method of the three-dimensional dynamic memory further comprises the following steps of: Figure 3

[0090] (1) removing a part of each first metal electrode layer 2 on both sides of the ring-shaped groove. The step corresponds to the preparation process of (c) in the embodiment. Figure 3

[0091] ​​​(2) fill the capacitor electrode layer in the position where the first metal electrode layer 2 is removed to keep the inner wall of the annular groove smooth. This step corresponds to the preparation process of (d) in Figure 3

[0092] The technical features of the above embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present disclosure.

[0093] The principles and implementation manners of the present application are described herein by using specific examples, and the above embodiments are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In conclusion, the content of the present disclosure should not be understood as a limitation of the present application.​

Claims

1. A three-dimensional dynamic memory, characterized in that, The three-dimensional dynamic memory includes: a substrate, several first metal electrode layers, at least one second metal electrode layer, at least one third metal electrode layer, several dielectric layers, at least one functional layer, and at least one capacitor dielectric layer; The plurality of first metal electrode layers and the plurality of dielectric layers are arranged in an alternating stacked manner; in the alternating stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate. Each of the third metal electrode layers is a T-shaped structure; the vertical segment of each of the third metal electrode layers extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate; the horizontal segment of each of the third metal electrode layers is disposed on the upper surface of the top dielectric layer. The outer surface of the vertical segment of each of the third metal electrode layers is covered with the second metal electrode layer; the outer surface of each of the second metal electrode layers is covered with the functional layer; The number of capacitor dielectric layers and the number of third metal electrode layers are the same, and they correspond one-to-one; Each of the capacitor dielectric layers is a hollow columnar structure centered on the corresponding third metal electrode layer; each of the capacitor dielectric layers extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate.

2. The three-dimensional dynamic memory according to claim 1, characterized in that, The three-dimensional dynamic memory further includes: a first capacitor electrode layer and a second capacitor electrode layer; The first capacitor electrode layer is evenly distributed between the inner wall of each hollow columnar capacitor dielectric layer and each first metal electrode layer. The outer wall of each hollow columnar capacitor dielectric layer is provided with a second capacitor electrode layer between each first metal electrode layer.

3. The three-dimensional dynamic memory according to claim 2, characterized in that, The width of the first capacitor electrode layer and the width of the second capacitor electrode layer are the same as the width of the corresponding first metal electrode layer.

4. The three-dimensional dynamic memory according to claim 2, characterized in that, The first capacitor electrode layer and the second capacitor electrode layer are made of materials that limit leakage current in the capacitor dielectric layer.

5. The three-dimensional dynamic memory according to claim 1, characterized in that, The resistance of the second metal electrode layer is higher than that of the corresponding third metal electrode layer.

6. The three-dimensional dynamic memory according to claim 1, characterized in that, The bottom of the functional layer, the bottom of the second metal electrode layer, and the bottom of the third metal electrode layer are all located within the region of the substrate.

7. The three-dimensional dynamic memory according to claim 1, characterized in that, The first metal electrode layer and the dielectric layer have the same number of layers, and the number of layers is the same as the number of storage cell layers required by the three-dimensional dynamic memory.

8. A method for fabricating a three-dimensional dynamic memory, characterized in that, The method for fabricating the three-dimensional dynamic memory includes: A first metal electrode layer and a dielectric layer are alternately stacked and grown on a substrate to form a substrate; in the staggered stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate; At least one annular groove is formed on the substrate; each annular groove extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate; For each of the aforementioned annular grooves, a capacitor dielectric layer is uniformly deposited within the annular groove; After filling the capacitor dielectric layer, a hole is formed at the center of each capacitor dielectric layer; each hole extends from the upper surface of the top dielectric layer toward the substrate and into the interior of the substrate. For each of the aforementioned holes, a functional layer and a second metal electrode layer are sequentially and uniformly deposited on the inner wall of the hole; After depositing the second metal electrode layer, the remaining space in the hole is filled with a third metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a predetermined area on the upper surface of the top dielectric layer.

9. A method for fabricating a three-dimensional dynamic memory, characterized in that, The method for fabricating the three-dimensional dynamic memory includes: A first metal electrode layer and a dielectric layer are alternately stacked and grown on a substrate to form a substrate; in the staggered stacked structure, the top layer is the dielectric layer and the bottom layer is the first metal electrode layer; the bottom first metal electrode layer is disposed on the upper surface of the substrate; Form at least one hole on the substrate; A functional layer and a second metal electrode layer are uniformly deposited sequentially on the inner wall of each of the holes. After depositing the second metal electrode layer, the remaining space in the hole is filled with a third metal electrode layer; the third metal electrode layer extends from the area of ​​the hole to a predetermined area on the upper surface of the top dielectric layer; After filling the third metal electrode layer, an annular groove is formed on the substrate with each third metal electrode layer as the center; the annular groove penetrates from the upper surface of the top dielectric layer and extends into the interior of the substrate in the direction of the substrate; For each of the aforementioned annular grooves, a capacitor dielectric layer is uniformly deposited within the annular groove.

10. The method for fabricating a three-dimensional dynamic memory according to claim 8 or 9, characterized in that, Before performing the step of "uniformly depositing a capacitor dielectric layer within the annular groove", the method for fabricating the three-dimensional dynamic memory further includes: Remove a portion of each of the first metal electrode layers on both sides of the annular groove inwards; Fill the area where the first metal electrode layer was removed with a capacitor electrode layer to keep the inner wall of the annular groove smooth.

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