A semiconductor device, a manufacturing method thereof, and a memory system

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same, as well as a memory system. The manufacturing method includes: providing a semiconductor structure, including a semiconductor layer, an initial stacked structure on the semiconductor layer, an initial gate isolation structure, and an initial contact structure; wherein the initial stacked structure includes alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate isolation structure includes a gate trench and a first sacrificial layer located within the gate trench; the initial contact structure includes a contact hole, an isolation pillar located within the contact hole, and a second sacrificial layer located within the contact hole, the initial contact structure extending along the stacking direction and connected to a target gate sacrificial layer; removing the first sacrificial layer within the gate trench and the second sacrificial layer within the contact hole; removing a portion of the gate sacrificial layer through the gate trench to form a first gap; the first gap and the corresponding contact hole being connected; and forming a conductive structure within the first gap and the contact hole.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its manufacturing method, and a memory system. Background Technology

[0002] As the number of stacked layers in 3D memory continues to increase, the etching depth of contact holes (CTs) extending to different gate layers becomes increasingly greater, placing higher demands on the etching processes for contact holes and etch stop layers. To reduce process complexity, a staircase contact (SCT) architecture has been proposed in related technical solutions, combining the stair step (SS) process and the contact hole process into one, greatly simplifying the process flow. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, as well as a memory system.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising:

[0006] A semiconductor structure is provided, including a semiconductor layer, an initial stacked structure on the semiconductor layer, an initial gate isolation structure, and an initial contact structure; wherein the initial stacked structure includes alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate isolation structure includes a gate trench and a first sacrificial layer located within the gate trench; the initial contact structure includes a contact hole, an isolation pillar located within the contact hole, and a second sacrificial layer located within the contact hole, and the initial contact structure extends along the stacking direction and is connected to a target gate sacrificial layer;

[0007] Remove the first sacrificial layer in the grid groove and the second sacrificial layer in the contact hole;

[0008] A portion of the gate sacrificial layer is removed through the gate line slot to form a first gap; the first gap is connected to the corresponding contact hole;

[0009] A conductive structure is formed within the first gap and the contact hole.

[0010] In some embodiments, the contact hole includes a first portion and a second portion that are connected to each other, the first portion extending along the stacking direction and penetrating the target gate sacrificial layer, the second portion extending along a direction parallel to the semiconductor layer and exposing the sidewalls of the target gate sacrificial layer, the second portion surrounding the first portion; wherein the isolation pillar extends along the stacking direction and is located within the first portion.

[0011] In some embodiments, the provision of the semiconductor structure includes:

[0012] An initial stacked structure is formed on the semiconductor layer;

[0013] Forming gate line trenches that penetrate the initial stacked structure and extend to the semiconductor layer;

[0014] A first sacrificial layer is formed within the gate wire slot; wherein the gate wire slot and the first sacrificial layer together form the initial gate wire isolation structure.

[0015] In some embodiments, after forming the first sacrificial layer within the gate wire slot, the manufacturing method further includes:

[0016] Forming contact holes that extend along the stacking direction to the target gate sacrificial layer;

[0017] A second sacrificial layer is formed inside the contact hole, the second sacrificial layer covering the sidewalls and bottom of the first part of the contact hole and filling the second part of the contact hole;

[0018] Remove the second sacrificial layer covering the bottom of the first portion of the contact hole;

[0019] An isolation pillar is formed within the first portion of the contact hole; wherein the contact hole, the isolation pillar, and the second sacrificial layer together form the initial contact structure.

[0020] In some embodiments, the provision of the semiconductor structure includes:

[0021] An initial stacked structure is formed on the semiconductor layer;

[0022] Forming contact holes that extend along the stacking direction to the target gate sacrificial layer;

[0023] A second sacrificial layer is formed inside the contact hole, the second sacrificial layer covering the sidewalls and bottom of the first part of the contact hole and filling the second part of the contact hole;

[0024] Remove the second sacrificial layer covering the bottom of the first portion of the contact hole;

[0025] An isolation pillar is formed within the first portion of the contact hole; wherein the contact hole, the isolation pillar, and the second sacrificial layer together form the initial contact structure.

[0026] In some embodiments, after forming the isolation post within the first portion of the contact hole, the manufacturing method further includes:

[0027] Forming gate line trenches that penetrate the initial stacked structure and extend to the semiconductor layer;

[0028] A first sacrificial layer is formed within the gate wire slot; wherein the gate wire slot and the first sacrificial layer together form the initial gate wire isolation structure.

[0029] In some embodiments, the initial contact structure further includes an oxide layer covering a first portion of the sidewall of the contact hole;

[0030] Before removing the first sacrificial layer in the grid slot and the second sacrificial layer in the contact hole, the manufacturing method further includes:

[0031] The initial contact structure is etched along the stacking direction to form at least one groove; wherein the dimension of the groove along the direction parallel to the semiconductor layer is greater than or equal to the distance between the isolation pillar and the oxide layer along the direction parallel to the semiconductor layer;

[0032] The groove is filled with insulating material to form a support structure.

[0033] In some embodiments, the semiconductor structure includes a core region and a connection region; the gate line spacers include a portion of the gate line spacers located in the core region and a portion of the gate line spacers located in the connection region;

[0034] Before removing the first sacrificial layer in the grid slot and the second sacrificial layer in the contact hole, the manufacturing method further includes:

[0035] A protective layer is formed, which covers the surface of the initial stacked structure of the core region and the connecting region;

[0036] Remove the protective layer covering the surface of the initial stacked structure of the core region;

[0037] Remove the first sacrificial layer located within a portion of the gate wire slots in the core region;

[0038] The gate sacrificial layer in the core region is removed by partially removing gate line slots in the core region to form a second gap;

[0039] Remove the protective layer from the surface of the initial stacked structure covering the connection area.

[0040] In some embodiments, removing the first sacrificial layer within the gate slot and the second sacrificial layer within the contact hole includes:

[0041] Remove the first sacrificial layer located in a portion of the grid line slot in the connection area and the second sacrificial layer located in the contact hole;

[0042] The step of removing a portion of the gate sacrificial layer through the gate line slot to form a first gap includes:

[0043] A portion of the gate sacrificial layer in the connection region is removed by a partial gate line slot in the connection region to form a first gap; wherein the first gap and the second gap are connected.

[0044] In some embodiments, forming a conductive structure within the first gap and the contact hole includes:

[0045] A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line slots and the contact hole; wherein, the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap together form a gate layer, and the gate layer and the interlayer insulating layer together form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole together form a connection layer, and the connection layer simultaneously fills the first part and the second part of the contact hole to form a contact structure.

[0046] In some embodiments, forming a conductive structure within the first gap and the contact hole includes:

[0047] A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line slots and the contact hole; wherein, the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap together form a gate layer, and the gate layer and the interlayer insulating layer together form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole together constitute a connection layer, the connection layer filling the second part of the contact hole and not filling the first part of the contact hole.

[0048] In some embodiments, after the dielectric layer, the first conductive layer, and the second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate wire slot and the contact hole, the manufacturing method further includes:

[0049] A first filling layer is formed, which fills the gap between the first portion of the sidewall of the contact hole and the isolation post to form a contact structure.

[0050] In some embodiments, the first filling layer is formed using an atomic layer deposition process.

[0051] In some embodiments, after forming the conductive structure within the first gap and the contact hole, the manufacturing method further includes:

[0052] Remove the second conductive layer and the first conductive layer within the grid slot.

[0053] In some embodiments, after removing the second conductive layer and the first conductive layer within the gate wire slot, the manufacturing method further includes:

[0054] An isolation layer is formed, which covers the sidewalls and bottom of the grid slot;

[0055] A second filling layer is formed; wherein the grid line slot, the isolation layer and the second filling layer together form a grid line isolation structure.

[0056] In some embodiments, the semiconductor structure further includes a channel structure located in the core region and a dummy channel structure located in the connection region;

[0057] After forming the second filling layer, the manufacturing method further includes:

[0058] A dielectric layer is formed covering the channel structure, the dummy channel structure, and the contact structure;

[0059] The dielectric layer is etched to form a first through-hole, a second through-hole, and a third through-hole that are respectively connected to the conductive structure in the channel structure, the dummy channel structure, and the contact structure.

[0060] Conductive material is filled into the first through hole, the second through hole, and the third through hole to form a first lead-out structure, a second lead-out structure, and a third lead-out structure, respectively.

[0061] In a second aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising:

[0062] A stacked structure, the stacked structure including a core region and a connection region; the stacked structure including alternately stacked gate layers and interlayer insulating layers;

[0063] A contact structure extending along the stacking direction into the target gate layer within the stacked structure; the contact structure includes an isolation pillar extending along the stacking direction and a conductive structure located between the contact hole sidewall and the isolation pillar; the contact structure is located in the connection region.

[0064] In some embodiments, the contact structure includes a first portion and a second portion connected to each other, the first portion extending along the stacking direction to a target gate layer, the second portion extending perpendicular to the stacking direction and connected to the target gate layer, the second portion surrounding the first portion; wherein the first portion includes an isolation pillar and a conductive structure located between the sidewall of the first portion and the isolation pillar, and the second portion includes a conductive structure.

[0065] In some embodiments, the semiconductor device further includes:

[0066] The channel structure located in the core area and the virtual channel structure located in the connecting area;

[0067] A dielectric layer covering the stacked structure located in the core region and the connection region;

[0068] A first lead-out structure, a second lead-out structure, and a third lead-out structure located within the dielectric layer and respectively connected to the conductive structure within the channel structure, the dummy channel structure, and the contact structure.

[0069] In some embodiments, the conductive structure of the second portion of the contact structure includes a dielectric layer, a first conductive layer, and a second conductive layer; wherein the dielectric layer, the first conductive layer, and the second conductive layer together form a connection layer;

[0070] The conductive structure of the first part of the contact structure includes the connecting layer.

[0071] In some embodiments, the third lead-out structure is connected to a connection layer.

[0072] In some embodiments, the conductive structure of the second portion of the contact structure includes a dielectric layer, a first conductive layer, and a second conductive layer; wherein the dielectric layer, the first conductive layer, and the second conductive layer together form a connection layer;

[0073] The conductive structure of the first part of the contact structure includes, in a radially outward direction, the connecting layer, the first filling layer, and the connecting layer.

[0074] In some embodiments, the third lead-out structure is connected to the two connection layers.

[0075] In some embodiments, the contact structure further includes an oxide layer located on the sidewall of the first portion; the semiconductor device further includes:

[0076] At least one support structure is embedded in the contact structure along the stacking direction, the dimension of the support structure perpendicular to the stacking direction being greater than or equal to the distance between the isolation pillar and the oxide layer perpendicular to the stacking direction.

[0077] In some embodiments, the semiconductor device further includes:

[0078] A gate line isolation structure that runs through the stacked structure along the stacking direction.

[0079] Thirdly, embodiments of this disclosure provide a memory system, including:

[0080] Semiconductor devices as described in the above technical solutions;

[0081] and a controller coupled to the semiconductor device, the controller being configured to control the semiconductor device.

[0082] This disclosure provides a semiconductor device and its manufacturing method, as well as a memory system. In this embodiment, contact holes are formed before the gate replacement process. This mitigates the damage to the gate layer during contact hole formation, which can affect structural stability and breakdown voltage, when the gate replacement process is performed first and then the contact holes are formed. Furthermore, isolation pillars are provided within the contact holes. Thus, when filling the contact holes with sacrificial material, only the remaining space excluding the isolation pillars needs to be filled, saving sacrificial material and consequently reducing manufacturing costs. Attached Figure Description

[0083] Figure 1A A schematic cross-sectional view of a memory provided as an example;

[0084] Figure 1B A three-dimensional structural diagram of a contact hole is provided as an example;

[0085] Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0086] Figure 3A A top view of a semiconductor device provided in an embodiment of this disclosure;

[0087] Figure 3B A top view of another semiconductor device provided in an embodiment of this disclosure;

[0088] Figures 4A to 4X A cross-sectional structural diagram of a semiconductor device during the manufacturing process, provided as an embodiment of this disclosure;

[0089] Figures 5A to 5J A cross-sectional structural diagram of another semiconductor device during the manufacturing process provided in this disclosure embodiment;

[0090] Figure 6A A top view of the support structure in a semiconductor device provided in this embodiment of the disclosure;

[0091] Figure 6B A top view of the support structure in the semiconductor device provided in this embodiment of the disclosure. Figure 2 ;

[0092] Figure 6C A top view of the support structure in a semiconductor device provided in this embodiment of the disclosure is shown in Figure 3.

[0093] Figure 7 A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0094] Figure 8 A cross-sectional structural schematic diagram of another semiconductor device provided in an embodiment of this disclosure;

[0095] Figure 9 A block diagram of a system having semiconductor devices provided for embodiments of this disclosure. Detailed Implementation

[0096] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0097] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0098] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0099] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0100] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0101] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0102] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0103] refer to Figure 1A , Figure 1A This is a schematic cross-sectional view of a memory provided as an example. Figure 1A As shown, the memory may include a composite substrate 100 and a stacked structure 101 located on the composite substrate 100, the stacked structure 101 including alternately stacked gate layers 102 and interlayer insulating layers 103. The memory may include an array region, wherein the array region includes a core region ( Figure 1A (Not shown in the diagram) and connection region 104. As an example, the core region may include multiple channel holes (CH) for storing data. Connection region 104 may include contact holes 105, which, when filled, form a contact structure that extends along the stacking direction to the target gate layer and serves to achieve electrical connection between the contact structure and the target gate layer. Connection region 104 may also include dummy channel holes (DCH) 106 for supporting purposes. The array region may include gate line slots that extend from the core region to the connection region. The gate line slots serve, but are not limited to, providing etchant pathways for replacing the gate sacrificial layer in the stacked structure 101 with the gate layer. After replacing the gate sacrificial layer in the core region and a portion of the gate sacrificial layer in the connection region 104 with the gate layer 102 through the gate line slots, the gate line slots can be filled to form a gate line isolation structure 107.

[0104] refer to Figure 1B , Figure 1B This is a 3D structural diagram of a contact hole provided as an example. Figure 1B As shown, it should be noted that each contact hole 105 has its corresponding target gate sacrificial layer. After the gate replacement process is performed, each contact structure has its corresponding target gate layer. Each contact structure can be connected to the target gate layer in a direction parallel to the composite substrate 100, but not to other gate layers other than the target gate layer. In this way, after applying voltage, an electrical connection is achieved between the contact structure and the target gate layer, but there is no electrical connection between the contact structure and other gate layers other than the target gate layer.

[0105] Still Figure 1AAs shown, in some embodiments, during the memory manufacturing process, after a gate replacement process is performed using gate line slots to fill the slots and form a gate isolation structure 107, contact holes 105 are etched to form, wherein the contact holes 105 are formed in the connection region 104. Since a gate replacement process has already been performed, the etching process of the stacked structure to form contact holes may damage the gate layer 102 and the interlayer insulating layer 103, thereby affecting the stability of the structure and the breakdown voltage. More specifically, the gate layer may include a dielectric layer 108, a titanium nitride layer 109, and a tungsten layer 110. The dielectric layer 108 may include a high dielectric constant material, such as aluminum oxide. The etching process to form contact holes may damage the dielectric layer 108.

[0106] Furthermore, in the memory manufacturing process, gate replacement is performed using gate line slots to form word lines (e.g., dielectric layer, titanium nitride layer, and tungsten layer); contact holes are then etched and filled, for example, by forming titanium nitride and tungsten layers, to achieve electrical connection between the contact structure and the target gate layer. This requires two complete processes to form the titanium nitride and tungsten layers, making the process complex and costly.

[0107] refer to Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 2 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising:

[0108] Step S201: Provide a semiconductor structure, including a semiconductor layer, an initial stacked structure on the semiconductor layer, an initial gate isolation structure, and an initial contact structure; wherein, the initial stacked structure includes alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate isolation structure includes gate trenches and a first sacrificial layer located within the gate trenches; the initial contact structure includes contact holes, isolation pillars located within the contact holes, and a second sacrificial layer located within the contact holes, and the initial contact structure extends along the stacking direction and is connected to the target gate sacrificial layer;

[0109] Step S202: Remove the first sacrificial layer in the grid slot and the second sacrificial layer in the contact hole;

[0110] Step S203: Remove part of the gate sacrificial layer through a gate line trench to form a first gap; the first gap is connected to the corresponding contact hole;

[0111] Step S204: Form a conductive structure within the first gap and the contact hole.

[0112] In this embodiment, the first sacrificial layer in the gate wire slot and the second sacrificial layer in the contact hole are removed simultaneously, and part of the gate sacrificial layer is removed through the gate wire slot to form a first gap; the first gap and the contact hole are connected to form an "L-shaped" path in the cross-sectional structural diagram; then, the conductive structure (e.g., dielectric layer, first conductive layer and second conductive layer) is filled in one step to achieve electrical connection between the contact structure and the target gate layer.

[0113] The following will combine Figure 3A as well as Figures 4A to 4X The manufacturing method of the semiconductor device provided in the embodiments of this disclosure will be described in detail. Figure 3A This is a top view of a semiconductor device provided in an embodiment of this disclosure. Figures 4A to 4X This is a cross-sectional structural diagram of a semiconductor device during the manufacturing process, provided as an embodiment of this disclosure. Figures 4A to 4X The schematic cross-sectional structure of the connection region of the semiconductor device can be regarded as Figure 3A A schematic diagram of the cross-sectional structure along the AA direction.

[0114] like Figure 3A As shown, the semiconductor device includes an array region 200, which includes a core region 201 and a connection region 202. The core region 201 of the semiconductor device may include a channel structure 203. The connection region 202 of the semiconductor device may include a dummy channel structure 204 and a contact structure 241. The array region 200 of the semiconductor device may include a gate line isolation structure 244, which may extend from the core region 201 to the connection region 202.

[0115] It should be noted that, Figure 3A A schematic top view of the channel structure 203 and the dummy channel structure 204, and Figures 4A to 4X The schematic cross-sectional view of the dummy channel structure 204 is shown in the figures. These figures only illustrate one optional structure of the channel structure 203 and the dummy channel structure 204. The specific structure of the channel structure 203 and the dummy channel structure 204 is not specifically limited in the embodiments of this disclosure.

[0116] Here, the stacking direction of the semiconductor device's multilayer structure is defined as the Z-direction, and the intersecting X and Y directions are defined on the surface perpendicular to the Z-direction. For example, the X and Y directions can be perpendicular to each other. Thus, the X, Y, and Z directions are mutually perpendicular. Here, the direction parallel to the semiconductor layer can be any direction in the XY plane, such as the X and Y directions. Figure 3A The grid isolation structure 244 is shown to be parallel to the Y direction.

[0117] For ease of explanation, Figure 3AThe diagram shows that the orthographic projections of the channel structure 203, the dummy channel structure 204, and the contact structure 241 in the XY plane are all circular. In reality, the orthographic projections of the channel structure 203, the dummy channel structure 204, and the contact structure 241 in the XY plane can be other shapes. This embodiment of the present disclosure does not impose any special limitation on the shape of the orthographic projections of the channel structure 203, the dummy channel structure 204, and the contact structure 241 in the XY plane.

[0118] For ease of illustration, Figure 3A The schematic diagrams of the channel structure 203, the dummy channel structure 204, the grid line isolation structure 244, and the contact structure 241 are not filled with graphics. In fact, the channel structure 203, the dummy channel structure 204, the grid line isolation structure 244, and the contact structure 241 are all formed by filling multiple material layers. The following will be explained in conjunction with the cross-sectional structural schematic diagrams of the grid line isolation structure 244 and the contact structure 241.

[0119] In this embodiment of the present disclosure, in step S201, a semiconductor structure is provided, including a semiconductor layer, an initial stacked structure on the semiconductor layer, an initial gate isolation structure, and an initial contact structure; wherein, the initial stacked structure includes alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate isolation structure includes gate trenches and a first sacrificial layer located within the gate trenches; the initial contact structure includes contact holes, isolation pillars located within the contact holes, and a second sacrificial layer located within the contact holes, and the initial contact structure extends along the stacking direction and is connected to the target gate sacrificial layer.

[0120] In this embodiment of the disclosure, there is no particular limitation on the process order of forming the initial gate line isolation structure 206 and the initial contact structure 205. In some embodiments, the initial contact structure 205 may be formed first, followed by the initial gate line isolation structure 206. The following will describe the process order in conjunction with... Figures 4A to 4M The process of forming the initial contact structure 205 first and then forming the initial gate line isolation structure 206 is described in detail.

[0121] In this embodiment of the disclosure, step S201 includes:

[0122] An initial stacked structure is formed on the semiconductor layer;

[0123] Form contact holes that extend along the stacking direction to the target gate sacrificial layer;

[0124] A second sacrificial layer is formed inside the contact hole, which covers the sidewalls and bottom of the first part of the contact hole and fills the second part of the contact hole.

[0125] Remove the second sacrificial layer from the bottom of the first portion covering the contact hole;

[0126] An isolation pillar is formed within the first part of the contact hole; wherein, the contact hole, the isolation pillar, and the second sacrificial layer together form the initial contact structure.

[0127] Such as 3A and Figure 4A As shown, an initial stacked structure 208 is formed on the semiconductor layer 207. The initial stacked structure 208 includes alternately stacked gate sacrificial layers 209 and interlayer insulating layers 210. The initial stacked structure 208 includes an array region 200, which includes a core region 201 and a connection region 202. A channel structure 203 and a dummy channel structure 204 can also be formed along the Z direction, penetrating the initial stacked structure 208 and extending to the semiconductor layer 207. The channel structure 203 is located in the core region 201, and the dummy channel structure 204 is located in the connection region 202.

[0128] Figure 4A Only the connection region 202 of the semiconductor device and the dummy channel structure 204 located in the connection region 202 are shown. Figure 4A The core region of the semiconductor device and the channel structure located in the core region are not shown. Figure 4A Only two dummy channel structures 204 located in the connection region 202 are shown. In fact, the number of dummy channel structures 204 in the connection region 202 of the semiconductor device provided in this embodiment is not limited to this.

[0129] In some embodiments, the semiconductor layer 207 may be a composite semiconductor layer. For example, the semiconductor layer 207 may sequentially include a substrate 211, a first silicon oxide layer 212, a stop layer 213, a second silicon oxide layer 214, and a polysilicon layer 215. In a specific example, the material of the stop layer 213 may also include silicon oxide.

[0130] In some embodiments, the substrate 211 may be a single-element semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate; or the substrate 211 may also be a composite semiconductor material substrate, such as a silicon-germanium (SiGe) substrate; or the substrate may also be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0131] In some embodiments, the formation of the gate sacrificial layer 209 and the interlayer insulating layer 210 on the semiconductor layer 207 can be achieved by one or more deposition processes. These deposition processes may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof.

[0132] It is understood that the number and thickness of the gate sacrificial layer 209 and the interlayer insulating layer 210 are not limited to... Figure 4A The quantity and thickness are shown. Those skilled in the art can set any number and thickness of gate sacrificial layer 209 and interlayer insulating layer 210 according to actual needs. Furthermore, the materials of gate sacrificial layer 209 and interlayer insulating layer 210 can be selected from suitable materials known in the art. Here, interlayer insulating layer 210 can be an oxide layer, for example, a silicon oxide layer; gate sacrificial layer 209 can be a nitride layer, for example, a silicon nitride layer.

[0133] In some embodiments, the channel structure 203 and the dummy channel structure 204 are formed simultaneously in the initial stacked structure 208 and have the same structure. The difference between the channel structure 203 and the dummy channel structure 204 is that the channel structure 203 can be used to store data, while the dummy channel structure 204 does not have the function of storing data and is only used to support the stability and reliability of the semiconductor device structure. The following will use... Figure 4A The illustrated dummy channel structure 204 is used as an example for explanation. The dummy channel structure 204 can be cylindrical, elliptical cylindrical, frustum-shaped, or cuboid in shape. The dummy channel structure 204, arranged radially inward, includes a barrier layer, a charge trapping layer, a tunneling layer, a channel layer, and a channel oxide layer. In a specific example, the materials of the barrier layer, charge trapping layer, tunneling layer, channel layer, and channel oxide layer can be silicon oxide, silicon nitride, silicon oxide, polycrystalline silicon, and silicon oxide, respectively.

[0134] like Figure 4B As shown, the initial stacked structure 208 is etched along the Z direction to form the first sub-contact hole 216, and the bottom of the first sub-contact hole 216 exposes part of the interlayer insulating layer 210 above the target gate sacrificial layer 217.

[0135] Here, the portion of the interlayer insulating layer 210 exposed above the target gate sacrificial layer 217 at the bottom of the first sub-contact hole 216 refers to the portion of the interlayer insulating layer 210 above the target gate sacrificial layer 217 etched from the initial stacked structure 208, with the bottom of the first sub-contact hole 216 remaining within this interlayer insulating layer 210. In other words, compared to the initial thickness of the interlayer insulating layer 210, the thickness of the interlayer insulating layer 210 located below the bottom of the first sub-contact hole 216 is reduced.

[0136] In some embodiments, the initial stacked structure 208 is etched to form a first sub-contact hole 216, and the bottom of the first sub-contact hole 216 may also expose the target gate sacrificial layer 217.

[0137] like Figure 4CAs shown, an oxide material layer 218 is formed, which covers the bottom and sidewalls of the first sub-contact hole 216, and also covers the surface of the initial stacked structure 208 located in the connection region 202.

[0138] Combination Figure 4C and Figure 4D As shown, the oxide material layer 218 covering the bottom of the first sub-contact hole 216 is removed, while the oxide material layer 218 covering the sidewall of the first sub-contact hole 216 is retained to form an oxide layer 219.

[0139] It should be noted that removing the oxide material layer 218 covering the bottom of the first sub-contact hole 216 also removes the interlayer insulating layer 210 exposed at the bottom of the first sub-contact hole 216, exposing the target gate sacrificial layer 217.

[0140] like Figure 4E As shown, a portion of the target gate sacrificial layer 217 is etched away through the first sub-contact hole 216 in a direction parallel to the semiconductor layer 207 to form a second sub-contact hole 220. The second sub-contact hole 220 and the target gate sacrificial layer 217 are located in the same layer. The bottom of the second sub-contact hole 220 exposes the interlayer insulating layer 210 adjacent to the target gate sacrificial layer 217, and the sidewalls of the second sub-contact hole 220 expose the sidewalls of the target gate sacrificial layer 217. More specifically, the bottom of the second sub-contact hole 220 exposes the interlayer insulating layer 210 below the target gate sacrificial layer 217. The size of the second sub-contact hole 220 in the direction perpendicular to the stacking direction (i.e., parallel to the semiconductor layer 207) is larger than the size of the first sub-contact hole 216 in the direction perpendicular to the stacking direction (i.e., parallel to the semiconductor layer 207). The first sub-contact hole 216 and the second sub-contact hole 220 together form a contact hole 221.

[0141] It should be noted that, according to the process sequence, such as Figure 4E As shown in the dashed box, contact hole 221 can be divided into a first sub-contact hole 216 and a second sub-contact hole 220. The etching depth of the first sub-contact hole 216 extends from the surface of the initial stacked structure 208 to the surface of the target gate sacrificial layer 217. The etching depth of the second sub-contact hole 220 is the same as the thickness of the target gate sacrificial layer 217. Of course, as... Figure 4EAs shown in the dashed box, the contact hole 221 can also be divided into a first part 222 and a second part 223. The etching depth of the first part 222 of the contact hole 221 extends from the surface of the initial stacked structure 208 to penetrate the target gate sacrificial layer 217. The second part 223 of the contact hole 221 and the target gate sacrificial layer 217 are located in the same layer, and the second part 223 surrounds the first part 222. The second part 223 extends in a direction parallel to the semiconductor layer 207 and exposes the sidewalls of the target gate sacrificial layer 217. The first part 222 extends in the Z direction to connect with the second part 223 in a direction parallel to the semiconductor layer 207, and the second part 223 surrounds the first part 222. The etching depth of the first part 222 of the contact hole 221 is greater than the etching depth of the first sub-contact hole 216. Here, the etching depth refers to the etching depth along the Z direction.

[0142] Figure 4E Only one contact hole 221 is shown; in reality, the number of contact holes 221 in the semiconductor device provided in this embodiment is not limited to this. In some embodiments, the number of contact holes 221 may be the same as the number of gate sacrificial layers 209 in the initial stacked structure 208. Each contact hole 221 has a corresponding gate sacrificial layer 209, namely, a target gate sacrificial layer 217. Different contact holes 221 correspond to different target gate sacrificial layers 217.

[0143] Combination Figure 4E and Figure 4F As shown, a second sacrificial material layer 224 is formed within the contact hole 221. The second sacrificial material layer 224 covers the sidewalls and bottom of the first portion 222 of the contact hole 221 and fills the second portion 223 of the contact hole 221. At this time, the second sacrificial material layer 224 is in direct contact with the oxide layer 219 covering the sidewalls of the first sub-contact hole 216. Of course, during the formation of the second sacrificial material layer 224, the second sacrificial material layer 224 will also cover the surface of the initial stacked structure 208.

[0144] In some embodiments, the process for forming the second sacrificial material layer 224 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0145] In some embodiments, the material of the second sacrificial material layer 224 may include, but is not limited to, polycrystalline silicon.

[0146] Combination Figure 4F and Figure 4GThe second sacrificial material layer 224 covering the bottom of the first portion 222 of the contact hole 221 is removed, leaving only the second sacrificial material layer 224 covering the sidewalls of the first portion 222 of the contact hole 221 and filling the second portion 223 of the contact hole 221, to form the second sacrificial layer 225. Of course, in the process of removing the second sacrificial material layer 224 covering the bottom of the first portion 222 of the contact hole 221, the second sacrificial material layer 224 covering the surface of the initial stacked structure 208 is also removed.

[0147] In some embodiments, a second sacrificial material layer 224 covering the bottom of the first portion 222 of the contact hole 221 may be used, including but not limited to an etch back process, to remove the second sacrificial material layer 224.

[0148] like Figure 4H As shown, a first insulating material layer 226 is formed within the contact hole 221. Since an oxide layer 219 and a second sacrificial layer 225 have already been formed within the first portion 222 of the contact hole 221, and the second portion 223 of the contact hole 221 has been filled with the second sacrificial layer 225, the insulating material is located within the first portion of the contact hole 221. Of course, the first insulating material layer 226 also covers the surface of the initial stacked structure 208 and the surfaces of the oxide layer 219 and the second sacrificial layer 225 within the first portion 222 of the contact hole 221.

[0149] Combination Figure 4H and Figure 4I As shown, the first insulating material layer 226 is planarized, removing the first insulating material layer 226 covering the surface of the initial stacked structure 208 to expose the oxide layer 219 and the surface of the second sacrificial layer 225 within the first portion 222 of the contact hole 221. The first insulating material layer 226 within the first portion 222 of the contact hole 221 is retained to form an insulating pillar 227. Here, the contact hole 221, the insulating pillar 227, the second sacrificial layer 225, and the oxide layer 219 together form the initial contact structure 205.

[0150] In some embodiments, planarization may include, but is not limited to, chemical mechanical polishing (CMP).

[0151] In this embodiment, after forming a channel structure and a dummy channel structure in the core region and the connection region, respectively, a contact hole is directly formed, and polysilicon material can be filled into the contact hole to form a second sacrificial layer; subsequently, oxide material can be filled into the contact hole to form an isolation pillar. This approach mitigates the damage to the gate layer during contact hole formation caused by performing a gate replacement process before forming the contact hole, thus affecting structural stability and breakdown voltage. Furthermore, it reduces the amount of polysilicon material used to fill the contact hole, thereby lowering process costs.

[0152] In this embodiment of the disclosure, after forming the isolation post within the first portion of the contact hole, the manufacturing method further includes:

[0153] This forms a gate line slit (GLS) that runs through the initial stacked structure and extends to the semiconductor layer;

[0154] A first sacrificial layer is formed within the grid slot; wherein the grid slot and the first sacrificial layer together form the initial grid isolation structure.

[0155] like Figure 4J As shown, the initial stacked structure 208 is etched to form a gate line trench 228 that penetrates the initial stacked structure 208 and extends to the semiconductor layer 207; wherein, the gate line trench 228 is located in the array region, for example, the gate line trench 228 may extend from the core region to the connection region 202. (Reference) Figure 3A Correspondingly, the gate isolation structure is located in the array region 200 and can extend from the core region 201 to the connection region 202.

[0156] like Figure 4K As shown, the substrate 211 exposed at the bottom of the gate trench 228 and the polysilicon layer 215 exposed on the sidewalls of the gate trench 228 can be oxidized. The material of the substrate 211 can be, for example, polysilicon. In this way, the polysilicon exposed at the bottom and sidewalls of the gate trench 228 can be oxidized to form silicon oxide.

[0157] In this embodiment of the disclosure, the silicon oxide formed at the bottom and sidewalls of the grid slot 228 can serve as an isolation element.

[0158] In some embodiments, the oxidation process for the substrate exposed at the bottom of the gate spacer and the polysilicon layer exposed on the sidewalls of the gate spacer includes, but is not limited to, wet oxidation.

[0159] like Figure 4L As shown, a first sacrificial material layer 229 is formed in the gate slot 228, and the first sacrificial material layer 229 also covers the surface of the initial stacked structure 208 and the surface of the initial contact structure 205.

[0160] In some embodiments, the material of the first sacrificial material layer 229 may be, but is not limited to, polycrystalline silicon.

[0161] In some embodiments, the process for forming the first sacrificial material layer 229 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0162] Combination Figure 4L and Figure 4MAs shown, the first sacrificial material layer 229 can be planarized by removing the first sacrificial material layer 229 covering the surface of the initial stacked structure 208 to expose the surface of the initial stacked structure 208, while retaining the first sacrificial material layer 229 located within the gate line slot 228 to form the first sacrificial layer 230. The gate line slot 228 and the first sacrificial layer 230 together form the initial gate line isolation structure 206.

[0163] In this embodiment, there is no particular limitation on the process sequence for forming the first gap 232 and the second gap. In some embodiments, a portion of the gate sacrificial layer 209 located in the connection region 202 may be removed first through a portion of the gate line slot 228 located in the connection region 202 to form the first gap 232, and then the gate sacrificial layer 209 located in the core region 201 may be removed through a portion of the gate line slot 228 located in the core region 201 to form the second gap. The following will be combined with... Figures 4N to 4Q The process of forming the first gap 232 and then the second gap is explained in detail.

[0164] In this embodiment of the disclosure, the gate wire slot includes a portion of the gate wire slot located in the core region and a portion of the gate wire slot located in the connection region; before step S202, the manufacturing method further includes:

[0165] A protective layer is formed, which covers the surface of the initial stacked structure of the core area and the connecting area;

[0166] Remove the protective layer from the surface of the initial stacked structure covering the connection area.

[0167] like Figure 4N As shown, a protective layer 231 is formed, which covers the surface of the initial stacked structure 208 located in the core region and the connection region 202. Of course, the protective layer 231 also covers the surfaces of the initial gate isolation structure 206 and the initial contact structure 205. Figure 4N Only the surface of the initial stacked structure 208, the surface of the initial gate line isolation structure 206, and the surface of the initial contact structure 205 covering the connection area 202 are shown. Figure 4N The surface of the initial stacked structure 208 covering the core area is not shown.

[0168] In some embodiments, the material of the protective layer 231 may include, but is not limited to, silicon oxide.

[0169] In some embodiments, the formation of the protective layer 231 can be achieved through an ALD deposition process.

[0170] Combination Figure 4N and Figure 4OAs shown, the protective layer 231 on the surface of the initial stacked structure 208 covering the connection area 202 can be removed, while the protective layer 231 on the surface of the initial stacked structure 208 covering the core area can be retained.

[0171] In this embodiment of the disclosure, the purpose of retaining the protective layer 231 on the surface of the initial stacked structure 208 covering the core region 201 is to protect the initial stacked structure 208 of the core region 201 from damage during subsequent processes.

[0172] In this embodiment of the disclosure, step S202 includes: removing the first sacrificial layer in a portion of the gate wire slot in the connection area and the second sacrificial layer in the contact hole;

[0173] Step S203 includes: removing a portion of the gate sacrificial layer located in the connection region through a partial gate line slot located in the connection region to form a first gap.

[0174] Combination Figure 4O and Figure 4P As shown, the first sacrificial layer 230 located in the grid groove 228 of the connection area 202 and the second sacrificial layer 225 located in the contact hole 221 are removed, while the isolation post 227 located in the first part 222 of the contact hole 221 is retained.

[0175] like Figure 4Q As shown, a portion of the gate sacrificial layer 209 located in the connection region 202 is removed by a portion of the gate line slot 228 located in the connection region 202 to form a first gap 232 (as shown). Figure 4Q (As shown in the dashed box). Thus, the first gap 232 located in the connection area 202 is connected to the contact hole 221 so as to form a conductive structure in subsequent processes.

[0176] In this embodiment of the disclosure, after the gate wire slot is formed, polysilicon material can be filled in the gate wire slot to form a first sacrificial layer; in subsequent processes, the first sacrificial layer in the gate wire slot and the second sacrificial layer in the contact hole can be removed simultaneously.

[0177] In this embodiment of the disclosure, after step S203, the manufacturing method further includes:

[0178] Remove the protective layer from the surface of the initial stacked structure covering the core area;

[0179] Remove the first sacrificial layer within a portion of the gate wire slots located in the core region;

[0180] A second gap is formed by removing the gate sacrificial layer in the core region through a partial gate line slot in the core region; wherein the first gap and the second gap are connected.

[0181] Here, the first sacrificial layer 230 in the gate line slot 228 in the connection region 202 and the second sacrificial layer 225 in the contact hole 221 are removed, and a portion of the gate sacrificial layer 209 is removed through the gate line slot 228 in the connection region 202 to form a first gap 232; then the first sacrificial layer in the gate line slot in the core region is removed, and the gate sacrificial layer is removed through the gate line slot in the core region to form a second gap.

[0182] For example, before removing the protective layer on the surface of the initial stacked structure covering the core region, a protective material, such as photoresist, can be filled in the first gap 232 and contact hole 221 located in the connection region 202 to reduce the damage to the structure located in the connection region caused by the subsequent process of removing the first sacrificial layer in the gate line slot in the core region and the gate sacrificial layer in the core region.

[0183] In this embodiment of the disclosure, step S204 includes:

[0184] A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through gate line slots and contact holes; wherein, the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap together form a gate layer, and the gate layer and the interlayer insulating layer together form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole together constitute a connection layer, and the connection layer fills the second part of the contact hole but does not fill the first part of the contact hole.

[0185] Combination Figure 4Q and Figure 4RAs shown, a dielectric layer 233, a first conductive layer 234, and a second conductive layer 235 are sequentially formed within the first gap 232, the second gap, and the contact hole 221 via gate line slots 228 and contact holes 221. The dielectric layer 233, the first conductive layer 234, and the second conductive layer 235 located in the core region and the connection region 202 together form the gate layer 236. That is, the gate layer 236 located in the core region and the gate layer 236 located in the connection region 202 are connected, and the gate layer 236 and the interlayer insulating layer 210 together form a stacked structure 237. Of course, during the formation of the dielectric layer 233, the first conductive layer 234, and the second conductive layer 235, the dielectric layer 233, the first conductive layer 234, and the second conductive layer 235 will also cover the surface of the stacked structure 237. The dielectric layer 233, the first conductive layer 234, and the second conductive layer 235 located within the contact hole 221 together form a connection layer 238, which is connected to the corresponding target gate layer 250. Within the first portion 222 of the contact hole 221, the connecting layer 238 covers the sidewalls of both the first portion 222 and the sidewalls of the isolation pillar 227. However, the connecting layer 238 does not completely fill the remaining space of the first portion 222 of the contact hole 221, excluding the isolation pillar 227. Therefore, a gap still exists between the connecting layer 238 covering the sidewalls of the first portion 222 and the sidewalls of the isolation pillar 227. In this embodiment, a dielectric layer, a first conductive layer, and a second conductive layer are simultaneously formed within the first gap, the second gap, and the contact hole using grid slots and contact holes. By filling the first gap, the second gap, and the contact hole in one step, manufacturing costs are further reduced.

[0186] In this embodiment of the present disclosure, after the dielectric layer, the first conductive layer, and the second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate wire slots and contact holes, the manufacturing method further includes:

[0187] A first filling layer is formed, which fills the gap between the first part of the sidewall of the contact hole and the isolation post to form a contact structure.

[0188] Combination Figure 4R and Figure 4S As shown, a first filler material layer 239 is formed, which can fill the gap between the first portion 222 sidewall of the contact hole 221 and the isolation post 227. Of course, the first filler material layer 239 will also cover the sidewall and bottom of the grid slot 228, and cover the surface of the stacked structure 237.

[0189] In this embodiment of the disclosure, the first filler layer is formed using an ALD process.

[0190] Combination Figure 4S and Figure 4TAs shown, the first filler material layer 239 covering the sidewalls and bottom of the grid groove 228 and the surface of the stacked structure 237 is removed, while the first filler material layer 239 located between the sidewall of the first portion 222 of the contact hole 221 and the isolation post 227 is retained to form the first filler layer 240.

[0191] In this embodiment of the disclosure, the distance between the oxide layer and the isolation pillar in the first portion of the contact hole along the direction parallel to the semiconductor layer is greater than or equal to the thickness of the gate layer. Thus, at least one connection layer (i.e., a dielectric layer, a first conductive layer, and a second conductive layer) is formed between the oxide layer and the isolation pillar of the contact hole. Exemplarily, Figure 4T The diagram illustrates the formation of two connecting layers between the oxide layer and the isolation pillar of the contact hole, and the gap between the two connecting layers is filled by a first filling layer, thereby filling the contact hole. Figure 5J This illustrates the formation of a connecting layer between the oxide layer of the contact hole and the isolation pillar.

[0192] Here, the contact structure 241 includes a first part 222 and a second part 223. The first part 222 includes an isolation pillar 227 and a conductive structure located between the oxide layer 219 on the sidewall of the first part 222 and the isolation pillar 227. Figure 4T The conductive structure between the oxide layer 219 and the isolation pillar 227 of the schematic first part 222 sidewall includes two connecting layers 238 and a first filling layer 240 located between the two connecting layers 238.

[0193] In this embodiment of the disclosure, after step S204, the manufacturing method further includes:

[0194] Remove the second conductive layer and the first conductive layer within the gate slot.

[0195] Combination Figure 4R and Figure 4U As shown, removing the first conductive layer 234 and the second conductive layer 235 covering the sidewalls and bottom of the gate wire slot 228 prevents electrical connection between different gate layers 236. Of course, while removing the first conductive layer 234 and the second conductive layer 235 within the gate wire slot 228, the first conductive layer 234 and the second conductive layer 235 covering the surface of the stacked structure 237 can also be removed to expose the dielectric layer 233 covering the surface of the stacked structure 237.

[0196] In some embodiments, a recess etch process can be used to remove the first and second conductive layers within the gate slots.

[0197] For example, a dielectric layer located at the bottom of the gate trench and on the surface of the stacked structure can be removed using processes including but not limited to dry etching.

[0198] In this embodiment of the disclosure, after removing the second conductive layer and the first conductive layer within the gate wire slots, the manufacturing method further includes:

[0199] A second isolation layer is formed, which covers the sidewalls and bottom of the grid slot;

[0200] A second filling layer is formed; wherein, the grid line slot, the second isolation layer and the second filling layer together form a grid line isolation structure.

[0201] like Figure 4V As shown, a second isolation layer 242 is formed within the gate line slot 228. This second isolation layer 242 also covers the surface of the stacked structure 237 and the surface of the contact structure 241. A second filler material is filled within the gate line slot 228 to form a second filler layer 243, which completely fills the gate line slot 228. The gate line slot 228, the second isolation layer 242, and the second filler layer 243 together form the gate line isolation structure 244.

[0202] In this embodiment of the disclosure, the semiconductor structure further includes a channel structure located in the core region and a dummy channel structure located in the connection region;

[0203] After forming the second filler layer, the manufacturing method further includes:

[0204] A medium layer is formed that covers the trench structure, the virtual trench structure, and the contact structure;

[0205] The etching dielectric layer forms a first through-hole, a second through-hole, and a third through-hole that are respectively connected to the conductive structures within the channel structure, the dummy channel structure, and the contact structure.

[0206] Conductive material is filled into the first through hole, the second through hole, and the third through hole to form the first lead-out structure, the second lead-out structure, and the third lead-out structure, respectively.

[0207] like Figure 4W As shown, a dielectric layer 245 is formed covering the connection area 202 and the core area. More specifically, the dielectric layer 245 covers the dummy channel structure 204, the channel structure and the contact structure 241.

[0208] like Figure 4X As shown, the dielectric layer 245 is etched to form a first through-hole, a second through-hole 246, and a third through-hole 247 that penetrate the dielectric layer 245 and are respectively connected to the conductive structures in the channel structure of the core region, the dummy channel structure 204 of the connection region 202, and the contact structure 241. Conductive material is filled into the first through-hole, the second through-hole 246, and the third through-hole 247 to form a first lead-out structure, a second lead-out structure 248, and a third lead-out structure 249, respectively. Figure 4XOnly the second lead-out structure 248 and the third lead-out structure 249 of the connection area 202 are shown in the diagram. Figure 4X The first lead-out structure of core area 201 is not shown.

[0209] In a specific example, the material of the dielectric layer 245 may include, but is not limited to, silicon oxide.

[0210] In some embodiments, the formation of the dielectric layer 245 and the filling of the conductive material can be achieved through one or more deposition processes. These deposition processes may include, but are not limited to, PVD, CVD, ALD, or any combination thereof.

[0211] In this embodiment of the disclosure, after forming the gate isolation structure, electrical signals are led out from the channel structure and also from the contact structure simultaneously; that is, a first lead-out structure, a second lead-out structure, and a third lead-out structure are formed at the same time. In fact, the second lead-out structure is connected to the dummy channel structure, and the second lead-out structure does not lead out electrical signals from the dummy channel structure.

[0212] The following will combine Figure 3B as well as Figures 5A to 5J This disclosure provides a detailed description of another method for manufacturing a semiconductor device according to embodiments thereof. Figure 3B A top view of another semiconductor device provided in an embodiment of this disclosure. Figures 5A to 5D , Figures 5F to 5J The schematic cross-sectional structure of the connecting area shown can be regarded as Figure 3B A schematic diagram of the cross-sectional structure along the BB direction. Figure 5E The schematic diagram showing the cross-sectional structure of the core area can be regarded as Figure 3B A schematic diagram of the cross-sectional structure along the CC direction.

[0213] The following will combine Figure 5A and Figure 5B The process of first forming the initial gate isolation structure and then forming the initial contact structure is explained in detail.

[0214] In this embodiment of the disclosure, step S201 includes:

[0215] An initial stacked structure is formed on the semiconductor layer;

[0216] Forming gate line slots that penetrate the initial stacked structure and extend to the semiconductor layer;

[0217] A first sacrificial layer is formed within the grid slot; wherein the grid slot and the first sacrificial layer together form the initial grid isolation structure.

[0218] like Figure 5AAs shown, an initial stacked structure 303 is formed on the semiconductor layer 302. The initial stacked structure 303 includes alternately stacked gate sacrificial layers 304 and interlayer insulating layers 305. A dummy channel structure 306 can be formed through the initial stacked structure 303 and extend to the semiconductor layer 302. A gate line partition 307 is formed through the initial stacked structure 303 and extend to the semiconductor layer 302. A first sacrificial layer 308 is formed in the gate line partition 307. The gate line partition 307 and the first sacrificial layer 308 together form an initial gate line isolation structure 309.

[0219] Here, the process for forming the initial gate isolation structure can be referred to Figures 4A to 4M The relevant descriptions will not be repeated here.

[0220] In this embodiment of the disclosure, after forming the first sacrificial layer within the gate wire slot, the manufacturing method further includes:

[0221] Form contact holes that extend along the stacking direction to the target gate sacrificial layer;

[0222] A second sacrificial layer is formed inside the contact hole, which covers the sidewalls and bottom of the first part of the contact hole and fills the second part of the contact hole.

[0223] Remove the second sacrificial layer from the bottom of the first portion covering the contact hole;

[0224] An isolation pillar is formed within the first part of the contact hole; wherein, the contact hole, the isolation pillar, and the second sacrificial layer together form the initial contact structure.

[0225] Still Figure 5A As shown, a capping layer 341 is formed covering the surfaces of the initial gate isolation structure 309 and the initial stacked structure 303; the capping layer 341 and the initial stacked structure 303 are etched along the Z direction to form a first sub-contact hole 310, the bottom of the first sub-contact hole 310 exposing a portion of the interlayer insulating layer 305 above the target gate sacrificial layer 311; an oxide layer 312 is formed, the oxide layer 312 covering the sidewall of the first sub-contact hole 310.

[0226] Here, the purpose of forming the cover layer 341 is to reduce the damage to the initial gate line isolation structure 309 caused by the process of forming the contact hole.

[0227] For example, an oxide material layer may be formed, which covers the bottom and sidewalls of the first sub-contact hole and the surface of the initial stacked structure located in the connection area; the oxide material layer covering the bottom of the first sub-contact hole and the surface of the initial stacked structure is removed, while the oxide material layer covering the sidewalls of the first sub-contact hole is retained to form an oxide layer.

[0228] like Figure 5BAs shown, a portion of the target gate sacrificial layer 311 is etched away through the first sub-contact hole 310 along a direction parallel to the semiconductor layer 302 to form a second sub-contact hole 313; wherein, the first sub-contact hole 310 and the second contact hole 313 together form a contact hole 314 (as shown). Figure 5B (As shown in the dashed box).

[0229] Here, for reference Figure 5B As shown in the dashed box, contact hole 314 can also be divided into a first part 315 and a second part 316. For more information on the first part 315 and the second part 316 of contact hole 314, please refer to... Figures 4A to 4M The relevant descriptions will not be repeated here.

[0230] Still Figure 5B As shown, the initial contact structure 317 includes a contact hole 314, an isolation pillar 319 located within the contact hole 314, and a second sacrificial layer 318 located within the contact hole 314.

[0231] In this embodiment of the disclosure, before step S202, the manufacturing method further includes:

[0232] The initial contact structure is etched along the stacking direction to form at least one groove; wherein the size of the groove along the direction parallel to the semiconductor layer is greater than or equal to the distance between the isolation pillar and the oxide layer along the direction parallel to the semiconductor layer;

[0233] The groove is filled with insulating material to form a support structure.

[0234] In some embodiments, combined with Figure 5C and 5D As shown, the initial contact structure 317 is etched along the stacking direction to form at least one trench 320; wherein the dimension of the trench 320 along the direction parallel to the semiconductor layer 302 is greater than or equal to the distance between the isolation pillar 319 and the oxide layer 312 along the direction parallel to the semiconductor layer 302. The trench 320 is filled with insulating material to form a support structure 321. This support structure 321 is used to reinforce the isolation pillar 319 and ensure the stability of the isolation pillar 319 structure. Of course, while filling the trench 320 with insulating material to form the support structure 321, the insulating material also covers the surface of the core region and the connection region 301 to form a protective layer 326 on the surface of the core region and the connection region 301. The dimension of the support structure 321 along the direction parallel to the semiconductor layer 302 is greater than the distance between the isolation pillar 319 and the oxide layer 312 along the direction parallel to the semiconductor layer 302.

[0235] Here, while filling the groove with insulating material to form a support structure, a protective layer is also formed covering the surface of the initial stacked structure. The purpose of forming the protective layer is to reduce damage to the structure located in the connection region caused by the subsequent removal of the gate sacrificial layer in the core region.

[0236] In this embodiment of the disclosure, a support structure is formed, which can function similarly to a "rivet" to connect the sidewall of the contact hole (e.g., the oxide layer on the sidewall of the contact hole) and the isolation pillar inside the contact hole, thereby fixing the isolation pillar and reducing the damage to the isolation pillar caused by the subsequent process of removing the second sacrificial layer inside the contact hole and forming a conductive structure inside the contact hole.

[0237] refer to Figure 6A , Figure 6A A top view of the support structure in a semiconductor device provided in this embodiment of the disclosure. Figure 6A Three different support structures are illustrated: a first support structure 322, a second support structure 323, and a third support structure 324. The first support structure 322 includes two sub-support structures, combined with… Figure 5C Each sub-support structure has a dimension along the direction parallel to the semiconductor layer 302 equal to the maximum dimension of the first portion 315 of the contact hole along the direction parallel to the semiconductor layer 302, and the two sub-support structures can form a certain angle. For example, if the first portion 315 of the contact hole is circular in a top view, then the dimension of the sub-support structure along the direction parallel to the semiconductor layer 302 is equal to the diameter of the first portion 315 of the contact hole. The second support structure 323 includes four sub-support structures, which can be arranged at intervals along the outer contour of the first portion 315 of the contact hole. The third support structure 324 includes eight sub-support structures, which can be arranged at intervals along the outer contour of the first portion 315 of the contact hole.

[0238] This disclosure does not impose a special limitation on the number of sub-support structures included in the supporting structure. The supporting structure may include only one sub-support structure or multiple sub-support structures. When the supporting structure includes multiple sub-support structures, this disclosure does not impose a special limitation on the arrangement of the multiple sub-support structures, or on the included angle between the multiple sub-support structures. Furthermore, this disclosure does not impose a special limitation on the size of the supporting structure, as long as the supporting structure can fulfill the function of fixing the isolation column.

[0239] The following will combine Figures 5E to 5H It explains in detail the process of forming the second gap first and then the first gap.

[0240] In this embodiment of the disclosure, the semiconductor structure includes a core region and a connection region; the gate line spacers include a portion of the gate line spacers located in the core region and a portion of the gate line spacers located in the connection region;

[0241] Before removing the first sacrificial layer within the grid slots and the second sacrificial layer within the contact holes, the manufacturing method further includes:

[0242] A protective layer is formed, which covers the surface of the initial stacked structure of the core area and the connecting area;

[0243] Remove the protective layer from the surface of the initial stacked structure covering the core area;

[0244] Remove the first sacrificial layer within a portion of the gate wire slots located in the core region;

[0245] The gate sacrificial layer in the core region is removed by partially removing gate line slots in the core region to form a second gap;

[0246] Remove the protective layer from the surface of the initial stacked structure covering the connection area.

[0247] Here, the protective layer on the surface of the initial stacked structure 303 covering the core region 300 is removed, while the protective layer on the surface of the initial stacked structure 303 covering the connection region 301 is retained. The purpose of retaining the protective layer on the surface of the initial stacked structure 303 covering the connection region 301 is to protect the initial stacked structure 303 of the connection region 301 from damage during subsequent processes.

[0248] Figure 5E A schematic cross-sectional view of the core area 300 is shown, revealing a channel structure 339 within the core area. (See diagram below.) Figure 5E As shown, the first sacrificial layer in a portion of the gate line slot 307 in the core region 300 is removed, and then the gate sacrificial layer in the core region 300 is removed through the portion of the gate line slot 307 in the core region 300 to form a second gap 327.

[0249] Figure 5F The schematic diagram shows the cross-sectional structure of the connecting area 301, combined with... Figure 5D and Figure 5F As shown, after the second gap is formed, the protective layer 326 on the surface of the initial stacked structure 303 covering the connection area 301 is removed.

[0250] In this embodiment of the disclosure, step S202 includes:

[0251] Remove the first sacrificial layer located in the grid line slots of the connection area and the second sacrificial layer located in the contact holes;

[0252] Step S203 includes:

[0253] A portion of the gate sacrificial layer in the connection region is removed by a partial gate line slot in the connection region to form a first gap; wherein the first gap and the second gap are connected.

[0254] Combination Figure 5F and Figure 5G As shown, the first sacrificial layer 308 located in the grid line slot 307 of the connection area 301 and the second sacrificial layer 318 located in the contact hole 314 are removed.

[0255] refer to Figure 6B , Figure 6B A top view of the support structure in the semiconductor device provided in this embodiment of the disclosure. Figure 2 .like Figure 6B As shown, after removing the second sacrificial layer inside the contact hole, the first support structure 322, the second support structure 323, or the third support structure 324 can be used to connect the oxide layer 312 and the isolation pillar 319, serving as a support and fixation function.

[0256] like Figure 5H As shown, a portion of the gate sacrificial layer 304 in the connection region 301 is removed by a partial gate line slot 307 located in the connection region 301 to form a first gap 328. Thus, the first gap 328 in the connection region 301, the second gap in the core region, and the contact hole 314 are connected.

[0257] Combination Figure 5H and Figure 5I As shown, a dielectric layer 329, a first conductive layer 330, and a second conductive layer 331 are sequentially formed within the first gap 328, the second gap, and the contact hole 314 via a gate line slot 307 and a contact hole 314. The dielectric layer 329, the first conductive layer 330, and the second conductive layer 331 located in the core region and the connection region 301 together form a gate layer 332. That is, the gate layer 332 located in the core region and the gate layer 332 located in the connection region 301 are connected, and the gate layer 332 and the interlayer insulating layer 305 together form a stacked structure 333. The dielectric layer 329, the first conductive layer 330, and the second conductive layer 331 located within the contact hole 314 together constitute a connection layer 334, which is connected to the gate layer 332. The connection layer 334 simultaneously fills the first portion 315 and the second portion 316 of the contact hole 314 to form a conductive structure within the contact hole 314. For ease of explanation, Figure 5I Only the gate layer 332 is shown in the first gap. Specifically, the gate layer 332 may include a dielectric layer 329, a first conductive layer 330, and a second conductive layer 331, as shown in the dashed box.

[0258] refer to Figure 6C , Figure 6CThis is a top view of the support structure in a semiconductor device provided in an embodiment of this disclosure. (See diagram 3.) Figure 6C As shown, a connecting layer 334 is formed in the contact hole. The connecting layer 334 occupies the space originally occupied by the second sacrificial layer. The first support structure 322, the second support structure 323, or the third support structure 324 can be used to connect the oxide layer 312 and the isolation pillar 319, playing a supporting and fixing role.

[0259] For example Figure 5I As shown, the first conductive layer 330 and the second conductive layer 331 are removed from the sidewalls and bottom of the gate slot 307. Simultaneously, the second conductive layer 331 located on the surface of the stacked structure 333 is also removed.

[0260] like Figure 5J As shown, a second isolation layer 336 is formed covering the sidewalls and bottom of the gate line slot 307, and the second isolation layer 336 may also cover the surface of the stacked structure 333. A second filling layer 337 is formed within the gate line slot 307, and the second filling layer 337 fills the gate line slot 307; wherein, the gate line slot 307, the second isolation layer 336 and the second filling layer 337 together form the gate line isolation structure 338.

[0261] refer to Figure 7 , Figure 7 This is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of this disclosure.

[0262] like Figure 7 As shown, this disclosure provides a semiconductor device, which includes:

[0263] The stacked structure 237 includes a core region and a connection region 202; the stacked structure 237 includes alternately stacked gate layers 236 and interlayer insulating layers 210;

[0264] A contact structure 241 extends along the stacking direction into the target gate layer 250 within the stacked structure 237; the contact structure 241 includes an isolation pillar 227 extending along the stacking direction and a conductive structure located between the sidewall of the contact hole 221 and the isolation pillar 227; the contact structure 241 is located in the connection region 202.

[0265] In this embodiment of the present disclosure, the contact structure 241 includes a first portion 222 and a second portion 223 connected to each other. The first portion 222 extends along the stacking direction to the target gate layer 250, and the second portion 223 extends perpendicular to the stacking direction and is connected to the target gate layer 250. The second portion 223 surrounds the first portion 222. The first portion 222 includes an isolation pillar 227 and a conductive structure located between the sidewall of the first portion 222 and the isolation pillar 227. The second portion 223 includes a conductive structure.

[0266] In this embodiment of the disclosure, the semiconductor device further includes:

[0267] The trench structure located in the core area and the virtual trench structure 204 located in the connecting area 202;

[0268] A dielectric layer 245 covers the stacked structure 237 located in the core area and the connecting area 202;

[0269] A first lead-out structure, a second lead-out structure, and a third lead-out structure 249 are located within the dielectric layer 245 and are respectively connected to the conductive structures within the channel structure, the dummy channel structure 204, and the contact structure 241. In this embodiment, the conductive structure of the second portion 223 of the contact structure 241 includes a dielectric layer 233, a first conductive layer 234, and a second conductive layer 235; wherein, the dielectric layer 233, the first conductive layer 234, and the second conductive layer 235 together form a connection layer 238;

[0270] The conductive structure of the first part 222 of the contact structure 241 includes, in a radially outward direction, a connecting layer 238, a first filling layer 240, and a connecting layer 238.

[0271] In this embodiment of the disclosure, the third lead-out structure 249 is connected to the two connection layers 238.

[0272] In this embodiment of the disclosure, the semiconductor device further includes:

[0273] A gate line isolation structure 244 that runs through the stacked structure 237 along the stacking direction.

[0274] In this embodiment of the disclosure, the semiconductor device may further include a source layer 251. Exemplarily, the semiconductor layer is thinned on the back side to expose the ends of the channel structure; the source layer 251 is formed to lead out the electrical signals of the channel structure.

[0275] refer to Figure 8 , Figure 8 This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this disclosure. Figure 8 As shown, this disclosure provides a semiconductor device, which includes:

[0276] The stacked structure 333 includes a core region and a connection region 301; the stacked structure 333 includes alternately stacked gate layers 332 and interlayer insulating layers 305;

[0277] A contact structure 335 extends along the stacking direction into the target gate layer 340 within the stacked structure 333; the contact structure 335 includes an isolation pillar 319 extending along the stacking direction and a conductive structure located between the sidewall of the contact hole 314 and the isolation pillar 319; the contact structure 335 is located in the connection region 301.

[0278] In this embodiment of the present disclosure, the contact structure 335 includes a first portion 315 and a second portion 316 connected to each other. The first portion 315 extends along the stacking direction to the target gate layer 340, and the second portion 316 extends perpendicular to the stacking direction and is connected to the target gate layer 340. The second portion 316 surrounds the first portion 315. The first portion 315 includes an isolation pillar 319 and a conductive structure located between the sidewall of the first portion 315 and the isolation pillar 319. The second portion 316 includes a conductive structure.

[0279] In this embodiment of the disclosure, the semiconductor device further includes:

[0280] The trench structure located in the core area and the virtual trench structure 306 located in the connecting area 301;

[0281] A dielectric layer covering the stacked structure 333 located in the core region and the connecting region 301;

[0282] The first lead-out structure, the second lead-out structure, and the third lead-out structure are located within the dielectric layer and are respectively connected to the conductive structures within the channel structure, the dummy channel structure 306, and the contact structure 335.

[0283] In this embodiment of the disclosure, the semiconductor device further includes:

[0284] A gate line isolation structure 338 that runs through the stacked structure 333 along the stacking direction.

[0285] In this embodiment of the disclosure, the semiconductor device further includes a source layer 342. Exemplarily, the semiconductor layer is thinned on the back side to expose the ends of the channel structure; the source layer 342 is formed to lead out the electrical signals of the channel structure.

[0286] It should be noted that, Figure 8 The provided cross-sectional structural diagram only shows the dummy channel structure, gate isolation structure, and contact structure located in the connection area; it does not show the dielectric layer, second lead-out structure, and third lead-out structure formed in subsequent processes. For information on the dielectric layer, second lead-out structure, and third lead-out structure, please refer to [link to relevant documentation]. Figure 7 .

[0287] It should be noted that, Figure 7 and Figure 8 The provided cross-sectional structural diagrams only show the connection area of ​​the semiconductor device, and do not show the core area of ​​the semiconductor device, the channel structure located in the core area, and the first lead-out structure.

[0288] In this embodiment of the present disclosure, the conductive structure of the second portion 316 of the contact structure 335 includes a dielectric layer 329, a first conductive layer 330, and a second conductive layer 331; wherein, the dielectric layer 329, the first conductive layer 330, and the second conductive layer 331 together form a connection layer 334.

[0289] The conductive structure of the first portion 315 of the contact structure 335 includes a connecting layer 334.

[0290] In this embodiment of the disclosure, the third lead-out structure is connected to a connection layer 334.

[0291] Figure 8 Combination Figure 5C In this embodiment of the disclosure, the contact structure 335 further includes an oxide layer 312 located on the sidewall of the first portion 315; the semiconductor device further includes:

[0292] At least one support structure 321 is embedded in the contact structure 335 along the stacking direction, and the dimension of the support structure 321 along the stacking direction is greater than or equal to the distance between the isolation pillar 319 and the oxide layer 312 along the stacking direction.

[0293] refer to Figure 9 , Figure 9 A block diagram of a memory system provided for an embodiment of this disclosure. (See diagram below.) Figure 9 As shown, this disclosure provides a memory system 400, which includes:

[0294] At least one semiconductor device 402 as described in the above technical solution; and

[0295] The controller 401 is coupled to the semiconductor device 402 and is configured to control the semiconductor device 402.

[0296] In this embodiment of the disclosure, the semiconductor device may be part of a memory, that is, the semiconductor device includes a memory cell array, which may form a memory together with peripheral circuitry; or, the semiconductor device may be a memory.

[0297] The memory system 400 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0298] In some embodiments, the controller 401 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0299] In other embodiments, controller 401 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0300] This disclosure provides a semiconductor device and its manufacturing method, as well as a memory system. In this embodiment, contact holes are formed before the gate replacement process. This mitigates the damage to the gate layer during contact hole formation, which can affect structural stability and breakdown voltage, when the gate replacement process is performed first and then the contact holes are formed. Furthermore, isolation pillars are provided within the contact holes. Thus, when filling the contact holes with sacrificial material, only the remaining space excluding the isolation pillars needs to be filled, saving sacrificial material and consequently reducing manufacturing costs.

[0301] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0302] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor structure is provided, including a semiconductor layer, an initial stacked structure on the semiconductor layer, an initial gate isolation structure, and an initial contact structure; wherein the initial stacked structure includes alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate isolation structure includes a gate trench and a first sacrificial layer located within the gate trench; the initial contact structure includes a contact hole, an isolation pillar located within the contact hole, and a second sacrificial layer located within the contact hole, and the initial contact structure extends along the stacking direction and is connected to a target gate sacrificial layer; The initial contact structure is etched along the stacking direction to form at least one groove; The groove is filled with insulating material to form a support structure; after the support structure is formed, the first sacrificial layer in the grid groove and the second sacrificial layer in the contact hole are removed. A portion of the gate sacrificial layer is removed through the gate line slot to form a first gap; the first gap is connected to the corresponding contact hole; A conductive structure is formed within the first gap and the contact hole.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The contact hole includes a first portion and a second portion that are connected to each other. The first portion extends along the stacking direction and penetrates the target gate sacrificial layer. The second portion extends along a direction parallel to the semiconductor layer and exposes the sidewall of the target gate sacrificial layer. The second portion surrounds the first portion. The isolation pillar extends along the stacking direction and is located within the first portion.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The provided semiconductor structure includes: An initial stacked structure is formed on the semiconductor layer; Forming gate line trenches that penetrate the initial stacked structure and extend to the semiconductor layer; A first sacrificial layer is formed within the gate wire slot; wherein the gate wire slot and the first sacrificial layer together form the initial gate wire isolation structure.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, After forming the first sacrificial layer within the grid slot, the manufacturing method further includes: Forming contact holes extending along the stacking direction to the target gate sacrificial layer; A second sacrificial layer is formed inside the contact hole, the second sacrificial layer covering the sidewalls and bottom of the first part of the contact hole and filling the second part of the contact hole; Remove the second sacrificial layer covering the bottom of the first portion of the contact hole; An isolation pillar is formed within the first portion of the contact hole; wherein the contact hole, the isolation pillar, and the second sacrificial layer together form the initial contact structure.

5. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The provided semiconductor structure includes: An initial stacked structure is formed on the semiconductor layer; Forming contact holes extending along the stacking direction to the target gate sacrificial layer; A second sacrificial layer is formed inside the contact hole, the second sacrificial layer covering the sidewalls and bottom of the first part of the contact hole and filling the second part of the contact hole; Remove the second sacrificial layer covering the bottom of the first portion of the contact hole; An isolation pillar is formed within the first portion of the contact hole; wherein the contact hole, the isolation pillar, and the second sacrificial layer together form the initial contact structure.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, After forming the isolation post within the first portion of the contact hole, the manufacturing method further includes: Forming gate line trenches that penetrate the initial stacked structure and extend to the semiconductor layer; A first sacrificial layer is formed within the gate wire slot; wherein the gate wire slot and the first sacrificial layer together form the initial gate wire isolation structure.

7. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The initial contact structure also includes an oxide layer covering the first portion of the sidewall of the contact hole; The dimension of the groove along the direction parallel to the semiconductor layer is greater than or equal to the distance between the isolation pillar and the oxide layer along the direction parallel to the semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The semiconductor structure includes a core region and a connection region; the gate line slots include a portion of the gate line slots located in the core region and a portion of the gate line slots located in the connection region; Before removing the first sacrificial layer in the grid slot and the second sacrificial layer in the contact hole, the manufacturing method further includes: A protective layer is formed, which covers the surface of the initial stacked structure of the core region and the connecting region; Remove the protective layer covering the surface of the initial stacked structure of the core region; Remove the first sacrificial layer located within a portion of the gate wire slots in the core region; The gate sacrificial layer in the core region is removed by partially removing gate line slots in the core region to form a second gap; Remove the protective layer from the surface of the initial stacked structure covering the connection area.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The removal of the first sacrificial layer in the grid slot and the second sacrificial layer in the contact hole includes: Remove the first sacrificial layer located in a portion of the grid line slot in the connection area and the second sacrificial layer located in the contact hole; The step of removing a portion of the gate sacrificial layer through the gate line slot to form a first gap includes: A portion of the gate sacrificial layer in the connection region is removed by a partial gate line slot in the connection region to form a first gap; wherein the first gap and the second gap are connected.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The formation of a conductive structure within the first gap and the contact hole includes: A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line slots and the contact hole; wherein, the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap together form a gate layer, and the gate layer and the interlayer insulating layer together form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole together form a connection layer, and the connection layer simultaneously fills the first part and the second part of the contact hole to form a contact structure.

11. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The formation of a conductive structure within the first gap and the contact hole includes: A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line slots and the contact hole; wherein, the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap together form a gate layer, and the gate layer and the interlayer insulating layer together form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole together constitute a connection layer, the connection layer filling the second part of the contact hole and not filling the first part of the contact hole.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, After the dielectric layer, the first conductive layer, and the second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate wire slots and the contact holes, the manufacturing method further includes: A first filling layer is formed, which fills the gap between the first portion of the sidewall of the contact hole and the isolation post to form a contact structure.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, The first filling layer is formed using an atomic layer deposition process.

14. The method for manufacturing a semiconductor device according to claim 10 or 12, characterized in that, After forming the conductive structure within the first gap and the contact hole, the manufacturing method further includes: Remove the second conductive layer and the first conductive layer within the grid slot.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, After removing the second conductive layer and the first conductive layer within the gate wire slot, the manufacturing method further includes: An isolation layer is formed, which covers the sidewalls and bottom of the grid slot; A second filling layer is formed; wherein the grid line slot, the isolation layer and the second filling layer together form a grid line isolation structure.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The semiconductor structure also includes a channel structure located in the core region and a dummy channel structure located in the connection region; After forming the second filling layer, the manufacturing method further includes: A dielectric layer is formed covering the channel structure, the dummy channel structure, and the contact structure; The dielectric layer is etched to form a first through-hole, a second through-hole, and a third through-hole that are respectively connected to the conductive structure in the channel structure, the dummy channel structure, and the contact structure. Conductive material is filled into the first through hole, the second through hole, and the third through hole to form a first lead-out structure, a second lead-out structure, and a third lead-out structure, respectively.

17. A semiconductor device, characterized in that, The semiconductor device includes: A stacked structure, the stacked structure including a core region and a connection region; the stacked structure including alternately stacked gate layers and interlayer insulating layers; A contact structure extending along the stacking direction into the target gate layer within the stacked structure; the contact structure includes an isolation pillar extending along the stacking direction and a conductive structure located between the contact hole sidewall and the isolation pillar; the contact structure is located in the connection region; At least one support structure embedded in the contact structure along the stacking direction.

18. The semiconductor device according to claim 17, characterized in that, The contact structure includes a first part and a second part connected to each other. The first part extends along the stacking direction to the target gate layer, and the second part extends perpendicular to the stacking direction and is connected to the target gate layer. The second part surrounds the first part. The first part includes an isolation pillar and a conductive structure located between the sidewall of the first part and the isolation pillar. The second part includes a conductive structure.

19. The semiconductor device according to claim 18, characterized in that, The semiconductor device further includes: The channel structure located in the core area and the virtual channel structure located in the connecting area; A dielectric layer covering the stacked structure located in the core region and the connection region; A first lead-out structure, a second lead-out structure, and a third lead-out structure located within the dielectric layer and respectively connected to the conductive structure within the channel structure, the dummy channel structure, and the contact structure.

20. The semiconductor device according to claim 19, characterized in that, The conductive structure of the second part of the contact structure includes a dielectric layer, a first conductive layer, and a second conductive layer; wherein the dielectric layer, the first conductive layer, and the second conductive layer together form a connection layer; The conductive structure of the first part of the contact structure includes the connecting layer.

21. The semiconductor device according to claim 20, characterized in that, The third lead-out structure is connected to one of the connection layers.

22. The semiconductor device according to claim 19, characterized in that, The conductive structure of the second part of the contact structure includes a dielectric layer, a first conductive layer, and a second conductive layer; wherein the dielectric layer, the first conductive layer, and the second conductive layer together form a connection layer; The conductive structure of the first part of the contact structure includes, in a radially outward direction, the connecting layer, the first filling layer, and the connecting layer.

23. The semiconductor device according to claim 22, characterized in that, The third lead-out structure is connected to the two connection layers.

24. The semiconductor device according to claim 18, characterized in that, The contact structure also includes an oxide layer located on the sidewall of the first portion; The dimension of the support structure along the direction perpendicular to the stacking direction is greater than or equal to the distance between the isolation pillar and the oxide layer along the direction perpendicular to the stacking direction.

25. The semiconductor device according to claim 17, characterized in that, The semiconductor device further includes: A gate line isolation structure that runs through the stacked structure along the stacking direction.

26. A memory system, characterized in that, The memory system includes: The semiconductor device as claimed in any one of claims 17 to 25; and A controller coupled to the semiconductor device, the controller being configured to control the semiconductor device.

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