Memory device and manufacturing method of memory device

Abstract

A memory device and a method of manufacturing the memory device are provided. The memory device includes a discharge contact; a source line adjacent to and spaced apart from the discharge contact; an etch stop pattern between the discharge contact and the source line, the etch stop pattern being closer to the source line than to the discharge contact; and a sub-support pattern on the source line and the etch stop pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0098156 filed on July 27, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a memory device and a method of manufacturing the memory device, and more particularly to a memory device including a discharge contact located in a connection area and a method of manufacturing the memory device. Background Art

[0004] The memory device may include a memory cell array in which data is stored, a peripheral circuit configured to perform a program, read, or erase operation of the memory cell array, and a control circuit configured to control the peripheral circuit.

[0005] The memory cell array may include a plurality of memory blocks. When the memory blocks are formed in a three-dimensional structure, the memory blocks may be separated from each other by slit regions.

[0006] The memory block formed in a three-dimensional structure may include a stacked structure in which memory cells are stacked in a vertical direction starting from a substrate. The stacked structure may include a plurality of gate lines and a plurality of insulating layers stacked alternately. The memory block may be located in a cell region of a memory device.

[0007] Connection areas can be specified at both ends of the unit area.

[0008] A discharge contact for removing pseudo ions that may be generated during the manufacturing process of the memory device may be located in the connection area. A source line may be located at the periphery of the discharge contact, and the source line and the discharge contact may be spaced apart from each other. A support pattern may be located on top of the source line. The support pattern may correspond to a structure that supports a stacked structure constituting a memory block.

[0009] The discharge contact may be formed of a conductive material to release pseudo ions. Therefore, the discharge contact should be spaced apart from the source line. When the distance between the source line and the discharge contact is too short compared to the reference distance, a bridge may occur between the source line and the discharge contact during the manufacturing process of the memory device. When the distance between the source line and the discharge contact is too long compared to the reference distance, the size of the memory device may increase. Summary of the invention

[0010] According to one aspect of the present disclosure, a memory device is provided, comprising: a discharge contact; a source line adjacent to the discharge contact and spaced apart from the discharge contact; an etch stop pattern between the discharge contact and the source line, the etch stop pattern being closer to the source line than to the discharge contact; and a sub-support pattern on the source line and the etch stop pattern.

[0011] According to another aspect of the present disclosure, a memory device is provided, comprising: a first portion and a second portion of a source line extending in a first direction, the first portion and the second portion being arranged parallel to each other; a discharge contact between the first portion and the second portion of the source line; a first etch stop pattern between the discharge contact and the first portion of the source line; a second etch stop pattern between the discharge contact and the second portion of the source line; a first sub-support pattern located on an area where first portions of the source lines facing each other are adjacent to and spaced apart from the first etch stop pattern; and a second sub-support pattern located on an area where second portions of the source lines facing each other are adjacent to and spaced apart from the second etch stop pattern.

[0012] According to another aspect of the present disclosure, a method for manufacturing a memory device is provided, the method comprising: forming a first portion and a second portion corresponding to a source line on a peripheral structure and forming an open area insulating layer between the first portion and the second portion; forming a first etch stop pattern adjacent to the first portion and a second etch stop pattern adjacent to the second portion in the open area insulating layer; forming a discharge contact penetrating the open area insulating layer between the first etch stop pattern and the second etch stop pattern; forming a pre-stacked structure on the first portion and the second portion, the first etch stop pattern and the second etch stop pattern, the open area insulating layer and the discharge contact; performing an etching process to form a first trench and a second trench, the first trench exposing a portion of the first etch stop pattern and a portion of the first portion while penetrating the pre-stacked structure, and the second trench exposing a portion of the second etch stop pattern and a portion of the second portion while penetrating the pre-stacked structure; and forming a first sub-support pattern in the first trench and a second sub-support pattern in the second trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments will be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0014] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0015] Figure 1 is a diagram illustrating a memory device;

[0016] Figure 2 is a diagram showing a memory cell array;

[0017] Figure 3 is a plan view showing a memory device according to an embodiment of the present disclosure;

[0018] Figure 4 is a cross-sectional view showing a memory device according to an embodiment of the present disclosure;

[0019] Figure 5 is a perspective view showing a memory device according to an embodiment of the present disclosure;

[0020] FIG. 6A to FIG. 6S is a view showing a method of manufacturing a memory device according to an embodiment of the present disclosure;

[0021] Figure 7 is a diagram showing a memory card system to which the memory device of the present disclosure is applied; and

[0022] Figure 8 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0023] The specific structural and functional descriptions disclosed herein are illustrative only, for the purpose of describing embodiments according to the concepts of the present disclosure. Additional embodiments according to the concepts of the present disclosure can be implemented in various forms. Therefore, the present disclosure should not be interpreted as being limited to the embodiments set forth herein.

[0024] Hereinafter, it should be understood that although the terms "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0025] Embodiments provide a memory device and a method of manufacturing the memory device, which can ensure a margin between a source line and a discharge contact.

[0026] Figure 1 is a diagram showing a memory device.

[0027] refer to Figure 1, the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0028] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line may be connected to each of the first to j-th memory blocks BLK1 to BLKj, and a bit line BL may be commonly connected to the first to j-th memory blocks BLK1 to BLKj.

[0029] The first memory block BLK1 to the j-th memory block BLKj may be formed in a two-dimensional structure or a three-dimensional structure. A memory block having a two-dimensional structure may include memory cells arranged parallel to a substrate. A memory block having a three-dimensional structure may include memory cells stacked in a vertical direction starting from a substrate. In the present embodiment, a memory block formed in a three-dimensional structure is disclosed.

[0030] The memory cell can store one bit or two bits or more of data according to the programming method. For example, the method of storing one bit of data in one memory cell is called a single-level cell (SLC) method, and the method of storing two bits of data in one memory cell is called a multi-level cell (MLC) method. The method of storing three bits of data in one memory cell is called a triple-level cell (TLC) method, and the method of storing four bits of data in one memory cell is called a quad-level cell (QLC) method. In addition, five or more bits of data can be stored in one memory cell.

[0031] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0032] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 is configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, and an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0033] The programming voltage is a voltage applied to the selected word line in the word line WL in the programming operation, and can be used to increase the threshold voltage of the memory cell connected to the selected word line. The on-voltage can be applied to the drain selection line DSL or the source selection line SSL, and can be used to turn on the drain selection transistor or the source selection transistor. The cut-off voltage can be applied to the drain selection line DSL or the source selection line SSL, and can be used to cut off the drain selection transistor or the source selection transistor. For example, the cut-off voltage can be set to 0V. The precharge voltage can be a voltage higher than 0V and can be applied to the bit line in the read operation. The verification voltage can be used in the verification operation to determine whether the threshold voltage of the selected memory cell has increased to the target level. The verification voltage can be set to various levels according to the target level and can be applied to the selected word line.

[0034] In a read operation of a selected memory cell, a read voltage may be applied to the selected word line. For example, the read voltage may be set to various levels according to the programming mode of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line in a word line WL in a programming or read operation, and may be used to turn on a memory cell connected to an unselected word line.

[0035] The erase voltage may be used to erase memory cells included in a selected memory block in an erase operation, and may be applied to the source line SL.

[0036] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the j-th memory block BLKj through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0037] The page buffer group 140 may include a page buffer (not shown) connected to each of the first to j-th memory blocks BLK1 to BLKj. The page buffer (not shown) may be connected to the first to j-th memory blocks BLK1 to BLKj, respectively, through the bit lines BL. In a read operation, in response to a page buffer control signal PBSIG, the page buffer (not shown) may sense a current or voltage of the bit line BL (which varies according to a threshold voltage of a selected memory cell), and may temporarily store the sensed data.

[0038] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL and may transmit an enable signal through the column line. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0039] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller to the control circuit 180 through the input / output line I / O, and may transmit data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0040] The control circuit 180 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation on a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation on the selected memory block and output the read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation on the selected memory block.

[0041] Figure 2 is a diagram showing a memory cell array.

[0042] refer to Figure 2 , the memory cell array 110 may be located on the peripheral circuit 170. For example, the peripheral circuit 170 may be located on one substrate, and the memory cell array 110 may be located on the peripheral circuit 170. Alternatively, the peripheral circuit 170 and the memory cell array 110 may be formed on different substrates, and the peripheral circuit 170 and the memory cell array 110 may contact each other.

[0043] The memory cell array 110 may include a first memory block BLK1 to a j-th memory block BLKj. The first memory block BLK1 to the j-th memory block BLKj may be arranged to be spaced apart from each other along the Y direction. The first memory block BLK1 to the j-th memory block BLKj may be configured identically to each other and may be separated from each other by slit regions 1SR, 2SR, 3SR, ... Each of the slit regions 1SR, 2SR, 3SR, ... may extend along the X direction. For example, the first memory block BLK1 may be located between the first slit region 1SR and the second slit region 2SR, and the second memory block BLK2 may be located between the second slit region 2SR and the third slit region 3SR. The first memory block BLK1 and the second memory block BLK2 may be separated from each other by the second slit region 2SR.

[0044] Each of the first memory block BLK1 to the j-th memory block BLKj may include a cell region CE and a connection region CN. A memory cell configured to store data may be located in the cell region CE, and a plurality of connection structures connected to the peripheral circuit 170 may be located in the connection region CN. For example, the connection structure may include a contact, a line, a support pattern, and a discharge contact. The contact may be configured to contact a gate line extending from the cell region CE, or to contact the peripheral circuit 170 located at the bottom of the memory cell array 110. These lines may be configured to be electrically connected to the contact. The support pattern may be configured to support a stacked structure located in the connection region CN. The discharge contact may be configured to discharge pseudo ions that may be generated during the manufacturing process of the memory device to a ground terminal. For example, pseudo ions may be generated mainly in an etching process. When pseudo ions remain in a partial region of the memory device, the reliability of the operation may be degraded by pseudo ions in the programming, reading, or erasing operations of the memory device. Therefore, the discharge contact may discharge pseudo ions that may be generated during the manufacturing process of the memory device through the ground terminal.

[0045] Figure 3 is a plan view showing a memory device according to an embodiment of the present disclosure.

[0046] refer to Figure 3 , showing Figure 2 1 and 2 show a layout of a first memory block BLK1 among the first to j-th memory blocks BLKj.

[0047] The first memory block BLK1 may be located between the first and second slit structures 1SLT and 2SLT. The first and second slit structures 1SLT and 2SLT may be structures formed in the first and second slit regions 1SR and 2SR and may be formed of an insulating material or a conductive material or may be formed of both.

[0048] The first memory block BLK1 may be divided into a cell region CE and a connection region CN.

[0049] A cell plug CP including a memory cell may be included in the cell region CE. Each of the cell plugs CP may include a core column CR, a channel layer CH, and a memory layer ML, which constitute a memory cell or a selection transistor. The memory layer ML may include a tunnel insulating layer TX, a charge trap layer CG, and a barrier layer BX. The core column CR may have a cylindrical shape and may be formed of an insulating material or a conductive material. The channel layer CH may have a cylindrical shape surrounding the side surface of the core column CR and may be formed of polysilicon. The tunnel insulating layer TX may have a cylindrical shape surrounding the side surface of the channel layer CH and may be formed of an oxide layer. The charge trap layer CG may have a cylindrical shape surrounding the side surface of the tunnel insulating layer TX and may be formed of a nitride layer. The barrier layer BX may have a cylindrical shape surrounding the side surface of the charge trap layer CG and may be formed of an oxide layer. When it is assumed that the first slit structure 1SLT and the second slit structure 2SLT extend along the X direction and are spaced apart from each other along the Y direction, the cell plugs CP extending in the Z direction may be arranged to be spaced apart from each other along the X direction and the Y direction.

[0050] The first support pattern 1SP and the second support pattern 2SP, the contact CT, the discharge contact DCC, and the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be included in the connection region CN. The first support pattern 1SP and the second support pattern 2SP may be configured to support a stacked structure constituting a memory block and may be formed of an insulating material. For example, the first support pattern 1SP and the second support pattern 2SP may be formed of an oxide layer. For example, the first support pattern 1SP and the second support pattern 2SP may be formed of a silicon oxide layer.

[0051] The description of the components will be as follows Figure 3The first support pattern 1SP may be configured in the form of lines connected to each other. For example, the first support pattern 1SP may include a first sub-support pattern 1sSP and a second sub-support pattern 2sSP extending in the X direction, and may be arranged in parallel to each other. In addition, the third sub-support pattern 3sSP may connect the end of the first sub-support pattern 1sSP to the end of the second sub-support pattern 2sSP. The second support pattern 2SP may be configured in the form of islands spaced apart from each other, and may be spaced apart from the first slit structure 1SLT and the second slit structure 2SLT and the first support pattern 1SP. For example, the second support pattern 2SP may be disposed between the first slit structure 1SLT and the first sub-support pattern 1sSP, between the cell plug CP and the third sub-support pattern 3sSP, and between the second slit structure 2SLT and the second sub-support pattern 2sSP. In other words, the second support pattern 2SP may be formed around the first support pattern 1SP within the boundary generated by the first slit structure 1SLT, the second slit structure 2SLT and the cell plug CP. The second support pattern 2SP may be formed in a quadrilateral or circular shape, or may be formed in a curved shape.

[0052] The contact CT and the discharge contact DCC may be located in an area surrounded by the first support pattern 1SP. The contact CT may be configured to electrically connect structures spaced apart from each other in the Z direction. Therefore, the contact CT may be formed by a conductive layer. Although not shown in the figure, in addition to being located in an area surrounded by the first support pattern 1SP, the contact CT may also be located between the second support patterns 2SP.

[0053] The discharge contact DCC can be arranged below the contact CT (eg Figure 4As shown, in the Z direction, below). The discharge contact DCC can be configured to discharge pseudo ions that may be generated during the manufacturing process of the memory device through the ground terminal. Pseudo ions can be mainly generated in a dry etching process. For example, the dry etching process can be mainly performed using a reactive ion etching (RIE) method or a method obtained by applying the RIE method. Plasma can be used in an etching process performed using the RIE method or a method obtained by applying the RIE method. The positive ions generated by the plasma may collide with the etching target layer, and therefore, the binding force of the surface of the etching target layer may be weakened. The molecules at the portion where the binding force is weakened in the etching target layer can be discharged from the chamber together with the free radicals. Some positive ions may remain in the etching target layer. The remaining positive ions may become pseudo ions and may have an impact on the region where the pseudo ions are retained. Therefore, the discharge contact DCC can be located in the region where the pseudo ions are retained and can be electrically connected to the ground terminal. The pseudo ions can be discharged through the discharge contact DCC and the ground terminal to be removed from the memory device.

[0054] In a plan view, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be located between the discharge contact DCC and the corresponding portion of the first support pattern 1SP. The first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of a conductive layer. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of a conductive layer connected to the second source layer SL2 (see Figure 4 ) are formed of the same material. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of a conductive material such as polysilicon, tungsten, or nickel. The first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be spaced apart from the discharge contact DCC and may overlap with the first support pattern 1SP. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may extend in the X direction and may be arranged parallel to each other. The first etch stop pattern ESP1 may be located between the discharge contact DCC and the first sub-support pattern 1sSP, and a portion of the first etch stop pattern ESP1 may overlap with the first sub-support pattern 1sSP. The second etch stop pattern ESP2 may be located between the discharge contact DCC and the second sub-support pattern 2sSP, and a portion of the second etch stop pattern ESP2 may overlap with the second sub-support pattern 2sSP.

[0055] Figure 4 is a cross-sectional view illustrating a memory device according to an embodiment of the present disclosure. Figure 5 is a perspective view showing a memory device according to an embodiment of the present disclosure.

[0056] refer to Figure 4and Figure 5 , which is along the Figure 3 A cross-sectional view of the memory device is shown taken along line A1 - A2 . The peripheral structure PER may be stacked on a substrate SUB on which a contact open region OFC is defined. Figure 1 The peripheral circuit 170 shown may be included in the peripheral structure PER, and a portion of the peripheral circuit 170 may be included in the peripheral structure PER. Figure 4 As shown in . For example, the ground terminal GTN may be included in the substrate SUB that contacts the open area OFC, and the peripheral contact pCT may be located on the ground terminal GTN. The ground terminal GTN may be a junction formed by doping impurities into the substrate SUB, or may be a wire made of a conductive material. When the ground terminal GTN is formed as a wire, the ground terminal GTN may be formed by forming a groove in the substrate SUB and filling a conductive material in the groove. The peripheral wire pMN may be located on the peripheral contact pCT. In the Y direction, the peripheral wire pMN may have a width wider than the width of the peripheral contact pCT. The peripheral contact pCT and the peripheral wire pMN may be formed of a conductive material. The peripheral insulating layer pIS may be formed on the periphery of the peripheral wire pMN and the peripheral contact pCT.

[0057] The source line SL located on the peripheral structure PER may include a first source layer SL1 to a third source layer SL3 and a first buffer layer BF1 and a second buffer layer BF2. The first buffer layer BF1 and the second buffer layer BF2 may be located between the first source layer SL1 to the third source layer SL3. For example, the first buffer layer BF1 may be located on the first source layer SL1, the third source layer SL3 may be located on the first buffer layer BF1, the second buffer layer BF2 may be located on the third source layer SL3, and the second source layer SL2 may be located on the second buffer layer BF2. The first source layer SL1 to the third source layer SL3 may be formed of a conductive material. For example, the first source layer SL1 to the third source layer SL3 may be formed of a conductive material such as polysilicon, tungsten, or nickel. The first buffer layer BF1 and the second buffer layer BF2 may be formed of an insulating layer. For example, the first buffer layer BF1 and the second buffer layer BF2 may be formed of an oxide layer. For example, the first buffer layer BF1 and the second buffer layer BF2 may be formed of a silicon oxide layer.

[0058] The source line SL may be divided into a first portion PR1 and a second portion PR2 relative to the contact open region OFC. In a cross section taken along line A1-A2, the first portion PR1 and the second portion PR2 may be located at both ends of the contact open region OFC, which may appear as if the source line SL is separated by the contact open region OFC. However, the source line SL extends continuously in other cross-sectional views of the memory block. Therefore, the first portion PR1 and the second portion PR2 located at both ends of the contact open region OFC are actually continuous. For example, referring to Figure 3 and Figure 4 Although the source line SL may not be located under the region surrounded by the first support pattern 1SP, the source line SL may be located under the second support pattern 2SP and the cell plug CP (below in the Z direction).

[0059] The discharge contact DCC and the first and second etch stop patterns ESP1 and ESP2 may be located between the source lines SL in the contact open region OFC, and the space between the discharge contact DCC and the first and second etch stop patterns ESP1 and ESP2 may be filled with an open region insulating layer OSI. The discharge contact DCC may contact the peripheral line pMN while penetrating the open region insulating layer OSI through the center of the contact open region OFC. The discharge contact DCC may be formed of a conductive material.

[0060] The first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be located at both sides of the discharge contact DCC and may be spaced apart from the discharge contact DCC. Figure 3, each of the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed in a line shape along the X direction and may be arranged parallel to each other. The first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of a conductive layer. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of the same material as the second source layer SL2. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of a conductive material such as polysilicon, tungsten, or nickel. Each of the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be maintained in a floating state. For example, each of the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may not be in contact with another conductive material. The first etch stop pattern ESP1 may be located between the first portion PR1 of the source line SL and the discharge contact DCC, and the second etch stop pattern ESP2 may be located between the second portion PR2 of the source line SL and the discharge contact DCC. The first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be symmetrical to each other with respect to the discharge contact DCC and may have the same size.

[0061] The first etch stop pattern ESP1 among the first etch stop pattern ESP1 and the second etch stop pattern ESP2 will be described in detail as follows. The first etch stop pattern ESP1 may have a first width W1, which represents the length in the Y direction. The first etch stop pattern ESP1 may be closer to the first portion PR1 of the source line SL than the discharge contact DCC. For example, when it is assumed that the width between the first etch stop pattern ESP1 and the first portion PR1 is the second width W2 and the width between the first etch stop pattern ESP1 and the discharge contact DCC is the third width W3, the third width W3 may be wider than the second width W2. The third width W3 may be narrower than the first width W1. That is, the third width W3 may be narrower than the first width W1, and the second width W2 may be narrower than the third width W3. Reference Figure 4 , the first width W1 may be a length between the left and right surfaces of the first etch stop pattern ESP1, and the third width W3 may be a length between the right surface of the discharge contact DCC and the left surface of the first etch stop pattern ESP1. The second width W2 may be a length between the right surface of the first etch stop pattern ESP1 and the left surface of the first portion PR1 of the source line SL. The ratio of the widths may result in a larger contact area between the first sub-support pattern 1sSP and the second sub-support pattern 2sSP and the first and second etch stop patterns ESP1 and ESP2 than the contact area between the first and second sub-support patterns 1sSP and 2sSP and the first and second portions PR1 and PR2 of the source line SL.

[0062] The width obtained by adding the first to third widths W1 to W3 may be the width between the discharge contact DCC and the source line SL. For example, the width between the discharge contact DCC and the source line SL may be the fourth width W4. The fourth width W4 may provide a sufficient margin to avoid a bridge between the source line SL and the discharge contact DCC due to the first and second etch stop patterns ESP1 and ESP2.

[0063] The stacked structure STK may be located on the source line SL. The stacked structure STK may include a first material layer MT1 and a gate line GL that are alternately stacked. The first material layer MT1 may be formed of an insulating material, and the gate line GL may be formed of a conductive material. For example, the first material layer MT1 may be formed of an oxide layer, and the gate line GL may be formed of a metal material (such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni)) or a semiconductor material (such as silicon (Si) or polycrystalline silicon (poly-Si)). However, the present disclosure is not limited thereto.

[0064] The alternately stacked first and second material layers MT1 and MT2 may be located on the open area insulating layer OSI, the discharge contact DCC, and the first and second etch stop patterns ESP1 and ESP2 contacting the open area OFC. The second material layer MT2 may be formed of a nitride layer.

[0065] The first slit structure 1SLT and the second slit structure 2SLT that penetrate the stack structure STK and a portion of the source line SL may be located on the source line SL. For example, the first slit structure 1SLT may be located on the first portion PR1 of the source line SL, and the second slit structure 2SLT may be located on the second portion PR2 of the source line SL. The first slit structure 1SLT may be located in the first slit region 1SR, and the second slit structure 2SLT may be located in the second slit region 2SR. The first slit structure 1SLT and the second slit structure 2SLT may be formed by an insulating layer or a conductive layer. When the first slit structure 1SLT and the second slit structure 2SLT are formed by an insulating layer, only the first slit structure 1SLT and the second slit structure 2SLT may be formed in the first slit region 1SR and the second slit region 2SR. When the first slit structure 1SLT and the second slit structure 2SLT are formed by a conductive layer, the first slit structure 1SLT and the second slit structure 2SLT and the slit insulating layer SIS located on the sidewalls of the first slit structure 1SLT and the second slit structure 2SLT may be formed in the first slit region 1SR and the second slit region 2SR. When the first slit structure 1SLT and the second slit structure 2SLT are formed by a conductive layer, the first slit structure 1SLT and the second slit structure 2SLT may be source contacts, and the bottom surface of the first slit structure 1SLT and the bottom surface of the second slit structure 2SLT may contact the source line SL. When the first slit structure 1SLT and the second slit structure 2SLT are formed by a conductive layer, the first slit structure 1SLT and the second slit structure 2SLT may be formed by polysilicon, tungsten, nickel, etc. The slit insulating layer SIS may be formed by an oxide layer. For example, the slit insulating layer SIS may be formed by a silicon oxide layer.

[0066] The first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be located between the contact open region OFC and the stack structure STK. The first sub-support pattern 1sSP may be located between the stack structure STK located on the first portion PR1 of the source line SL and the contact open region OFC, and the second sub-support pattern 2sSP may be located between the stack structure STK located on the second portion PR2 of the source line SL and the contact open region OFC. Therefore, the side surface of the first sub-support pattern 1sSP and the side surface of the second sub-support pattern 2sSP located within the contact open region OFC may contact the first material layer MT1 and the second material layer MT2, and the side surface of the first sub-support pattern 1sSP and the side surface of the second sub-support pattern 2sSP located outside the contact open region OFC may contact the first material layer MT1 and the gate line GL. The first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be structures that support the stack structure STK to avoid warping or degradation, and may be formed by an insulating layer. For example, the first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be formed by an oxide layer. For example, the first and second sub-support patterns 1sSP and 2sSP may be formed of a silicon oxide layer. Bottom surfaces of the first and second sub-support patterns 1sSP and 2sSP may contact the source line, the open area insulating layer OSI, and the first and second etch stop patterns ESP1 and ESP2.

[0067] The contact CT may be located between the first sub-support pattern 1sSP and the second sub-support pattern 2sSP. The contact CT may be spaced apart from the first sub-support pattern 1sSP and the second sub-support pattern 2sSP. The side surface of the contact CT may contact the first material layer MT1 and the second material layer MT2, and the bottom of the contact CT may contact the discharge contact DCC. The contact CT may be formed by a conductive layer. For example, the contact CT may be formed by a conductive layer such as polysilicon, tungsten, or nickel.

[0068] In the above structure, when the depth of the groove where the first sub-support pattern 1sSP and the second sub-support pattern 2sSP are located becomes the target depth, the first etching stop pattern ESP1 and the second etching stop pattern ESP2 can be used to stop the etching process. When the depth of the groove becomes the target depth, the etching process for forming the groove stops. To this end, when a component different from the component of the stacked structure STK is detected, the etching process for forming the groove can be stopped. For example, when a component of the source line SL is detected, the etching process can be stopped.

[0069] When the first etching stop pattern ESP1 and the second etching stop pattern ESP2 are not present, when the region of the source line SL exposed by the groove is too narrow, components of the source line may be detected in the later stage of the etching process. That is, when the width between the source line SL and the discharge contact DCC is too wide, an over-etching process may be performed, resulting in exposure of the source line SL and the discharge contact DCC. Therefore, in a subsequent process of forming the third source layer SL3, an electric bridge may occur between the source line SL and the discharge contact DCC. In order to prevent the occurrence of an electric bridge, when the width between the source line SL and the discharge contact DCC is formed to be too narrow, positive ions to be discharged through the source line SL and the discharge contact DCC may move to the source line SL. Therefore, it is important to adjust the width between the source line SL and the discharge contact DCC.

[0070] In this embodiment, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed between the source line SL and the discharge contact DCC so that the width between the source line SL and the discharge contact DCC may be maintained at the fourth width W4. Due to the first etch stop pattern ESP1 and the second etch stop pattern ESP2, the trench filled with the first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be formed to a target depth, and the distance between the source line SL and the discharge contact DCC may be sufficiently ensured.

[0071] FIG. 6A to FIG. 6S is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0072] refer to Fig. 6A , the ground terminal GTN may be formed in a substrate SUB on which a contact open region OFC is defined. The contact open region OFC may be a region in which a structure for electrically connecting the cell region and the peripheral structure PER to each other is to be located. The ground terminal GTN may be formed by doping impurities into the substrate SUB or by forming a trench in the substrate SUB and filling the trench with a conductive material. The ground terminal GTN may be connected to a terminal supplied with a ground voltage.

[0073] The peripheral structure PER may be formed on the substrate SUB. The peripheral structure PER may include a peripheral contact pCT, a peripheral wire pMN, and a peripheral insulating layer pIS. The peripheral contact pCT may be located on the ground terminal GTN, and the peripheral wire pMN may be located on the peripheral contact pCT. The peripheral contact pCT may have a width narrower than that of the ground terminal GTN. The peripheral wire pMN may have a width wider than that of the peripheral contact pCT. The peripheral contact pCT and the peripheral wire pMN may be formed of a conductive material. The peripheral insulating layer pIS may be formed of an oxide layer surrounding the peripheral contact pCT and the peripheral wire pMN. Although not shown in the figure, the peripheral circuit ( Figure 1 The structure included in 170) shown may also be included in the peripheral structure PER.

[0074] The first source layer SL1, the first buffer layer BF1, the sacrificial layer SC, the second buffer layer BF2, and the second source layer SL2 may be sequentially stacked on the peripheral structure PER. The first source layer SL1 and the second source layer SL2 may be formed of a conductive layer, and the first buffer layer BF1 and the second buffer layer BF2 may be formed of an insulating layer. For example, the first source layer SL1 and the second source layer SL2 may be formed of a conductive layer such as polysilicon, tungsten, or nickel, and the first buffer layer BF1 and the second buffer layer BF2 may be formed of an oxide layer such as a silicon oxide layer. The sacrificial layer SC may be formed of the same material as the first source layer SL1 and the second source layer SL2, or may be formed of a material having an etching selectivity different from that of the first buffer layer BF1 and the second buffer layer BF2. For example, the sacrificial layer SC may be formed of a material having an etching selectivity higher than that of the first buffer layer BF1 and the second buffer layer BF2 in a wet etching process. The sacrificial layer SC may be thinner than the first source layer SL1, and the second source layer SL2 may be thinner than the sacrificial layer SC. The first buffer layer BF1 and the second buffer layer BF2 may have the same thickness, and may be thinner than the second source layer SL2 .

[0075] refer to Figure 6B , the second source layer SL2, the second buffer layer BF2, the sacrificial layer SC, the first buffer layer BF1, and the first source layer SL1 formed in the contact open region OFC may be removed, thereby forming a first trench T1 exposing a portion of the peripheral structure PER. For example, the first trench T1 may be formed by performing a dry etching process. The etching process for forming the first trench T1 may be performed until a portion of the peripheral insulating layer pIS included in the peripheral structure PER is exposed.

[0076] refer to Figure 6C, the first trench T1 may be filled with an open area insulating layer OSI. The open area insulating layer OSI may be formed of an oxide layer. For example, the open area insulating layer OSI may be formed of a silicon oxide layer. After the open area insulating layer OSI is formed on the entire structure including the first trench T1, a planarization process is performed until the second source layer SL2 is exposed, so that the open area insulating layer OSI may remain only in the first trench.

[0077] refer to Fig.6D The second trench T2 and the third trench T3 may be formed in the open area insulating layer OSI to form a first etch stop pattern and a second etch stop pattern ( Figure 4 The second trench T2 and the third trench T3 may be formed in an area close to the first portion PR1 and the third trench T3 may be formed in an area close to the second portion PR2. The second trench T2 and the third trench T3 may be formed in an area close to the first portion PR1 and the third trench T3 may be formed in an area close to the second portion PR2. Each of the second trench T2 and the third trench T3 may have a first width W1. The width between the second trench T2 and the first portion PR1 may be a second width W2, and the width between the third trench T3 and the second portion PR2 may also be a second width W2. The second width W2 may be narrower than the first width W1.

[0078] refer to Fig. 6E , the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed in the second trench T2 and the third trench T3. For example, the first etch stop pattern ESP1 may be formed in the second trench T2, and the second etch stop pattern ESP2 may be formed in the third trench T3. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of a conductive layer. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of the same material as the second source layer SL2. For example, the first etch stop pattern ESP1 and the second etch stop pattern ESP2 may be formed of a conductive material such as polysilicon, tungsten, or nickel. After the conductive layer corresponding to the first etch stop pattern ESP1 and the second etch stop pattern ESP2 is formed on the entire structure, a planarization process may be performed until the open area insulating layer OSI is exposed, so that the first etch stop pattern ESP1 and the second etch stop pattern ESP2 remain only in the second trench T2 and the third trench T3.

[0079] refer to Fig. 6F, the open area insulating layer OSI located between the first etch stop pattern ESP1 and the second etch stop pattern ESP2 and a portion of the peripheral insulating layer pIS may be removed, thereby forming a first hole H1 exposing a portion of the peripheral line pMN. The first hole H1 may penetrate the open area insulating layer OSI and may penetrate a portion of the peripheral insulating layer pIS, thereby exposing a portion of the peripheral line pMN. A dry etching process may be performed to form the first hole H1. The width between the first hole H1 and the first etch stop pattern ESP1 or the second etch stop pattern ESP2 may be a third width W3. The third width W3 may be wider than the second width W2, and may be narrower than the first width W1.

[0080] refer to Figure 6G , the discharge contact DCC may be formed in the first hole H1. The discharge contact DCC may be formed of a conductive layer. For example, the discharge contact DCC may be formed of a conductive material such as polysilicon, tungsten, or nickel. Since the discharge contact DCC is formed in a state where the peripheral line pMN is exposed through the bottom surface of the first hole H1, the discharge contact DCC may contact the peripheral line pMN.

[0081] refer to Figure 6H , the pre-stacked structure pSTK can be formed on top of the second source layer SL2, the open area insulating layer OSI, the first etching stop pattern ESP1 and the second etching stop pattern ESP2, and the discharge contact DCC. The pre-stacked structure pSTK can be formed by alternately stacking the first material layer MT1 and the second material layer MT2. For example, the first material layer MT1 can be formed on top of the second source layer SL2, the open area insulating layer OSI, the first etching stop pattern ESP1 and the second etching stop pattern ESP2, and the discharge contact DCC, and the second material layer MT2 can be formed on the first material layer MT1. The first material layer MT1 can be formed again on top of the second material layer MT2, and so on. In this way, a pre-stacked structure pSTK including the first material layer MT1 and the second material layer MT2 stacked alternately can be formed. The first material layer MT1 can be formed of an oxide layer, and the second material layer MT2 can be formed of a material having an etching selectivity different from that of the first material layer MT1. For example, the second material layer MT2 can be formed of a nitride layer.

[0082] refer to Fig.6I, a portion of the pre-stacked structure pSTK may be etched to form a fourth trench T4 and a fifth trench T5 exposing a portion of the second source layer SL2, the open region insulating layer OSI, and the first etching stop pattern ESP1 and the second etching stop pattern ESP2. The fourth trench T4 and the fifth trench T5 may be partially formed in the boundary region of the contact open region OFC. Therefore, the first material layer MT1 and the second material layer MT2 included in the pre-stacked structure pSTK may be isolated into a portion included in the contact open region OFC and a portion included outside the contact open region OFC. The etching process for forming the fourth trench T4 and the fifth trench T5 may be performed as an anisotropic dry etching process. The etching process for forming the fourth trench T4 and the fifth trench T5 may be performed until the second source layer SL2, the first etching stop pattern ESP1, or the second etching stop pattern ESP2 is exposed. For example, when a component of the second source layer SL2, the first etching stop pattern ESP1, or the second etching stop pattern ESP2 is detected, the etching process for forming the fourth trench T4 and the fifth trench T5 may be stopped. The fourth trench T4 may be formed to expose a portion of the first etch stop pattern ESP1 and the second source layer SL2, and the fifth trench T5 may be formed to expose a portion of the second etch stop pattern ESP2 and the second source layer SL2. In the etching process for forming the fourth transistor T4 and the fifth transistor T5, since the area of ​​the second source layer SL2 exposed by the fourth trench T4 and the fifth trench T5 is narrow, even when any component of the second source layer SL2 is not detected, the area where the first etch stop pattern ESP1 and the second etch stop pattern ESP2 are exposed is wider than the area where the second source layer SL2 is exposed. Therefore, a component of the first etch stop pattern ESP1 or the second etch stop pattern ESP2 may be detected. When a component of the first etch stop pattern ESP1 or the second etch stop pattern ESP2 is detected, the etching process may be stopped, so that over-etching of the etching process for forming the fourth trench T4 and the fifth trench T5 may be prevented.

[0083] refer to Figure 6J , the first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be formed in the fourth trench T4 and the fifth trench T5. The first sub-support pattern 1sSP may be formed in the fourth trench T4, and the second sub-support pattern 2sSP may be formed in the fifth trench T5. The first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be formed by an insulating layer. For example, the first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be formed by an oxide layer. For example, the first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be formed by a silicon oxide layer.

[0084] refer to Figure 6K, the sixth trench T6 and the seventh trench T7 may be formed in the first slit region 1SR and the second slit region 2SR of the pre-stacked structure pSTK. The first slit region 1SR and the second slit region 2SR may be regions that divide the memory blocks. Therefore, the sixth trench T6 and the seventh trench T7 may be formed to expose a portion of the sacrificial layer SC while penetrating the pre-stacked structure pSTK, the second source layer SL2, and the second buffer layer BF2. The sixth trench T6 may be formed in the first slit region 1SR, and the seventh trench T7 may be formed in the second slit region 2SR. Since the sixth trench T6 and the seventh trench T7 penetrate the pre-stacked structure pSTK, the first material layer MT1 and the second material layer MT2 may be exposed through the sidewalls of the sixth trench T6 and the seventh trench T7.

[0085] refer to Figure 6L , the second material layer MT2 exposed by the sixth trench T6 and the seventh trench T7 may be removed. For example, an isotropic dry etching process or a wet etching process may be performed to remove the second material layer MT2. Since the second material layer MT2 between the first sub-support pattern 1sSP and the second sub-support pattern 2sSP is not exposed by the first sub-support pattern 1sSP and the second sub-support pattern 2sSP, the second material layer MT2 between the first sub-support pattern 1sSP and the second sub-support pattern 2sSP may remain. As the second material layer MT2 is removed, a first recess REC1 may be formed between the first material layers MT1. The first recess REC1 may refer to an empty space between the first material layers MT1.

[0086] refer to Figure 6M , can be formed by the first recess ( Figure 6L The REC1 shown in the figure is filled with a conductive layer to form a gate line GL. The gate line GL can be formed of a metal material (such as tungsten (W), molybdenum (Mo), cobalt (Co) or nickel (Ni)) or a semiconductor material (such as silicon (Si) or polysilicon (poly-Si)).

[0087] refer to Figure 6N, a sidewall insulating layer (i.e., a slit insulating layer) SIS may be formed on the sidewalls of the sixth trench T6 and the seventh trench T7. The sidewall insulating layer SIS may be formed of an oxide layer. For example, the sidewall insulating layer SIS may be formed of a silicon oxide layer. The sidewall insulating layer SIS may be formed using the following method. For example, after an oxide layer corresponding to the sidewall insulating layer SIS is formed along the surface of the entire structure including the sixth trench T6 and the seventh trench T7, the oxide layer formed on the bottom surface of the sixth trench T6 and the seventh trench T7 and on the top surface of the pre-stacked structure pSTK may be removed. The oxide layer retained on the sidewalls of the sixth trench T6 and the seventh trench T7 may become the sidewall insulating layer SIS. A portion of the sacrificial layer SC may be exposed through the bottom surfaces of the sixth trench T6 and the seventh trench T7 in which the sidewall insulating layer SIS is formed.

[0088] refer to Fig.6O , an etching process for removing the sacrificial layer SC exposed through the sixth trench T6 and the seventh trench T7 may be performed. For example, a wet etching process may be performed as an etching process for removing the sacrificial layer SC. The wet etching process may be performed using an etchant having an etching selectivity to the sacrificial layer SC, which is higher than the etching selectivity to the sidewall insulating layer SIS, the first buffer layer BF1, and the second buffer layer BF2. Therefore, the sacrificial layer SC located between the first buffer layer BF1 and the second buffer layer BF2 may be removed through the sixth trench T6 and the seventh trench T7. As the sacrificial layer SC is removed, a second recess REC2 may be formed between the first buffer layer BF1 and the second buffer layer BF2.

[0089] refer to Figure 6P, the third source layer SL3 may be filled in the second recess REC2. The third source layer SL3 may be formed of the same material as the first source layer SL1 and the second source layer SL2. For example, the third source layer SL3 may be formed of a conductive material such as polysilicon, tungsten, or nickel. As the third source layer SL3 is formed, a source line SL may be formed, which includes the first source layer SL1 to the third source layer SL3 and the first buffer layer BF1 and the second buffer layer BF2. Alternatively, the third source layer SL3 may be formed after removing the first buffer layer BF1 and the second buffer layer BF2. In this embodiment, the first buffer layer BF1 and the second buffer layer BF2 may be retained. However, in some embodiments, the first buffer layer BF1 and the second buffer layer BF2 may be removed. The third source layer SL3 may be formed through the sixth trench and the seventh trench. After the third source layer SL3 is filled in the second recess REC2, the third source layer SL3 can be formed along the lower portion of the side walls of the sixth trench T6 and the seventh trench T7, and therefore, an etching process or a cleaning process for removing a portion of the third source layer SL3 remaining in the sixth trench T6 and the seventh trench T7 can be further performed.

[0090] refer to Figure 6Q , the first slit structure 1SLT and the second slit structure 2SLT may be formed in the sixth trench T6 and the seventh trench T7. The first slit structure 1SLT may be formed in the sixth trench T6, and the second slit structure 2SLT may be formed in the seventh trench T7. The first slit structure 1SLT and the second slit structure 2SLT may be formed of an insulating material or a conductive material. When the first slit structure 1SLT and the second slit structure 2SLT are formed of a conductive material, each of the first slit structure 1SLT and the second slit structure 2SLT may become a source contact contacting the source line SL. The source contact may be a contact that transmits a source voltage to the source line SL.

[0091] refer to Figure 6R, a portion of the first material layer MT1 and the second material layer MT2 between the first sub-support pattern 1sSP and the second sub-support pattern 2sSP may be removed, thereby forming a second hole H2 exposing a portion of the discharge contact DCC. The etching process for forming the second hole H2 may be performed as an anisotropic dry etching process. The anisotropic dry etching process may be performed mainly using a reactive ion etching (RIE) method or a method obtained by applying the RIE method. Plasma may be used in an etching process performed using the RIE method or a method obtained by applying the RIE method. The positive ions generated by the plasma may collide with the etching target layer, and therefore, the bonding force of the surface of the etching target layer may be weakened. The molecules at the portion where the bonding force is weakened in the etching target layer may be discharged from the chamber together with the free radicals. As the depth of the second hole H2 becomes deeper, some positive ions may remain on the lower portion 61 of the second hole H2.

[0092] refer to Figure 6S , a contact CT may be formed in the second hole H2. The contact CT may be formed of a conductive layer. After forming the contact CT, positive ions remaining in the second hole H2 may be discharged from the memory device through the discharge contact DCC and the ground terminal GTN.

[0093] Figure 7 is a diagram showing a memory card system to which the memory device of the present disclosure is applied.

[0094] refer to Figure 7 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0095] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control programming, reading, or erasing operations, or may control background operations of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0096] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. Exemplarily, the controller 3100 can communicate with an external device through at least one of various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced mini disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication protocols mentioned above.

[0097] The memory device 3200 may include a memory unit and may be configured to Figure 1 The memory devices 100 shown are identical.

[0098] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a universal flash storage (UFS).

[0099] Figure 8 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0100] refer to Figure 8 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0101] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one interface, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0102] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured to Figure 1 The illustrated memory devices 100 are identical. A plurality of memory devices 4221 to 422n may communicate with a controller 4210 via channels CH1 to CHn.

[0103] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power input from the host 4100 and charge the power supply PWR. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide power to the SSD 4200. Exemplarily, the auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0104] The buffer memory 4240 may operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0105] According to the present disclosure, since a margin between a source line and a discharge contact is ensured, occurrence of a bridge between the source line and the discharge contact can be prevented, and increase in size of a memory device can be prevented.

[0106] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0107] In the above-described embodiments, all steps may be selectively performed, or some steps may be performed, and steps may be omitted. In each embodiment, the steps do not have to be performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be clear to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0108] Meanwhile, exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many changes within the spirit and scope of the present disclosure. It should be clear to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: Discharge contacts; a source line adjacent to the discharge contact and spaced apart from the discharge contact; an etch stop pattern, located between the discharge contact and the source line, the etch stop pattern being closer to the source line than to the discharge contact; as well as The sub-support pattern is located on the source line and the etching stop pattern.

2. The memory device according to claim 1, wherein the width of the etch stop pattern is a first width, wherein the width between the etch stop pattern and the source line is a second width, and The second width is smaller than the first width.

3. The memory device according to claim 2, wherein a width between the etch stop pattern and the discharge contact is a third width, and The third width is greater than the second width. 4 . The memory device of claim 1 , wherein the etch stop pattern is formed of a same material as the source line. The memory device of claim 1 , wherein the etch stop pattern is formed of a conductive material. 6 . The memory device of claim 1 , wherein the etch stop pattern is formed of polysilicon, tungsten, or nickel.

7. The memory device of claim 1, wherein the discharge contact is formed of a conductive layer.

8. The memory device of claim 1, further comprising: A contact member located on top of the discharge contact member; as well as The peripheral wire, the peripheral contact piece and the ground terminal are located below the discharge contact piece. 9 . The memory device of claim 1 , further comprising a slit structure on the source line, the slit structure being spaced apart from the sub-support pattern. 10 . The memory device of claim 9 , wherein the slit structure is formed of an insulating material or a conductive material. 11 . The memory device of claim 1 , further comprising an open area insulating layer filling a space between the source line and the discharge contact. 12 . The memory device of claim 11 , wherein the etch stop pattern is located in the open area insulating layer. 13 . The memory device of claim 1 , wherein a contact area between the sub-support pattern and the etch stop pattern is larger than a contact area between the sub-support pattern and the source line.

14. A memory device comprising: A first portion and a second portion of a source line extending in a first direction, the first portion and the second portion being arranged parallel to each other; a discharge contact disposed between the first portion and the second portion of the source line; a first etch stop pattern located between the discharge contact and the first portion of the source line; a second etch stop pattern located between the discharge contact and the second portion of the source line; a first sub-support pattern located on a region in which the first portion of the source line is adjacent to and spaced apart from the first etch stop pattern; as well as A second sub-support pattern is located on a region where the second portion of the source line is adjacent to and spaced apart from the second etch stop pattern. 15 . The memory device of claim 14 , wherein the first etch stop pattern and the second etch stop pattern extend in the first direction and are arranged parallel to each other. 16 . The memory device of claim 14 , wherein each of the first etch stop pattern and the second etch stop pattern is floated.

17. The memory device of claim 14, wherein a width between the first etch stop pattern or the second etch stop pattern and the discharge contact is greater than a width between the first etch stop pattern or the second etch stop pattern and the corresponding first portion or the second portion of the source line.

18. The memory device according to claim 14, wherein the first sub-support pattern contacts a portion of the first etch stop pattern and a portion of the first portion of the source line, and The second sub-support pattern contacts a portion of the second etch stop pattern and a portion of the second portion of the source line.

19. A memory device according to claim 18, wherein the contact area between the first etch stop pattern and the second etch stop pattern and the corresponding first sub-support pattern and the second sub-support pattern is greater than the contact area between the first portion and the second portion of the source line and the corresponding first sub-support pattern and the second sub-support pattern. 20 . The memory device of claim 14 , wherein the first and second etch stop patterns are formed of a same material as the source lines contacting the first and second sub-support patterns. 21 . The memory device of claim 14 , wherein the first etch stop pattern and the second etch stop pattern are formed of polysilicon, tungsten, or nickel.

22. A method of manufacturing a memory device, the method comprising: forming a first portion and a second portion corresponding to the source line on the peripheral structure, and forming an open area insulating layer between the first portion and the second portion; forming a first etch stop pattern adjacent to the first portion and a second etch stop pattern adjacent to the second portion in the open area insulating layer; forming a discharge contact penetrating the open region insulating layer between the first etch stop pattern and the second etch stop pattern; forming a pre-stack structure on the first portion and the second portion, the first etch stop pattern and the second etch stop pattern, the open area insulating layer, and the discharge contact; performing an etching process to form a first trench and a second trench, the first trench exposing a portion of the first etch stop pattern and a portion of the first portion while penetrating the pre-stacked structure, and the second trench exposing a portion of the second etch stop pattern and a portion of the second portion while penetrating the pre-stacked structure; as well as A first sub-support pattern is formed in the first trench, and a second sub-support pattern is formed in the second trench.

23. The method of claim 22, wherein forming the first portion and the second portion on the peripheral structure and forming the open area insulating layer between the first portion and the second portion comprises: forming a structure corresponding to the source line on the peripheral structure; allowing the first portion and the second portion to remain by removing a portion of the structure; as well as The open area insulating layer is formed between the first portion and the second portion.

24. The method of claim 23, wherein forming the structure comprises: A first source layer, a first buffer layer, a sacrificial layer, a second buffer layer and a second source layer are sequentially stacked on the peripheral structure. 25 . The method of claim 22 , wherein the first etch stop pattern and the second etch stop pattern are formed of the same material as an uppermost layer among layers included in the first portion and the second portion. 26 . The method of claim 24 , wherein the etching process stops when the first portion, the second portion, the first etch stop pattern, or the second etch stop pattern is exposed.

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