Preparation method of resistive random access memory

Abstract

The present invention provides a method for fabricating a resistive random access memory (RRAM), comprising: providing a substrate having a first bottom electrode formed therein; sequentially forming a first insulating dielectric layer and a second insulating dielectric layer on the substrate; performing a first photolithography process to etch the first and second insulating dielectric layers to form a bottom electrode connection hole; forming a bottom electrode metal layer to fill the bottom electrode connection hole and extend to cover the surface of the second insulating dielectric layer; performing a chemical mechanical polishing process to remove the bottom electrode metal layer from the surface of the second insulating dielectric layer, and forming the bottom electrode connection hole and the bottom electrode metal layer remaining in the bottom electrode connection hole to form a bottom electrode connector; forming a resistive material core layer to cover the second insulating dielectric layer and the bottom electrode connector; and performing a second photolithography process to etch the resistive material core layer to form a resistive core pattern. The present invention achieves process controllability of the RRAM and improves the process window for RRAM fabrication.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a resistive random access memory. Background Art

[0002] The basic structure of the storage unit of the resistive memory is a sandwich structure formed by the first bottom electrode, the resistive material core layer and the top electrode. It is generally integrated between the metal layers of the copper back-end process. The main preparation process includes the preparation process of the bottom electrode, the top electrode, the resistive material core layer, the bottom electrode connector and the top electrode connector. Among them, the bottom electrode connector is to first form the bottom electrode connection hole and then fill the bottom electrode connection hole with metal material, which is basically filled with tungsten or tantalum nitride. At present, filling with tungsten requires the introduction of new equipment for tungsten deposition process and chemical mechanical polishing process, which increases the equipment cost. Filling with tantalum nitride can be extended to the equipment of the copper back-end process without adding new equipment cost. However, the filling property of tantalum nitride is not as good as that of tungsten. The filling height of tantalum nitride needs to be reduced to ensure the filling property of tantalum nitride. In addition, the process window is relatively small, and it is difficult to control the stability of the process. Summary of the Invention

[0003] The object of the present invention is to provide a method for preparing a resistive random access memory, thereby achieving process controllability of the resistive random access memory and improving the process window for preparing the resistive random access memory.

[0004] In order to achieve the above object, the present invention provides a method for preparing a resistive random access memory, comprising:

[0005] providing a substrate, wherein a first bottom electrode is formed on the substrate;

[0006] forming a first insulating dielectric layer and a second insulating dielectric layer in sequence on the substrate, wherein the first insulating dielectric layer and the second insulating dielectric layer are made of different materials;

[0007] Performing a first photolithography process, using the second insulating dielectric layer as a photoresist isolation layer, etching the first insulating dielectric layer and the second insulating dielectric layer to form a bottom electrode connection hole;

[0008] forming a bottom electrode metal layer to fill the bottom electrode connection hole and extend to cover the surface of the second insulating dielectric layer;

[0009] performing a chemical mechanical polishing process, using the second insulating dielectric layer as a polishing stop layer, to remove the bottom electrode metal layer on the surface of the second insulating dielectric layer, wherein the bottom electrode connection hole and the bottom electrode metal layer remaining in the bottom electrode connection hole form a bottom electrode connector, and the bottom electrode connector is electrically connected to the first bottom electrode;

[0010] forming a core layer of resistive material covering the second insulating dielectric layer and the bottom electrode connector; and,

[0011] A second photolithography process is performed to etch the resistive material core layer using the second insulating dielectric layer as an etch stop layer to form a resistive core pattern, wherein the resistive core pattern is electrically connected to the bottom electrode connector.

[0012] Optionally, the material of the first insulating dielectric layer includes silicon nitride, silicon oxynitride or silicon carbide nitride, and the material of the second insulating dielectric layer includes oxide.

[0013] Optionally, the total thickness of the first insulating dielectric layer and the second insulating dielectric layer is 800 angstroms to 1200 angstroms.

[0014] Optionally, the material of the first bottom electrode includes copper, and the material of the bottom electrode metal layer includes tantalum nitride.

[0015] Optionally, the step of performing the first photolithography process includes:

[0016] forming a first photoresist layer covering the second insulating dielectric layer, wherein the second insulating dielectric layer isolates the first photoresist layer from the first insulating dielectric layer;

[0017] patterning the first photoresist layer to form a first patterned photoresist layer;

[0018] Using the first patterned photoresist layer as a mask, the second insulating dielectric layer and the first insulating dielectric layer are sequentially etched to expose the first bottom electrode to form the bottom electrode connection hole.

[0019] Optionally, the step of performing a second photolithography process includes:

[0020] forming a second photoresist layer to cover the resistive material core layer;

[0021] patterning the second photoresist layer to form a second patterned photoresist layer;

[0022] The second patterned photoresist layer is used as a mask to etch the resistive material core layer to form a resistive core pattern.

[0023] Optionally, after etching the resistive material core layer using the second patterned photoresist layer as a mask, the second insulating dielectric layer is further etched downward to expose the first insulating dielectric layer.

[0024] Optionally, after performing the second photolithography process, the method further includes:

[0025] forming a covering dielectric layer to cover the substrate, wherein the covering dielectric layer is filled above the resistive switching core pattern;

[0026] A top electrode is formed in the cover dielectric layer and electrically connected to the resistive switching core pattern.

[0027] Optionally, before forming the top electrode, the method further includes: forming a top electrode connector in the cover dielectric layer, wherein the top electrode and the resistive switching core pattern are electrically connected via the top electrode connector.

[0028] Optionally, the covering dielectric layer includes a first covering dielectric layer and a second covering dielectric layer sequentially formed from bottom to top, the first covering dielectric layer and the first insulating dielectric layer are made of the same material, and the second covering dielectric layer and the second insulating dielectric layer are made of the same material.

[0029] In the preparation method of the resistive random access memory provided by the present invention, a substrate is provided, in which a first bottom electrode is formed; a first insulating dielectric layer and a second insulating dielectric layer are sequentially formed on the substrate, and the materials of the first insulating dielectric layer and the second insulating dielectric layer are different; a first photolithography process is performed, and the second insulating dielectric layer is used as a photoresist isolation layer, and the first insulating dielectric layer and the second insulating dielectric layer are etched to form a bottom electrode connection hole; a bottom electrode metal layer is formed to fill the bottom electrode connection hole and extend to cover the surface of the second insulating dielectric layer; a chemical mechanical polishing process is performed, and the second insulating dielectric layer is used as a polishing stop layer, and the bottom electrode metal layer on the surface of the second insulating dielectric layer is removed, and the bottom electrode connection hole and the bottom electrode metal layer retained in the bottom electrode connection hole form a bottom electrode connector, and the bottom electrode connector is electrically connected to the first bottom electrode; a resistive material core layer is formed to cover the second insulating dielectric layer and the bottom electrode connector; and a second photolithography process is performed, and the second insulating dielectric layer is used as an etch stop layer, and the resistive material core layer is etched to form a resistive core pattern, and the resistive core pattern is electrically connected to the bottom electrode connector. The present invention forms two insulating dielectric layers, namely a first insulating dielectric layer and a second insulating dielectric layer. The second insulating layer can serve as a photoresist isolation layer in a first photolithography process for forming a bottom electrode connection hole, as a polishing stop layer in a chemical mechanical polishing process for a bottom electrode metal layer, and as an etching stop layer in a second photolithography process for forming a resistive switching core pattern. This achieves process controllability of a resistive switching memory and improves the process window for preparing the resistive switching memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A flow chart of a method for preparing a resistive random access memory provided by the present invention;

[0031] Figures 2A to 2J Schematic cross-sectional view of corresponding steps in the method for preparing a resistive random access memory provided in the first embodiment of the present invention;

[0032] Figure 3 Schematic cross-sectional view of corresponding steps in the method for preparing a resistive random access memory provided in the second embodiment of the present invention;

[0033] Figures 4A to 4C Schematic cross-sectional view of corresponding steps in the method for preparing a resistive random access memory provided in the third embodiment of the present invention;

[0034] Figure 5 Schematic cross-sectional view of corresponding steps in the method for preparing a resistive random access memory provided in the fourth embodiment of the present invention.

[0035] Wherein, the accompanying drawings are marked as follows:

[0036] 10-substrate; 21-first bottom electrode; 22-second bottom electrode; 31-first insulating dielectric layer; 32-second insulating dielectric layer; 41-first photoresist layer; 42-first patterned photoresist layer; 43-second patterned photoresist layer; 50-bottom electrode connection hole; 52-bottom electrode connector; 60-bottom electrode metal layer; 70-resistive material core layer; 71-bottom metal layer; 72-resistive layer; 73-top metal layer; 74-resistive core pattern; 80-covering dielectric layer; 81-first covering dielectric layer; 82-second covering dielectric layer; 91-first top electrode connector; 92-second top electrode connector; 110-first top electrode; 120-second top electrode. DETAILED DESCRIPTION

[0037] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0038] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, and "one end" and "the other end" generally refer to two corresponding parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] Figure 1This is a flow chart of the method for preparing the resistive random access memory provided by the present invention. Figure 1 This embodiment provides a method for preparing a resistive random access memory, comprising:

[0040] Step S1: providing a substrate, wherein a first bottom electrode is formed in the substrate;

[0041] Step S2: forming a first insulating dielectric layer and a second insulating dielectric layer in sequence on the substrate, wherein the first insulating dielectric layer and the second insulating dielectric layer are made of different materials;

[0042] Step S3: performing a first photolithography process, using the second insulating dielectric layer as a photoresist isolation layer, etching the first insulating dielectric layer and the second insulating dielectric layer to form a bottom electrode connection hole;

[0043] Step S4: forming a bottom electrode metal layer to fill the bottom electrode connection hole and extend to cover the surface of the second insulating dielectric layer;

[0044] Step S5: performing a chemical mechanical polishing process, using the second insulating dielectric layer as a polishing stop layer, removing the bottom electrode metal layer on the surface of the second insulating dielectric layer, and forming a bottom electrode connector through the bottom electrode connection hole and the bottom electrode metal layer remaining in the bottom electrode connection hole, and the bottom electrode connector is electrically connected to the first bottom electrode;

[0045] Step S6: forming a core layer of resistive switching material to cover the second insulating dielectric layer and the bottom electrode connector;

[0046] Step S7: performing a second photolithography process, using the second insulating dielectric layer as an etch stop layer, etching the resistive material core layer to form a resistive core pattern, and electrically connecting the resistive core pattern to the bottom electrode connector.

[0047] Example 1

[0048] Figures 2A to 2J The cross-sectional diagram of the corresponding steps in the method for preparing the resistive random access memory provided in the first embodiment is shown below in conjunction with Figures 2A to 2J The method for preparing the resistive random access memory provided in the first embodiment is described in detail.

[0049] Please refer to Figure 2A, perform step S1: provide a substrate 10. The substrate 10 may include a semiconductor material, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate; the substrate 10 may also include an integrated circuit, such as a MOS transistor, a triode, or a diode; the substrate 10 may also include an interconnect layer, such as a copper interconnect layer or a graphene interconnect layer; the substrate 10 may also include an insulating dielectric layer, such as a silicon oxide layer or a silicon nitride layer. In this embodiment, the substrate 10 has been formed with a copper back-end process to form a bottom electrode, that is, the substrate 10 includes a first bottom electrode 21 and a second bottom electrode 22, wherein the material of the first bottom electrode 21 and the second bottom electrode 22 includes copper, wherein the substrate 10 includes a logic region and an array region, wherein the storage cells of the resistive random access memory are located on the array region, the first bottom electrode 21 is located in the array region, and the second bottom electrode 22 is located in the logic region.

[0050] Please continue to refer to Figure 2A , step S2 is performed: a deposition process is performed to sequentially form a first insulating dielectric layer 31 and a second insulating dielectric layer 32 on the substrate 10, that is, the first insulating dielectric layer 31 covers the substrate 10, the first bottom electrode 21 and the second bottom electrode 22, and the second insulating dielectric layer 32 covers the first insulating dielectric layer 31. In this embodiment, the first insulating dielectric layer 31 and the second insulating dielectric layer 32 are made of different materials. The material of the first insulating dielectric layer 31 includes silicon nitride, silicon oxynitride or silicon carbide nitride, such as Si3N4, SiN x , SiON, SiCN, the material of the second insulating dielectric layer 32 includes oxides, such as SiO2, SiO x , PEOX, PETOES, USG, FSG, not limited to the above materials; the total thickness of the first insulating dielectric layer 31 and the second insulating dielectric layer 32 is preferably 800 angstroms to 1200 angstroms, for example, 800 angstroms, 1000 angstroms and 1200 angstroms, and the thickness of the first insulating dielectric layer 31 is greater than the thickness of the second insulating dielectric layer 32.

[0051] Please refer to Figure 2B and Figure 2C , executing step S3: the step of performing the first photolithography process includes:

[0052] A first photoresist layer 41 is formed to cover the second insulating dielectric layer 32 . The second insulating dielectric layer 32 isolates the first photoresist layer 41 from the first insulating dielectric layer 31 .

[0053] The first photoresist layer 41 is patterned to form a first patterned photoresist layer 42. Since the material of the first insulating dielectric layer 31 contains nitrogen, the second insulating dielectric layer 32 is used as a photoresist isolation layer to prevent the first photoresist layer 41 from being reacted by the nitrogen. If the first photoresist layer 41 is reacted by the nitrogen, photoresist residue will appear at the patterned position (opening) when forming the first patterned photoresist layer 42, affecting the pattern transfer. Therefore, the second insulating dielectric layer 32 is required as a photoresist isolation layer.

[0054] Using the first patterned photoresist layer 42 as a mask, the second insulating dielectric layer 32 and the first insulating dielectric layer 31 are sequentially etched to expose the first bottom electrode 21 and form a bottom electrode connection hole 50. The bottom electrode connection hole 50 vertically penetrates the second insulating dielectric layer 32 and the first insulating dielectric layer 31. Then, the first patterned photoresist layer 42 is removed.

[0055] Please refer to Figure 2D , execute step S4: form a bottom electrode metal layer 60 to fill the bottom electrode connection hole and extend to cover the surface of the second insulating dielectric layer 32. In this embodiment, the material of the bottom electrode metal layer 60 includes tantalum nitride. Filling with tantalum nitride can be extended to the equipment of the copper back-end process for forming the bottom electrode without adding additional equipment costs.

[0056] Please refer to Figure 2E , perform step S5: perform a chemical mechanical polishing process, use the second insulating dielectric layer 32 as a polishing stop layer, remove the bottom electrode metal layer on the surface of the second insulating dielectric layer 32, and form a bottom electrode connector 52 through the bottom electrode connection hole and the bottom electrode metal layer retained in the bottom electrode connection hole. The bottom electrode connector 52 is electrically connected to the first bottom electrode 21, wherein the bottom electrode connector 52 is located directly above the first bottom electrode 21 and covers at least a portion of the top surface of the first bottom electrode 21.

[0057] Please refer to Figure 2F , step S6 is performed: forming a resistive material core layer 70 to cover the second insulating dielectric layer 32 and the bottom electrode connector 52. In this embodiment, the resistive material core layer 70 includes a bottom metal layer 71, a resistive layer 72, and a top metal layer 73 stacked in sequence from bottom to top. The materials of the bottom metal layer 71 and the top metal layer 73 include one or more of TiN, TaN, Al, Ir, Pt, Au, W, Ti, and Ta. The material of the resistive layer 72 includes TaO x , HfO x 、AlO x 、TiO x , CuO x One or more of, but not limited to, the above materials.

[0058] Please refer to Figure 2G and Figure 2H, executing step S7: the step of performing the second photolithography process includes:

[0059] A second photoresist layer (the complete second photoresist layer is not shown in the figure) is formed to cover the resistive material core layer 70 , that is, the second photoresist layer covers the top metal layer 73 .

[0060] The second photoresist layer is patterned to form a second patterned photoresist layer 43 . The second patterned photoresist layer 43 is located directly above the bottom electrode connector 52 .

[0061] The second patterned photoresist layer 43 is used as a mask and the second insulating dielectric layer 32 is used as an etching stop layer to etch the resistive material core layer 70 (the top metal layer 73, the resistive layer 72 and the bottom metal layer 71 are etched in sequence) to form a resistive core pattern 74. The resistive core pattern 74 is electrically connected to the bottom electrode connector 52. The resistive core pattern 74 is located directly above the bottom electrode connector 52 and at least covers the top surface of the bottom electrode connector 52. It can also extend to cover a portion of the top surface of the second insulating dielectric layer 32. That is, the width of the resistive core pattern 74 is greater than or equal to the width of the bottom electrode connector 52 (the width is Figure 2H In this embodiment, after etching the resistive material core layer 70 using the second patterned photoresist layer 43 as a mask, the second insulating dielectric layer 32 is further etched downward to expose the first insulating dielectric layer 31. Then, the second patterned photoresist layer 43 is removed.

[0062] Please refer to Figure 2I Furthermore, after performing the second photolithography process, the process further includes forming a cover dielectric layer 80 to cover the substrate 10. In this embodiment, the cover dielectric layer 80 covers the first insulating dielectric layer 31 and the resistive core pattern 74, and the cover dielectric layer 80 fills the upper portion of the resistive core pattern 74. In this embodiment, the cover dielectric layer 80 includes a first cover dielectric layer 81 and a second cover dielectric layer 82 formed sequentially from bottom to top, which helps improve the etching selectivity and subsequently forms a top electrode connector with a better morphology by etching. The first cover dielectric layer 81 is made of the same material as the first insulating dielectric layer 31, and the second cover dielectric layer 82 is made of the same material as the second insulating dielectric layer 32.

[0063] Please refer to Figure 2JFurthermore, after forming the covering dielectric layer 80, the method further includes: first forming a top electrode connection hole and a top electrode groove (not shown in the figure) in the covering dielectric layer 80, and then filling the top electrode connection hole and the top electrode groove with a metal material to form a top electrode connector and a top electrode, specifically forming a first top electrode connector 91 and a second top electrode connector 92 and a first top electrode 110 and a second top electrode 120, the first top electrode connector 91 penetrates part of the thickness of the second covering dielectric layer 82 and the first covering dielectric layer 81 and is electrically connected to the resistive core pattern 74, the first top electrode 110 is located above the first top electrode connector 91 and penetrates the second top electrode connector 92. Part of the thickness of the second covering dielectric layer 82 is electrically connected to the first top electrode connector 91, the second top electrode connector 92 passes through part of the thickness of the second covering dielectric layer 82, the first covering dielectric layer 81 and the first insulating dielectric layer 31 and is electrically connected to the second bottom electrode 22, the second top electrode 120 is located above the second top electrode connector 92 and passes through part of the thickness of the second covering dielectric layer 82 and is electrically connected to the second top electrode connector 92, that is, the second top electrode 120 is electrically connected to the second bottom electrode 22 through the second top electrode connector 92, and the first top electrode 110 is electrically connected to the resistive core pattern 74 through the first top electrode connector 91.

[0064] In this embodiment, by forming two insulating dielectric layers, namely a first insulating dielectric layer and a second insulating dielectric layer, the second insulating layer can serve as a photoresist isolation layer in the first photolithography process for forming the bottom electrode connection hole, as a polishing stop layer in the chemical mechanical polishing process of the bottom electrode metal layer, and as an etching stop layer in the second photolithography process for forming the resistive switching core pattern, thereby realizing the process controllability of the resistive switching memory and improving the process window for the preparation of the resistive switching memory.

[0065] Example 2

[0066] Figure 3 The cross-sectional diagram of the corresponding steps in the method for preparing the resistive random access memory provided in the second embodiment is shown below in conjunction with Figure 3 The preparation method of the resistive random access memory provided in the second embodiment is described in detail. Figure 3 The difference between this embodiment and the first embodiment is that, in this embodiment, the first top electrode 110 is directly in contact with the resistive core pattern 74 to achieve electrical connection, that is, no top electrode connector is formed between the first top electrode 110 and the resistive core pattern 74. In this embodiment, the first top electrode 110 penetrates the second cover dielectric layer 82 and the first cover dielectric layer 81 and is electrically connected to the resistive core pattern 74, which helps to reduce the height of the resistive memory. Other than that, the same as the first embodiment.

[0067] Example 3

[0068] Figures 4A to 4CThe cross-sectional diagram of the corresponding steps in the method for preparing the resistive random access memory provided in the third embodiment is shown below in conjunction with Figures 4A to 4C The method for manufacturing the resistive random access memory provided in the third embodiment is described in detail. The difference between the third embodiment and the first embodiment lies in the step of performing the second photolithography process. Other aspects are the same as those of the first embodiment.

[0069] Please refer to Figure 4A , the step of performing the second photolithography process includes:

[0070] A second photoresist layer (the complete second photoresist layer is not shown in the figure) is formed to cover the resistive material core layer 70 , that is, the second photoresist layer covers the top metal layer 73 .

[0071] The second photoresist layer is patterned to form a second patterned photoresist layer 43 . The second patterned photoresist layer 43 is located directly above the bottom electrode connector 52 .

[0072] The second patterned photoresist layer 43 is used as a mask and the second insulating dielectric layer 32 is used as an etching stop layer to etch the resistive material core layer 70 (the top metal layer 73, the resistive layer 72 and the bottom metal layer 71 are etched in sequence) to form a resistive core pattern 74. The resistive core pattern 74 is electrically connected to the bottom electrode connector 52. The resistive core pattern 74 is located directly above the bottom electrode connector 52 and at least covers the top surface of the bottom electrode connector 52. It can also extend to cover a portion of the top surface of the second insulating dielectric layer 32. That is, the width of the resistive core pattern 74 is greater than or equal to the width of the bottom electrode connector 52 (the width is Figure 4A In this embodiment, after etching the resistive material core layer 70 using the second patterned photoresist layer 43 as a mask, the second insulating dielectric layer 32 is not further etched downward to expose the first insulating dielectric layer 31 as in the first embodiment. That is, the second insulating dielectric layer 32 is retained. Subsequently, the second patterned photoresist layer 43 is removed.

[0073] Please refer to Figure 4B Furthermore, after performing the second photolithography process, the process further includes forming a cover dielectric layer 80 to cover the substrate 10. In this embodiment, the cover dielectric layer 80 covers the second insulating dielectric layer 32 and the resistive core pattern 74, and the cover dielectric layer 80 fills the upper portion of the resistive core pattern 74. In this embodiment, the cover dielectric layer 80 includes a first cover dielectric layer 81 and a second cover dielectric layer 82 formed sequentially from bottom to top, which helps improve the etching selectivity and subsequently forms a top electrode connector with a better morphology by etching. The first cover dielectric layer 81 is made of the same material as the first insulating dielectric layer 31, and the second cover dielectric layer 82 is made of the same material as the second insulating dielectric layer 32.

[0074] Please refer to Figure 4CFurthermore, after forming the covering dielectric layer 80, the present invention further includes: first forming a top electrode connection hole and a top electrode groove (not shown in the figure) in the covering dielectric layer 80, and then filling the top electrode connection hole and the top electrode groove with a metal material to form a top electrode connector and a top electrode, specifically forming a first top electrode connector 91 and a second top electrode connector 92 and a first top electrode 110 and a second top electrode 120, the first top electrode connector 91 penetrates a portion of the thickness of the second covering dielectric layer 82 and is electrically connected to the first covering dielectric layer 81 and the resistive core pattern 74, the first top electrode 110 is located above the first top electrode connector 91 and penetrates the second covering dielectric layer 82. Part of the thickness of layer 82 is electrically connected to the first top electrode connector 91, the second top electrode connector 92 passes through part of the thickness of the second covering dielectric layer 82, the first covering dielectric layer 81, the second insulating dielectric layer 32 and the first insulating dielectric layer 31 and is electrically connected to the second bottom electrode 22, the second top electrode 120 is located above the second top electrode connector 92 and passes through part of the thickness of the second covering dielectric layer 82 and is electrically connected to the second top electrode connector 92, that is, the second top electrode 120 is electrically connected to the second bottom electrode 22 through the second top electrode connector 92, and the first top electrode 110 and the resistive core graphic 74 are electrically connected through the first top electrode connector 91.

[0075] Example 4

[0076] Figure 5 The cross-sectional diagram of the corresponding steps in the method for preparing the resistive random access memory provided in the fourth embodiment is shown below in conjunction with Figure 5 The preparation method of the resistive random access memory provided in the fourth embodiment is described in detail. Figure 5 The difference between this embodiment and the third embodiment is that, in this embodiment, the first top electrode 110 is directly in contact with the resistive core pattern 74 to achieve electrical connection, that is, no top electrode connector is formed between the first top electrode 110 and the resistive core pattern 74. In this embodiment, the first top electrode 110 penetrates the second cover dielectric layer 82 and the first cover dielectric layer 81 and is electrically connected to the resistive core pattern 74, which helps to reduce the height of the resistive memory. Otherwise, the same as the third embodiment.

[0077] In summary, in the preparation method of the resistive memory provided by the present invention, a substrate is provided, in which a first bottom electrode is formed; a first insulating dielectric layer and a second insulating dielectric layer are sequentially formed on the substrate, and the materials of the first insulating dielectric layer and the second insulating dielectric layer are different; a first photolithography process is performed, and the second insulating dielectric layer is used as a photoresist isolation layer, and the first insulating dielectric layer and the second insulating dielectric layer are etched to form a bottom electrode connection hole; a bottom electrode metal layer is formed to fill the bottom electrode connection hole and extend to cover the surface of the second insulating dielectric layer; a chemical mechanical polishing process is performed, and the second insulating dielectric layer is used as a polishing stop layer, and the bottom electrode metal layer on the surface of the second insulating dielectric layer is removed, and the bottom electrode connection hole and the bottom electrode metal layer retained in the bottom electrode connection hole form a bottom electrode connector, and the bottom electrode connector is electrically connected to the first bottom electrode; a resistive material core layer is formed to cover the second insulating dielectric layer and the bottom electrode connector; and a second photolithography process is performed, and the second insulating dielectric layer is used as an etch stop layer, and the resistive material core layer is etched to form a resistive core pattern, and the resistive core pattern is electrically connected to the bottom electrode connector. The present invention forms two insulating dielectric layers, namely a first insulating dielectric layer and a second insulating dielectric layer. The second insulating layer can serve as a photoresist isolation layer in a first photolithography process for forming a bottom electrode connection hole, as a polishing stop layer in a chemical mechanical polishing process for a bottom electrode metal layer, and as an etching stop layer in a second photolithography process for forming a resistive switching core pattern. This achieves process controllability of a resistive switching memory and improves the process window for preparing the resistive switching memory.

[0078] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for preparing a resistive random access memory, characterized in that: include: providing a substrate, wherein a first bottom electrode is formed on the substrate; forming a first insulating dielectric layer and a second insulating dielectric layer in sequence on the substrate, wherein the first insulating dielectric layer and the second insulating dielectric layer are made of different materials; Performing a first photolithography process, using the second insulating dielectric layer as a photoresist isolation layer, etching the first insulating dielectric layer and the second insulating dielectric layer to form a bottom electrode connection hole; forming a bottom electrode metal layer to fill the bottom electrode connection hole and extend to cover the surface of the second insulating dielectric layer; performing a chemical mechanical polishing process, using the second insulating dielectric layer as a polishing stop layer, to remove the bottom electrode metal layer on the surface of the second insulating dielectric layer, wherein the bottom electrode connection hole and the bottom electrode metal layer remaining in the bottom electrode connection hole form a bottom electrode connector, and the bottom electrode connector is electrically connected to the first bottom electrode; forming a core layer of resistive material to cover the second insulating dielectric layer and the bottom electrode connector; as well as, A second photolithography process is performed to etch the resistive material core layer using the second insulating dielectric layer as an etch stop layer to form a resistive core pattern, wherein the resistive core pattern is electrically connected to the bottom electrode connector.

2. The method for preparing a resistive random access memory according to claim 1, wherein: The material of the first insulating dielectric layer includes silicon nitride, silicon oxynitride or silicon carbide nitride, and the material of the second insulating dielectric layer includes oxide.

3. The method for preparing a resistive random access memory according to claim 2, wherein: The total thickness of the first insulating dielectric layer and the second insulating dielectric layer is 800 angstroms to 1200 angstroms.

4. The method for preparing a resistive random access memory according to claim 1, wherein: The material of the first bottom electrode includes copper, and the material of the bottom electrode metal layer includes tantalum nitride.

5. The method for preparing a resistive random access memory according to claim 1, wherein: The steps of performing a first photolithography process include: forming a first photoresist layer covering the second insulating dielectric layer, wherein the second insulating dielectric layer isolates the first photoresist layer from the first insulating dielectric layer; patterning the first photoresist layer to form a first patterned photoresist layer; Using the first patterned photoresist layer as a mask, the second insulating dielectric layer and the first insulating dielectric layer are sequentially etched to expose the first bottom electrode to form the bottom electrode connection hole.

6. The method for preparing a resistive random access memory according to claim 1, wherein: The steps of performing the second photolithography process include: forming a second photoresist layer to cover the resistive material core layer; patterning the second photoresist layer to form a second patterned photoresist layer; The second patterned photoresist layer is used as a mask to etch the resistive material core layer to form a resistive core pattern.

7. The method for preparing a resistive random access memory according to claim 6, wherein: After etching the resistive material core layer using the second patterned photoresist layer as a mask, the second insulating dielectric layer is further etched downward to expose the first insulating dielectric layer.

8. The method for preparing a resistive random access memory according to claim 1 or 7, wherein: After performing the second photolithography process, the method further includes: forming a covering dielectric layer to cover the substrate, wherein the covering dielectric layer is filled above the resistive switching core pattern; A top electrode is formed in the cover dielectric layer and electrically connected to the resistive switching core pattern.

9. The method for preparing a resistive random access memory according to claim 8, wherein: Before forming the top electrode, the method further includes: forming a top electrode connector in the cover dielectric layer, wherein the top electrode and the resistive switching core pattern are electrically connected via the top electrode connector.

10. The method for preparing a resistive random access memory according to claim 8, wherein: The cover dielectric layer includes a first cover dielectric layer and a second cover dielectric layer formed sequentially from bottom to top. The first cover dielectric layer is made of the same material as the first insulating dielectric layer, and the second cover dielectric layer is made of the same material as the second insulating dielectric layer.

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