Resistive random access memory and preparation method thereof
By setting up the core graphics and bottom electrode in the dislocation of the storage memory, the length of the electrical connection is increased, and the string of the string of the memory in the low resistance state in the low resistance state will cause the breakdown failure, and the protection of the breakdown is achieved.
Patent Information
- Application Number
- CN202310932333.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-27
- Publication Date
- 2025-01-28
AI Technical Summary
Resistive variable memory is prone to breakdown failure during high voltage operation, mainly because its series resistance is small in low resistance operation.
By setting up the core graphics and the first bottom electrode in the blocking memory, the electrical connection length between them is increased by the vertical dislocation settings, thereby increasing the series resistance of the memory.
The increasing series resistance plays a partial pressure when the blocking memory is in a low resistance operation state, effectively preventing the memory from overloading.
Smart Images
Figure CN119383981A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a resistive random access memory and a preparation method thereof. Background Art
[0002] The basic structure of the storage unit of the resistive memory is a sandwich structure consisting of a bottom electrode, a resistive material core layer and a top electrode, which is generally integrated between the metal layers of the copper back-end process. The main preparation processes include the preparation processes of the bottom electrode, the top electrode, the resistive material core layer, the bottom electrode connector and the top electrode connector. The resistive memory has two operating states: high resistance and low resistance. In the low resistance operating state, the series resistance in the resistive memory is generally only a hundred ohms, which can easily cause the resistive memory to fail due to breakdown when operated at high voltage. Summary of the invention
[0003] The object of the present invention is to provide a resistive random access memory and a method for preparing the same, so as to increase the series resistance of the resistive random access memory to prevent the resistive random access memory from being overloaded and broken down.
[0004] In order to achieve the above object, the present invention provides a resistive random access memory, comprising:
[0005] a substrate having a first bottom electrode formed therein;
[0006] an insulating dielectric layer, located on the substrate;
[0007] A bottom electrode connecting line, which vertically penetrates the insulating dielectric layer, and a portion of the lower surface of the bottom electrode connecting line contacts the first bottom electrode to be electrically connected;
[0008] A resistive switching core pattern is located on the bottom electrode connection line, and a portion of the upper surface of the bottom electrode connection line contacts the resistive switching core pattern to be electrically connected;
[0009] The resistive switching core pattern and the first bottom electrode are staggered in the longitudinal direction to increase the electrical connection length between the resistive switching core pattern and the first bottom electrode.
[0010] Optionally, the resistive switching core pattern and the first bottom electrode are electrically connected to two ends of the bottom electrode connection line in an extension direction, respectively.
[0011] Optionally, the length of the bottom electrode connecting line is 50 μm to 5000 μm.
[0012] Optionally, the bottom electrode connecting line is straight or arc-shaped.
[0013] Optionally, the filling material of the bottom electrode connecting line includes tungsten.
[0014] Optionally, a covering dielectric layer is further included, wherein the covering dielectric layer covers the insulating dielectric layer, the resistive switching core pattern and the bottom electrode connecting line, and the top surface of the covering dielectric layer is flat.
[0015] Optionally, a top electrode is further included, and the top electrode penetrates the covering dielectric layer and is electrically connected to the resistive switching core pattern.
[0016] The present invention also provides a method for preparing a resistive random access memory, comprising:
[0017] forming a substrate, wherein a first bottom electrode is formed in the substrate;
[0018] forming an insulating dielectric layer on the substrate;
[0019] forming a bottom electrode connecting line that vertically penetrates the insulating dielectric layer, wherein a portion of the lower surface of the bottom electrode connecting line contacts the first bottom electrode to be electrically connected; and,
[0020] A resistive switching core pattern is formed on the bottom electrode connection line, and a portion of the upper surface of the bottom electrode connection line contacts the resistive switching core pattern to be electrically connected;
[0021] The resistive switching core pattern and the first bottom electrode are staggered in the longitudinal direction to increase the electrical connection length between the resistive switching core pattern and the first bottom electrode.
[0022] Optionally, the step of forming the bottom electrode connecting line includes:
[0023] Performing a first photolithography process to etch the insulating dielectric layer to form a bottom electrode connection groove, wherein the bottom electrode connection groove exposes a portion of the surface of the substrate and the first bottom electrode;
[0024] The bottom electrode connection groove is filled with metal material to form the bottom electrode connection line.
[0025] Optionally, the step of forming the resistive switching core pattern includes:
[0026] Forming a resistive switching core material layer to cover the insulating dielectric layer and the bottom electrode connecting line;
[0027] A second photolithography process is performed to etch the resistive switching core material layer to form the resistive switching core pattern.
[0028] The resistive memory and the preparation method thereof provided by the present invention include: a substrate, an insulating dielectric layer, a bottom electrode connection line and a resistive core pattern, wherein a first bottom electrode is formed in the substrate, the insulating dielectric layer is located on the substrate, the bottom electrode connection line vertically penetrates the insulating dielectric layer, a part of the lower surface of the bottom electrode connection line contacts the first bottom electrode for electrical connection, the resistive core pattern is located on the bottom electrode connection line, and a part of the upper surface of the bottom electrode connection line contacts the resistive core pattern for electrical connection; in the present invention, the resistive core pattern and the first bottom electrode are staggered in the longitudinal direction to increase the electrical connection length between the resistive core pattern and the first bottom electrode, and the increased electrical connection length is used to increase the series resistance of the resistive memory, and when the resistive memory is in a low-resistance operation state, the increased series resistance plays a voltage dividing role, which can prevent the resistive memory from overload breakdown. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A flowchart of a method for preparing a resistive random access memory provided by an embodiment of the present invention;
[0030] Figures 2A to 2G A schematic cross-sectional view of corresponding steps in a method for preparing a resistive random access memory provided by an embodiment of the present invention.
[0031] Wherein, the accompanying drawings are marked as follows:
[0032] 10-substrate; 21-first bottom electrode; 22-second bottom electrode; 30-insulating dielectric layer; 31-first insulating dielectric layer; 32-second insulating dielectric layer; 41-first patterned photoresist layer; 42-second patterned photoresist layer; 50-bottom electrode connecting groove; 52-bottom electrode connecting line; 60-bottom electrode connecting hole; 62-bottom electrode connector; 70-resistive material core layer; 71-bottom metal layer; 72-resistive layer; 73-top metal layer; 74-resistive core pattern; 80-covering dielectric layer; 81-first covering dielectric layer; 82-second covering dielectric layer; 83-third covering dielectric layer; 84-fourth covering dielectric layer; 90-top electrode connector; 110-first top electrode; 120-second top electrode. DETAILED DESCRIPTION
[0033] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0034] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, and "one end" and "the other end" generally refer to two corresponding parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0035] Figure 2G This is a cross-sectional schematic diagram of the corresponding steps in the method for preparing the resistive random access memory provided in this embodiment, and is also a cross-sectional schematic diagram of the resistive random access memory provided in this embodiment. Figure 2G , this embodiment provides a resistive memory, including a substrate 10, an insulating dielectric layer 30, a bottom electrode connection line 52 and a resistive core pattern 74. The substrate 10 may include a semiconductor material, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, and a fully depleted silicon substrate on an insulating layer; the substrate 10 may also include an integrated circuit, such as a MOS tube, a triode, and a diode; the substrate 10 may also include an interconnection layer, such as a copper interconnection layer and a graphene interconnection layer; the substrate 10 may also include an insulating dielectric layer, such as a silicon oxide layer and a silicon nitride layer. In this embodiment, the substrate 10 has adopted a copper back-end process to form a bottom electrode, that is, the substrate 10 includes a first bottom electrode 21 and a second bottom electrode 22, wherein the material of the first bottom electrode 21 and the second bottom electrode 22 includes copper, wherein the substrate 10 includes a logic area and an array area, the storage unit of the resistive memory is located on the array area, the first bottom electrode 21 is located in the array area, and the second bottom electrode 22 is located in the logic area.
[0036] The insulating dielectric layer 30 is located on the substrate 10. In this embodiment, the insulating dielectric layer 30 includes a first insulating dielectric layer 31 and a second insulating dielectric layer 32 stacked on the substrate 10 from bottom to top, that is, the first insulating dielectric layer 31 covers the substrate 10, the first bottom electrode 21 and the second bottom electrode 22, and the second insulating dielectric layer 32 covers the first insulating dielectric layer 31. In this embodiment, the first insulating dielectric layer 31 and the second insulating dielectric layer 32 are made of different materials. The material of the first insulating dielectric layer 31 includes silicon nitride, silicon oxynitride or silicon carbide, such as Si 3 N 4 、SiN x , SiON, SiCN; the material of the second insulating dielectric layer 32 includes oxides, such as SiO2 、SiO x , PEOX, PETOES, USG, FSG, not limited to the above materials; the total thickness of the first insulating dielectric layer 31 and the second insulating dielectric layer 32 is preferably 800 angstroms to 1200 angstroms, for example 800 angstroms, 1000 angstroms and 1200 angstroms.
[0037] The bottom electrode connection line 52 vertically penetrates the insulating dielectric layer 30, and a portion of the lower surface of the bottom electrode connection line 52 contacts the first bottom electrode 21 for electrical connection. A bottom electrode connector 62 is also formed in the insulating dielectric layer 30, and the bottom electrode connector 62 vertically penetrates the insulating dielectric layer 30, and the lower surface of the bottom electrode connector 62 contacts the second bottom electrode 22 for electrical connection. In this embodiment, the filling material of the bottom electrode connection line 52 and the bottom electrode connector 62 includes tungsten, and the length d of the bottom electrode connection line 52 is preferably 50μm to 5000μm, and the length d of the bottom electrode connection line 52 is greater than the lateral dimension of the first bottom electrode 21 ( Figure 2G The thickness of the bottom electrode connection line 52 is preferably 80nm to 120nm (the same as the thickness of the insulating dielectric layer 30), and the width of the bottom electrode connection line 52 is preferably 50nm to 200nm, which is not limited to the above size range and material; the bottom electrode connection line 52 is straight or arc-shaped. Figure 2G The middle bottom electrode connection line 52 is in a straight line shape (line length is d).
[0038] The resistive switching core pattern 74 is located on the bottom electrode connection line 52. A portion of the upper surface of the bottom electrode connection line 52 contacts the resistive switching core pattern 74 for electrical connection. The lateral size of the resistive switching core pattern 74 is ( Figure 2E In this embodiment, the resistive switching core pattern 74 and the first bottom electrode 21 are arranged in the longitudinal direction ( Figure 2G The resistive core pattern 74 and the first bottom electrode 21 are staggered in the longitudinal direction (the projection positions of the resistive core pattern 74 and the first bottom electrode 21 on the substrate 10 are different) to increase the electrical connection length between the resistive core pattern 74 and the first bottom electrode 21. The increase in the electrical connection length increases the series resistance of the resistive memory. When the resistive memory is in a low-resistance operation state, the increased series resistance plays a voltage-dividing role, which can prevent the resistive memory from being overloaded and broken down. In this embodiment, the preferred method is that the resistive core pattern 74 and the first bottom electrode 21 are respectively electrically connected to the two ends of the bottom electrode connection line 52 in the extension direction (if the bottom electrode connection line 52 is a straight line, its extension direction is the length direction), and the electrical connection length between the resistive core pattern 74 and the first bottom electrode 21 is further increased, which is conducive to increasing the series resistance of the resistive memory and preventing the resistive memory from being overloaded and broken down.
[0039] In this embodiment, the resistive switching core pattern 74 includes a bottom metal layer, a resistive switching layer and a top metal layer stacked in sequence from bottom to top, wherein the materials of the bottom metal layer and the top metal layer include one or more of TiN, TaN, Al, Ir, Pt, Au, W, Ti, and Ta, and the material of the resistive switching layer includes TaO x , HfO x 、AlO x 、TiO x , CuO x One or more of, but not limited to, the above materials.
[0040] Furthermore, it also includes a covering dielectric layer 80, which covers the insulating dielectric layer 30, the resistive core pattern 74 and the bottom electrode connection line 52, and the top surface of the covering dielectric layer 80 is flat. Specifically, the covering dielectric layer 80 includes a first covering dielectric layer 81, a second covering dielectric layer 82, a third covering dielectric layer 83 and a fourth covering dielectric layer 84 formed from bottom to top, wherein the top surface of the fourth covering dielectric layer 84 is flat. In this embodiment, the covering dielectric layer 80 includes a first covering dielectric layer 81, a second covering dielectric layer 82, a third covering dielectric layer 83 and a fourth covering dielectric layer 84 formed from bottom to top, which is conducive to improving the etching selectivity, and subsequently etching to form a top electrode connector with a better morphology, wherein the first covering dielectric layer 81 and the third covering dielectric layer 83 are made of the same material as the first insulating dielectric layer 31, and the second covering dielectric layer 82 and the fourth covering dielectric layer 84 are made of the same material as the second insulating dielectric layer 32.
[0041] Furthermore, it also includes a top electrode connector 90 and a top electrode, wherein the top electrode includes a first top electrode 110 and a second top electrode 120, the first top electrode 110 penetrates the fourth covering dielectric layer 84, the third covering dielectric layer 83 and the first covering dielectric layer 81 and is electrically connected to the resistive core pattern 74, the top electrode connector 90 penetrates part of the thickness of the second covering dielectric layer 82 and the first covering dielectric layer 81 and is electrically connected to the second bottom electrode 22, the second top electrode 120 is located above the top electrode connector 90 and penetrates part of the thickness of the fourth covering dielectric layer 84, the third covering dielectric layer 83 and the second covering dielectric layer 82 and is electrically connected to the top electrode connector 90, that is, the second top electrode 120 and the second bottom electrode 22 are electrically connected via the top electrode connector 90 and the bottom electrode connector 62, and the first top electrode 110 and the first bottom electrode 21 are electrically connected via the resistive core pattern 74 and the bottom electrode connecting line 52.
[0042] In this embodiment, the resistive core pattern and the first bottom electrode are staggered in the longitudinal direction to increase the electrical connection length between the resistive core pattern and the first bottom electrode. The increased electrical connection length increases the series resistance of the resistive memory. When the resistive memory is in a low-resistance operation state, the increased series resistance acts as a voltage divider, which can prevent the resistive memory from overload breakdown.
[0043] Figure 1 This is a flow chart of the method for preparing the resistive random access memory provided in this embodiment. Figure 1 Based on the same inventive concept, this embodiment also provides a method for preparing a resistive random access memory, which is used to prepare the resistive random access memory. The method comprises:
[0044] Step S1: providing a substrate, wherein a first bottom electrode is formed in the substrate;
[0045] Step S2: forming an insulating dielectric layer on the substrate;
[0046] Step S3: forming a bottom electrode connecting line that vertically penetrates the insulating dielectric layer, and a portion of the lower surface of the bottom electrode connecting line contacts the first bottom electrode to be electrically connected;
[0047] Step S4: forming a resistive switching core pattern on the bottom electrode connection line, and a portion of the upper surface of the bottom electrode connection line contacts the resistive switching core pattern to be electrically connected.
[0048] Figures 2A to 2G The cross-sectional schematic diagram of the corresponding steps in the method for preparing the resistive random access memory provided in this embodiment is shown below in conjunction with Figures 2A to 2G The method for preparing the resistive random access memory provided in this embodiment is described in detail.
[0049] Please refer to Figure 2A , perform step S1: provide a substrate 10, the substrate 10 may include a semiconductor material, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate; the substrate 10 may also include an integrated circuit, such as a MOS tube, a triode, a diode; the substrate 10 may also include an interconnect layer, such as a copper interconnect layer, a graphene interconnect layer; the substrate 10 may also include an insulating dielectric layer, such as a silicon oxide layer, a silicon nitride layer. In this embodiment, the substrate 10 has adopted a copper back-end process to form a bottom electrode, that is, the substrate 10 includes a first bottom electrode 21 and a second bottom electrode 22, wherein the material of the first bottom electrode 21 and the second bottom electrode 22 includes copper, wherein the substrate 10 includes a logic area and an array area, the storage unit of the resistive memory is located on the array area, the first bottom electrode 21 is located in the array area, and the second bottom electrode 22 is located in the logic area.
[0050] Please continue to refer to Figure 2A, perform step S2: perform a deposition process to form an insulating dielectric layer 30 on the substrate 10. In this embodiment, the insulating dielectric layer 30 includes a first insulating dielectric layer 31 and a second insulating dielectric layer 32 stacked on the substrate 10 from bottom to top, that is, the first insulating dielectric layer 31 covers the substrate 10, the first bottom electrode 21 and the second bottom electrode 22, and the second insulating dielectric layer 32 covers the first insulating dielectric layer 31. In this embodiment, the first insulating dielectric layer 31 and the second insulating dielectric layer 32 are made of different materials. The material of the first insulating dielectric layer 31 includes silicon nitride, silicon oxynitride or silicon carbide, such as Si 3 N 4 、SiN x , SiON, SiCN, the material of the second insulating dielectric layer 32 includes oxides, such as SiO 2 、SiO x , PEOX, PETOES, USG, FSG, not limited to the above materials; the total thickness of the first insulating dielectric layer 31 and the second insulating dielectric layer 32 is preferably 800 angstroms to 1200 angstroms, for example 800 angstroms, 1000 angstroms and 1200 angstroms.
[0051] Please refer to Figure 2B and Figure 2C , executing step S3: the step of forming the bottom electrode connecting line comprises:
[0052] A first photolithography process is performed to etch the insulating dielectric layer 30 to form a bottom electrode connection groove 50. Specifically, a first patterned photoresist layer 41 is formed to cover the insulating dielectric layer 30. The first patterned photoresist layer 41 is used as a mask to sequentially etch the second insulating dielectric layer 32 and the first insulating dielectric layer 31 to form a bottom electrode connection groove 50. At the same time, a bottom electrode connection hole 60 is formed by etching. The bottom electrode connection groove 50 vertically penetrates the insulating dielectric layer 30 and exposes a portion of the surface of the substrate 10 and the first bottom electrode 21. The bottom electrode connection hole 60 vertically penetrates the insulating dielectric layer 30 and exposes a portion of the surface of the second bottom electrode 22. Then, the first patterned photoresist layer 41 is removed.
[0053] Furthermore, a metal material is filled in the bottom electrode connection groove 50 to form a bottom electrode connection line 52, and a metal material is simultaneously filled in the bottom electrode connection hole 60 to form a bottom electrode connector 62, wherein a portion of the lower surface of the bottom electrode connection line 52 contacts the first bottom electrode 21 for electrical connection, and the lower surface of the bottom electrode connector 62 contacts the second bottom electrode 22 for electrical connection. In this embodiment, the filling material of the bottom electrode connection line 52 and the bottom electrode connector 62 includes tungsten, and the length d of the bottom electrode connection line 52 is preferably 50 μm to 5000 μm, and the length d of the bottom electrode connection line 52 is greater than the lateral dimension of the first bottom electrode 21 ( Figure 2CThe thickness of the bottom electrode connection line 52 is preferably 80nm to 120nm (the same as the thickness of the insulating dielectric layer 30), and the width of the bottom electrode connection line 52 is preferably 50nm to 200nm, which is not limited to the above size range and material; the bottom electrode connection line 52 is straight or arc-shaped. Figure 2C The middle bottom electrode connection line 52 is in a straight line shape (line length is d).
[0054] Please refer to Figure 2D and 2E , executing step S4: the step of forming a resistive switching core pattern comprises:
[0055] The resistive switching core material layer 70 is formed to cover the insulating dielectric layer 30, the bottom electrode connection line 52 and the bottom electrode connection member 62. In this embodiment, the resistive switching core material layer 70 includes a bottom metal layer 71, a resistive switching layer 72 and a top metal layer 73 stacked in sequence from bottom to top, wherein the materials of the bottom metal layer 71 and the top metal layer 73 include one or more of TiN, TaN, Al, Ir, Pt, Au, W, Ti and Ta, and the material of the resistive switching layer 72 includes TaO x , HfO x 、AlO x 、TiO x , CuO x One or more of, but not limited to, the above materials.
[0056] A second photolithography process is performed to etch the resistive core material layer 70 to form a resistive core pattern 74. Specifically, a second patterned photoresist layer 42 is formed to cover the resistive core material layer 70. The second patterned photoresist layer 42 is used as a mask to etch the resistive core material layer 70 (sequentially etching the top metal layer 73, the resistive layer 72 and the bottom metal layer 71) to form a resistive core pattern 74. The resistive core pattern 74 is located on the bottom electrode connection line 52. A portion of the upper surface of the bottom electrode connection line 52 contacts the resistive core pattern 74 to be electrically connected. The lateral size of the resistive core pattern 74 ( Figure 2E The length d of the bottom electrode connection line 52 is smaller than the length d of the bottom electrode connection line 52. Then, the second patterned photoresist layer 42 is removed.
[0057] In this embodiment, the resistive switching core pattern 74 and the first bottom electrode 21 are arranged along the longitudinal direction ( Figure 2GThe resistive core pattern 74 and the first bottom electrode 21 are staggered in the longitudinal direction (the projection positions of the resistive core pattern 74 and the first bottom electrode 21 on the substrate 10 are different) to increase the electrical connection length between the resistive core pattern 74 and the first bottom electrode 21. The increase in the electrical connection length increases the series resistance of the resistive memory. When the resistive memory is in a low-resistance operation state, the increased series resistance plays a voltage-dividing role, which can prevent the resistive memory from being overloaded and broken down. In this embodiment, the preferred method is that the resistive core pattern 74 and the first bottom electrode 21 are respectively electrically connected to the two ends of the bottom electrode connection line 52 in the extension direction (if the bottom electrode connection line 52 is a straight line, its extension direction is the length direction), and the electrical connection length between the resistive core pattern 74 and the first bottom electrode 21 is further increased, which is conducive to increasing the series resistance of the resistive memory and preventing the resistive memory from being overloaded and broken down.
[0058] Please refer to Figure 2F and Figure 2G , further, after forming the resistive switching core pattern, it also includes: forming a covering dielectric layer 80 to cover the insulating dielectric layer 30, the resistive switching core pattern 74 and the bottom electrode connection line 52, and the top surface of the covering dielectric layer 80 is flat. Specifically, the covering dielectric layer 80 includes a first covering dielectric layer 81, a second covering dielectric layer 82, a third covering dielectric layer 83 and a fourth covering dielectric layer 84 formed from bottom to top, and the first covering dielectric layer 81 and the second covering dielectric layer 82 are first formed, the first covering dielectric layer 81 covers the insulating dielectric layer 30, the resistive switching core pattern 74 and the bottom electrode connection line 52, the second covering dielectric layer 82 covers the first covering dielectric layer 81 and fills above the resistive switching core pattern 74, and then performs a chemical mechanical polishing process to make the top surface of the second covering dielectric layer 82 flat and expose the first covering dielectric layer 81. Then, the third covering dielectric layer 83 and the fourth covering dielectric layer 84 are formed in sequence to cover the second covering dielectric layer 82, and the top surface of the fourth covering dielectric layer 84 is flat. In this embodiment, the covering dielectric layer 80 includes a first covering dielectric layer 81, a second covering dielectric layer 82, a third covering dielectric layer 83 and a fourth covering dielectric layer 84 formed from bottom to top, which is beneficial to improving the etching selectivity and subsequently etching to form a top electrode connector with a better morphology, wherein the first covering dielectric layer 81 and the third covering dielectric layer 83 are made of the same material as the first insulating dielectric layer 31, and the second covering dielectric layer 82 and the fourth covering dielectric layer 84 are made of the same material as the second insulating dielectric layer 32.
[0059] Furthermore, after forming the covering dielectric layer 80, the method further includes: first forming a top electrode connection hole and a top electrode groove (not shown in the figure) in the covering dielectric layer 80, and then filling the top electrode connection hole and the top electrode groove with a metal material to form a top electrode connector 90 and a top electrode, specifically forming a first top electrode 110 and a second top electrode 120, the first top electrode 110 penetrates the fourth covering dielectric layer 84, the third covering dielectric layer 83 and the first covering dielectric layer 81 and is electrically connected to the resistive core pattern 74, and the top electrode connector 90 penetrates the second covering dielectric layer Part of the thickness of the fourth covering dielectric layer 84, the third covering dielectric layer 83 and the second covering dielectric layer 82 is electrically connected to the second bottom electrode 22, the second top electrode 120 is located above the top electrode connector 90 and passes through part of the thickness of the fourth covering dielectric layer 84, the third covering dielectric layer 83 and the second covering dielectric layer 82 and is electrically connected to the top electrode connector 90, that is, the second top electrode 120 and the second bottom electrode 22 are electrically connected through the top electrode connector 90 and the bottom electrode connector 62, and the first top electrode 110 and the first bottom electrode 21 are electrically connected through the resistive core graphic 74 and the bottom electrode connecting line 52.
[0060] In summary, the resistive memory and the preparation method thereof provided by the present invention include: a substrate, an insulating dielectric layer, a bottom electrode connecting line and a resistive core pattern, wherein a first bottom electrode is formed in the substrate, the insulating dielectric layer is located on the substrate, the bottom electrode connecting line vertically penetrates the insulating dielectric layer, a portion of the lower surface of the bottom electrode connecting line contacts the first bottom electrode for electrical connection, the resistive core pattern is located on the bottom electrode connecting line, and a portion of the upper surface of the bottom electrode connecting line contacts the resistive core pattern for electrical connection; in the present invention, the resistive core pattern and the first bottom electrode are staggered in the longitudinal direction to increase the electrical connection length between the resistive core pattern and the first bottom electrode, and the increased electrical connection length is used to increase the series resistance of the resistive memory. When the resistive memory is in a low-resistance operation state, the increased series resistance plays a voltage dividing role, which can prevent the resistive memory from overload breakdown.
[0061] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.
Claims
1. A resistive random access memory, characterized in that: include: a substrate having a first bottom electrode formed therein; an insulating dielectric layer, located on the substrate; A bottom electrode connecting line, which vertically penetrates the insulating dielectric layer, and a portion of the lower surface of the bottom electrode connecting line contacts the first bottom electrode to be electrically connected; A resistive switching core pattern is located on the bottom electrode connection line, and a portion of the upper surface of the bottom electrode connection line contacts the resistive switching core pattern to be electrically connected; The resistive switching core pattern and the first bottom electrode are staggered in the longitudinal direction to increase the electrical connection length between the resistive switching core pattern and the first bottom electrode.
2. The resistive random access memory according to claim 1, wherein: The resistive switching core pattern and the first bottom electrode are electrically connected to two ends of the bottom electrode connection line in an extending direction, respectively.
3. The resistive random access memory according to claim 1, wherein: The length of the bottom electrode connecting line is 50 μm to 5000 μm.
4. The resistive random access memory according to claim 3, wherein: The bottom electrode connecting line is in a straight line or an arc shape.
5. The resistive random access memory according to claim 3, wherein: The filling material of the bottom electrode connection line includes tungsten.
6. The resistive random access memory according to claim 1, wherein: It also includes a covering dielectric layer, which covers the insulating dielectric layer, the resistive switching core pattern and the bottom electrode connecting line, and the top surface of the covering dielectric layer is flat.
7. The resistive random access memory according to claim 6, wherein: It also includes a top electrode, which penetrates the covering dielectric layer and is electrically connected to the resistive switching core pattern.
8. A method for preparing a resistive random access memory, characterized in that: include: forming a substrate, wherein a first bottom electrode is formed in the substrate; forming an insulating dielectric layer on the substrate; forming a bottom electrode connecting line that vertically penetrates the insulating dielectric layer, wherein a portion of the lower surface of the bottom electrode connecting line contacts the first bottom electrode to be electrically connected; as well as, A resistive switching core pattern is formed on the bottom electrode connection line, and a portion of the upper surface of the bottom electrode connection line contacts the resistive switching core pattern to be electrically connected; The resistive switching core pattern and the first bottom electrode are staggered in the longitudinal direction to increase the electrical connection length between the resistive switching core pattern and the first bottom electrode.
9. The method for preparing a resistive random access memory according to claim 8, wherein: The steps of forming the bottom electrode connection line include: Performing a first photolithography process to etch the insulating dielectric layer to form a bottom electrode connection groove, wherein the bottom electrode connection groove exposes a portion of the surface of the substrate and the first bottom electrode; The bottom electrode connection groove is filled with metal material to form the bottom electrode connection line.
10. The method for preparing a resistive random access memory according to claim 8, wherein: The steps of forming the resistive switching core pattern include: Forming a resistive switching core material layer to cover the insulating dielectric layer and the bottom electrode connecting line; A second photolithography process is performed to etch the resistive switching core material layer to form the resistive switching core pattern.