Storage structure and operation method thereof, semiconductor device and formation method thereof

Abstract

The present disclosure relates to a storage structure and an operating method thereof, a semiconductor device and a method for forming the same. The storage structure comprises: a substrate; a storage layer located on the substrate, the storage layer comprising a plurality of storage cells arranged along a first direction, wherein adjacent storage cells in the storage layer along the first direction are electrically connected, the storage cells comprising a phase change structure, and a transistor structure located above the phase change structure along a second direction and electrically connected to the phase change structure, the transistor structure comprising a first channel region, the phase change structure comprising a phase change layer, the resistance of the first channel region being less than the resistance of the phase change layer. The present disclosure improves the performance of semiconductor devices, and can also increase the storage density of semiconductor devices, reduce the manufacturing cost of semiconductor devices, and expand the application areas of semiconductor devices.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a storage structure and an operating method thereof, a semiconductor device and a forming method thereof. Background Art

[0002] As the demand for high-capacity memory continues to grow, memory manufacturing has shifted toward pursuing higher storage density and smaller storage nodes. Clearly, two-dimensional flash memory structures are no longer able to meet these high storage density requirements. Compared to two-dimensional structures, three-dimensional structures offer significant potential for achieving even higher storage density. As the spacing between memory cells continues to shrink, floating gate memory cells are increasingly experiencing issues such as doping, data loss, and coupling ratio problems.

[0003] NAND memory structure is a commonly used memory structure. However, NAND memory still has many problems, such as slow read and write speed, complex process, short storage time at high temperature, and poor compatibility with CMOS process, which limit the further improvement of memory performance.

[0004] Therefore, how to improve the performance of memory, reduce the manufacturing cost of memory, and expand the application field of memory is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a memory structure and an operating method thereof, a semiconductor device and a forming method thereof, which are used to improve the performance of the memory, reduce the manufacturing cost of the memory, and expand the application field of the memory.

[0006] According to some embodiments, the present disclosure provides a storage structure comprising:

[0007] substrate;

[0008] A storage layer is located on the substrate, the storage layer includes a plurality of storage cells arranged along a first direction, and the storage cells adjacent to each other along the first direction in the storage layer are electrically connected, the storage cells include a phase change structure, and a transistor structure located above the phase change structure along a second direction and electrically connected to the phase change structure, the transistor structure includes a first channel region, the phase change structure includes a phase change layer, the resistance of the first channel region is less than the resistance of the phase change layer, the first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate.

[0009] In some embodiments, the transistor structure further includes a first source region and a first drain region located on opposite sides of the first channel region along the first direction;

[0010] The phase change structure further includes a first electrode and a second electrode located on opposite sides of the phase change layer along the first direction, the first source region is located on a surface of the first electrode, the first drain region is located on a surface of the second electrode, and the first channel region is located on a surface of the phase change layer;

[0011] In two adjacent memory cells along the first direction, the first source region in one memory cell is electrically connected to the first drain region in the other memory cell, and the first electrode in one memory cell is electrically connected to the second electrode in the other memory cell.

[0012] In some embodiments, the memory layer includes a plurality of memory columns arranged at intervals along a third direction, each memory column includes a plurality of memory cells arranged along the first direction, the transistor structures in adjacent memory cells in the memory columns are electrically connected, the third direction is parallel to the top surface of the substrate and intersects the first direction; the memory structure further includes:

[0013] a word line group located on the substrate, the word line group comprising a plurality of word lines spaced apart along the first direction, the word lines extending along the third direction and covering the first channel regions of the plurality of transistor structures in the storage layer;

[0014] A bit line is located on the substrate, and the bit line is electrically connected to the transistor structure in the storage layer.

[0015] In some embodiments, the storage column includes a first end and a second end that are oppositely distributed along the first direction; the storage column further includes:

[0016] a first gating structure electrically connected to the transistor structure in the memory cell located at the first end;

[0017] The second gating structure is electrically connected to the transistor structure in the memory cell located at the second end.

[0018] In some embodiments, the first gating structure includes a second channel region, and a second source region and a second drain region located on opposite sides of the second channel region along the first direction; the second gating structure includes a third channel region, and a third source region and a third drain region located on opposite sides of the third channel region along the first direction; and the semiconductor structure further includes:

[0019] a first gate line covering the second channel region of the first gate structure in the storage layer;

[0020] A second gate line covers the third channel region of the second gate structure in the storage layer.

[0021] In some embodiments, further comprising:

[0022] a source line located above the storage layer and electrically connected to the second drain region of the first gating structure, wherein the second source region of the first gating structure is electrically connected to the first drain region of the storage unit located at the first end;

[0023] The third drain region of the second gating structure is electrically connected to the first source region of the memory cell located at the second end, and the bit line is electrically connected to the third source region of the second gating structure.

[0024] In some embodiments, the first gating structure further includes a first conductive layer and a second conductive layer connected to opposite sides of the second channel region along the first direction, the second source region is located above the first conductive layer and electrically connected to the first conductive layer, the second drain region is located above the second conductive layer and electrically connected to the second conductive layer, the first conductive layer, the second conductive layer, the first electrode and the second electrode are arranged in the same layer, and the sum of the thickness of the first channel region along the second direction and the thickness of the phase change layer along the second direction is equal to the thickness of the second channel region along the second direction.

[0025] According to some other embodiments, the present disclosure further provides a semiconductor device, including:

[0026] substrate;

[0027] A stacked structure is located on the substrate and includes a plurality of storage layers arranged at intervals along a second direction, the storage layers include a plurality of storage cells arranged along a first direction, and the storage cells adjacent to each other along the first direction in the storage layers are electrically connected, the storage cells include a phase change structure, and a transistor structure located above the phase change structure along the second direction and electrically connected to the phase change structure, the transistor structure includes a first channel region, the phase change structure includes a phase change layer, the resistance of the first channel region is less than the resistance of the phase change layer, the first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate.

[0028] In some embodiments, further comprising:

[0029] a word line structure located on the substrate, comprising a plurality of word line groups arranged at intervals along the second direction, the word line groups comprising a plurality of word lines arranged at intervals along the first direction, the word lines extending along the third direction and covering the plurality of transistor structures in the storage layer, the third direction being parallel to the top surface of the substrate and intersecting the first direction;

[0030] The bit line structure is located on the substrate and includes a plurality of bit lines spaced apart along the second direction. The bit lines extend along the third direction, and each bit line is electrically connected to all the transistor structures in one storage layer.

[0031] According to some further embodiments, the present disclosure further provides a method for forming a semiconductor device, comprising the following steps:

[0032] providing a substrate;

[0033] A stacked structure is formed on the substrate, the stacked structure including a plurality of storage layers arranged at intervals along a second direction, the storage layers including a plurality of storage cells arranged along a first direction, the storage cells adjacent to each other along the first direction in the storage layers being electrically connected, the storage cells including a phase change structure, and a transistor structure located above the phase change structure along the second direction and electrically connected to the phase change structure, the transistor structure including a first channel region, the phase change structure including a phase change layer, the resistance of the first channel region being less than the resistance of the phase change layer, the first direction being parallel to the top surface of the substrate, and the second direction being perpendicular to the top surface of the substrate.

[0034] According to some further embodiments, the present disclosure further provides a method for operating the storage structure as described above, comprising the following steps:

[0035] Selecting one of the storage units in the storage layer as a target storage unit to be read or written;

[0036] The transistor structure in the target memory cell is turned off, and the transistor structures in the other memory cells that are in the same memory layer as the target memory cell and are electrically connected to the target memory cell are turned on.

[0037] Some embodiments of the present disclosure provide a storage structure and an operation method thereof, a semiconductor device and a formation method thereof. A phase change storage cell is formed by setting a transistor structure and a phase change structure electrically connected to the transistor structure in the storage cell, and multiple storage cells in the storage layer are electrically connected. The resistance of the first channel region in the transistor structure is smaller than the resistance of the phase change layer in the phase change structure. Thus, the target storage cell can be stored by turning off the transistor structure in the target storage cell in the storage layer and turning on the transistor structure in other storage cells that are in the same storage layer as the target storage cell and are electrically connected to the target storage cell. This simplifies the read and write operations of the storage cell, improves the read and write efficiency of the storage cell, and improves the performance of the semiconductor device. It can also increase the storage density of the semiconductor device, reduce the manufacturing cost of the semiconductor device, and expand the application field of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Attachment Figure 1 is a schematic diagram of a three-dimensional structure of a storage structure in a specific embodiment of the present disclosure;

[0039] Attachment Figure 2 is a schematic top view of a storage structure in a specific embodiment of the present disclosure;

[0040] Attachment Figure 3 is a schematic cross-sectional view of a storage unit in a specific embodiment of the present disclosure;

[0041] Attachment Figure 4 is a schematic cross-sectional view of a storage layer in a specific embodiment of the present disclosure;

[0042] Attachment Figure 5 is a circuit diagram of a storage unit in a specific embodiment of the present disclosure;

[0043] Attachment Figure 6 is a flow chart of a method for operating a storage structure in a specific embodiment of the present disclosure;

[0044] Attachment Figure 7 is a schematic diagram of a specific embodiment of the present disclosure when a write operation is performed on a target storage unit in a storage layer;

[0045] Attachment Figure 8 is a schematic diagram of a specific embodiment of the present disclosure when a read operation is performed on a target storage unit in a storage layer;

[0046] Attachment Figure 9 is a schematic structural diagram of a semiconductor device in a specific embodiment of the present disclosure;

[0047] Attachment Figure 10 is a flow chart of a method for forming a semiconductor device in a specific embodiment of the present disclosure;

[0048] Attachment Figure 11 -Attached Figure 14 It is a schematic diagram of the main process structure in the process of forming a semiconductor device according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The following describes in detail the specific implementations of the storage structure and its operating method, the semiconductor device and its forming method provided by the present disclosure in conjunction with the accompanying drawings.

[0050] This specific embodiment provides a storage structure, Figure 1 is a schematic diagram of the three-dimensional structure of the storage structure in the specific embodiment of the present disclosure, Figure 2 is a top view of the storage structure in a specific embodiment of the present disclosure, Figure 3 is a schematic cross-sectional view of a storage unit in a specific embodiment of the present disclosure, Figure 4 is a cross-sectional schematic diagram of the storage layer in a specific embodiment of the present disclosure, Figure 5 : is a circuit diagram of a storage unit in a specific embodiment of the present disclosure. Figure 1-Figure 5 As shown, the storage structure includes:

[0051] substrate 10;

[0052] A storage layer is located on the substrate 10, the storage layer includes a plurality of storage cells 21 arranged along a first direction D1, and the storage cells 21 adjacent to each other along the first direction D1 in the storage layer are electrically connected, the storage cells 21 include a phase change structure 50, and a transistor structure located above the phase change structure along a second direction D2 and electrically connected to the phase change structure 50, the transistor structure includes a first channel region 32, the phase change structure 50 includes a phase change layer 31, the resistance of the first channel region 32 is less than the resistance of the phase change layer 31, the first direction D1 is parallel to the top surface of the substrate 10, and the second direction D2 is perpendicular to the top surface of the substrate 10.

[0053] Specifically, the substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment is described using the substrate 10 as an example. In other embodiments, the substrate 10 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 10 is used to support the device structure above it. The substrate 10 includes a top surface and a bottom surface relatively distributed, and the storage layer is located on the top surface of the substrate 10. The storage layer includes a plurality of storage cells 21 arranged along the first direction D1, and any two adjacent storage cells 21 along the first direction D1 are electrically connected. The storage cell 21 includes the phase change structure 50 and the transistor structure superimposed on the phase change structure 50 along the second direction D2. The phase change structure 50 is used to store information. In one example, the first channel region 32 in the transistor structure is superimposed on the phase change layer 31 along the second direction D2, and the first channel region 32 is in contact and electrically connected to the phase change layer 31. The phase change structure 50 includes a phase change layer 31 comprising a phase change material. The phase change material can transition between a crystalline state and an amorphous state, and the resistivity of the phase change material in the crystalline state is different from the resistivity in the amorphous state. In one example, the phase change material can be germanium antimony telluride. When operating the memory cell 21, the heat in the phase change layer 31 is adjusted to cause the phase change layer 31 to transition between the crystalline state and the amorphous state, ultimately enabling data read and write operations based on the resistance change of the phase change layer 31.

[0054] The resistance of the first channel region 32 is less than the resistance of the phase change layer 31, which means that the resistance of the first channel region 32 is less than the resistance of the phase change layer 31 in a crystalline state, and the resistance of the first channel region 32 is less than the resistance of the phase change layer 31 in an amorphous state. Therefore, when the transistor structure in a memory cell 21 is turned on, current flows through the first channel region 32 in the memory cell 21 but does not flow through the phase change layer 32 in the memory cell 21, thereby preventing read and write operations from being performed on the phase change structure 50 in the memory cell 21. When the transistor structure in a memory cell 21 is turned off, current flows through the phase change layer 32 in the memory cell 21 but does not flow through the first channel region 32 in the memory cell 21, thereby enabling read and write operations on the phase change structure 50 in the memory cell 21. This specific embodiment adopts the phase change structure 50 as the storage element in the storage unit 21, and makes the resistance of the first channel region 32 in the transistor structure smaller than the resistance of the phase change layer 31 in the phase change structure 50, thereby forming a phase change storage unit. This not only simplifies the read and write operations of the storage unit, improves the read and write efficiency of the storage unit, and improves the performance of the semiconductor device, but also can increase the storage density of the semiconductor device, reduce the manufacturing cost of the semiconductor device, and expand the application field of the semiconductor device.

[0055] In some embodiments, the transistor structure further includes a first source region 331 and a first drain region 332 located on opposite sides of the first channel region 32 along the first direction D1;

[0056] The phase change structure 50 further includes a first electrode 301 and a second electrode 302 located on opposite sides of the phase change layer 31 along the first direction D1. The first source region 331 is located on a surface of the first electrode 301, and the first drain region 332 is located on a surface of the second electrode 302. The first channel region 32 is located on a surface of the phase change layer 31.

[0057] In two adjacent memory cells 21 along the first direction D1, the first source region 331 in one memory cell 21 is electrically connected to the first drain region 332 in the other memory cell 21, and the first electrode 301 in one memory cell 21 is electrically connected to the second electrode 302 in the other memory cell 21.

[0058] Specifically, if Figure 3 and Figure 4As shown, the transistor structure is located above the phase change structure 50 along the second direction D2, and the first channel region 32 is located on the surface of the phase change layer 31 and is in contact and electrically connected to the phase change layer 31. The first source region 331 is located on the surface of the first electrode 301 and is in contact and electrically connected to the first electrode 301. The first drain region 332 is located on the surface of the second electrode 302 and is in contact and electrically connected to the second electrode 302. In one example, the material of the first electrode 301 and the second electrode 302 are the same, for example, both are conductive materials such as TiN. The material of the first source region 331 and the first drain region 332 are the same, for example, both are silicon materials including first-type dopant ions. The material of the first channel region 32 can be silicon materials including second-type dopant ions, and the first-type dopant ions and the second-type dopant ions have opposite conductivity types. In one example, the first-type dopant ions are N-type ions, and the second-type dopant ions are P-type ions. In one example, the top surface of the first electrode 301 and the top surface of the second electrode 302 are flush with the top surface of the phase change layer 31 , so as to further simplify the manufacturing process of the storage structure.

[0059] In one example, in two adjacent memory cells 21 along the first direction D1, the first source region 331 in one memory cell 21 is directly in contact and electrically connected to the first drain region 332 in the other memory cell 21, and the first electrode 301 in one memory cell 21 is directly in contact and electrically connected to the second electrode 302 in the other memory cell 21, so that the first electrodes 301 and the second electrodes 302 in multiple memory cells 21 can be formed synchronously, and the first source regions 331 and the first drain regions 332 in multiple memory cells 21 can be formed synchronously, thereby further simplifying the manufacturing process of the storage structure and improving the manufacturing efficiency of the storage structure.

[0060] In some embodiments, the memory layer includes a plurality of memory columns arranged at intervals along a third direction D3, each memory column includes a plurality of memory cells 21 arranged along the first direction D1, the transistor structures in adjacent memory cells 21 in the memory column are electrically connected, the third direction D3 is parallel to the top surface of the substrate 10, and the third direction D3 intersects the first direction D1; the memory structure further includes:

[0061] a word line group located on the substrate 10, the word line group including a plurality of word lines 11 spaced apart along the first direction D1, the word lines 11 extending along the third direction D3 and covering the first channel regions 32 of the plurality of transistor structures in the storage layer;

[0062] The bit line 14 is located on the substrate 10 and is electrically connected to the transistor structure in the storage layer.

[0063] For example, if Figure 1-Figure 5 As shown, the plurality of memory columns in the memory layer are arranged at intervals along the third direction D3, and any two adjacent memory cells 21 in each memory column are electrically connected. Each memory column also includes a gate dielectric layer 15, which extends along the first direction D1 and continuously covers the surfaces of the plurality of first channel regions 32 arranged along the first direction D1. In one example, the material of the gate dielectric layer 15 can be an oxide material, such as silicon dioxide. The word line group in the memory structure includes a plurality of word lines 11 arranged at intervals along the first direction D1, each word line 11 extending along the third direction D3 and continuously covering the surface of the gate dielectric layer 15 located on the first channel region 32 in the plurality of memory cells 21 arranged at intervals along the third direction D3. By adjusting the magnitude of the voltage applied to the word line 11, the on and off of the transistor structure is controlled. The bit line 14 extends along the third direction D3 and is electrically connected to the transistor structures in the memory cells 21 at the ends of a plurality of memory columns arranged at intervals along the third direction D3 in the memory layer. Because the transistor structures in any two adjacent memory cells 21 in a memory column are electrically connected, one bit line 14 is electrically connected to the transistor structures in all memory cells 21 in the memory layer. In one example, the memory structure further includes a bit line plug 40, which extends along the second direction D2. One end of the bit line plug 40 is electrically connected to the transistor structure in the memory cell 21, and the other end is electrically connected to the bit line 14.

[0064] To further simplify the read and write operations of the storage structure, in some embodiments, the storage column includes a first end and a second end that are oppositely distributed along the first direction D1; the storage column further includes:

[0065] a first gating structure electrically connected to the transistor structure in the memory cell 21 located at the first end;

[0066] The second gating structure is electrically connected to the transistor structure in the memory cell 21 located at the second end.

[0067] In some embodiments, the first gating structure includes a second channel region 41, and a second source region 43 and a second drain region 42 located on opposite sides of the second channel region 41 along the first direction D1; the second gating structure includes a third channel region 45, and a third source region 47 and a third drain region 46 located on opposite sides of the third channel region 45 along the first direction D1; the semiconductor structure further includes:

[0068] A first gate line 12 covering the second channel region 41 of the first gate structure in the storage layer;

[0069] The second gate line 13 covers the third channel region 45 of the second gate structure in the storage layer.

[0070] In some embodiments, the storage structure further includes:

[0071] a source line 20 located above the storage layer and electrically connected to the second drain region 42 of the first gating structure, wherein the second source region 43 of the first gating structure is electrically connected to the first drain region 332 of the storage cell 21 located at the first end;

[0072] The third drain region 46 of the second gating structure is electrically connected to the first source region 331 in the memory cell 21 located at the second end, and the bit line 14 is electrically connected to the third source region 47 of the second gating structure.

[0073] In one example, the storage structure further includes a source line plug 44 , which extends along the second direction D2 . One end of the source line plug 44 is electrically connected to the second drain region 42 , and the other end is electrically connected to the source line 20 .

[0074] In some embodiments, the first gating structure further includes a first conductive layer 48 and a second conductive layer 49 connected to opposite sides of the second channel region 41 along the first direction D1, the second source region 43 is located above the first conductive layer 48 and electrically connected to the first conductive layer 48, the second drain region 42 is located above the second conductive layer 49 and electrically connected to the second conductive layer 49, the first conductive layer 48, the second conductive layer 49, the first electrode 301 and the second electrode 302 are arranged in the same layer, and the sum of the thickness of the first channel region 32 along the second direction D1 and the thickness of the phase change layer 32 along the second direction D2 is equal to the thickness of the second channel region 41 along the second direction D2.

[0075] Specifically, the first conductive layer 48, the second conductive layer 49, the first electrode 301, and the second electrode 302 can be formed simultaneously, thereby further simplifying the manufacturing process of the memory structure. The first and second gating structures are used to activate the switching elements of the memory column, and do not serve as memory elements. Therefore, the first and second gating structures only have transistors and no phase change structure. The sum of the thickness of the first channel region 32 along the second direction D1 and the thickness of the phase change layer 31 along the second direction D2 is equal to the thickness of the second channel region 41 along the second direction D2, thereby improving the flatness of the memory structure and further simplifying the manufacturing process of the memory structure.

[0076] In one example, the second gating structure further includes a third conductive layer and a fourth conductive layer connected to opposite sides of the third channel region 45 along the first direction D1. The third source region 47 is located above and electrically connected to the third conductive layer. The third drain region 46 is located above and electrically connected to the fourth conductive layer. The third conductive layer, the fourth conductive layer, the first electrode 301, and the second electrode 302 are disposed in the same layer. The sum of the thickness of the first channel region 32 along the second direction D1 and the thickness of the phase change layer 32 along the second direction D2 is equal to the thickness of the third channel region 45 along the second direction D2. One end of the bit line plug 40 is electrically connected to the second source region 47, and the other end is electrically connected to the bit line 14.

[0077] This specific embodiment also provides an operating method of the storage structure as described above, Figure 6 This is a flowchart of the operation method of the storage structure in the specific embodiment of the present disclosure, Figure 7 This is a schematic diagram of a specific embodiment of the present disclosure when performing a write operation on a target storage unit in a storage layer, Figure 8 FIG. 1 is a schematic diagram of a specific embodiment of the present disclosure performing a read operation on a target storage unit in a storage layer. Figures 1-8 As shown, the operation method of the storage structure includes the following steps:

[0078] Step S61, selecting one of the storage units 21 in the storage layer as a target storage unit to be read or written;

[0079] Step S62 , turning off the transistor structure in the target memory cell, and turning on the transistor structures in other memory cells that are in the same memory layer as the target memory cell and are electrically connected to the target memory cell.

[0080] For example, if Figure 7 As shown, Figure 7The storage unit shown in the dotted box is the target storage unit. Figure 7 When the target memory cell shown in FIG is written, the word line 11 (eg Figure 7 The third word line WL2 in the transmission selection voltage V select , controlling the transistor structure in the target memory cell to be closed; and simultaneously switching to other word lines (e.g. Figure 7 The first word line WL0, the second word line WL1, the fourth word line WL3 and the fifth word line WL4 in the transmission turn-on voltage V pass , so that the transistor structures in the memory cells other than the target memory cell in the memory layer are turned on. And, a write voltage V is applied to the bit line 14 electrically connected to the memory layer. write , to write data to the target storage unit.

[0081] For example, Figure 8 As shown, Figure 8 The storage unit shown in the dotted box is the target storage unit. Figure 8 When a read operation is performed on the target memory cell in the embodiment, the word line 11 (eg Figure 8 The third word line WL2 in the transmission selection voltage V select , controlling the transistor structure in the target memory cell to be closed; and simultaneously switching to other word lines (e.g. Figure 8 The first word line WL0, the second word line WL1, the fourth word line WL3 and the fifth word line WL4 in the transmission turn-on voltage V pass , so that the transistor structures in the memory cells other than the target memory cell in the memory layer are turned on. And, a write voltage V is applied to the bit line 14 electrically connected to the memory layer. read , to read the data stored in the target storage unit.

[0082] This embodiment also provides a semiconductor device, Figure 9 The schematic diagram of the structure of the semiconductor device in the specific embodiment of the present disclosure. The schematic diagram of the structure of the storage layer in the semiconductor device can be found in Figure 1-Figure 5 .like Figure 1-Figure 5 and Figure 9 As shown, the semiconductor device includes:

[0083] substrate 10;

[0084] A stacked structure is located on the substrate 10 and includes a plurality of storage layers arranged at intervals along a second direction D2. The storage layers include a plurality of storage cells 21 arranged along a first direction D1, and the storage cells 21 adjacent to each other along the first direction D1 in the storage layer are electrically connected. The storage cells 21 include a phase change structure 50, and a transistor structure located above the phase change structure 50 along the second direction D2 and electrically connected to the phase change structure 50. The transistor structure includes a first channel region 32, and the phase change structure 50 includes a phase change layer 31. The resistance of the first channel region 32 is less than the resistance of the phase change layer 31. The first direction D1 is parallel to the top surface of the substrate 10, and the second direction D2 is perpendicular to the top surface of the substrate 10.

[0085] In some embodiments, the semiconductor device further comprises:

[0086] a word line structure, located on the substrate 10, comprising a plurality of word line groups arranged at intervals along the second direction D2, the word line groups comprising a plurality of word lines 11 arranged at intervals along the first direction D1, the word lines 11 extending along the third direction D3 and covering the plurality of transistor structures in the storage layer, the third direction D3 being parallel to the top surface of the substrate 10 and intersecting the first direction D1;

[0087] The bit line structure is located on the substrate 10 and includes a plurality of bit lines 14 spaced apart along the second direction D2. The bit lines 14 extend along the third direction D3, and each bit line 14 is electrically connected to all the transistor structures in one storage layer.

[0088] Specifically, the semiconductor device includes a plurality of storage layers arranged at intervals along the second direction D2, each of the storage layers includes a plurality of storage columns arranged at intervals along the third direction D3, and each of the storage columns includes a plurality of storage cells 21 arranged along the first direction D1, thereby forming a semiconductor device with a three-dimensional stacked structure to improve the storage capacity and storage density of the semiconductor device.

[0089] The semiconductor device also includes a plurality of first gating structures electrically connected one-to-one with the plurality of storage columns in each storage layer, and a plurality of second gating structures electrically connected one-to-one with the plurality of storage columns in each storage layer. The semiconductor device also includes a first gating line group and a second gating line group. The first gating line group includes a plurality of first gating lines 12 spaced apart along the second direction D2, each of which is electrically connected to all of the first gating structures in one storage layer. The second gating line group includes a plurality of second gating lines 13 spaced apart along the second direction D2, each of which is electrically connected to all of the second gating structures in one storage layer. The semiconductor device may include only one source line 20, which is electrically connected to all of the first gating structures in the stacked structure via the source line plug 44.

[0090] In one example, the semiconductor device further includes a first isolation layer 90 and a second isolation layer 91, wherein the first isolation layer 90 covers the surface of the gate dielectric layer 15, and the first gate line 12, the second gate line 13, and the word line 11 all penetrate the first isolation layer 90 along the third direction D3, and the second isolation layer 91 covers the surface of the first isolation layer 90. The first isolation layer 90 and the second isolation layer 91 are both used to isolate adjacent storage layers to prevent signal crosstalk between adjacent storage layers. In one example, the material of the first isolation layer 90 and the material of the second isolation layer 91 are both low dielectric constant materials, for example, the material of the first isolation layer 90 is silicon carbonitride, and the material of the second isolation layer 91 is silicon dioxide or silicon oxycarbide.

[0091] This embodiment also provides a method for forming a semiconductor device. Figure 10 is a flow chart of a method for forming a semiconductor device in a specific embodiment of the present disclosure, Figure 11 -Attached Figure 14 This is a schematic diagram of the main process structure in the process of forming a semiconductor device in the specific embodiment of the present disclosure. The structural schematic diagram of the semiconductor device formed in this specific embodiment can be found in Figure 1-Figure 5 and Figure 9 .like Figure 1-Figure 5 and Figures 9-14 As shown, the method for forming the semiconductor device includes the following steps:

[0092] Step S101, providing a substrate 10;

[0093] In step S102, a stacked structure is formed on the substrate 10. The stacked structure includes a plurality of memory layers spaced apart along a second direction D2. The memory layers include a plurality of memory cells 21 arranged along a first direction D1. Adjacent memory cells 21 in the memory layers along the first direction D1 are electrically connected. The memory cells 21 include a phase change structure 50 and a transistor structure located above and electrically connected to the phase change structure 50 along the second direction D2. The transistor structure includes a first channel region 32. The phase change structure 50 includes a phase change layer 31. The resistance of the first channel region 32 is less than the resistance of the phase change layer 31. The first direction D1 is parallel to the top surface of the substrate 10, and the second direction D2 is perpendicular to the top surface of the substrate 10. The term "plurality" in this embodiment refers to more than two.

[0094] For example, dopant ions are implanted into the substrate 10 to form a P-well region 103, such as Figure 11 Afterwards, a conductive material such as TiN is deposited on the substrate 10 to form an initial conductive layer. The initial conductive layer is patterned to form a plurality of conductive blocks 100 spaced apart along the first direction D1 and the third direction D3, as shown. Figure 11 As shown. Next, a first gating region, a second gating region, and a storage cell region located between the first gating region and the second gating region along the first direction D1 are defined on the substrate 10. Then, the phase change layer 31 is formed between the two conductive blocks 100 adjacent to each other along the first direction D1 in the storage cell region, and the two conductive blocks 100 located on opposite sides of the phase change layer 31 along the first direction D1 serve as the first electrode 301 and the second electrode 302 of the phase change structure 50. Next, a polysilicon material doped with P-type ions is deposited on the phase change layer 31 and between the adjacent conductive blocks 100 along the first direction D1 in the first gating region, and between the adjacent conductive blocks 100 along the first direction D1 in the second gating region, forming the first channel region 32 located above the phase change layer 31 in the storage region, forming the second channel region 41 in the first gating region, and forming the third channel region 45 in the second gating region, as shown. Figure 12As shown. The two conductive blocks 100 on opposite sides of the second channel region 41 along the first direction D1 serve as the first conductive layer 48 and the second conductive layer 49 in the first gating structure. The two conductive blocks 100 on opposite sides of the third channel region 45 along the first direction D1 serve as the third conductive layer and the fourth conductive layer in the second gating structure. Polysilicon material is deposited on the first electrode 301, the second electrode 302, the first conductive layer 48, the second conductive layer 49, the third conductive layer and the fourth conductive layer to form an initial source and drain layer. Then, the gate dielectric layer 15 covering the initial source and drain layer is formed, as shown. Figure 12 shown.

[0095] Then, the word line 11 is formed on the gate dielectric layer 15 and is located above the first channel region 32. The first gate line 12 is located above the second channel region 41. The second gate line 13 is located above the third channel region 45. Then, N-type ions are implanted into the initial source and drain layer to form the first source region 331 and the first drain region 332 located on opposite sides of the first channel region 32 along the first direction D1. The second source region 43 and the second drain region 42 are also formed on opposite sides of the second channel region 41 along the first direction D1. The third source region 47 and the third drain region 46 are also formed on opposite sides of the third channel region 45 along the first direction D1. Figure 3 and Figure 4 Then, the first isolation layer 90 is formed to cover the word line 11, the first gate line 12 and the second gate line 13, and the second isolation layer 91 is formed to cover the first isolation layer 90. Figure 13 As shown. Then, the first isolation layer 90 and the second isolation layer 91 above the third source region 47 in the second gating structure are removed to expose the third source region 47. A bit line plug 40 and the bit line 14 electrically connected to the bit line plug 40 are formed above the third source region 47, as shown. Figure 4 and Figure 14 As shown. Then, the next memory layer is formed above the second isolation layer 91 until a stacked structure of a plurality of memory layers spaced apart along the second direction D2 is formed. After the stacked structure is formed, a plurality of source line plugs 44 are formed extending into the stacked structure along the second direction D2, and the source line 20 is formed above the source line plugs 44 and electrically connected to all the source line plugs 44, as shown. Figure 9 shown.

[0096] Some embodiments of this specific embodiment provide a storage structure and an operation method thereof, a semiconductor device and a formation method thereof. A phase change storage cell is formed by setting a transistor structure and a phase change structure electrically connected to the transistor structure in the storage cell, and multiple storage cells in the storage layer are electrically connected. The resistance of the first channel region in the transistor structure is smaller than the resistance of the phase change layer in the phase change structure. Thus, the target storage cell can be stored by turning off the transistor structure in the target storage cell in the storage layer and turning on the transistor structure in other storage cells that are in the same storage layer as the target storage cell and are electrically connected to the target storage cell. This simplifies the read and write operations of the storage cell, improves the read and write efficiency of the storage cell, improves the performance of the semiconductor device, and can also increase the storage density of the semiconductor device, reduce the manufacturing cost of the semiconductor device, and expand the application field of the semiconductor device.

[0097] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A storage structure, characterized in that: include: substrate; A storage layer is located on the substrate, the storage layer includes a plurality of storage cells arranged along a first direction, and the storage cells adjacent to each other along the first direction in the storage layer are electrically connected, the storage cells include a phase change structure, and a transistor structure located above the phase change structure along a second direction and electrically connected to the phase change structure, the transistor structure includes a first channel region, the phase change structure includes a phase change layer, the resistance of the first channel region is less than the resistance of the phase change layer, the first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate.

2. The storage structure according to claim 1, characterized in that: The transistor structure further includes a first source region and a first drain region located on opposite sides of the first channel region along the first direction; the phase change structure further includes a first electrode and a second electrode located on opposite sides of the phase change layer along the first direction, the first source region is located on a surface of the first electrode, the first drain region is located on a surface of the second electrode, and the first channel region is located on a surface of the phase change layer; In two adjacent memory cells along the first direction, the first source region in one memory cell is electrically connected to the first drain region in the other memory cell, and the first electrode in one memory cell is electrically connected to the second electrode in the other memory cell.

3. The storage structure according to claim 2, characterized in that: The memory layer includes a plurality of memory columns arranged at intervals along a third direction, each memory column includes a plurality of memory cells arranged along the first direction, the transistor structures in adjacent memory cells in the memory columns are electrically connected, and the third direction is parallel to the top surface of the substrate and intersects with the first direction; The storage structure also includes: a word line group located on the substrate, the word line group comprising a plurality of word lines spaced apart along the first direction, the word lines extending along the third direction and covering the first channel regions of the plurality of transistor structures in the storage layer; A bit line is located on the substrate, and the bit line is electrically connected to the transistor structure in the storage layer.

4. The storage structure according to claim 3, characterized in that: The storage column includes a first end and a second end that are relatively distributed along the first direction; the storage column further includes: a first gating structure electrically connected to the transistor structure in the memory cell located at the first end; a second gating structure electrically connected to the transistor structure in the memory cell at the second end; The first gating structure includes a second channel region, and a second source region and a second drain region located on opposite sides of the second channel region along the first direction; the second gating structure includes a third channel region, and a third source region and a third drain region located on opposite sides of the third channel region along the first direction; the storage structure further includes: a first gate line covering the second channel region of the first gate structure in the storage layer; A second gate line covers the third channel region of the second gate structure in the storage layer.

5. The storage structure according to claim 4, characterized in that: Also includes: a source line located above the storage layer and electrically connected to the second drain region of the first gating structure, wherein the second source region of the first gating structure is electrically connected to the first drain region of the storage unit located at the first end; The third drain region of the second gating structure is electrically connected to the first source region of the memory cell located at the second end, and the bit line is electrically connected to the third source region of the second gating structure.

6. The storage structure according to claim 4, characterized in that: The first gating structure also includes a first conductive layer and a second conductive layer connected to opposite sides of the second channel region along the first direction, the second source region is located above the first conductive layer and electrically connected to the first conductive layer, the second drain region is located above the second conductive layer and electrically connected to the second conductive layer, the first conductive layer, the second conductive layer, the first electrode and the second electrode are arranged in the same layer, and the sum of the thickness of the first channel region along the second direction and the thickness of the phase change layer along the second direction is equal to the thickness of the second channel region along the second direction.

7. A semiconductor device, characterized in that: include: substrate; A stacked structure is located on the substrate and includes a plurality of storage layers arranged at intervals along a second direction, the storage layers include a plurality of storage cells arranged along a first direction, and the storage cells adjacent to each other along the first direction in the storage layers are electrically connected, the storage cells include a phase change structure, and a transistor structure located above the phase change structure along the second direction and electrically connected to the phase change structure, the transistor structure includes a first channel region, the phase change structure includes a phase change layer, the resistance of the first channel region is less than the resistance of the phase change layer, the first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate.

8. The semiconductor device according to claim 7, wherein: Also includes: a word line structure located on the substrate, comprising a plurality of word line groups arranged at intervals along the second direction, the word line groups comprising a plurality of word lines arranged at intervals along the first direction, the word lines extending along a third direction and covering the plurality of transistor structures in the storage layer, the third direction being parallel to the top surface of the substrate and intersecting the first direction; The bit line structure is located on the substrate and includes a plurality of bit lines spaced apart along the second direction. The bit lines extend along the third direction, and each bit line is electrically connected to all the transistor structures in one storage layer.

9. A method for forming a semiconductor device, characterized in that: The steps include: providing a substrate; A stacked structure is formed on the substrate, the stacked structure including a plurality of storage layers arranged at intervals along a second direction, the storage layers including a plurality of storage cells arranged along a first direction, the storage cells adjacent to each other along the first direction in the storage layers being electrically connected, the storage cells including a phase change structure, and a transistor structure located above the phase change structure along the second direction and electrically connected to the phase change structure, the transistor structure including a first channel region, the phase change structure including a phase change layer, the resistance of the first channel region being less than the resistance of the phase change layer, the first direction being parallel to the top surface of the substrate, and the second direction being perpendicular to the top surface of the substrate.

10. A method for operating the storage structure according to claim 1, characterized in that: The steps include: Selecting one of the storage units in the storage layer as a target storage unit to be read or written; The transistor structure in the target memory cell is turned off, and the transistor structures in the other memory cells that are in the same memory layer as the target memory cell and are electrically connected to the target memory cell are turned on.

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