Quasi-vertical super junction diode and monolithic integrated full-bridge rectifier circuit

Abstract

The invention discloses a quasi-vertical super-junction diode and a monolithic integrated full-bridge rectifier circuit. The diode comprises a Si substrate, an N + GaN conduction layer and a heterogeneous super-junction structure layer which are sequentially arranged from bottom to top, p-BN ring regions and N GaN ring regions are arranged in the heterogeneous super-junction structure layer at intervals along the longitudinal direction in a concentric ring distribution mode; a P-type BN material doped with Mg is arranged in the P-BN ring region and on the side surface of the heterogeneous super-junction structure layer; an anode is arranged on the surface of the heterogeneous super-junction structure layer; the surface of the N + GaN conduction layer is provided with a cathode which surrounds the heterogeneous super-junction structure layer and is spaced from the heterogeneous super-junction structure layer. The monolithic integrated full-bridge rectifier circuit comprises two alternating current input ends, a rectifier circuit composed of four diodes, a filter circuit composed of two filter capacitors and a filter resistor, and two output ends, wherein the diodes are quasi-vertical super-junction diodes. According to the invention, diode withstand voltage and circuit integration can be improved, a voltage application window is widened, power processing capability is enhanced, and conversion efficiency is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductors, and in particular relates to a quasi-vertical super junction diode and a monolithic integrated full-bridge rectifier circuit. Background Art

[0002] Compared with Si-based materials, third-generation semiconductor materials such as GaN have excellent electrical properties such as large bandgap, high critical breakdown electric field, high saturation velocity, good thermal conductivity, high temperature resistance and corrosion resistance, and are considered suitable for applications in high frequency, high power, strong radiation, etc. In recent years, thanks to excellent characteristics such as low saturation velocity, low breakdown voltage, low inversion layer mobility and high device resistance, GaN-based power devices have developed rapidly and have been widely used in power systems.

[0003] Full-bridge rectifier circuits are mostly composed of discrete devices with low integration. In the existing technology, most GaN power devices are still used in the form of single tubes in rectifier circuits. However, with the increasing requirements for the power handling capacity of the rectifier system and the miniaturization of equipment, as well as the diversification of usage scenarios, higher requirements are placed on the reliability of the circuit system. The existing board-level integrated rectifier system will become increasingly difficult to adapt to the needs of the development of the times. Compared with traditional GaN integrated circuits, silicon-based GaN monolithic integrated circuits have smaller size, smaller parasitics, higher power density, lower cost and higher reliability, allowing them to be used in power systems with complex working environments and limited volume, such as small-volume high-power power supplies, new energy vehicles, photovoltaic inverters, electric locomotive traction modules and other occasions.

[0004] However, the existing GaN-based monolithic rectifier circuit has low waveform rectification efficiency and low circuit carrying capacity. In addition, the voltage application window of the full-bridge rectifier circuit is narrow, and the withstand voltage level of its core device diode is low, which restricts the performance and development of the full-bridge rectifier circuit. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a quasi-vertical super junction diode and a monolithic integrated full-bridge rectifier circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a quasi-vertical super junction diode, comprising:

[0007] A Si substrate, an N+GaN conductive layer, and a heterogeneous superjunction structure layer are arranged in sequence from bottom to top; in the heterogeneous superjunction structure layer, a P-BN ring region and an N GaN ring region are arranged in a concentric ring distribution manner along the longitudinal direction; the inside of the P-BN ring region and the side of the heterogeneous superjunction structure layer are all P-type BN materials doped with Mg; an anode is arranged on the surface of the heterogeneous superjunction structure layer; and a cathode is arranged on the surface of the N+GaN conductive layer, which surrounds the heterogeneous superjunction structure layer and has a spacing.

[0008] In one embodiment of the present invention, the doping concentration of Si in the N+GaN conducting layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 .

[0009] In one embodiment of the present invention, the doping concentration of Si in the N GaN ring region is 1.8×10 15 cm -3 ~1.5×10 16 cm -3 .

[0010] In one embodiment of the present invention, the doping concentration of Mg in the P-type BN material is 1.7×10 14 cm -3 ~1.0×10 16 cm -3 .

[0011] In one embodiment of the present invention, the depth of the P-BN ring region is 1 μm to 6 μm; the widths of the P-BN ring region and the N GaN ring region are 3 μm to 5 μm.

[0012] In a second aspect, an embodiment of the present invention provides a method for preparing a quasi-vertical super junction diode, which is used to prepare the quasi-vertical super junction diode described in the first aspect, and the method for preparing the quasi-vertical super junction diode includes:

[0013] Obtaining a Si-based GaN epitaxial layer structure, wherein the Si-based GaN epitaxial layer structure comprises, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer;

[0014] Etching and removing the outer N+GaN conduction layer and the N-type GaN drift layer to expose the Si substrate and form a step structure;

[0015] The outer N-type GaN drift layer is removed by etching, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a step structure;

[0016] Etching a plurality of groove structures distributed in concentric rings from the top of the N-type GaN drift layer downwards, and etching to a depth to expose the N+GaN conducting layer;

[0017] The P-type BN material doped with Mg is sputtered inside the groove structure, on the surface of the device, and on the side of the N-type GaN drift layer by using a magnetron sputtering process, and a thermal annealing treatment is performed, so that the N-type GaN drift layer forms a P-BN ring region and an N GaN ring region distributed in concentric rings;

[0018] Growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate;

[0019] The passivation layer on the upper surface of the device is removed to expose the P-type BN material layer, and the passivation layer at predetermined positions on both sides of the N+GaN conductive layer is removed to form a cathode contact opening; and an opening is etched at a position corresponding to the N GaN ring region in the exposed P-type BN material layer to form an anode contact opening;

[0020] An anode is formed by metal evaporation inside and on the surface of the anode contact opening, and a cathode is formed by metal evaporation inside and on the surface of the cathode contact opening, which surrounds the N-type GaN drift layer and has a certain distance therebetween.

[0021] In a third aspect, an embodiment of the present invention provides a monolithic integrated full-bridge rectifier circuit, comprising:

[0022] A first AC input terminal, a second AC input terminal, a positive polarity forward diode, a positive polarity reverse diode, a negative polarity forward diode, a negative polarity reverse diode, a first filter capacitor, a filter resistor, a second filter capacitor, a first output terminal, and a second output terminal; wherein,

[0023] The first AC input terminal is connected to the anode of the positive polarity end forward diode and the cathode of the positive polarity end reverse diode;

[0024] The second AC input terminal is connected to the anode of the forward diode at the negative polarity end and the cathode of the reverse diode at the negative polarity end;

[0025] The cathode of the positive polarity end forward diode is connected to the cathode of the negative polarity end forward diode, the first end of the first filter capacitor, and the first end of the filter resistor;

[0026] The second end of the filter resistor is connected to the first end of the second filter capacitor and the first output end;

[0027] The anode of the positive polarity end reverse diode is connected to the anode of the negative polarity end reverse diode, the second end of the first filter capacitor, the second end of the second filter capacitor, and the second output end;

[0028] Among them, the forward diode at the positive polarity end, the reverse diode at the positive polarity end, the forward diode at the negative polarity end and the reverse diode at the negative polarity end constitute a rectifier circuit, each diode is implemented by the quasi-vertical super junction diode described in the first aspect, and the preparation method is the preparation method of the quasi-vertical super junction diode described in the second aspect; the first filter capacitor, the filter resistor and the second filter capacitor constitute an RC filter circuit.

[0029] In one embodiment of the present invention, the working principle of the monolithic integrated full-bridge rectifier circuit includes:

[0030] The rectifier circuit is used to convert the bidirectional alternating current input from the first alternating current input terminal and the second alternating current input terminal into a unidirectional pulsating current;

[0031] The high-frequency AC component in the unidirectional pulsating current is removed by using the RC filter circuit, so that the DC component is converted into the DC and then output through the first output terminal and the second output terminal.

[0032] In one embodiment of the present invention, the working principle of the rectifier circuit includes:

[0033] When the input signal is a positive periodic voltage, the first AC input terminal is positive polarity, the second AC input terminal is negative polarity, the forward diode at the positive polarity terminal is turned on, the reverse diode at the positive polarity terminal is turned off, the reverse diode at the negative polarity terminal is turned on, and the forward diode at the negative polarity terminal is turned off; the input AC voltage value is the voltage difference between the first AC input terminal and the second AC input terminal, the first output terminal is positive polarity, and the second output terminal is negative polarity;

[0034] When the input signal is a negative periodic voltage, the first AC input terminal is negative polarity, and the second AC input terminal is positive polarity; the forward diode at the positive polarity terminal is cut off, and the reverse diode at the positive polarity terminal is turned on, the reverse diode at the negative polarity terminal is cut off, and the forward diode at the negative polarity terminal is turned on; the input AC voltage value is the voltage difference between the second AC input terminal and the first AC input terminal, the first output terminal is positive polarity, and the second output terminal is negative polarity.

[0035] In a fourth aspect, an embodiment of the present invention provides a method for preparing a monolithic integrated full-bridge rectifier circuit, which is used to prepare the monolithic integrated full-bridge rectifier circuit described in the third aspect, and the method for preparing the monolithic integrated full-bridge rectifier circuit includes:

[0036] On the same Si substrate of the Si-based GaN epitaxial layer structure, a plurality of quasi-vertical super junction diodes are obtained; wherein the Si-based GaN epitaxial layer structure comprises, from bottom to top, a Si substrate, an N+GaN conducting layer and an N-type GaN drift layer; each quasi-vertical super junction diode is prepared by the preparation method of the quasi-vertical super junction diode described in the second aspect;

[0037] On the surface of the passivation layer on the Si substrate, a TaN target is used to form a resistive film by sputtering;

[0038] A passivation layer is grown again on all surfaces and sides of the Si substrate where the multi-device structure is exposed, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form a first layer of metal interconnection according to the connection requirements of the monolithic integrated full-bridge rectifier circuit;

[0039] The passivation layer is grown again, holes are opened by etching the passivation layer, and metal evaporation and filter capacitor preparation are performed in the holes. According to the connection requirements of the monolithic integrated full-bridge rectifier circuit, a second layer of metal interconnection is formed.

[0040] Beneficial effects of the present invention:

[0041] The diode of the embodiment of the present invention uses silicon-based GaN material, which can reduce the circuit cost. The groove is filled with Mg-doped P-type BN material on the silicon-based gallium nitride substrate to form a heterogeneous superjunction structure composed of P-BN and N GaN, thereby forming a Mg-doped P-type BN-SJ superjunction quasi-vertical diode. In the superjunction structure, the P-BN layer and the N-GaN layer are arranged in a longitudinal groove structure. After the reverse voltage is applied, the depletion layer diffuses laterally and finally integrates to form a depletion layer "equivalent to the groove depth". At this time, as long as the depletion layer of each PN junction diffuses to half of the groove interval, a depletion layer with a thickness equivalent to the groove depth can be obtained, so that the withstand voltage value of the device is improved. The present invention uses a quasi-vertical diode with Mg-doped P-type BN superjunction technology to replace the traditional Schottky diode, and utilizes the high breakdown field strength of BN material (boron nitride), the electric field adjustment ability of the JBS ring structure, and the suppression of the sidewall leakage current by the sidewall coverage of the P-BN device to improve the withstand voltage of the diode.

[0042] The monolithic integrated full-bridge rectifier circuit provided by the embodiment of the present invention is realized based on the provided quasi-vertical superjunction diode. It is the first full-bridge rectifier monolithic integrated circuit based on silicon-based GaN quasi-vertical Schottky diode, which realizes the improvement of integration, greatly reduces the circuit volume, and can improve the circuit reliability. At present, the voltage resistance level of the core device diode of the rectifier circuit is low, and the present invention adopts Mg-doped P-type BN superjunction technology to improve the quasi-vertical diode to replace the traditional Schottky diode, and utilizes the high breakdown field strength of the BN material and the electric field regulation ability of the superjunction structure to greatly improve the voltage resistance level of the Schottky diode, broaden the voltage application window of the full-bridge rectifier circuit, and enhance the power handling capacity of the rectifier circuit. The conversion efficiency of the existing half-wave rectifier circuit is low, and the half-wave rectifier circuit can only use half of the AC signal, and the utilization rate of the input AC power is low. The present invention adopts a bridge full-wave rectifier circuit, which can fully use the positive half-cycle and negative half-cycle of the AC signal, and can effectively improve the conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A three-dimensional schematic diagram of a quasi-vertical super junction diode provided by an embodiment of the present invention;

[0044] Figure 2 A three-dimensional cross-sectional schematic diagram of a quasi-vertical super junction diode provided by an embodiment of the present invention;

[0045] Figure 3 A schematic diagram for comparing quasi-vertical super junction diodes of different sizes provided by an embodiment of the present invention;

[0046] Figure 4 A schematic flow chart of a method for preparing a quasi-vertical super junction diode provided by an embodiment of the present invention;

[0047] Figure 5a to Figure 5j A schematic diagram of a process flow of a method for preparing a quasi-vertical super junction diode provided by an embodiment of the present invention;

[0048] Figure 6 A circuit schematic diagram of a monolithic integrated full-bridge rectifier circuit provided in an embodiment of the present invention;

[0049] Figure 7 An overall three-dimensional schematic diagram of a monolithic integrated full-bridge rectifier circuit provided by an embodiment of the present invention;

[0050] Figure 8 A schematic top view of a monolithic integrated full-bridge rectifier circuit provided in an embodiment of the present invention;

[0051] Fig. 9 A schematic flow chart of a method for preparing a monolithic integrated full-bridge rectifier circuit provided in an embodiment of the present invention;

[0052] Figure 10a to Figure 10h A schematic diagram of a process flow of a method for preparing a monolithic integrated full-bridge rectifier circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0054] In a first aspect, an embodiment of the present invention provides a quasi-vertical super junction diode, see Figure 1 The three-dimensional schematic diagram of the quasi-vertical super junction diode shown in Figure 2 The three-dimensional cross-sectional diagram of the quasi-vertical super junction diode shown in FIG. Figure 3 The quasi-vertical super junction diodes of different sizes are shown in the figure. The quasi-vertical super junction diode includes:

[0055] A Si substrate, an N+GaN conductive layer, and a heterogeneous superjunction structure layer are arranged in sequence from bottom to top; in the heterogeneous superjunction structure layer, a P-BN ring region and an N GaN ring region are arranged in a concentric ring distribution manner along the longitudinal direction; the inside of the P-BN ring region and the side of the heterogeneous superjunction structure layer are all P-type BN materials doped with Mg; an anode is arranged on the surface of the heterogeneous superjunction structure layer; and a cathode is arranged on the surface of the N+GaN conductive layer, which surrounds the heterogeneous superjunction structure layer and has a spacing.

[0056] in, Figure 1 to Figure 3 In the figure, Si Substarte represents Si substrate; N+GaN represents N+GaN conductive layer; N GaN represents N-type GaN drift layer; P-BN represents P-type BN material doped with Mg; P-BN SJ (SJ represents super junction) column represents the columnar region shown in the cross section of the P-BN ring region; N GaN SJ column represents the columnar region shown in the cross section of the N GaN ring region; P-BN ring represents the P-BN ring region; NGaN ring represents the N GaN ring region.

[0057] Specifically, the Si substrate may adopt a 111 crystal plane.

[0058] The N+GaN conducting layer is located on the upper surface of the Si substrate and has a cylindrical structure. Its thickness can be set as required, for example, about 0.6 μm to 1 μm.

[0059] In an optional embodiment, the doping concentration of Si in the N+GaN conducting layer may be 1.0×10 18 cm -3 ~1.0×10 20 cm -3It is understandable that, generally speaking, the higher the doping concentration, the lower the cathode electrode contact resistance, and the smaller the overall on-resistance will be after the device is turned on. However, too high a concentration may reduce the device withstand voltage to a certain extent, so it needs to be reasonably selected according to needs.

[0060] The N-type GaN drift layer is located in the central area of ​​the upper surface of the N+GaN conduction layer and is a cylindrical structure. Its thickness can be set as needed, for example, it can be around 3μm to 5μm. The N-type GaN drift layer is etched to have P-BN ring areas and N GaN ring areas spaced apart in a concentric ring distribution along the longitudinal direction. Figure 2 and Figure 3 It is understood that the P-BN ring area and the N GaN ring area are nested in size, arranged at intervals, and distributed in concentric circles. The number of P-BN rings and N GaN rings can be determined according to the flow demand, and single rings or multiple rings are both possible.

[0061] Figure 2 The depth of the P-BN SJ column represents the depth of the P-BN ring region, the width of the P-BN SJ column represents the width of the P-BN ring region, the depth of the N GaN SJ column represents the depth of the N GaN ring region, and the width of the N GaN SJ column represents the width of the N GaN ring region; in the embodiment of the present invention, the lower surface of the P-BN ring region and the lower surface of the N GaN ring region are flush, and both contact the N+GaN conductive layer; in an optional implementation manner, the depth of the P-BN ring region may be 1μm to 6μm; the widths of the P-BN ring region and the N GaN ring region may be 3μm to 5μm.

[0062] The doping concentration of Si in the N-type GaN drift layer, that is, the doping concentration of Si in the N GaN ring region, can be 1.8×10 15 cm -3 ~1.5×10 16 cm -3 . This doping concentration will also affect the device's withstand voltage. Theoretically, the lower the doping concentration, the higher the device's withstand voltage will be. It will also affect the device's forward conduction characteristics. The lower the doping concentration, the greater the forward conduction resistance. Therefore, this value needs to be considered together with the Si doping concentration in the N+GaN conduction layer and the Mg doping concentration in the P-BN. Moreover, in the superjunction structure, if you want to obtain the best withstand voltage level, the concentration of the N region must also match the concentration of the P BN to ensure that the depletion layer can be fully expanded before breakdown occurs. For details, please refer to the concentration relationship in the basic structure of the superjunction described in the relevant part of formula (1) below.

[0063] The P-BN ring region and the side surfaces of the heterogeneous super junction structure layer are all P-type BN materials doped with Mg, such as Figure 3As shown, the Mg-doped P-type BN material also covers part of the upper surface of the N-type GaN drift layer, that is, the upper surface of the P-BN ring region is slightly higher than the upper surface of the N GaN ring region, and occupies part of the upper surface area of ​​the N GaN ring region. Figure 3 The cross section of the P-BN ring region is T-shaped.

[0064] The doping concentration of Mg in the P-type BN material will affect the depletion capability of the P-BN ring in the reverse direction. Generally speaking, a higher concentration means a stronger depletion capability, and the reverse withstand voltage of the device will also be improved to a certain extent. However, when the concentration rises to a certain level, the withstand voltage will no longer continue to increase or even degrade. In an optional embodiment, the doping concentration of Mg in the P-type BN material can be 1.7×10 14 cm -3 ~1.0×10 16 cm -3 .

[0065] An anode is arranged on the surface of the heterogeneous super junction structure layer; a cathode is arranged on the surface of the N+GaN conductive layer, surrounding the heterogeneous super junction structure layer and having a spacing, Figure 1 and Figure 2 It can be seen that the cathode is also in the shape of a ring.

[0066] The anode metal may be Ni / Au; the cathode metal may be Ti / Al / Ni / Au.

[0067] It should be noted that, as a quasi-vertical super junction diode used alone, the side passivation layer does not need to be retained, wherein the passivation layer such as Figure 3 This is shown in the white area on the side of the device.

[0068] The diode in the embodiment of the present invention adopts a quasi-vertical diode structure. Unlike the conventional vertical device, the current is only transported vertically. The anode and cathode are on the front and back of the wafer respectively. The anode and cathode of the quasi-vertical device are on the same surface (see Figure 1 and 2 Such a quasi-vertical structure facilitates the subsequent use of on-chip wiring to connect devices to complete circuit construction.

[0069] The diode of the embodiment of the present invention uses silicon-based GaN material, which can reduce the circuit cost. The grooves are filled with Mg-doped P-type BN material on the silicon-based gallium nitride substrate to form a heterogeneous superjunction structure composed of P-BN and N GaN, thereby forming a Mg-doped P-type BN-SJ superjunction quasi-vertical diode. In the superjunction structure, the P-BN layer and the N-GaN layer are arranged in a longitudinal groove structure. After the reverse voltage is applied, the depletion layer diffuses laterally and finally integrates to form a depletion layer "equivalent to the groove depth". At this time, as long as the depletion layer of each PN junction diffuses to half of the groove interval, a depletion layer with a thickness equivalent to the groove depth can be obtained, so that the withstand voltage value of the device is improved. The present invention adopts a quasi-vertical diode improved by Mg-doped P-type BN superjunction technology to replace the traditional Schottky diode, and utilizes the high breakdown field strength of BN material (boron nitride), the electric field regulation capability of the JBS (junction barrier Schottky diode) ring structure, and the suppression of sidewall leakage current by the sidewall coverage of the P-BN device to improve the withstand voltage of the diode. If the proposed quasi-vertical superjunction diode is subsequently used to construct a monolithic integrated full-bridge rectifier circuit, the power processing capability of the rectifier circuit can be enhanced.

[0070] In the embodiment of the present invention, in order to ensure that the superjunction obtains the best reverse withstand voltage performance, it is required that the N GaN region and the P-BN region in the drift region are completely depleted at the critical breakdown voltage and can achieve the best charge compensation. The width of the N GaN region and the P-GaN region in the drift region and the doping concentration Q of the N and P regions are n With Q p The following relationship must be satisfied:

[0071]

[0072] Among them, Q n and Q p Respectively represent the doping concentration of N and P regions, that is, the total charge density of ionized impurities in the depletion layer; for simplicity, they are described as N region and P region respectively; ε sn and ε sp Respectively represent the relative dielectric constants of the N-region and P-region materials, E cn and E cp are the critical breakdown electric fields of the N-region material and the P-region material, respectively; in the embodiment of the present invention, the N-region material is an N-type doped GaN material; the P-region material is an Mg-doped BN material; q represents the elementary charge constant, which is 1.6×10 -19 ; W n and W p are the widths of the N column and P column in the super junction structure respectively; N D and N A They are the impurity concentrations activated in the N region and the P region respectively.

[0073] In a second aspect, an embodiment of the present invention provides a method for preparing a quasi-vertical super junction diode, which is used to prepare the quasi-vertical super junction diode described in the first aspect, see Figure 4 , the method for preparing the quasi-vertical super junction diode may include the following steps:

[0074] S1, obtaining a Si-based GaN epitaxial layer structure, wherein the Si-based GaN epitaxial layer structure includes, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer;

[0075] For the structure of GaN epitaxial layer on Si, please refer to Figure 5a It is understood that Si Substarte means Si substrate; N+GaN means N+GaN conductive layer; N GaN means N-type GaN drift layer.

[0076] The Si substrate may adopt a 111 crystal plane. The doping concentration of Si in the N+GaN conducting layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 The doping concentration of Si in the N-type GaN drift layer is 1.8×10 15 cm -3 ~1.5×10 16 cm -3 .

[0077] S2, etching and removing the outer N+GaN conducting layer and the N-type GaN drift layer to expose the Si substrate and form a step structure;

[0078] This step is to perform mesa isolation etching to isolate each active device area. Specifically, the outer side of the N-type GaN drift layer and the N+GaN conduction layer is etched downward until the Si substrate is exposed. It can be understood that the retained N-type GaN drift layer and the N+GaN conduction layer are in a cylindrical structure. The etching adopts Cl-based ICP (inductively coupled) etching, and the etching gases are mainly Cl2 and BCl3, among which BCl3 is a sidewall protection gas, which can effectively improve the selectivity and improve the etching morphology. The etching power adopts fast etching conditions, with an upper power between 130W and 140W, a lower power between 40W and 50W, and a cavity pressure between 5 and 7mt. The device structure formed in this step is shown in Figure 5b shown.

[0079] S3, etching and removing the outer N-type GaN drift layer, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a step structure;

[0080] This step is to perform mesa etching, and etch down the N-type GaN drift layer on the outside to expose the N+GaN conduction layer for subsequent cathode metal evaporation. It can be understood that the retained N-type GaN drift layer is still a cylindrical structure. The etching conditions of this step are consistent with S2, and the etching depth is about 1μm. The device structure formed in this step is shown in Figure 5c shown.

[0081] S4, etching a plurality of groove structures distributed in concentric rings from the top of the N-type GaN drift layer downwards, and etching to a depth to expose the N+GaN conducting layer;

[0082] This step is to perform SJ deep trench etching in the P-type super junction area of ​​the anode region. Cl-based ICP etching is also used. However, since the N+GaN conduction layer has higher requirements for etching damage than MESA (table), only a smaller etching power can be used. The upper electrode power is between 55W and 70W, and the lower electrode power is between 14W and 20W. The etched groove structure is distributed in concentric rings. The depth of the groove structure can be 1μm to 6μm, and the width can be 3μm to 5μm.

[0083] The device structure formed in this step is shown in Figure 5d shown.

[0084] S5, sputtering a P-type BN material doped with Mg inside the groove structure, on the surface of the device, and on the side of the N-type GaN drift layer by a magnetron sputtering process, and performing a thermal annealing treatment, so that the N-type GaN drift layer forms a P-BN ring region and an N GaN ring region distributed in concentric rings;

[0085] This step is to sputter P-BN and perform thermal annealing to activate impurities to achieve P-BN deposition. Specifically, a dual-target RF magnetron sputtering method is used to grow the P-BN layer inside the groove structure, on the surface of the device, and on the side of the N-type GaN drift layer. The chamber pressure is between 4 and 6mt, the sputtering gas is Ar, and the sputtering power is 140 to 150W. The sputtering depth needs to be adjusted according to the depth of the groove structure (i.e., the P-BN groove), which needs to be slightly greater than the etching depth of the P-BN groove. After sputtering, anneal at 1100 to 1200°C for more than 10 minutes to activate Mg impurities. The device structure formed in this step is shown in Figure 5e As shown, it can be understood that the N-type GaN drift layer forms a P-BN ring region and an N GaN ring region distributed in concentric rings, and there is also Mg-doped P-type BN material (P-BN for short) on the surface and side.

[0086] S6, growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate;

[0087] like Figure 5fAs shown, a SiN passivation layer is grown on the entire upper surface and side surfaces of the device excluding the side surfaces of the Si substrate using PECVD (plasma enhanced chemical vapor deposition) equipment, with a target thickness of about 120 nm, using SiH4 and NH3 as the reaction gas, and He as the carrier gas, at a pressure of 600 mt and 250°C.

[0088] In order to distinguish it from the preparation method of the monolithic integrated full-bridge rectifier circuit described later, the passivation layer grown here is called the first passivation layer.

[0089] S7, removing the passivation layer on the upper surface of the device to expose the P-type BN material layer, and removing the passivation layer at predetermined positions on both sides of the N+GaN conductive layer to form a cathode contact opening; performing opening etching at a position corresponding to the N GaN ring region in the exposed P-type BN material layer to form an anode contact opening;

[0090] Figure 5g The figure shows the etching of the passivation layer. First, the passivation layer on the upper surface of the device is removed to expose the P-type BN material layer. The passivation layer at the predetermined positions on both sides of the N+GaN conductive layer can be removed at the same time to form a cathode contact opening. The cathode contact opening is on both sides of the N+GaN conductive layer and has a spacing with the N-type GaN drift layer.

[0091] The passivation layer is etched using F-based ICP etching to remove the SiN layer in the opening area. To ensure that the metal contact area is etched cleanly, an overetching amount of at least 40% to 50% must be ensured.

[0092] Figure 5h The figure shows P-BN etching, in which an opening is etched at the center position corresponding to the N GaN ring area in the exposed P-type BN material layer to form an anode contact opening; this etching adopts F-based ICP etching, and the main etching gases are SF6, CF4, CHF3, etc. Since BN etching is more difficult, the power used for etching is relatively large, wherein the upper power is between 150W and 200W, and the lower power is controlled at about 65 to 70W. Due to the high selectivity of F-based etching to GaN materials, the etching can be set to an etching over-etching amount greater than 30% of the target depth to ensure that the BN area to be etched can be etched cleanly.

[0093] S8, forming an anode by performing metal evaporation inside and on the surface of the anode contact opening, and forming a cathode surrounding the N-type GaN drift layer and having a certain distance therebetween by performing metal evaporation inside and on the surface of the cathode contact opening.

[0094] See also Figure 5i For the anode Schottky contact, metal Ni / Au is evaporated to form an anode (Anode). The metal layer is formed by evaporation, and the thickness adopts the thick gate condition Ni / Au=45 / 400 (nm), and the metal pattern is formed by metal lift-off.

[0095] See also Figure 5j For the cathode ohmic contact, metal Ti / Al / Ni / Au is evaporated to form a cathode (Cathode). The metal layer is formed by evaporation, and the thickness of each layer is A metal lift-off method is used to form a metal pattern.

[0096] In this way, a quasi-vertical super junction diode is finally formed. If the quasi-vertical super junction diode is used alone, the passivation layer can be removed. If other devices still need to be interconnected later, the passivation layer can be retained.

[0097] As mentioned above, the diode in the embodiment of the present invention is a Mg-doped P-type BN-SJ super junction diode, which is obtained by growing Mg-doped P-type BN material in grooves on a silicon-based gallium nitride substrate. While reducing circuit costs, a quasi-vertical heterojunction structure diode is formed by P-BN and NGaN, which can improve the withstand voltage of the diode.

[0098] In a third aspect, based on the proposed quasi-vertical superjunction diode, an embodiment of the present invention provides a monolithic integrated full-bridge rectifier circuit, see Figure 6 As shown in the circuit schematic diagram, the monolithic integrated full-bridge rectifier circuit includes:

[0099] A first AC input terminal, a second AC input terminal, a positive polarity forward diode, a positive polarity reverse diode, a negative polarity forward diode, a negative polarity reverse diode, a first filter capacitor, a filter resistor, a second filter capacitor, a first output terminal, and a second output terminal; wherein,

[0100] The first AC input terminal is connected to the anode of the positive polarity end forward diode and the cathode of the positive polarity end reverse diode;

[0101] The second AC input terminal is connected to the anode of the forward diode at the negative polarity end and the cathode of the reverse diode at the negative polarity end;

[0102] The cathode of the positive polarity end forward diode is connected to the cathode of the negative polarity end forward diode, the first end of the first filter capacitor, and the first end of the filter resistor;

[0103] The second end of the filter resistor is connected to the first end of the second filter capacitor and the first output end;

[0104] The anode of the positive polarity end reverse diode is connected to the anode of the negative polarity end reverse diode, the second end of the first filter capacitor, the second end of the second filter capacitor, and the second output end;

[0105] Among them, the forward diode at the positive polarity end, the reverse diode at the positive polarity end, the forward diode at the negative polarity end and the reverse diode at the negative polarity end constitute a rectifier circuit, each diode is implemented by the quasi-vertical super junction diode described in the first aspect, and the preparation method is the preparation method of the quasi-vertical super junction diode described in the second aspect; the first filter capacitor, the filter resistor and the second filter capacitor constitute an RC filter circuit.

[0106] Figure 6 In the figure, the first AC input terminal is marked with 1, the second AC input terminal is marked with 2, the first output terminal is marked with 3, and the second output terminal is marked with 4; the positive polarity end forward diode, the positive polarity end reverse diode, the negative polarity end forward diode, and the negative polarity end reverse diode are marked with D1, D2, D3, and D4 respectively; the first filter capacitor and the second filter capacitor are marked with C1 and C2 respectively, and the filter resistor is marked with R;

[0107] Figure 7 It is the overall three-dimensional schematic diagram of the monolithic integrated full-bridge rectifier circuit. Figure 8 This is a top view of the monolithic integrated full-bridge rectifier circuit. Ports 1 to 4 are the first AC input terminal, the second AC input terminal, the first output terminal, and the second output terminal, respectively. The light-colored connecting lines correspond to the first layer, and the light-colored connecting lines correspond to the second layer. For the connection relationship of each diode group in the first layer or the second layer, please refer to Figure 7 and Figure 8 Please understand the comparison, and I will not explain them one by one here.

[0108] The working principle of the monolithic integrated full-bridge rectifier circuit includes:

[0109] The rectifier circuit is used to convert the bidirectional alternating current input from the first alternating current input terminal and the second alternating current input terminal into a unidirectional pulsating current;

[0110] The high-frequency AC component in the unidirectional pulsating current is removed by using the RC filter circuit, so that the DC component is converted into the DC and then output through the first output terminal and the second output terminal.

[0111] The working principle of the rectifier circuit includes:

[0112] 1) When the input signal is a positive periodic voltage, the first AC input terminal is positive polarity, the second AC input terminal is negative polarity, the forward diode at the positive polarity terminal is turned on, the reverse diode at the positive polarity terminal is turned off, the reverse diode at the negative polarity terminal is turned on, and the forward diode at the negative polarity terminal is turned off; the input AC voltage value is the voltage difference between the first AC input terminal and the second AC input terminal, the first output terminal is positive polarity, and the second output terminal is negative polarity;

[0113] Specifically, when the input signal at the input end is a positive periodic voltage, the first AC input end 1 is positive polarity, and the second AC input end 2 is negative polarity. Due to the existence of the positive polarity voltage at the first AC input end 1, the positive polarity end forward diode D1 is turned on, and the positive polarity end reverse diode D2 is turned off; due to the existence of the negative polarity voltage at the second AC input end 2, the negative polarity end reverse diode D4 is turned on, and the negative polarity end forward diode D3 is turned off. Therefore, at this time, the input end starts from the first AC input end 1, and the loop is turned on through the positive polarity end forward diode D1, the load (and the RC filter circuit integrated at the output end), and the negative polarity end reverse diode D4. At this time, the output port voltage is the difference between the voltages of the first AC input end 1 and the second AC input end 2, that is, the input AC voltage value, and the first output end 3 is positive polarity, and the second output end 4 is negative polarity.

[0114] 2) When the input signal is a negative periodic voltage, the first AC input terminal is negative polarity, and the second AC input terminal is positive polarity; the forward diode at the positive polarity terminal is cut off, and the reverse diode at the positive polarity terminal is turned on, the reverse diode at the negative polarity terminal is cut off, and the forward diode at the negative polarity terminal is turned on; the input AC voltage value is the voltage difference between the second AC input terminal and the first AC input terminal, the first output terminal is positive polarity, and the second output terminal is negative polarity.

[0115] Specifically, when the input signal at the input end is a negative periodic voltage, the first AC input end 1 is negative polarity and the second AC input end 2 is positive polarity. Due to the presence of the negative polarity voltage at the first AC input end 1, the positive polarity forward diode D1 is cut off and the positive polarity reverse diode D2 is turned on; due to the presence of the positive polarity voltage at the second AC input end 2. At this time, the negative polarity reverse diode D4 is cut off and the negative polarity forward diode D3 is turned on. Therefore, at this time, the input end starts from the first AC input end, and the loop is turned on through the positive polarity reverse diode D2, the load (and the RC filter circuit), and the negative polarity forward diode D3. At this time, the output port voltage is the difference between the voltages of the second AC input end 2 and the first AC input end 1, that is, the input AC voltage value. And the first output end 3 is still positive polarity, and the second output end 4 is still negative polarity.

[0116] The waveform after rectification by the rectifier circuit changes from the bidirectional alternating current at the input end to a unidirectional pulsating current.

[0117] In an embodiment of the present invention, the first filter capacitor and the second filter capacitor are both MIM parallel plate dielectric capacitors suitable for monolithic integration process, the dielectric layer material is silicon nitride, the dielectric layer thickness range is 0.5μm to 5μm, the length and width of the capacitor plate are adjustable within 10μm to 100μm, and different capacitance values ​​are obtained by adjusting the dielectric layer thickness and the area of ​​the capacitor plate.

[0118] The filter resistor is a TFR on-chip microstrip resistor, and the materials constituting the resistor include TaN, NiCr, etc.; the required resistance value and corresponding current carrying capacity can be achieved through different aspect ratios.

[0119] For the RC filter circuit, the alternating current becomes a unidirectional pulsating current after being rectified by the rectifier circuit. This current still contains too many AC components, and an RC low-pass filter circuit is needed to remove the high-frequency AC components and convert the pulsating current into DC.

[0120] The RC filter circuit is an improved version of the single capacitor filter circuit, which is composed of two capacitors and one resistor. In the rising section of the positive polarity unidirectional pulsating signal, the first filter capacitor C1 is charged. Since the discharge of the capacitor takes a certain amount of time, the charge in the first filter capacitor C1 is not completely released before the next rising cycle of the pulsation, and will be recharged when the next cycle arrives, thereby achieving a first-level filtering. A filter resistor R is added between the first filter capacitor C1 and the second filter capacitor C2, so that most of the AC ripple filtered by the first filter capacitor C1 is applied to the filter resistor R, and is output to the load after secondary filtering by the second filter capacitor C2.

[0121] The filtering effect of the circuit is related to the RC value of the low-pass filter network and the frequency of the input signal. The larger the values ​​of the filter resistor R and the second filter capacitor C2, the better the filtering effect. However, an excessively large filter resistor R will affect the output voltage of the circuit, that is, the value of the filter resistor R1 should not be too large.

[0122] The monolithic integrated full-bridge rectifier circuit provided by the embodiment of the present invention is realized based on the provided quasi-vertical superjunction diode. It is the first full-bridge rectifier monolithic integrated circuit based on silicon-based GaN quasi-vertical Schottky diode, which realizes the improvement of integration, greatly reduces the circuit volume, and can improve the circuit reliability. At present, the voltage resistance level of the core device diode of the rectifier circuit is low, and the present invention adopts Mg-doped P-type BN superjunction technology to improve the quasi-vertical diode to replace the traditional Schottky diode, and utilizes the high breakdown field strength of the BN material and the electric field regulation ability of the superjunction structure to greatly improve the voltage resistance level of the Schottky diode, broaden the voltage application window of the full-bridge rectifier circuit, and enhance the power handling capacity of the rectifier circuit. The conversion efficiency of the existing half-wave rectifier circuit is low, and the half-wave rectifier circuit can only use half of the AC signal, and the utilization rate of the input AC power is low. The present invention adopts a bridge full-wave rectifier circuit, which can fully use the positive half-cycle and negative half-cycle of the AC signal, and can effectively improve the conversion efficiency.

[0123] In a fourth aspect, an embodiment of the present invention provides a method for preparing a monolithic integrated full-bridge rectifier circuit, which is used to prepare the monolithic integrated full-bridge rectifier circuit described in the third aspect, see Fig. 9 , the preparation method of the monolithic integrated full-bridge rectifier circuit comprises the following steps:

[0124] S100, obtaining a plurality of quasi-vertical super junction diodes prepared on a Si substrate having a same Si-based GaN epitaxial layer structure; wherein the Si-based GaN epitaxial layer structure comprises, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer; each quasi-vertical super junction diode is prepared by the preparation method of the quasi-vertical super junction diode described in the second aspect;

[0125] For details, please refer to the relevant content of the second aspect. The obtained single quasi-vertical super junction diode is as follows: Figure 5j As shown in the figure. Since S100 is made on the same Si substrate with GaN epitaxial layer structure, multiple quasi-vertical superjunction diodes are prepared. The results are shown in Fig.10a As shown, SiN x Represents the passivation layer, that is, the first passivation layer mentioned above. Layer1 represents the first layer.

[0126] S200, forming a resistive thin film on the surface of the passivation layer on the Si substrate by sputtering using a TaN target;

[0127] This step is to evaporate the resistor film, see Fig.10b Specifically, TaN target material is used to form a resistor film by sputtering, which is represented by Resist Film, that is, a filter resistor is formed. Fig.10b Shown on the right.

[0128] S300, growing a passivation layer again on all surfaces and sides of the Si substrate where the multi-device structure is exposed, opening holes by etching the passivation layer, and performing metal evaporation in the holes to form a first layer of metal interconnection according to the connection requirements of the monolithic integrated full-bridge rectifier circuit;

[0129] First, if Fig.10c As shown, a second passivation layer is grown (the passivation layer material is the same as the first layer, see SiN x , layer2 represents the second layer), covering all surfaces of the current structure.

[0130] Then as Fig.10d As shown, holes are opened in the anode region and cathode region of the diode by etching the second passivation layer, and holes are also opened in the two ends of the resistor film by etching the passivation layer. Metal Via represents a metal via, and Metal Via1 represents a first-layer metal via.

[0131] Afterwards, if Fig.10e As shown, metal is evaporated in the opening area, and a through hole is formed to connect to the first layer according to the connection requirements of diodes and other devices in the monolithic integrated full-bridge rectifier circuit. The metal evaporation method is consistent with the previous diode preparation process to achieve circuit connection between diodes. Among them, anode metal evaporation is performed in the anode contact opening, and cathode metal evaporation is performed in the cathode contact opening. The process parameters are consistent with the corresponding steps in the second aspect. For details, please refer to the relevant content above. Among them, which devices are specifically connected to the first layer of metal interconnection and how to connect them, please refer to Figure 6 to Figure 8 I understand. I won't explain them one by one here.

[0132] S400, growing the passivation layer again, opening holes by etching the passivation layer, and performing metal evaporation and filter capacitor preparation in the holes, and forming a second layer of metal interconnection according to the connection requirements of the monolithic integrated full-bridge rectifier circuit.

[0133] like Fig.10f As shown, a third passivation layer (the third layer is indicated as layer3) is grown to cover all surfaces of the current structure.

[0134] Then as Figure 10g As shown, holes are opened in the anode region, cathode region and both ends of the resistor film of the diode by etching the third passivation layer. Metal Via 2 represents the second-layer metal via.

[0135] Afterwards, if Fig.10hAs shown, metal is evaporated in the opening area, and filter capacitors are prepared at the same time. According to the connection requirements of diodes and other devices in the monolithic integrated full-bridge rectifier circuit, through holes are formed to connect with the second layer. The metal evaporation method is consistent with the previous text to connect the diode circuit. Among them, the process parameters of S400 can be consistent with S300.

[0136] For details on which devices the second-layer metal interconnects connect and how they are connected, see Figure 6 to Figure 8 I understand. I won't explain them one by one here.

[0137] The final circuit structure, diode positions, interconnections, etc. can be found in Figure 6 to Figure 8 shown.

[0138] The method for preparing a monolithic integrated full-bridge rectifier circuit provided in an embodiment of the present invention is based on the method for preparing a quasi-vertical super junction diode provided, and multiple quasi-vertical super junction diodes are prepared on the same Si substrate. Then, a TaN target material is used on the surface of the passivation layer on the Si substrate to form a resistive film by sputtering; then, a passivation layer is grown again on all surfaces and sides exposed by the multi-device structure on the Si substrate, holes are opened by etching the passivation layer, and metal evaporation and filter capacitor preparation are performed in the holes, and the first layer of metal interconnection is formed according to the connection requirements of the monolithic integrated full-bridge rectifier circuit; finally, the passivation layer is grown again, holes are opened by etching the passivation layer, and metal evaporation is performed in the holes, and the second layer of metal interconnection is formed according to the connection requirements of the monolithic integrated full-bridge rectifier circuit, thereby preparing a monolithic integrated full-bridge rectifier circuit.

[0139] The monolithic integrated full-bridge rectifier circuit is implemented based on the provided quasi-vertical superjunction diode, which improves the integration, greatly reduces the circuit volume, and can improve the circuit reliability. The present invention uses quasi-vertical diodes with Mg-doped P-type BN superjunction technology to replace traditional Schottky diodes, and utilizes the high breakdown field strength of BN materials and the electric field regulation ability of the superjunction structure to greatly improve the withstand voltage level of the Schottky diode, broaden the voltage application window of the full-bridge rectifier circuit, and enhance the power handling capacity of the rectifier circuit. However, the existing technology mostly uses traditional Schottky diodes, lacks effective junction terminal technology to increase the device operating voltage, and limits the working range of existing devices.

[0140] The present invention adopts a bridge full-wave rectifier circuit, which can fully utilize the positive half-cycle and negative half-cycle of the AC signal and effectively improve the conversion efficiency. The use of a more efficient bridge full-wave rectifier circuit achieves more efficient AC-DC conversion, reduces the rectification pressure that a single tube needs to bear, and is conducive to improving the economy and reliability of the circuit. However, the original half-wave rectifier circuit sacrifices half of the AC signal to achieve the rectification effect, so its current utilization rate is not high.

[0141] It should be noted that, in the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0142] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0143] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0144] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A quasi-vertical super junction diode, characterized in that: include: Si substrate, N+GaN conductive layer, and heterogeneous super junction structure layer are arranged in sequence from bottom to top; In the heterogeneous super junction structure layer, P-BN ring regions and N GaN ring regions are arranged in a concentric ring distribution manner in the longitudinal direction; the P-BN ring region and the side of the heterogeneous super junction structure layer are all made of Mg-doped P-type BN material; an anode is arranged on the surface of the heterogeneous super junction structure layer; and a cathode is arranged on the surface of the N+GaN conductive layer, which surrounds the heterogeneous super junction structure layer and has a distance therebetween.

2. The quasi-vertical super junction diode according to claim 1, characterized in that: The doping concentration of Si in the N+GaN conducting layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 .

3. The quasi-vertical super junction diode according to claim 1, characterized in that: The doping concentration of Si in the N GaN ring region is 1.8×10 15 cm -3 ~1.5×10 16 cm -3 .

4. The quasi-vertical super junction diode according to claim 1, characterized in that: In the P-type BN material, the Mg doping concentration is 1.7×10 14 cm -3 ~1.0×10 16 cm -3 .

5. The quasi-vertical super junction diode according to claim 1, characterized in that: The depth of the P-BN ring region is 1 μm to 6 μm; the widths of the P-BN ring region and the N GaN ring region are 3 μm to 5 μm.

6. A method for preparing a quasi-vertical super junction diode, characterized in that: For preparing the quasi-vertical super junction diode according to any one of claims 1 to 5, the preparation method of the quasi-vertical super junction diode comprises: Obtaining a Si-based GaN epitaxial layer structure, wherein the Si-based GaN epitaxial layer structure comprises, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer; Etching and removing the outer N+GaN conduction layer and the N-type GaN drift layer to expose the Si substrate and form a step structure; The outer N-type GaN drift layer is removed by etching, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a step structure; Etching a plurality of groove structures distributed in concentric rings from the top of the N-type GaN drift layer downwards, and etching to a depth to expose the N+GaN conducting layer; The P-type BN material doped with Mg is sputtered inside the groove structure, on the surface of the device, and on the side of the N-type GaN drift layer by using a magnetron sputtering process, and a thermal annealing treatment is performed, so that the N-type GaN drift layer forms a P-BN ring region and an N GaN ring region distributed in concentric rings; Growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate; The passivation layer on the upper surface of the device is removed to expose the P-type BN material layer, and the passivation layer at predetermined positions on both sides of the N+GaN conductive layer is removed to form a cathode contact opening; and an opening is etched at a position corresponding to the N GaN ring region in the exposed P-type BN material layer to form an anode contact opening; An anode is formed by metal evaporation inside and on the surface of the anode contact opening, and a cathode is formed by metal evaporation inside and on the surface of the cathode contact opening, which surrounds the N-type GaN drift layer and has a certain distance therebetween.

7. A monolithic integrated full-bridge rectifier circuit, characterized in that: include: A first AC input terminal, a second AC input terminal, a positive polarity forward diode, a positive polarity reverse diode, a negative polarity forward diode, a negative polarity reverse diode, a first filter capacitor, a filter resistor, a second filter capacitor, a first output terminal, and a second output terminal; wherein, The first AC input terminal is connected to the anode of the positive polarity end forward diode and the cathode of the positive polarity end reverse diode; The second AC input terminal is connected to the anode of the forward diode at the negative polarity end and the cathode of the reverse diode at the negative polarity end; The cathode of the positive polarity end forward diode is connected to the cathode of the negative polarity end forward diode, the first end of the first filter capacitor, and the first end of the filter resistor; The second end of the filter resistor is connected to the first end of the second filter capacitor and the first output end; The anode of the positive polarity end reverse diode is connected to the anode of the negative polarity end reverse diode, the second end of the first filter capacitor, the second end of the second filter capacitor, and the second output end; Among them, the forward diode at the positive polarity end, the reverse diode at the positive polarity end, the forward diode at the negative polarity end and the reverse diode at the negative polarity end constitute a rectifier circuit, each diode is implemented by the quasi-vertical super junction diode described in any one of claims 1-5, and the preparation method is the preparation method of the quasi-vertical super junction diode described in claim 6; the first filter capacitor, the filter resistor and the second filter capacitor constitute an RC filter circuit.

8. The monolithic integrated full-bridge rectifier circuit according to claim 7, characterized in that: The working principle of the monolithic integrated full-bridge rectifier circuit includes: The rectifier circuit is used to convert the bidirectional alternating current input from the first alternating current input terminal and the second alternating current input terminal into a unidirectional pulsating current; The high-frequency AC component in the unidirectional pulsating current is removed by using the RC filter circuit, so that the DC component is converted into the DC and then output through the first output terminal and the second output terminal.

9. The monolithic integrated full-bridge rectifier circuit according to claim 8, characterized in that: The working principle of the rectifier circuit includes: When the input signal is a positive periodic voltage, the first AC input terminal is positive polarity, the second AC input terminal is negative polarity, the forward diode at the positive polarity terminal is turned on, the reverse diode at the positive polarity terminal is turned off, the reverse diode at the negative polarity terminal is turned on, and the forward diode at the negative polarity terminal is turned off; the input AC voltage value is the voltage difference between the first AC input terminal and the second AC input terminal, the first output terminal is positive polarity, and the second output terminal is negative polarity; When the input signal is a negative periodic voltage, the first AC input terminal is negative polarity, and the second AC input terminal is positive polarity; the forward diode at the positive polarity terminal is cut off, and the reverse diode at the positive polarity terminal is turned on, the reverse diode at the negative polarity terminal is cut off, and the forward diode at the negative polarity terminal is turned on; the input AC voltage value is the voltage difference between the second AC input terminal and the first AC input terminal, the first output terminal is positive polarity, and the second output terminal is negative polarity.

10. A method for preparing a monolithic integrated full-bridge rectifier circuit, characterized in that: For preparing the monolithic integrated full-bridge rectifier circuit according to any one of claims 7 to 9, the preparation method of the monolithic integrated full-bridge rectifier circuit comprises: On the same Si substrate of the Si-based GaN epitaxial layer structure, a plurality of quasi-vertical super junction diodes are obtained; wherein the Si-based GaN epitaxial layer structure comprises, from bottom to top, a Si substrate, an N+GaN conducting layer and an N-type GaN drift layer; each quasi-vertical super junction diode is prepared by the method for preparing the quasi-vertical super junction diode according to claim 6; On the surface of the passivation layer on the Si substrate, a TaN target is used to form a resistive film by sputtering; A passivation layer is grown again on all surfaces and sides of the Si substrate where the multi-device structure is exposed, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form a first layer of metal interconnection according to the connection requirements of the monolithic integrated full-bridge rectifier circuit; The passivation layer is grown again, holes are opened by etching the passivation layer, and metal evaporation and filter capacitor preparation are performed in the holes. According to the connection requirements of the monolithic integrated full-bridge rectifier circuit, a second layer of metal interconnection is formed.

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