Groove MOS device and preparation method thereof

Abstract

According to the trench MOS device and the preparation method thereof, the floating gate is arranged to reduce the electric field intensity at the corner of the bottom of the trench MOS device, improve the withstand voltage of the device, reduce the electric leakage and improve the reliability, specifically, the floating gate utilizes the electric field coupling principle, and due to the fact that the floating gate is isolated from other electrodes by the oxide layer, when the device is closed, the floating gate is separated from the other electrodes by the oxide layer; the drain electrode can generate a large voltage, and an electric field is generated in the surrounding space. Due to the fact that capacitance coupling exists between the floating gate and the electrode, the floating gate can sense a part of an electric field, induced charges are generated on the floating gate, the potential of the floating gate is gradually increased along with accumulation of the charges, the potential difference between the floating gate and the drain electrode is gradually reduced, and the intensity of the electric field between the floating gate and the drain electrode is reduced accordingly. The gate oxide layer in the corner area of the bottom of the groove is not in a high-field-intensity environment, the voltage on the floating gate is the voltage of the induction drain electrode, the larger the voltage of the drain electrode is, the larger the voltage on the floating gate is, and a small voltage difference is always kept.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench MOS device and a preparation method thereof. Background Art

[0002] As an important power semiconductor device, trench MOS devices are widely used in many fields such as power electronics, communications, and industrial control.

[0003] As electronic devices continue to pursue higher power density, higher efficiency and higher reliability, trench MOS devices are facing increasingly severe challenges. In the structure of trench MOS devices, the electric field environment of the oxide layer at the bottom of the trench is crucial. However, in actual applications, the oxide layer at the bottom of the trench is often subjected to a high electric field strength.

[0004] High field strength can cause many serious problems. First, it greatly increases the risk of oxide layer breakdown. Under high voltage and high current working conditions, once the oxide layer is broken down, it will directly lead to the failure of the trench MOS device, and may paralyze the entire electronic system. Secondly, high field strength will cause a large amount of charge accumulation and traps in the oxide layer, which will gradually affect the performance stability of the device. Over time, problems such as unstable threshold voltage and increased leakage current will occur, significantly shortening the service life of the trench MOS. Summary of the invention

[0005] Based on this, the purpose of the present invention is to provide a trench MOS device and a preparation method thereof, aiming to reduce the electric field strength at the bottom corner of the trench MOS device, improve the device's withstand voltage, reduce leakage, and improve reliability.

[0006] A trench MOS device according to an embodiment of the present invention, when the trench MOS device is an N-type trench MOS device, comprises a substrate, an epitaxial layer disposed on the substrate, and an electric field coupling structure disposed in the epitaxial layer; The epitaxial layer comprises a first N-type layer, a P-type layer and a second N-type layer arranged in sequence in a direction away from the substrate, the electric field coupling structure is embedded in the first N-type layer, the P-type layer and the second N-type layer, the electric field coupling structure is composed of a gate portion and a floating gate arranged on a side close to the substrate and symmetrical with respect to the gate portion, the gate portion, the floating gate and the epitaxial layer are separated by an oxide layer, wherein the gate portion and the floating gate are both polysilicon; When the trench MOS device is a P-type trench MOS device, all doping is inverted.

[0007] Furthermore, the electric field coupling structure is embedded in the first N-type layer, the P-type layer and the second N-type layer to a depth of 1 μm to 1.5 μm.

[0008] Furthermore, the thickness of the floating gate is 0.2 μm to 0.5 μm.

[0009] Furthermore, the thickness of the oxide layer between the floating gate and the first N-type layer is 150Å~500Å.

[0010] Furthermore, the thickness of the oxide layer between the floating gate and the gate portion is 300Å~500Å.

[0011] Furthermore, the floating gate is located in the first N-type layer.

[0012] Further, the impurities of the first N-type layer and the second N-type layer are P elements, and the doping concentration of the second N-type layer is lower than the doping concentration of the first N-type layer.

[0013] Furthermore, the doping concentration of the first N-type layer is 1E17cm -3 ~1E19cm -3 , the doping concentration of the second N-type layer is 1E13cm -3 ~1E17cm -3 .

[0014] Furthermore, the impurity of the P-type layer is B element, and the doping concentration is 1E10cm -3 ~1E14cm -3 . A method for preparing a trench MOS device according to an embodiment of the present invention is used to prepare the above trench MOS device, and the method includes: When the trench MOS device is an N-type trench MOS device, an N-type substrate is provided, and a trench is etched on the N-type substrate; The substrate with the groove is subjected to thermal oxidation treatment to grow a first oxide layer on the surface of the groove as a dielectric layer of the gate polysilicon sidewall; Growing first polysilicon on the first oxide layer, grinding and etching back, and then etching the middle part of the first polysilicon; Performing thermal oxidation treatment on the first polysilicon after etching to form a second oxide layer on the surface of the first polysilicon after etching to obtain a floating gate; Growing a second polysilicon in the groove formed by the first oxide layer and the second oxide layer, and then grinding and etching back to obtain a gate portion; Doping a well region and a source electrode in a predetermined portion of the N-type substrate to obtain a P-type layer and a second N-type layer, respectively, wherein the remaining portion of the N-type substrate is the first N-type layer; When the trench MOS device is a P-type trench MOS device, all doping is inverted.

[0015] The beneficial effects of the present invention are: By setting a floating gate, the electric field strength at the bottom corner of the trench MOS device is reduced, the device's withstand voltage is improved, leakage is reduced, and reliability is improved. Specifically, as a key component of the device, the floating gate utilizes the principle of electric field coupling. Since it is isolated from other electrodes by an oxide layer, when the device is turned off, a large voltage will be generated at the drain, generating an electric field in the surrounding space. Due to the capacitive coupling between the floating gate and the electrode, the floating gate will sense a part of the electric field, thereby generating induced charges on the floating gate. As the charge accumulates, the potential of the floating gate gradually increases, so the potential difference between the floating gate and the drain gradually decreases, and the electric field strength between the floating gate and the drain decreases accordingly, resulting in the gate oxide layer in the corner area at the bottom of the trench not being in a high field strength environment, and the voltage on the floating gate is the voltage of the induced drain. The larger the drain voltage, the larger the voltage on the floating gate, and the smaller the voltage difference is always maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic structural diagram of a trench MOS device provided by an embodiment of the present invention; Figure 2 A flowchart of a method for manufacturing a trench MOS device provided by an embodiment of the present invention; Figure 3 A schematic diagram of a process flow for preparing a trench MOS device provided in an embodiment of the present invention.

[0017] Description of main component symbols:

[0018] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0019] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0020] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0022] In traditional trench MOS devices, the gate oxide layer of the device is the isolation oxide layer between the trench gate and the substrate. The breakdown point of the trench MOS device is usually at the PN junction and the bottom corner of the trench. The stronger the electric field, the stronger the collision ionization at the bottom corner of the trench. Therefore, the gate oxide layer also affects the withstand voltage and leakage of the device. Especially for low-opening trench MOS devices with low threshold voltage, the gate oxide layer itself cannot be too thick. When subjected to high withstand voltage, the oxide layer at the bottom corner of the trench will leak or even break down due to the high field strength, affecting the function and reliability of the device. In view of this, this scheme is proposed, and the specific implementation method is as follows.

[0023] The embodiment of the present invention provides a trench MOS device, see Figure 1 , is a schematic structural diagram of a trench MOS device provided by an embodiment of the present invention. Specifically, when the trench MOS device is an N-type trench MOS device, the trench MOS device includes a substrate 1, an epitaxial layer disposed on the substrate 1, and an electric field coupling structure disposed in the epitaxial layer; The epitaxial layer includes a first N-type layer 2, a P-type layer 3 and a second N-type layer 4 which are sequentially arranged in a direction away from the substrate. The electric field coupling structure is embedded in the first N-type layer 2, the P-type layer 3 and the second N-type layer 4. The impurities of the first N-type layer 2 and the second N-type layer 4 are P (phosphorus) elements, and the doping concentration of the second N-type layer 4 is less than the doping concentration of the first N-type layer 2. The doping concentration of the first N-type layer 2 is 1E17cm -3 ~1E19cm -3 , the doping concentration of the second N-type layer 4 is 1E13cm -3 ~1E17cm -3 The impurity of P-type layer 3 is B (boron) element, and the doping concentration is 1E10cm -3 ~1E14cm -3 .

[0024] It should be noted that the electric field coupling structure is embedded in the first N-type layer 2, the P-type layer 3 and the second N-type layer 4 to a depth of 1μm~1.5μm. Exemplarily, the electric field coupling structure is embedded in the first N-type layer 2, the P-type layer 3 and the second N-type layer 4 to a depth of 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, but not limited to this. It can be understood that the electric field coupling structure is actually prepared in a groove with a depth of 1μm~1.5μm.

[0025] The electric field coupling structure consists of a gate portion 7 and a floating gate 6 which is arranged on a side close to the substrate 1 and is symmetrical about the gate portion 7. The gate portion 7, the floating gate 6 and the epitaxial layer are separated by an oxide layer 5, wherein the gate portion 7 and the floating gate 6 are both polycrystalline silicon. It should be noted that the thickness of the floating gate 6 is 0.2μm~0.5μm, and the thickness can be understood as the distance in the depth direction. Exemplarily, the thickness of the floating gate 6 is 0.2μm, 0.3μm, 0.4μm or 0.5μm, but is not limited to this.

[0026] In this embodiment, the thickness of the oxide layer between the floating gate 6 and the first N-type layer 2 is 150Å~500Å, and exemplarily, the thickness of the oxide layer between the floating gate 6 and the first N-type layer 2 is 150Å, 200Å, 300Å, 400Å or 500Å, but not limited thereto; the thickness of the oxide layer between the floating gate 6 and the gate portion 7 is 300Å~500Å, and exemplarily, the thickness of the oxide layer between the floating gate 6 and the gate portion 7 is 300Å, 350Å, 400Å, 450Å or 500Å, but not limited thereto. As can be seen from the above, the floating gate 6 is located in the first N-type layer 2 in the depth direction. In addition, the oxide layer between the floating gate 6 and the first N-type layer 2 is the first oxide layer 51, and the oxide layer between the floating gate 6 and the gate portion 7 is the second oxide layer 52.

[0027] It can be understood that G represents the gate, S represents the source, and D represents the drain, wherein the second N-type layer 4 is electrically connected to the source, the gate portion 7 is electrically connected to the gate, and the substrate 1 is electrically connected to the drain.

[0028] When the trench MOS device is a P-type trench MOS device, all doping is inverted. Specifically, the epitaxial layer includes a first P-type layer, an N-type layer and a second P-type layer arranged in sequence away from the substrate. The electric field coupling structure is embedded in the first P-type layer, the N-type layer and the second P-type layer, and the doping concentration of the second P-type layer is higher than the doping concentration of the first P-type layer.

[0029] In order to prepare the above-mentioned trench MOS device, an embodiment of the present invention provides a method for preparing a trench MOS device, see Figure 2 and Figure 3 , Figure 2A flowchart of a method for manufacturing a trench MOS device provided by an embodiment of the present invention is provided. Figure 3 A schematic diagram of a manufacturing process flow of a trench MOS device provided in an embodiment of the present invention, when the trench MOS device is an N-type trench MOS device, the method specifically includes the following steps: S100: providing an N-type substrate, and etching a groove on the N-type substrate.

[0030] Specifically, a groove with a depth of 1 μm to 1.5 μm is etched on the N-type substrate 11 , and then an electric field coupling structure is formed in the groove.

[0031] S200: thermally oxidizing the substrate with the trenches to grow a first oxide layer on the surface of the trenches as a dielectric layer of the gate polysilicon sidewalls.

[0032] In this embodiment, a high-quality thin oxide layer is grown as a dielectric layer of the polysilicon sidewall by thermal oxidation treatment, that is, oxygen is introduced at a high temperature of 800°C to 1100°C, to obtain a first oxide layer 51 with a thickness of 150Å to 500Å. In addition, the first oxide layer 51 also serves to isolate the substrate.

[0033] S300: growing first polysilicon on the first oxide layer, grinding and etching back, and then etching the middle part of the first polysilicon.

[0034] The first polysilicon 12 is deposited on the first oxide layer 51 of the groove, and after being polished and etched back by CMP process, the thickness is 0.2 μm-0.5 μm. On this basis, the middle part of the first polysilicon 12 is etched.

[0035] S400: performing thermal oxidation treatment on the first polysilicon after etching to form a second oxide layer on the surface of the first polysilicon after etching to obtain a floating gate.

[0036] Specifically, the thickness of the second oxide layer 52 is 300Å-500Å, so as to form a thicker oxide layer around the gate portion 7 as an isolation layer, that is, the floating gate 6 is not connected to any electrode.

[0037] S500: growing a second polysilicon in the groove formed by the first oxide layer and the second oxide layer, and then grinding and etching back to obtain a gate portion.

[0038] After being polished and etched back by CMP process, the plane of the second polysilicon is located at a depth of 0.1 μm to 0.2 μm in the trench, in order to ensure that no polysilicon residue will cause a short circuit, so as to form the gate portion 7 .

[0039] S600: doping a well region and a source electrode in a predetermined portion of the N-type substrate to obtain a P-type layer and a second N-type layer, respectively, wherein the remaining portion of the N-type substrate is the first N-type layer.

[0040] It should be noted that the well region is doped with B (boron) element, the temperature is 700℃~1000℃, and the doping concentration is 1E10cm -3 ~1E14cm -3 , and obtain the P-type layer 3; doping the source with P (phosphorus) as the impurity, the temperature is 800℃~1100℃, and the doping concentration is 1E13cm -3 ~1E17cm -3 , a second N-type layer 4 is obtained, and further, an oxide layer is deposited as a dielectric layer, and then through holes are etched, and metal aluminum is deposited to form MOS electrodes, wherein the floating gate 6 is not connected to any electrode.

[0041] In some other embodiments of the present invention, when the trench MOS device is a P-type trench MOS device, all doping is inverted.

[0042] The present invention will be further described below with specific embodiments: Example 1 Embodiment 1 of the present invention provides a trench MOS device, taking an N-type trench MOS device as an example, comprising a substrate, an epitaxial layer disposed on the substrate, and an electric field coupling structure disposed in the epitaxial layer; The epitaxial layer includes a first N-type layer, a P-type layer and a second N-type layer arranged in sequence away from the substrate, the electric field coupling structure is embedded in the first N-type layer, the P-type layer and the second N-type layer, the impurities of the first N-type layer and the second N-type layer are P (phosphorus) elements, and the doping concentration of the second N-type layer is less than the doping concentration of the first N-type layer, and the doping concentration of the first N-type layer is 1E18cm -3 , the doping concentration of the second N-type layer is 1E17cm -3 The impurity of the P-type layer is B (boron) element, and the doping concentration is 1E12cm -3 .

[0043] It should be noted that the depth of the electric field coupling structure embedded in the first N-type layer, the P-type layer and the second N-type layer is 1.2 μm, that is, the depth of the trench is 1.2 μm.

[0044] The electric field coupling structure consists of a gate portion and a floating gate that is located on a side close to the substrate and symmetrical about the gate portion. The gate portion, the floating gate and the epitaxial layer are separated by an oxide layer. The gate portion and the floating gate are both polysilicon. It should be noted that the thickness of the floating gate is 0.3μm.

[0045] In this embodiment, the thickness of the oxide layer between the floating gate and the first N-type layer is 200Å; the thickness of the oxide layer between the floating gate and the gate portion is 300Å. As can be seen from the above, the floating gate is located in the first N-type layer in the depth direction. In addition, the oxide layer between the floating gate and the first N-type layer is the first oxide layer, and the oxide layer between the floating gate and the gate portion is the second oxide layer.

[0046] Example 2 Embodiment 2 of the present invention also provides a trench MOS device, which differs from Embodiment 1 in that the thickness of the oxide layer between the floating gate and the first N-type layer is 300Å.

[0047] Example 3 Embodiment 3 of the present invention also provides a trench MOS device, which differs from Embodiment 1 in that the thickness of the oxide layer between the floating gate and the first N-type layer is 400Å.

[0048] Example 4 Embodiment 4 of the present invention also provides a trench MOS device, which differs from Embodiment 1 in that the thickness of the oxide layer between the floating gate and the first N-type layer is 500Å.

[0049] Example 5 Embodiment 5 of the present invention also provides a trench MOS device, which differs from Embodiment 3 in that the thickness of the oxide layer between the floating gate and the gate portion is 400Å.

[0050] Example 6 Embodiment 6 of the present invention also provides a trench MOS device, which differs from Embodiment 3 in that the thickness of the oxide layer between the floating gate and the gate portion is 500Å.

[0051] Comparative Example 1 Comparative Example 1 also provides a trench MOS device, which differs from Example 1 in that no floating gate is provided.

[0052] Comparative Example 2 Comparative Example 2 also provides a trench MOS device, which differs from Embodiment 2 of the present invention in that no floating gate is provided.

[0053] Comparative Example 3 Comparative Example 3 also provides a trench MOS device, which differs from Embodiment 2 of the present invention in that no floating gate is provided.

[0054] The trench MOS devices in Examples 1 to 6 and Comparative Examples 1 to 3 were tested under the same conditions, and the specific results are as follows:

[0055] It can be seen from the table that the trench MOS device in the embodiment of the present invention effectively reduces the electric field strength at the bottom corner of the trench MOS device due to the design of the floating gate, and at the same time, improves the breakdown voltage. In addition, within a certain range, as the thickness of the oxide layer between the floating gate and the first N-type layer increases, the electric field strength at the bottom corner of the trench MOS device becomes smaller and the breakdown voltage becomes larger.

[0056] In summary, the trench MOS device and its preparation method in the embodiment of the present invention, by setting a floating gate, can reduce the electric field strength at the bottom corner of the trench MOS device, improve the withstand voltage of the device, reduce leakage, and improve reliability. Specifically, the floating gate is a key component of the device, and the floating gate utilizes the electric field coupling principle. Since it is isolated from other electrodes by an oxide layer, when the device is turned off, a large voltage will be generated at the drain, generating an electric field in the surrounding space. Due to the capacitive coupling between the floating gate and the electrode, the floating gate will sense a part of the electric field, thereby generating induced charges on the floating gate. As the charge accumulates, the potential of the floating gate gradually increases, so the potential difference between the floating gate and the drain gradually decreases, and the electric field strength between the floating gate and the drain decreases accordingly, resulting in the gate oxide layer in the corner area at the bottom of the trench not being in a high field strength environment, and the voltage on the floating gate is the voltage of the induced drain. The larger the drain voltage, the larger the voltage on the floating gate, and the smaller the voltage difference is always maintained.

[0057] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A trench MOS device, characterized in that: When the trench MOS device is an N-type trench MOS device, it includes a substrate, an epitaxial layer arranged on the substrate, and an electric field coupling structure arranged in the epitaxial layer; The epitaxial layer comprises a first N-type layer, a P-type layer and a second N-type layer arranged in sequence in a direction away from the substrate, the electric field coupling structure is embedded in the first N-type layer, the P-type layer and the second N-type layer, the electric field coupling structure is composed of a gate portion and a floating gate arranged on a side close to the substrate and symmetrical with respect to the gate portion, the gate portion, the floating gate and the epitaxial layer are separated by an oxide layer, wherein the gate portion and the floating gate are both polysilicon; When the trench MOS device is a P-type trench MOS device, all doping is inverted.

2. The trench MOS device according to claim 1, characterized in that: The electric field coupling structure is embedded in the first N-type layer, the P-type layer and the second N-type layer to a depth of 1 μm to 1.5 μm.

3. The trench MOS device according to claim 1, characterized in that: The thickness of the floating gate is 0.2 μm to 0.5 μm.

4. The trench MOS device according to claim 3, characterized in that: The thickness of the oxide layer between the floating gate and the first N-type layer is 150Å-500Å.

5. The trench MOS device according to claim 4, characterized in that: The thickness of the oxide layer between the floating gate and the gate portion is 300Å~500Å.

6. The trench MOS device according to claim 1, characterized in that: The floating gate is located in the first N-type layer.

7. The trench MOS device according to claim 1, characterized in that: Impurities in the first N-type layer and the second N-type layer are P elements, and a doping concentration of the second N-type layer is less than a doping concentration of the first N-type layer.

8. The trench MOS device according to claim 7, characterized in that: The doping concentration of the first N-type layer is 1E17cm -3 ~1E19cm -3 , the doping concentration of the second N-type layer is 1E13cm -3 ~1E17cm -3 .

9. The trench MOS device according to claim 1, characterized in that: The impurity of the P-type layer is B element, and the doping concentration is 1E10cm -3 ~1E14cm -3 .

10. A method for preparing a trench MOS device, characterized in that: For preparing the trench MOS device according to any one of claims 1 to 9, the method comprises: When the trench MOS device is an N-type trench MOS device, an N-type substrate is provided, and a trench is etched on the N-type substrate; The substrate with the groove is subjected to thermal oxidation treatment to grow a first oxide layer on the surface of the groove as a dielectric layer of the gate polysilicon sidewall; Growing first polysilicon on the first oxide layer, grinding and etching back, and then etching the middle part of the first polysilicon; Performing thermal oxidation treatment on the first polysilicon after etching to form a second oxide layer on the surface of the first polysilicon after etching to obtain a floating gate; Growing a second polysilicon in the groove formed by the first oxide layer and the second oxide layer, and then grinding and etching back to obtain a gate portion; Doping a well region and a source electrode in a predetermined portion of the N-type substrate to obtain a P-type layer and a second N-type layer, respectively, wherein the remaining portion of the N-type substrate is the first N-type layer; When the trench MOS device is a P-type trench MOS device, all doping is inverted.

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