Semiconductor device, preparation method and electronic equipment

Abstract

The invention relates to a semiconductor device, a preparation method and electronic equipment. The semiconductor device comprises a substrate, a first type active column, a second type active column, a first grid electrode, a second grid electrode and a third grid electrode. The second gate is used for connecting a source signal. The first gate is used for connecting a gate signal. The third gate is used for connecting a gate signal. The second-type active column comprises n second-type well regions, the n second-type well regions are arranged, and the doping concentration of the second-type well regions is larger than the doping concentration of the second-type active column of the substrate, so that the number of carriers in the second-type active column can be increased, the current conduction rate between the grid electrode and the drain electrode can be increased, the distribution of an electric field can be optimized, and the reliability of the device can be improved. Therefore, the on resistance of the device is reduced, the gate-drain charge is reduced, the Miller capacitance is reduced, the switching power consumption of the device is reduced, the switching on speed and the switching off speed of the device are improved, the conduction loss is further reduced, and the electrical property of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art

[0002] Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJ MOSFET) is a commonly used power switching device. Power consumption is an important indicator to measure the electrical properties of SJ MOSFET. The size of power consumption has a crucial impact on the normal operation of the device.

[0003] However, in conventional technology, the switching speed of SJ MOSFET is slow and the power consumption is large, thereby reducing the electrical performance of the semiconductor device. Summary of the invention

[0004] The purpose of this application is to provide a semiconductor device, a preparation method and an electronic device, which solves the problems of slow switching speed and high power consumption of semiconductor devices and improves the reliability and electrical properties of semiconductor devices. To achieve the purpose of this application, this application provides the following technical solutions:

[0005] In a first aspect, the present application provides a semiconductor device, comprising a substrate, a first-type active column, a second-type active column, and a first-type active column arranged in sequence along a first direction parallel to a top surface of the substrate on the substrate, and a first gate, a second gate, and a third gate arranged in sequence along the first direction;

[0006] The second gate is located directly above the second-type active column and is used to connect the source signal;

[0007] The first gate covers part of the top surface of the first-type active pillar and part of the top surface of the second-type active pillar, and is used to connect a gate signal;

[0008] The third gate covers a portion of the top surface of the first-type active pillar and a portion of the top surface of the second-type active pillar, and is used to connect the gate signal;

[0009] The second-type active pillar includes n second-type well regions arranged at intervals along a second direction perpendicular to the substrate;

[0010] Wherein, 2≤n≤8, and n is an integer.

[0011] The semiconductor device of the present application comprises a substrate, a first type active column, a second type active column, and a first type active column arranged in sequence along a first direction parallel to the top surface of the substrate on the substrate, and a first gate, a second gate, and a third gate arranged in sequence along the first direction. By setting the gate to a structure of a separated first gate, a second gate, and a third gate, and using the second gate to connect the source signal, the area of ​​the gate can be reduced, the breakdown voltage of the device can be increased, the switching speed of the device can be increased, and the switching loss can be reduced. By connecting the gate signal through the first gate and the second gate, the control signal can be transmitted to the gate of the semiconductor device, thereby realizing the switching control of the device. The first gate and the second gate cover part of the top surface of the first type active column and part of the top surface of the second type active column, and the gate can cover the conductive channel of the device, thereby improving the gate's control ability over the carriers in the channel and improving the sensitivity of the device. Therefore, the device loss can be reduced when the control signal controls the semiconductor device. By setting n second-type well regions in the second-type active column and utilizing the doping concentration of the second-type well region to be greater than the doping concentration of the second-type active column of the substrate, the number of carriers in the second-type active column can be increased, the current conduction rate between the gate and the drain can be improved, and the distribution of the electric field can be optimized, thereby reducing the on-resistance of the device, reducing the gate-drain charge, and reducing the Miller capacitance, reducing the switching power consumption of the device, and increasing the switching on and off speeds of the device, further reducing the conduction loss, and improving the electrical properties of the semiconductor device.

[0012] In one embodiment, a groove is formed between the sidewall of the first gate, the sidewall of the third gate, and the gate dielectric layer of the second gate;

[0013] The gate conductive layer of the second gate is located in the groove.

[0014] In one embodiment, the sidewall of the first gate is coated on the outer surface of the gate conductive layer of the first gate;

[0015] The sidewall of the third gate is coated on the outer surface of the gate conductive layer of the third gate.

[0016] In one embodiment, the first-type active column includes a second-type doped region, the source electrode covers a portion of the top surface of the second-type doped region, and the first gate or the third gate covers a portion of the top surface of the second-type doped region.

[0017] In one embodiment, the second gate further includes a source electrode, which covers partially exposed top surfaces of the two first-type active pillars, a top surface of a gate conductive layer of the second gate, an outer surface of a sidewall of the first gate, and an outer surface of a sidewall of the third gate.

[0018] In one embodiment, the first-type active pillar includes a protrusion extending along the first direction to the inside of the second-type active pillar.

[0019] In one of the embodiments, the conductivity type of the substrate is the second type;

[0020] A side of the substrate facing away from the second-type active pillar includes a drain.

[0021] In one embodiment, a top surface of the gate conductive layer of the second gate is lower than a top surface of the first gate or a top surface of the third gate.

[0022] In a second aspect, the present application further provides an electronic device, including:

[0023] The semiconductor device according to any one of the first aspects.

[0024] The electronic device of the present application includes a semiconductor device of any one of the above embodiments, and by setting the gate to a structure of a separated first gate, a second gate, and a third gate, and using the second gate to connect the source signal, the area of ​​the gate can be reduced, the breakdown voltage of the device can be increased, the switching speed of the device can be increased, and the switching loss can be reduced. By connecting the gate signal through the first gate and the second gate, the control signal can be transmitted to the gate of the semiconductor device, thereby realizing the switching control of the device. The first gate and the second gate cover part of the top surface of the first type active column and part of the top surface of the second type active column, and the gate can cover the conductive channel of the device, thereby improving the gate's control ability over the carriers in the channel and improving the sensitivity of the device. Therefore, the device loss can be reduced when the control signal controls the semiconductor device. By setting n second-type well regions in the second-type active column and utilizing the doping concentration of the second-type well region to be greater than the doping concentration of the second-type active column of the substrate, the number of carriers in the second-type active column can be increased, the current conduction rate between the gate and the drain can be improved, and the distribution of the electric field can be optimized, thereby reducing the on-resistance of the device, reducing the gate-drain charge, and reducing the Miller capacitance, reducing the switching power consumption of the device, and increasing the switching on and off speeds of the device, further reducing the conduction loss, and improving the electrical properties of the semiconductor device.

[0025] In a third aspect, the present application further provides a method for preparing a semiconductor device, comprising:

[0026] providing a substrate;

[0027] Forming on the substrate a first-type active column, a second-type active column, and a first-type active column sequentially arranged along a first direction parallel to the top surface of the substrate, wherein the second-type active column includes n second-type well regions spaced apart and arranged along a second direction perpendicular to the substrate, wherein 2≤n≤8, and n is an integer;

[0028] A first gate, a second gate, and a third gate are formed which are arranged in sequence along the first direction; the second gate is located directly above the second-type active column and is used to connect the source signal; the first gate covers part of the top surface of the first-type active column and part of the top surface of the second-type active column, and is used to connect the gate signal; the third gate covers part of the top surface of the first-type active column and part of the top surface of the second-type active column, and is used to connect the gate signal.

[0029] The preparation method of the semiconductor device of the present application includes providing a substrate, and then forming a first type active column, a second type active column, and a first type active column arranged in sequence along a first direction parallel to the top surface of the substrate on the substrate, and finally forming a first gate, a second gate, and a third gate arranged in sequence along the first direction. The second gate is located directly above the second type active column and is used to connect the source signal. The first gate covers the top surface of part of the first type active column and part of the second type active column, and is used to connect the gate signal. The third gate covers the top surface of part of the first type active column and part of the second type active column, and is used to connect the gate signal. By setting the gate to a structure of a separated first gate, a second gate, and a third gate, and using the second gate to connect the source signal, the area of ​​the gate can be reduced, the breakdown voltage of the device can be increased, the switching speed of the device can be increased, and the switching loss can be reduced. By connecting the gate signal through the first gate and the second gate, the control signal can be transmitted to the gate of the semiconductor device, thereby realizing the switching control of the device. The first gate and the second gate cover part of the top surface of the first type active column and part of the top surface of the second type active column, so that the gate can cover the conductive channel of the device, thereby improving the gate's control ability over the carriers in the channel and improving the sensitivity of the device. Therefore, the device loss can be reduced when the control signal controls the semiconductor device. By setting n second-type well regions in the second-type active column and using the doping concentration of the second-type well region to be greater than the doping concentration of the second-type active column of the substrate, the number of carriers in the second-type active column can be increased, the current conduction rate between the gate and the drain can be increased, and the distribution of the electric field can be optimized, thereby reducing the on-resistance of the device, reducing the gate-drain charge, and reducing the Miller capacitance, reducing the switching power consumption of the device, and increasing the switching on and off speeds of the device, further reducing the conduction loss, and improving the electrical properties of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment;

[0032] Figure 2 is a schematic cross-sectional structural diagram of a semiconductor device provided in another embodiment;

[0033] Figure 3 is a schematic diagram of an output characteristic curve of a semiconductor device provided in another embodiment;

[0034] Figure 4 is a schematic diagram of a breakdown voltage curve of a semiconductor device provided in another embodiment;

[0035] Figure 5 is a schematic diagram of a transfer characteristic curve of a semiconductor device provided in another embodiment;

[0036] Figure 6 is a schematic diagram of a charge curve of a semiconductor device provided in another embodiment;

[0037] Figure 7 is a schematic diagram of a capacitance-voltage curve of a semiconductor device provided in another embodiment;

[0038] Figure 8 is a schematic diagram of a switching curve of a semiconductor device provided in another embodiment;

[0039] Fig. 9 is a flow chart of a method for preparing a semiconductor device provided in yet another embodiment;

[0040] Fig.10 is a schematic cross-sectional structural diagram of a structure obtained in step S11 in a method for preparing a semiconductor device provided in another embodiment;

[0041] Fig.11 is a schematic cross-sectional view of a structure obtained in step S12 of a method for preparing a semiconductor device provided in another embodiment;

[0042] Fig.12 is a schematic cross-sectional structural diagram of a structure obtained in step S12 in a method for preparing a semiconductor device provided in yet another embodiment;

[0043] Fig.13 is a schematic cross-sectional view of a structure obtained in step S131 in a method for preparing a semiconductor device provided in yet another embodiment;

[0044] Fig.14 It is a schematic cross-sectional structural diagram of a structure obtained in step S132 in a method for preparing a semiconductor device provided in yet another embodiment.

[0045] Description of Reference Numerals

[0046] 10. Substrate; 20. First type active pillar; 201. Second type doped region; 30. Second type active pillar; 40. First gate; 50. Second gate; 60. Third gate; 70. Side wall of the first gate; 80. Side wall of the third gate; 90. Gate dielectric layer; 100. Source; 110. Second type well region; 120. Drain; 130. Gate material layer. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0050] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0053] The power consumption of SJ MOSFET is mainly divided into two categories, one is static loss and the other is dynamic loss. Static loss is mainly caused by on-resistance, and dynamic loss is mainly caused by switching loss. The shorter the switching time of the device, the faster the switching, the less dynamic loss of the device, and the more conducive to reducing energy consumption.

[0054] However, in conventional technology, the switching speed of SJ MOSFET is slow, the power consumption is large, and the reduction of gate area will lead to a decrease in current density and an increase in on-resistance, thereby reducing the electrical properties and reliability of the semiconductor device.

[0055] The present application embodiment provides a semiconductor device. Figure 1 and Figure 2 , the semiconductor device may include: a substrate 10, a first-type active column 20, a second-type active column 30, and a first-type active column 20 arranged in sequence along a first direction parallel to the top surface of the substrate 10 on the substrate 10, and a first gate 40, a second gate 50, and a third gate 60 arranged in sequence along the first direction. The second gate 50 is located directly above the second-type active column 30 and is used to connect the source 100 signal. The first gate 40 covers a portion of the top surface of the first-type active column 20 and a portion of the top surface of the second-type active column 30, and is used to connect the gate signal. The third gate 60 covers a portion of the top surface of the first-type active column 20 and a portion of the top surface of the second-type active column 30, and is used to connect the gate signal. The second-type active column 30 includes n second-type well regions 110 arranged at intervals along a second direction perpendicular to the substrate 10. Wherein, 2≤n≤8, and n is an integer.

[0056] For example, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, and a silicon carbide (SiC) substrate. The thickness of the substrate 10 may be 5 to 10 μm, for example, the thickness of the substrate 10 may be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. The doping concentration of the substrate 10 may be 0.5e20 cm -3 ~1.5e20cm -3 For example, the doping concentration of the substrate 10 may be 0.5e20cm -3 , 1e20cm -3 or 1.5e20cm -3 .

[0057] Exemplarily, the first direction is defined as Figure 1 The direction of OX shown in , the second direction is defined as Figure 1 The direction of OY is shown in .

[0058] Exemplarily, the first type active pillar 20 may be a P type active pillar or an N type active pillar. Specifically, in the present embodiment, the first type active pillar 20 is a P type active pillar, and the second type active pillar 30 may be a P type active pillar or an N type active pillar. Specifically, in the present embodiment, the second type active pillar 30 is an N type active pillar. It should be noted that the first type active pillar 20 and the second type active pillar 30 have different conductivity types.

[0059] Exemplarily, the second gate 50 is located directly above the second-type active pillar 30 and is used to connect the source 100 signal, which can reduce the area of ​​the gate, thereby increasing the switching speed of the device and reducing the switching loss.

[0060] In another example, the second gate 50 is located directly above the second-type active pillar 30 and is not connected to the source 100 signal to reduce the area of ​​the gate, thereby increasing the switching speed of the device and reducing the switching loss.

[0061] For example, see Figure 2 The second-type well region 110 may be a P-type well region or an N-type well region. Specifically, in this embodiment, the second-type well region 110 is an N-type well region.

[0062] Exemplarily, the second-type active pillar 30 includes n second-type well regions 110 arranged at intervals along a second direction perpendicular to the substrate 10. Wherein, 2≤n≤8, n is an integer, for example, the number of the second-type well regions 110 may be 2, 3, 4, 5, 6, 7 or 8. Specifically, in this embodiment, the number of the second-type well regions 110 is 4.

[0063] It should be noted that the doping concentration of the second-type well region 110 is greater than the doping concentration of the second-type active pillar 30 of the substrate 10. Specifically, the doping concentration of the second-type well region 110 may be 6e15cm -3 ~9e15cm -3 For example, the doping concentration of the second type well region 110 may be 6e15cm -3 、7e15cm -3 、8e15cm -3 or 9e15cm -3 The size of the second-type well region 110 along the first direction may be 0.3um~1um, for example, the size of the second-type well region 110 along the first direction may be 0.3um, 0.5μm, 0.7um, 0.9μm or 1μm. The size of the second-type well region 110 along the second direction may be 0.3um~1um, for example, the size of the second-type well region 110 along the second direction may be 0.3um, 0.5μm, 0.7um, 0.9μm or 1μm.

[0064] As an example, compared with a semiconductor device of a conventional structure, in the case where the second-type active pillar 30 includes two second-type well regions 110 arranged at intervals along a second direction perpendicular to the substrate 10, the static results of the semiconductor device in the embodiment of the present application are shown in Table 1, and the output characteristic curve of the semiconductor device in the embodiment of the present application is shown in Table 1. Figure 3 As shown in , the breakdown voltage curve of the semiconductor device in the embodiment of the present application is as follows Figure 4The transfer characteristic curve of the semiconductor device in the embodiment of the present application is shown in Figure 5 As shown in , the semiconductor device including two second-type well regions has a saturation current increased by 20% and an on-resistance decreased by 15% compared to the conventional structure.

[0065]

[0066] Table 1

[0067] As an example, compared with the semiconductor device of the conventional structure, in the case where the second type active pillar 30 includes two second type well regions 110 arranged at intervals along the second direction perpendicular to the substrate 10, the dynamic results are shown in Table 2. Under the conditions of a saturated drain current of 10A, a power supply voltage of 400V, and a threshold voltage of 10V, the gate charge curve of the semiconductor device in the embodiment of the present application is as shown in Figure 6 Under the conditions of a signal frequency of 100 kHz, a power supply voltage of 400 V, and a threshold voltage of 0 V, the capacitance-voltage curve of the semiconductor device in the embodiment of the present application is as shown in Figure 7 As shown in . Compared with the traditional structure, the gate-drain charge of the semiconductor device including two second-type well regions is reduced by 31%, the Miller capacitance is reduced by 45%, the turn-on time is shortened by 6%, the turn-off time is shortened by 14%, and the switching time is shortened by 11%.

[0068]

[0069] Table 2

[0070] As an example, under the conditions of a rated current of 5A, a rated voltage of 300V, a rated output power of 1500W, a switching frequency of 250kHz, and a duty cycle of 2%, compared with a semiconductor device of a conventional structure, the power consumption of the second type active column 30 including two second type well regions 110 arranged at intervals along a second direction perpendicular to the substrate 10 is shown in Table 3. Under the conditions of a resistance of 5Ω, a power supply voltage of 400V, and a threshold voltage of 18V, the switching curve of the semiconductor device in the embodiment of the present application is as shown in FIG. Figure 8 As shown in . Compared with the traditional structure, the semiconductor device including two second-type well regions has a 15% reduction in conduction loss, a 11.5% reduction in switching loss, a 14.9% reduction in total power consumption, and a 1.2% increase in switching efficiency.

[0071]

[0072] Table 3

[0073] The semiconductor device of the present application comprises a substrate 10, a first type active column 20, a second type active column 30, a first type active column 20 arranged in sequence along a first direction parallel to the top surface of the substrate 10, and a first gate 40, a second gate 50, and a third gate 60 arranged in sequence along the first direction on the substrate 10. By setting the gate to a structure of a separated first gate 40, a second gate 50, and a third gate 60, and using the second gate 50 to connect the source 100 signal, the area of ​​the gate can be reduced, the breakdown voltage of the device can be increased, the dynamic on-resistance of the device can be reduced, the switching speed of the device can be increased, and the switching loss can be reduced. By connecting the gate signal with the first gate 40 and the second gate 50, the control signal can be transmitted to the gate of the semiconductor device, thereby realizing the switching control of the device. The first gate 40 and the second gate 50 cover part of the top surface of the first type active column 20 and part of the top surface of the second type active column 30, so that the gate can cover the conductive channel of the device, thereby improving the gate's control ability over the carriers in the channel and improving the sensitivity of the device. Therefore, the device loss can be reduced when the control signal controls the semiconductor device. By arranging n second-type well regions 110 in the second-type active column 30, and using the doping concentration of the second-type well region 110 to be greater than the doping concentration of the second-type active column 30 of the substrate 10, the number of carriers in the second-type active column 30 can be increased, the current conduction rate between the gate and the drain 120 can be improved, and the distribution of the electric field can be optimized, thereby reducing the on-resistance of the device, reducing the gate-drain charge, and reducing the Miller capacitance, reducing the switching power consumption of the device, and increasing the switching on and off speeds of the device, further reducing the conduction loss, and improving the electrical properties of the semiconductor device.

[0074] In some embodiments, please refer to Figure 2 A groove is formed between the sidewall 70 of the first gate, the sidewall 80 of the third gate, and the gate dielectric layer 90 of the second gate 50; the gate conductive layer (not shown) of the second gate 50 is located in the groove.

[0075] As an example, the material of the first gate sidewall 70 and the third gate sidewall 80 can be but is not limited to insulating material. The first gate sidewall 70 and the third gate sidewall 80 insulate the first gate 40 , the second gate 50 and the third gate 60 .

[0076] As an example, the gate dielectric layer 90 of the second gate 50 may include but is not limited to an oxide layer, and the gate dielectric layer 90 of the second gate 50 insulates the second gate 50 from the second-type active pillar 30 .

[0077] The semiconductor device provided in the embodiment of the present application can insulate the first gate 40, the second gate 50 and the third gate 60 by setting the side wall 70 of the first gate and the side wall 80 of the third gate, thereby avoiding short-circuiting of signals between the first gate 40, the second gate 50 and the third gate 60, achieving electrical isolation of the semiconductor device, and further achieving efficient transmission of signals.

[0078] In some embodiments, please refer to Figure 2 The sidewall spacer 70 of the first gate is coated on the outer surface of the gate conductive layer of the first gate 40 . The sidewall spacer 80 of the third gate is coated on the outer surface of the gate conductive layer of the third gate 60 .

[0079] As an example, the thickness of the sidewall 70 of the first gate can be flexibly set according to the distance between the first gate 40 and the source 100 of the semiconductor device, and the thickness of the sidewall 80 of the third gate can be flexibly set according to the distance between the third gate 60 and the source 100 of the semiconductor device.

[0080] The semiconductor device provided in the embodiment of the present application can prevent direct contact between the first gate 40 and the source 100 by coating the sidewall 70 of the first gate on the outer surface of the gate conductive layer of the first gate 40, thereby avoiding parasitic capacitance and leakage. The sidewall 70 of the first gate can limit the distance between the first gate 40 and the source 100, thereby reducing the capacitance between the first gate 40 and the source 100, thereby improving the switching speed of the device. The sidewall 80 of the third gate is coated on the outer surface of the gate conductive layer of the third gate 60, which can prevent direct contact between the third gate 60 and the source 100, thereby avoiding parasitic capacitance and leakage. The sidewall 80 of the third gate can limit the distance between the third gate 60 and the source 100, thereby reducing the capacitance between the third gate 60 and the source 100, thereby improving the switching speed of the device.

[0081] In some embodiments, please refer to Figure 2 The first type active pillar 20 includes a second type doping region 201 , the source 100 covers a portion of the top surface of the second type doping region 201 , and the first gate 40 or the third gate 60 covers a portion of the top surface of the second type doping region 201 .

[0082] As an example, the second-type doping region 201 may be a P-type doping region or an N-type doping region. Specifically, in this embodiment, the second-type doping region 201 is an N-type doping region.

[0083] The semiconductor device provided in the embodiment of the present application, by setting a second-type doped region 201 in the first-type active column 20, when the semiconductor device is in the on state, the second-type doped region 201 can provide an injection point for electrons, so that the electrons flow to the drain region through the channel controlled by the gate, thereby forming an on-current.

[0084] In some embodiments, please refer to Figure 2 The second gate 50 further includes a source 100 , which covers the partially exposed top surfaces of the two first-type active pillars 20 , the top surface of the gate conductive layer of the second gate 50 , the outer surface of the sidewall 70 of the first gate, and the outer surface of the sidewall 80 of the third gate.

[0085] As an example, the material of the source 100 may be, but is not limited to, polysilicon, metal, metal alloy, silicon nitride, aluminum oxide, or the like.

[0086] The semiconductor device provided in the embodiment of the present application can connect the two first-type active pillars 20 to the source signal by covering the partially exposed top surfaces of the two first-type active pillars 20, the top surface of the gate conductive layer of the second gate 50, the outer surface of the side wall 70 of the first gate, and the outer surface of the side wall 80 of the third gate with the source 100, thereby realizing signal driving of the device.

[0087] In some embodiments, please refer to Figure 2 , the first-type active pillar 20 includes a protrusion extending along the first direction to the inside of the second-type active pillar 30 .

[0088] The semiconductor device provided in the embodiment of the present application can cover the conductive channel of the device with the first gate 40 and the third gate 60 by setting a protrusion extending along the first direction to the inside of the second type active pillar 30 in the first type active pillar 20, thereby improving the gate's control ability over carriers in the channel and improving the sensitivity of the device.

[0089] In some embodiments, see Figure 2 The conductivity type of the substrate 10 is the second type. The side of the substrate 10 facing away from the second type active pillar 30 includes a drain 120 .

[0090] As an example, the conductivity type of the substrate 10 may be a P-type substrate 10 or an N-type substrate 10 . Specifically, in the present embodiment, the substrate 10 is an N-type substrate 10 .

[0091] As an example, the material of the drain 120 may be, but is not limited to, polysilicon, metal, metal alloy, silicon nitride, aluminum oxide, or the like.

[0092] The semiconductor device provided in the embodiment of the present application can change the conductivity type of the semiconductor and adjust the conductivity of the semiconductor by setting the conductivity type of the substrate 10. The free carrier concentration in the substrate 10 can be increased, and the current carrying capacity and switching speed of the device can be improved. The defects in the semiconductor body are reduced, and the crystal quality is improved, thereby improving the electrical performance of the device, increasing the breakdown voltage and reducing the leakage current. By setting the drain 120 on the side of the substrate 10 away from the second type active column 30, the carriers flowing from the source 100 through the conductive channel can be collected and discharged into the external circuit, thereby achieving electrical conduction.

[0093] In some embodiments, see Figure 2 , the top surface of the gate conductive layer of the second gate 50 is lower than the top surface of the first gate 40 or the top surface of the third gate 60 .

[0094] As an example, the top surface of the gate conductive layer of the second gate 50 is lower than the top surface of the first gate 40 or the top surface of the third gate 60 , so that the second gate 50 can be directly connected to the source 100 .

[0095] The semiconductor device provided in the embodiment of the present application can directly connect the second gate 50 to the source 100 by setting the top surface of the gate conductive layer of the second gate 50 to be lower than the top surface of the first gate 40 or the top surface of the third gate 60, thereby reducing the area of ​​the gate, reducing the dynamic on-resistance of the device, and further reducing the gate-drain charge, which can improve the switching speed of the device and reduce the switching loss.

[0096] An embodiment of the present application provides an electronic device, comprising the semiconductor device in any one of the above embodiments.

[0097] The electronic device of the present application includes the semiconductor device in any of the above embodiments. By setting the gate to a structure of a separated first gate, a second gate and a third gate, and using the second gate to connect the source signal, the area of ​​the gate can be reduced, the breakdown voltage of the device can be increased, the switching speed of the device can be increased, and the switching loss can be reduced. By connecting the gate signal through the first gate and the second gate, the control signal can be transmitted to the gate of the semiconductor device, thereby realizing the switching control of the device. The first gate and the second gate cover part of the top surface of the first type active column and part of the top surface of the second type active column, which can realize the coverage of the conductive channel of the device by the gate, thereby improving the control ability of the gate to the carriers in the channel and improving the sensitivity of the device. Therefore, the device loss can be reduced when the control signal controls the semiconductor device. By setting n second-type well regions in the second-type active column and utilizing the doping concentration of the second-type well region to be greater than the doping concentration of the second-type active column of the substrate, the number of carriers in the second-type active column can be increased, the current conduction rate between the gate and the drain can be improved, and the distribution of the electric field can be optimized, thereby reducing the on-resistance of the device, reducing the gate-drain charge, and reducing the Miller capacitance, reducing the switching power consumption of the device, and increasing the switching on and off speeds of the device, further reducing the conduction loss, and improving the electrical properties of the semiconductor device.

[0098] The present invention provides a method for preparing a semiconductor device. Fig. 9 , the method for preparing the semiconductor device may include:

[0099] S11: providing a substrate.

[0100] For example, see Fig.10 The substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, and a silicon carbide (SiC) substrate. The thickness of the substrate 10 may be 5 to 10 μm, for example, the thickness of the substrate 10 may be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. The doping concentration of the substrate 10 may be 0.5e20 cm -3 ~1.5e20cm -3 For example, the doping concentration of the substrate 10 may be 0.5e20cm -3 , 1e20cm -3 or 1.5e20cm -3 .

[0101] S12: forming a first type active column, a second type active column, and a first type active column arranged in sequence along a first direction parallel to the top surface of the substrate on the substrate, wherein the second type active column includes n second type well regions arranged at intervals along a second direction perpendicular to the substrate, wherein 2≤n≤8, and n is an integer.

[0102] Exemplarily, the first direction is defined as Fig.10 The direction of OX shown in , the second direction is defined as Fig.10 The direction of OY is shown in .

[0103] For example, see Fig.11 , the first type active pillar 20, the second type active pillar 30, and the first type active pillar 20 arranged in sequence along a first direction parallel to the top surface of the substrate 10 can be formed on the substrate 10 by, but not limited to, an ion implantation process. The first type active pillar 20 can be a P-type active pillar or an N-type active pillar. Specifically, in this embodiment, the first type active pillar 20 is a P-type active pillar, and the second type active pillar 30 can be a P-type active pillar or an N-type active pillar. Specifically, in this embodiment, the second type active pillar 30 is an N-type active pillar. It should be noted that the first type active pillar 20 and the second type active pillar 30 have different conductivity types.

[0104] For example, see Fig.12 , the number of the second-type well regions 110 may be 2, 3, 4, 5, 6, 7 or 8. Specifically, in the present embodiment, the number of the second-type well regions 110 is 4. The second-type well region 110 may be a P-type well region or an N-type well region. Specifically, in the present embodiment, the second-type well region 110 is an N-type well region. The doping concentration of the second-type well region 110 is greater than the doping concentration of the second-type active pillar 30 of the substrate 10. Specifically, the doping concentration of the second-type well region 110 may be 6e15cm -3 ~9e15cm -3 For example, the doping concentration of the second type well region 110 may be 6e15cm -3 、7e15cm -3 、8e15cm -3 or 9e15cm -3 The size of the second-type well region 110 along the first direction may be 0.3um~1um, for example, the size of the second-type well region 110 along the first direction may be 0.3um, 0.5μm, 0.7um, 0.9μm or 1μm. The size of the second-type well region 110 along the second direction may be 0.3um~1um, for example, the size of the second-type well region 110 along the second direction may be 0.3um, 0.5μm, 0.7um, 0.9μm or 1μm.

[0105] Please refer to Fig.11 The first-type active pillar 20 may include a second-type doping region 201 , the source 100 covers a portion of the top surface of the second-type doping region 201 , and the first gate 40 or the third gate 60 covers a portion of the top surface of the second-type doping region 201 .

[0106] S13: forming a first gate, a second gate, and a third gate arranged in sequence along a first direction; the second gate is located directly above the second type active column and is used to connect the source signal; the first gate covers part of the top surface of the first type active column and part of the top surface of the second type active column, and is used to connect the gate signal; the third gate covers part of the top surface of the first type active column and part of the top surface of the second type active column, and is used to connect the gate signal.

[0107] Exemplarily, forming the first gate 40, the second gate 50, and the third gate 60 sequentially arranged along the first direction may include the following steps:

[0108] S131 : forming a stacked gate dielectric layer and a gate material layer 130 on the top surfaces of the first-type active pillars and the second-type active pillars.

[0109] For example, see Fig.13 A stacked gate dielectric layer 90 and a gate material layer 130 may be formed on the top surfaces of the first type active pillar 20 and the second type active pillar 30 by, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0110] S132: etching the gate material layer to form a first gate, a second gate and a third gate.

[0111] For example, see Fig.14 The gate material layer 130 may be etched by, but not limited to, a dry etching process or a wet etching process to form the first gate 40 , the second gate 50 and the third gate 60 .

[0112] It should be noted that after forming the first gate 40, the second gate 50 and the third gate 60, the step of forming the sidewall 70 of the first gate and the sidewall 80 of the third gate may also be included, and a groove is formed between the sidewall 70 of the first gate, the sidewall 80 of the third gate and the gate dielectric layer 90 of the second gate 50. The gate conductive layer of the second gate 50 is located in the groove. The material of the sidewall 70 of the first gate and the sidewall 80 of the third gate can be but is not limited to an insulating material, and the sidewall 70 of the first gate and the sidewall 80 of the third gate insulate the first gate 40, the second gate 50 and the third gate 60.

[0113] Exemplarily, the second gate 50 is located directly above the second-type active pillar 30 and is used to connect the source signal, which can reduce the area of ​​the gate, thereby increasing the switching speed of the device and reducing the switching loss.

[0114] In another example, the second gate 50 is located directly above the second-type active pillar 30 and is not connected to the source signal, so as to reduce the area of ​​the gate, thereby increasing the switching speed of the device and reducing the switching loss.

[0115] S133: forming a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is connected to the first gate electrode and the third gate electrode, the source electrode covers partially exposed top surfaces of the two first-type active pillars, the top surface of the gate conductive layer of the second gate electrode, the outer surface of the side wall of the first gate electrode, and the outer surface of the side wall of the third gate electrode, and the drain electrode is located on a side of the substrate away from the second-type active pillar.

[0116] As an example, see Figure 2 , the gate electrode (not shown), the source 100 and the drain 120 may be formed by, but not limited to, physical vapor deposition, chemical vapor deposition or atomic layer deposition processes. The material of the gate electrode may be, but not limited to, a metal material. The material of the source 100 may be, but not limited to, polysilicon, metal, metal alloy, silicon nitride or aluminum oxide, etc. The material of the drain 120 may be, but not limited to, polysilicon, metal, metal alloy, silicon nitride or aluminum oxide, etc.

[0117] The manufacturing method of the semiconductor device of the present application includes providing a substrate, and then forming a first-type active pillar, a second-type active pillar, a first-type active pillar, and a second-type active pillar arranged in sequence along a first direction parallel to the top surface of the substrate on the substrate. The second-type active pillar includes n second-type well regions arranged at intervals along a second direction perpendicular to the substrate, where 2 < n < 8 and n is an integer. Finally, a first gate, a second gate, and a third gate are formed in sequence along the first direction. The second gate is located directly above the second-type active pillar and is used to connect to the source signal. The first gate covers the top surfaces of part of the first-type active pillars and part of the second-type active pillars, and is used to connect to the gate signal. The third gate covers the top surfaces of part of the first-type active pillars and part of the second-type active pillars, and is used to connect to the gate signal. By setting the gate as a structure of separate first gate, second gate, and third gate, and using the second gate to connect to the source signal, the area of the gate can be reduced, the breakdown voltage of the device can be increased, the switching speed of the device can be increased, and the switching loss can be reduced. By connecting the gate signal through the first gate and the second gate, the control signal can be transmitted to the gate of the semiconductor device, thereby realizing the switching control of the device. The first gate and the second gate cover the top surfaces of part of the first-type active pillars and part of the second-type active pillars, which can realize the coverage of the gate on the conductive channel of the device, and further improve the control ability of the gate on the carriers in the channel and the sensitivity of the device. Therefore, the device loss can be reduced when the control signal controls the semiconductor device. By arranging n second-type well regions in the second-type active pillar and using the doping concentration of the second-type well region to be greater than that of the second-type active pillar of the substrate, the number of carriers in the second-type active pillar can be increased, the current conduction rate between the gate and the drain can be increased, the distribution of the electric field can be optimized, thereby reducing the on-resistance of the device, reducing the gate-drain charge, and reducing the Miller capacitance, reducing the switching power consumption of the device, increasing the switching on-speed and off-speed of the device, further reducing the conduction loss, and improving the electrical properties of the semiconductor device.

[0118] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0119] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it cannot be understood as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that: The device comprises a substrate, a first-type active column, a second-type active column, and a first-type active column arranged in sequence along a first direction parallel to a top surface of the substrate on the substrate, and a first gate, a second gate, and a third gate arranged in sequence along the first direction; The second gate is located directly above the second-type active column and is used to connect the source signal; The first gate covers part of the top surface of the first-type active pillar and part of the top surface of the second-type active pillar, and is used to connect a gate signal; The third gate covers a portion of the top surface of the first-type active pillar and a portion of the top surface of the second-type active pillar, and is used to connect the gate signal; The second-type active pillar includes n second-type well regions arranged at intervals along a second direction perpendicular to the substrate; Wherein, 2≤n≤8, and n is an integer.

2. The semiconductor device according to claim 1, wherein: A groove is formed between the sidewall of the first gate, the sidewall of the third gate, and the gate dielectric layer of the second gate; The gate conductive layer of the second gate is located in the groove.

3. The semiconductor device according to claim 2, characterized in that The sidewall of the first gate is coated on the outer surface of the gate conductive layer of the first gate; The sidewall of the third gate is coated on the outer surface of the gate conductive layer of the third gate.

4. The semiconductor device according to claim 3, characterized in that The first-type active column includes a second-type doped region, the source electrode covers a portion of the top surface of the second-type doped region, and the first gate or the third gate covers a portion of the top surface of the second-type doped region.

5. The semiconductor device according to claim 2, wherein: The second gate further includes a source electrode, which covers partially exposed top surfaces of the two first-type active pillars, a top surface of the gate conductive layer of the second gate, an outer surface of the sidewall of the first gate, and an outer surface of the sidewall of the third gate.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that: The first-type active pillar includes a protrusion extending along the first direction to the inside of the second-type active pillar.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that: The conductivity type of the substrate is the second type; A side of the substrate facing away from the second-type active pillar includes a drain.

8. The semiconductor device according to any one of claims 2 to 4, characterized in that: A top surface of the gate conductive layer of the second gate is lower than a top surface of the first gate or a top surface of the third gate.

9. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 8.

10. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; Forming on the substrate a first-type active column, a second-type active column, and a first-type active column sequentially arranged along a first direction parallel to the top surface of the substrate, wherein the second-type active column includes n second-type well regions spaced apart and arranged along a second direction perpendicular to the substrate, wherein 2≤n≤8, and n is an integer; A first gate, a second gate, and a third gate are formed which are arranged in sequence along the first direction; the second gate is located directly above the second-type active column and is used to connect the source signal; the first gate covers part of the top surface of the first-type active column and part of the top surface of the second-type active column, and is used to connect the gate signal; the third gate covers part of the top surface of the first-type active column and part of the top surface of the second-type active column, and is used to connect the gate signal.

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