Manufacturing method of semiconductor structure

Abstract

The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps of: providing a substrate comprising a substrate layer and a gate structure, forming a side wall on the side surface of the gate structure, forming an active region and a drain region on the upper surface layer of the substrate layer, and forming metal silicide layers on the source region and the drain region; putting the substrate into an etching cavity and carrying out surface treatment by adopting oxygen plasma so as to generate a protective oxide layer on the metal silicide layer; thinning the side wall; and forming a CESL stress layer, an interlayer dielectric layer and a contact hole. According to the invention, the problem of metal silicide loss can be effectively improved, the loss of the metal silicide is only limited to the oxidation loss part, the loss cannot be increased due to the increase of the etching amount of the side wall, and the process window can be expanded. In addition, the oxygen plasma surface treatment is carried out in the etching cavity, so that the process cavity does not need to be replaced, and the process simplification and the cost reduction are facilitated. And the treatment temperature is relatively low, so that the stability of the metal silicide is facilitated.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a semiconductor structure. Background Art

[0002] Starting from the 90nm technology node, various technologies for stress-induced carrier mobility enhancement have gradually appeared in CMOS manufacturing. For NMOS, stress memorization technique (SMT) has been used to improve electron mobility. The characteristic of SMT is that this technology can significantly accelerate the electron mobility of NMOS devices by virtue of tensile stress, thereby improving the driving current of NMOS devices. For PMOS, the method of embedding silicon germanium (SiGe) in the source / drain region is adopted to introduce local compressive strain or stress proximity technology (SPT). This technology removes the sidewall before the formation of the contact hole etch stop layer (CESL) after the completion of self-aligned silicide, and has proved the enhancement of CESL proximity and the maximum stress transfer from CESL to the channel. In addition to the improvement of mobility, stress proximity technology also expands the process window for subsequent interlayer dielectric gap filling.

[0003] At present, the stress proximity technology process generally adopts dry etching, and uses heavy polymer gas plasma to etch the silicon nitride sidewall. Heavy polymer gases mainly include CH2F2 and CH3F, but due to the limited selectivity between silicon nitride and silicide, there will be excessive silicide loss, resulting in the silicide being etched through in the subsequent contact hole etching process, or the process window will be reduced due to the reduction of the etching amount of silicon nitride in the SPT process.

[0004] In an improved method, before the etching process of side wall thinning, the metal silicide layer is first rinsed with deionized water filled with ozone, or ozone ions are sputtered to the surface of the metal silicide layer by sputtering, so that a thin film oxide layer is generated on the surface of the metal silicide, and the thin film oxide layer is used as a protective layer to prevent the subsequent etching steps from damaging the metal silicide layer. However, in this improved method, the substrate needs to be placed in an ozone machine for treatment before being placed in an etching machine, which is inefficient, and there are problems such as shunting during the process, which seriously affects production capacity; if the method of rinsing with deionized water containing O3 is used, the liquid must be replaced regularly to ensure the content of O3, and the cost price is relatively high; if the method of ozone ion sputtering is used, for example, NiSi metal silicide is prone to phase change at high temperature, Ni diffusion leads to a decrease in electrical properties, and the lattice damage that may be caused by sputtering cannot be determined; and the cost of O3 is relatively high. In addition, the ozone treatment temperature is relatively high, such as 150°C-600°C, which is not conducive to the stability of metal silicide.

[0005] Therefore, how to improve the sidewall etching process of stress proximity technology to reduce the loss of silicide while ensuring the sidewall etching amount and process window, while controlling production costs and ensuring the stability of metal silicide has become an important technical problem that technical personnel in this field need to solve urgently.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the technical problems existing in the prior art as described above, the object of the present invention is to provide a method for manufacturing a semiconductor structure, which is used to solve the problem that the sidewall etching process of the existing stress proximity technology is prone to excessive silicide loss, resulting in the silicide being etched through in the subsequent contact hole etching process, or the process window is reduced due to the reduction of the sidewall etching amount.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0009] A substrate is provided, the substrate comprising a substrate layer and a gate structure located on the substrate layer, sidewalls are formed on the sides of the gate structure, an upper surface layer of the substrate layer on both sides of the gate structure forms an active region and a drain region, and a metal silicide layer is formed on the source region and the drain region;

[0010] Placing the substrate in an etching chamber, and performing surface treatment on the substrate using oxygen plasma to form a protective oxide layer on the metal silicide layer;

[0011] Introducing etching gas into the etching chamber to thin the sidewall to a preset width;

[0012] forming a stacked CESL stress layer and an interlayer dielectric layer on the substrate;

[0013] A plurality of contact holes are formed, wherein the contact holes are located above the source region or above the drain region, the contact holes penetrate the interlayer dielectric layer and the CESL stress layer, and the metal silicide layer is exposed at the bottom of the contact holes.

[0014] Optionally, when the substrate is surface treated by oxygen plasma, the O2 flow rate introduced into the etching chamber is greater than 200 sccm, the surface treatment temperature range is 60° C.-65° C., and the surface treatment time range is 30 seconds-60 seconds.

[0015] Optionally, the thickness of the protective oxide layer is in the range of 15 angstroms to 25 angstroms, and the etching selectivity ratio of the etching gas to the sidewall and the protective oxide layer is greater than 15:1.

[0016] Optionally, the sidewall spacer includes a silicon nitride layer, and after thinning the sidewall spacer, the silicon nitride layer is completely removed, or the width of the remaining silicon nitride layer is 30%-60% of the width of the silicon nitride layer before thinning.

[0017] Optionally, the gate structure includes a gate dielectric layer and a polysilicon layer located on the gate dielectric layer, the sidewall includes a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer is sandwiched between the sidewall of the polysilicon layer and the silicon nitride layer.

[0018] Optionally, before forming a stacked CESL stress layer and an interlayer dielectric layer on the substrate, the protective oxide layer is retained.

[0019] Optionally, before forming the stacked CESL stress layer and the interlayer dielectric layer on the substrate, the method further includes removing the protective oxide layer.

[0020] Optionally, after thinning the sidewall to a preset width, a step of wet cleaning to remove etching byproducts is further included, wherein hydrofluoric acid is added to a cleaning solution used in the wet cleaning, and the protective oxide layer is removed during the wet cleaning process.

[0021] Optionally, the material of the metal silicide layer includes at least one of cobalt silicide, nickel silicide and titanium silicide, the CESL stress layer includes a silicon nitride layer, and the thickness of the CESL stress layer ranges from 300 angstroms to 400 angstroms.

[0022] Optionally, the gate structure is a gate structure of a PMOS transistor.

[0023] As described above, the method for manufacturing the semiconductor structure of the present invention uses oxygen plasma in the etching chamber to perform surface treatment on the substrate to generate a protective oxide layer on the metal silicide layer. After that, in the process of introducing etching gas into the etching chamber to thin the side wall to a preset width, the metal silicide layer will not be etched because of the protection of the protective oxide layer, thereby effectively improving the problem of metal silicide loss caused by side wall etching in stress proximity technology, wherein the loss of metal silicide is limited to the part of oxidation loss, and the loss will not increase due to the increase in the amount of side wall etching, which is conducive to expanding the process window. Since the oxygen plasma surface treatment in the present invention is carried out in the etching chamber, there is no need to replace the process chamber, which improves the production capacity, is more conducive to simplifying the process and reducing costs, and avoids contamination and damage to the wafer during the transfer chamber. The oxygen plasma surface treatment in the present invention is carried out at a lower temperature, which is more conducive to the stability of metal silicide. Since the method of ozone ion sputtering is avoided, the risk of damage to the structure on the wafer can be reduced. In addition, in the factory production process, O2 is a bulk gas that can be produced by itself, and is cheaper than O3. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The diagram shows a structure schematically presented before a sidewall etching process using a stress proximity technology in a semiconductor process.

[0025] Figure 2 The diagram shows a structure schematically presented after a sidewall etching process using a stress proximity technique is performed in a semiconductor process.

[0026] Figure 3 It shows a schematic diagram of a structure presented after a contact hole process is performed on a structure that has undergone a sidewall thinning process during a semiconductor process.

[0027] Figure 4 It is a process flow chart of the method for manufacturing the semiconductor structure of the present invention.

[0028] Figure 5 A schematic diagram showing an exemplary structure of a substrate provided for the method for manufacturing a semiconductor structure of the present invention.

[0029] Figure 6 The schematic diagram of the structure obtained after the method for manufacturing the semiconductor structure of the present invention uses oxygen plasma to perform surface treatment on the substrate to generate a protective oxide layer on the metal silicide layer is shown.

[0030] Figure 7 It is a schematic diagram showing the structure obtained after the sidewall is thinned to a preset width according to the manufacturing method of the semiconductor structure of the present invention.

[0031] Figure 8It is a schematic diagram showing the structure obtained after forming a stacked CESL stress layer and an interlayer dielectric layer on a substrate according to the manufacturing method of the semiconductor structure of the present invention.

[0032] Fig. 9 It is a schematic diagram showing the structure obtained after forming a plurality of contact holes according to the method for manufacturing a semiconductor structure of the present invention.

[0033] Description of Reference Numerals

[0034] 101 Substrate

[0035] 102 Shallow Trench Isolation Structure

[0036] 103 Gate Structure

[0037] 104 Side Wall

[0038] 105 Metal silicide layer

[0039] 106 Contact hole

[0040] 107 interlayer dielectric layer

[0041] Steps S1 to S5

[0042] 201 substrate layer

[0043] 202 Gate structure

[0044] 2021 Gate dielectric layer

[0045] 2022 Polysilicon layer

[0046] 203 Side Wall

[0047] 2031 Silicon Nitride Layer

[0048] 2032 Silicon oxide layer

[0049] 204 Source and drain region metal silicide layer

[0050] 205 Shallow Trench Isolation Structure

[0051] 206 Gate metal silicide layer

[0052] 207a Source and drain region protective oxide layer

[0053] 207b Gate protection oxide layer

[0054] 208 CESL stress layer

[0055] 209 interlayer dielectric layer

[0056] 210 Contact hole DETAILED DESCRIPTION

[0057] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0059] In the manufacturing process of a semiconductor device, after the metal silicide is grown, the sidewall is thinned by stress proximity technology, which can expand the subsequent deposition process window and make the stress applied by the stress layer closer to the channel. When performing the sidewall thinning process, the silicon nitride area of ​​the sidewall is completely or partially removed. In the sidewall thinning process of partially removing the sidewall, the remaining silicon nitride layer width is usually between 30% and 60% of the silicon nitride layer width before thinning, and the specific sidewall removal amount is determined by the integration requirements. Whether it is partial or full sidewall removal, the sidewall etching process needs to be optimized to minimize the damage to the self-aligned metal silicide and avoid increased resistance.

[0060] Specifically, the loss of metal silicide needs to be strictly controlled during the sidewall etching. If the metal silicide loss is too large or the process window for subsequent contact hole etching is too small, the silicide may be etched through, resulting in excessive resistance.

[0061] like Figures 1 to 3 As shown, it is a schematic diagram of the structure presented in each step of a semiconductor process, wherein: Figure 1 The structure shown is a schematic diagram before the sidewall etching process of the stress proximity technology is performed, including a substrate 101, a shallow trench isolation structure 102, a gate structure 103, a sidewall 104 and a metal silicide layer 105. Figure 2 The schematic diagram shows the structure after the sidewall etching process of the stress proximity technology is performed, wherein the metal silicide layer 105 on both sides of the gate structure 103 is lost in a large amount during the sidewall etching process and becomes very thin. Figure 3It is a schematic diagram of the structure after the contact hole process is performed on the structure after the sidewall thinning process, wherein the contact hole 106 is formed in the interlayer dielectric layer 107. Because the metal silicide 105 on both sides of the gate structure 103 is too thin, the metal silicide 105 is etched through during the contact hole etching process, which will cause the contact resistance of the contact hole 106 to be too large.

[0062] The present invention improves the sidewall etching process of the stress proximity technology, and can reduce the loss of metal silicide under the premise of ensuring the sidewall etching amount and the process window.

[0063] See also Figure 4 The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0064] S1: providing a substrate, the substrate comprising a substrate layer and a gate structure located on the substrate layer, sidewalls are formed on the sides of the gate structure, an upper surface layer of the substrate layer on both sides of the gate structure forms an active region and a drain region, and a metal silicide layer is formed on the source region and the drain region;

[0065] S2: placing the substrate into an etching chamber, and performing surface treatment on the substrate using oxygen plasma to form a protective oxide layer on the metal silicide layer;

[0066] S3: introducing etching gas into the etching chamber to thin the sidewall to a preset width;

[0067] S4: sequentially forming a CESL stress layer and an interlayer dielectric layer on the substrate;

[0068] S5: forming a plurality of contact holes, wherein the contact holes are located above the source region or above the drain region, the contact holes penetrate the interlayer dielectric layer and the CESL stress layer, and the metal silicide layer is exposed at the bottom of the contact holes.

[0069] Combine the following Figure 5-Figure 9 The steps of the method for manufacturing the semiconductor structure of the present invention are described in detail.

[0070] First see Figure 5 , perform the step S1: provide a substrate, the substrate includes a substrate layer 201 and a gate structure 202 located on the substrate layer 201, side walls 203 are formed on the sides of the gate structure 202, and the upper surface layer of the substrate layer 201 on both sides of the gate structure 202 forms an active region and a drain region (not shown), and a metal silicide layer is formed on the source region and the drain region (indicated by the source and drain region metal silicide layer 204 in the figure).

[0071] As an example, the substrate layer 201 may be made of silicon, silicon on insulator, germanium, germanium silicon, silicon carbide, III-V compounds or other suitable semiconductor substrates. The substrate layer 201 may be provided with an N-well or a P-well as required.

[0072] As an example, the gate structure 202 includes a gate dielectric layer 2021 and a polysilicon layer 2022 located on the gate dielectric layer 2021 , and the gate dielectric layer 2021 includes a silicon oxide layer.

[0073] As an example, the number of the gate structures 202 can be adjusted as needed. Figure 5 Two gate structures are presented, corresponding to two PMOS transistors, which are respectively located in different areas of the substrate layer 201 and separated by a shallow trench isolation structure 205.

[0074] As an example, a metal silicide layer (denoted by the gate metal silicide layer 206 in the figure) is also formed on the polysilicon layer 2022 .

[0075] As an example, the material of the source and drain metal silicide layer 204 and the gate metal silicide layer 206 includes at least one of cobalt silicide, nickel silicide and titanium silicide, wherein the metal silicide can be formed by depositing metal and performing an annealing process.

[0076] As an example, the sidewall spacer 203 includes a silicon nitride layer 2031 . In this embodiment, the sidewall spacer 203 also includes a silicon oxide layer 2032 . The silicon oxide layer 2032 is sandwiched between the sidewall of the polysilicon layer 2022 and the silicon nitride layer 2031 .

[0077] Please see again Figure 6 , executing the step S2: placing the substrate into an etching chamber, and performing surface treatment on the substrate using oxygen plasma to generate a protective oxide layer on the metal silicide layer.

[0078] Specifically, the protective oxide layer is used to enhance the etching resistance of the metal silicide layer. In this embodiment, the thickness of the protective oxide layer is in the range of 15 angstroms to 25 angstroms, and the protective oxide layer includes a source and drain region protective oxide layer 207a located on the top surface of the source and drain region metal silicide layer 204 and a gate region protective oxide layer 207b located on the top surface of the gate region metal silicide layer 206.

[0079] It should be pointed out that the surface treatment of the substrate by oxygen plasma in the present invention is carried out in the etching chamber, and the etching machine itself will pass a lot of gas, including oxygen (O2). The present invention directly introduces oxygen into the etching chamber before the side wall etching, and the oxygen dissociates under the action of the electric field, and reacts with the metal silicide at a certain temperature (for example, 60°C) to generate the protective oxide layer. Compared with the use of other gases, such as ozone, the use of oxygen in the present invention is more conducive to simplifying the process and reducing costs, because if ozone is used, the substrate needs to be placed in an ozone machine for treatment first, and then placed in an etching machine, which is more expensive.

[0080] As an example, when the substrate is surface treated by oxygen plasma, the O2 flow rate introduced into the etching chamber is greater than 200 sccm, the temperature range of the surface treatment is 60°C-65°C, and the time range of the surface treatment is 30 seconds-60 seconds. The present invention performs the surface treatment at a temperature of 60°C-65°C, which is relatively low, and the metal silicide is not prone to phase change, which is more conducive to the stability of the metal silicide.

[0081] Please see again Figure 7 , executing the step S3: introducing etching gas into the etching chamber to thin the sidewall 203 to a preset width.

[0082] Specifically, the object to be thinned is mainly the silicon nitride layer 2031. In this embodiment, a high selectivity etching gas is used to thin the silicon nitride layer 2031, and the etching selectivity of the etching gas to the sidewall 203 and the protective oxide layer is greater than 15: 1. During the sidewall thinning process, the metal silicide layer 4 will not be etched or the etching amount is small because it is protected by the protective oxide layer.

[0083] As examples, etching gases include, but are not limited to, CH2F2 and CH3F.

[0084] Specifically, the etching process time can be freely controlled according to the silicon nitride remaining target, for example, after thinning the sidewall 203, the silicon nitride layer 2031 is completely removed, or the remaining width of the silicon nitride layer 2031 is 30%-60% of the width of the silicon nitride layer 2031 before thinning.

[0085] As an example, after thinning the sidewall spacer 203 to a preset width, a wet cleaning step is further included to remove etching byproducts.

[0086] Please see again Figure 8 , executing the step S4: sequentially forming a CESL stress layer 208 and an interlayer dielectric layer 209 on the substrate.

[0087] Specifically, the CESL stress layer 208 is used to provide stress on one hand, and to serve as a contact hole etching stop layer on the other hand. The CESL stress layer 208 may be, for example, a stressed silicon nitride layer, and its thickness may be adjusted according to actual process requirements, for example, the thickness range is 300 angstroms to 400 angstroms. Since the sidewall 203 is thinned, the stress of the CESL stress layer 208 is more easily transferred to the channel, which is beneficial to improving carrier mobility.

[0088] Specifically, the interlayer dielectric layer 209 may be made of silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass or other suitable dielectric materials. The interlayer dielectric layer 209 may be formed by chemical vapor deposition or other suitable methods.

[0089] It should be noted that before forming the CESL stress layer 208 on the substrate, the protective oxide layer can be removed or retained as needed, wherein: Figure 8 FIG. 4 shows a situation where the CESL stress layer 208 and the interlayer dielectric layer 209 are deposited after the protective oxide layer is removed.

[0090] As an example, a step of removing the protective oxide layer can be added to the wet cleaning step after the sidewall etching, or hydrofluoric acid can be added to the cleaning solution used in the wet cleaning step after the sidewall etching, so that the protective oxide layer is removed during the wet cleaning process.

[0091] Please see again Fig. 9 , perform the step S5: form a plurality of contact holes 210, wherein the contact holes 210 are located above the source region or above the drain region, the contact holes 210 penetrate the interlayer dielectric layer 209 and the CESL stress layer 208, and the bottom of the contact holes 210 exposes the metal silicide layer 204 of the source and drain regions.

[0092] Specifically, the contact hole 210 is formed by semiconductor patterning processes such as photolithography and etching, and subsequently a metal plug may be further filled in the contact hole 210 , and other required components such as metal electrodes and metal conductive lines may be fabricated on the interlayer dielectric layer 209 .

[0093] At this point, a semiconductor structure is produced, such as Fig. 9As shown, the semiconductor structure includes a substrate, a CESL stress layer 208, an interlayer dielectric layer 209 and a plurality of contact holes 210, wherein the substrate includes a substrate layer 201 and a gate structure 202 located on the substrate layer 201, sidewalls 203 are formed on the sides of the gate structure 202, the upper surface layer of the substrate layer 201 on both sides of the gate structure 202 forms a source region and a drain region (not shown), source and drain region metal silicide layers 204 are formed on the source region and the drain region, the CESL stress layer 205 is located on the substrate and covers the gate structure 202, the interlayer dielectric layer 209 is located on the CESL stress layer 205, the contact hole 210 is located above the source region or above the drain region, the contact hole 210 penetrates the interlayer dielectric layer 209 and the CESL stress layer 205, and the bottom of the contact hole 210 exposes the source and drain region metal silicide layer 204. Since the manufacturing method of the semiconductor structure of the present invention reduces the loss of metal silicide through the protective oxide layer, the loss of metal silicide is limited to the oxidation loss part, and the loss will not increase due to the increase of the side wall etching amount. On the one hand, it can avoid that the contact hole pierces the metal silicide and causes the contact resistance between the contact plug and the substrate layer to increase. On the other hand, it can ensure a sufficient side wall etching amount, which is conducive to expanding the process window.

[0094] In summary, the method for manufacturing the semiconductor structure of the present invention uses oxygen plasma in the etching chamber to perform surface treatment on the substrate to generate a protective oxide layer on the metal silicide layer, and then in the process of introducing etching gas into the etching chamber to thin the side wall to a preset width, the metal silicide layer will not be etched because of the protection of the protective oxide layer, thereby effectively improving the problem of metal silicide loss caused by side wall etching in stress proximity technology, wherein the loss of metal silicide is limited to the part of oxidation loss, and the loss will not increase due to the increase in the amount of side wall etching, which is conducive to expanding the process window. Since the oxygen plasma surface treatment in the present invention is carried out in the etching chamber, there is no need to replace the process chamber, which improves the production capacity, is more conducive to simplifying the process and reducing costs, and avoids contamination and damage to the wafer during the transfer chamber. The oxygen plasma surface treatment in the present invention is carried out at a lower temperature, which is more conducive to the stability of metal silicide. Since the method of ozone ion sputtering is avoided, the risk of damage to the structure on the wafer can be reduced. In addition, in the factory production process, O2 is a bulk gas that can be produced by itself, and is cheaper than O3. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: A substrate is provided, the substrate comprising a substrate layer and a gate structure located on the substrate layer, sidewalls are formed on the sides of the gate structure, an upper surface layer of the substrate layer on both sides of the gate structure forms an active region and a drain region, and a metal silicide layer is formed on the source region and the drain region; Placing the substrate in an etching chamber, and performing surface treatment on the substrate using oxygen plasma to form a protective oxide layer on the metal silicide layer; Introducing etching gas into the etching chamber to thin the sidewall to a preset width; forming a CESL stress layer and an interlayer dielectric layer on the substrate in sequence; A plurality of contact holes are formed, wherein the contact holes are located above the source region or above the drain region, the contact holes penetrate the interlayer dielectric layer and the CESL stress layer, and the metal silicide layer is exposed at the bottom of the contact holes.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: When the substrate is surface treated by oxygen plasma, the O2 flow rate introduced into the etching chamber is greater than 200 sccm, the surface treatment temperature range is 60° C.-65° C., and the surface treatment time range is 30 seconds-60 seconds.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein: The thickness of the protective oxide layer is in the range of 15 angstroms to 25 angstroms, and the etching selectivity ratio of the etching gas to the sidewall and the protective oxide layer is greater than 15:

1.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The sidewall spacer includes a silicon nitride layer. After the sidewall spacer is thinned, the silicon nitride layer is completely removed, or the width of the remaining silicon nitride layer is 30%-60% of the width of the silicon nitride layer before thinning.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The gate structure includes a gate dielectric layer and a polysilicon layer located on the gate dielectric layer, the sidewall includes a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer is sandwiched between the sidewall of the polysilicon layer and the silicon nitride layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming a stacked CESL stress layer and an interlayer dielectric layer on the substrate, the protective oxide layer is retained.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming the stacked CESL stress layer and the interlayer dielectric layer on the substrate, the method further includes a step of removing the protective oxide layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: After thinning the sidewall to a preset width, a step of wet cleaning to remove etching byproducts is also included, wherein hydrofluoric acid is added to the cleaning solution used in the wet cleaning, and the protective oxide layer is removed during the wet cleaning process.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The material of the metal silicide layer includes at least one of cobalt silicide, nickel silicide and titanium silicide. The CESL stress layer includes a silicon nitride layer. The thickness of the CESL stress layer ranges from 300 angstroms to 400 angstroms.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: The gate structure is a gate structure of a PMOS transistor.

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