Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a substrate, an isolation layer, an active region, a gate and a gate dielectric layer, wherein the isolation layer is located on the substrate and is provided with two openings parallel to each other; the active region is located on the isolation layer, the active region comprises a source region, a channel region and a drain region connected in sequence, the source region and the drain region are respectively provided in one of the openings, the channel region is located above the isolation layer and is provided parallel to the surface of the substrate; the gate is provided around the channel region along the extension direction of the channel region; the gate dielectric layer is provided between the gate and the channel region. The present application increases the contact area between the gate and the channel region, which is beneficial to improving the current transmission cross-sectional area and the electric field control effect in the channel region, reducing the area of ​​the semiconductor device, and reducing or avoiding the short channel effect of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the feature size of the integrated circuit manufacturing process technology continues to shrink, the short-channel effect of semiconductor devices becomes more and more obvious. The method of only improving the control ability of the gate by technologies such as increasing the channel concentration and reducing the thickness of the gate oxide layer can no longer meet the requirements of the development of Moore's law.

[0003] Generally, a high dielectric constant (High-K) material and a metal gate can be used to replace the gate dielectric layer and polysilicon gate made of silicon oxynitride (SiON) (i.e., using the HKMG technology). Thus, when the gate length is very small, by reducing the thickness of the gate oxide layer, the gate electrode capacitance can be increased, the control ability of the gate over the channel can be improved, and the threshold voltage can be adjusted at the same time. However, in semiconductor devices using HKMG, the substrate parasitic capacitance always exists and its influence becomes more and more obvious; at the same time, since the channel shape of the semiconductor device has not changed, it cannot be well matched with the improved metal gate, and there is a defect of too large area in the design. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof, which can save the area of the semiconductor device while reducing or avoiding the influence of the short-channel effect on the performance of the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, including:

[0006] A substrate;

[0007] An isolation layer located on the substrate, and two parallel openings are provided in the isolation layer;

[0008] An active region located on the isolation layer, the active region includes a source region, a channel region and a drain region connected in sequence, wherein the source region and the drain region are respectively disposed in one of the openings, and the channel region is located above the isolation layer and is parallel to the surface of the substrate;

[0009] A gate surrounding the channel region along the extending direction of the channel region;

[0010] A gate dielectric layer disposed between the gate and the channel region.

[0011] In one embodiment, the cross-sectional shape of the active region along the direction perpendicular to the substrate is a U shape with an opening downward.

[0012] In one embodiment, the isolation layer includes:

[0013] A first isolation layer located on the substrate, and the first isolation layer is provided with the opening;

[0014] A second isolation layer covering the inner wall of the opening and the surface of the first isolation layer on the side away from the substrate.

[0015] In one embodiment, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes silicon nitride.

[0016] In one embodiment, the material of the gate includes a metal material, and the metal material includes at least one of copper metal, aluminum metal, and tungsten metal; the material of the gate dielectric layer includes a high-k material.

[0017] In a second aspect, the present application also provides a method for manufacturing a semiconductor device, including:

[0018] Providing a substrate, forming an isolation layer on the substrate, and two parallel openings are formed in the isolation layer;

[0019] Forming an active region, a gate, and a gate dielectric layer on the isolation layer, wherein the active region includes a source region, a channel region, and a drain region connected in sequence, the source region and the drain region are respectively formed in one of the openings, the channel region is formed above the isolation layer and is parallel to the surface of the substrate, the gate surrounds the channel region along the extending direction of the channel region, and the gate dielectric layer is formed between the gate and the channel region.

[0020] In one embodiment, the step of forming an active region, a gate, and a gate dielectric layer on the isolation layer includes:

[0021] Forming a source region and a drain region in the openings respectively, and the tops of the source region and the drain region are higher than the surface of the isolation layer;

[0022] Forming a lower layer gate on the isolation layer between two adjacent openings, a first trench is formed in the lower layer gate, and the extending direction of the first trench is parallel to the connecting direction of two adjacent openings;

[0023] Forming a lower layer gate dielectric in the first trench, a second trench is formed in the lower layer gate dielectric and the extending direction of the second trench is parallel to the extending direction of the first trench;

[0024] Forming a channel region in the second trench, and the channel region connects the source region and the drain region to form the active region of the semiconductor device;

[0025] Form an upper gate dielectric on the channel region, where the upper gate dielectric is connected to the lower gate dielectric and forms a gate dielectric layer surrounding the channel region;

[0026] Form an upper gate on the upper gate dielectric, where the upper gate is connected to the lower gate and forms a gate surrounding the channel region.

[0027] In one embodiment, the step of forming the lower gate on the isolation layer between two adjacent openings includes:

[0028] Form the lower gate on the isolation layer;

[0029] Perform planarization on the lower gate to make the surface of the lower gate flush with the surfaces of the source region and the drain region;

[0030] Remove part of the lower gate so that the remaining lower gate is located between the two openings, and form the first trench in the lower gate.

[0031] In one embodiment, the step of forming the lower gate dielectric in the first trench includes:

[0032] Form the lower gate dielectric on the inner wall of the first trench, where the lower gate dielectric at least extends and covers the lower gate, the source region, and the drain region around the first trench;

[0033] Etch the lower gate dielectric so that the remaining lower gate dielectric is located on the inner wall of the first trench, and a second trench is formed in the lower gate dielectric.

[0034] In one embodiment, the isolation layer includes the first isolation layer and the second isolation layer, and the step of forming the isolation layer on the substrate and forming two parallel openings in the isolation layer includes:

[0035] Form the first isolation layer on the substrate;

[0036] Etch the first isolation layer to form the opening in the first isolation layer;

[0037] Form the second isolation layer on the first isolation layer, where the second isolation layer covers the inner wall of the opening.

[0038] The unexpected effect of this application is that by setting the gate surrounding the channel region, the contact area between the gate and the channel region is increased, which is beneficial to improving the cross-sectional area of current transmission in the channel region, thereby enhancing the electric field control effect in the channel region; by setting an isolation layer between the gate and the substrate, the influence of the short-channel effect on the performance of semiconductor devices is reduced or avoided. Description of the Drawings

[0039] In order to more clearly illustrate the technical solutions in the embodiments of this application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0040] Figure 1 It is a three-dimensional structural schematic diagram of a semiconductor device provided by an embodiment of this application.

[0041] Figure 2 It is Figure 1 a schematic cross-sectional structure diagram of the semiconductor device shown along the AB direction.

[0042] Figure 3 It is Figure 1 a schematic cross-sectional structure diagram of the semiconductor device shown along the CD direction.

[0043] Figure 4 It is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of this application.

[0044] Figure 5 It is a three-dimensional structural schematic diagram corresponding to the step of providing a substrate in the manufacturing method of a semiconductor device provided by an embodiment of this application.

[0045] Figure 6 It is a three-dimensional structural schematic diagram corresponding to the step of forming an opening in the manufacturing method of a semiconductor device provided by an embodiment of this application.

[0046] Figure 7 It is a three-dimensional structural schematic diagram corresponding to the step of forming an isolation layer in the manufacturing method of a semiconductor device provided by an embodiment of this application.

[0047] Figure 8 It is a flowchart corresponding to the step of forming an active region, a gate, and a gate dielectric layer on the isolation layer in the manufacturing method of a semiconductor device provided by an embodiment of this application.

[0048] Figure 9 It is a three-dimensional structural schematic diagram corresponding to the step of forming a source region and a drain region in the manufacturing method of a semiconductor device provided by an embodiment of this application.

[0049] Figure 10 A three-dimensional structure diagram corresponding to the step of forming a lower gate in the manufacturing method of a semiconductor device provided by an embodiment of the present application.

[0050] Figure 11 A three-dimensional structure diagram corresponding to the step of forming a first trench in the manufacturing method of a semiconductor device provided by an embodiment of the present application.

[0051] Figure 12 For Figure 11 A cross-sectional structure diagram of the semiconductor device in along the AB direction.

[0052] Figure 13 A three-dimensional structure diagram corresponding to the step of forming a lower gate dielectric in the manufacturing method of a semiconductor device provided by an embodiment of the present application.

[0053] Figure 14 For Figure 13 A cross-sectional structure diagram of the semiconductor device in along the AB direction.

[0054] Figure 15 A three-dimensional structure diagram corresponding to the step of forming a channel region in the manufacturing method of a semiconductor device provided by an embodiment of the present application.

[0055] Figure 16 For Figure 15 A cross-sectional structure diagram of the semiconductor device in along the AB direction.

[0056] Figure 17 A three-dimensional structure diagram corresponding to the step of forming a gate dielectric layer in the manufacturing method of a semiconductor device provided by an embodiment of the present application.

[0057] Figure 18 For Figure 17 A cross-sectional structure diagram of the semiconductor device in along the AB direction.

[0058] Figure 19 A three-dimensional structure diagram corresponding to the step of forming a gate in the manufacturing method of a semiconductor device provided by an embodiment of the present application.

[0059] Figure 20 For Figure 19 A cross-sectional structure diagram of the semiconductor device in along the AB direction.

[0060] Explanation of the reference numerals: 100 - substrate; 110 - isolation layer; 111 - opening; 112 - first isolation layer; 113 - second isolation layer; 120 - active region; 121 - source region; 122 - drain region; 123 - channel region; 130 - gate; 131 - lower gate; 131a - first trench; 132 - upper gate; 140 - gate dielectric layer; 141 - lower gate dielectric; 141a - second trench; 142 - upper gate dielectric. DETAILED DESCRIPTION

[0061] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0063] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0064] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, an element or feature described as "under other elements" or "beneath it" or "underneath it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "underneath" can include both upward and downward orientations. In addition, the device may also have additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0065] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0066] Figure 1 A three-dimensional structural schematic diagram of a semiconductor device provided for an embodiment of the present application, Figure 2 is Figure 1 a schematic cross-sectional structure diagram of the semiconductor device along the extension direction of the vertical channel region (i.e., the AB direction), Figure 3 is Figure 1 a schematic cross-sectional structure diagram of the semiconductor device along the extension direction of the channel region (i.e., the CD direction).

[0067] Referring to Figures 1 to 3 , the present application provides a semiconductor device, including a substrate 100, an isolation layer 110, an active region 120, a gate 130 and a gate dielectric layer 140; wherein, the isolation layer 110 is located on the substrate 100, and the isolation layer 110 is provided with two parallel openings 111; the active region 120 is located on the isolation layer 110, and the active region 120 includes a source region 121, a channel region 123 and a drain region 122 connected in sequence, wherein, the source region 121 and the drain region 122 are respectively disposed in one of the openings 111, and the channel region 123 is located above the isolation layer 110 and is arranged parallel to the surface of the substrate 100; the gate 130 is disposed around the channel region 123 along the extension direction of the channel region 123 (i.e., the X direction); the gate dielectric layer 140 is disposed between the gate 130 and the channel region 123.

[0068] As described above, by providing a gate surrounding the channel region in the present application, the contact area between the gate and the channel region is increased, which is beneficial to increasing the cross-sectional area of current transmission in the channel region, thereby improving the electric field control effect in the channel region; by providing an isolation layer between the gate and the substrate, the influence of the short-channel effect on the performance of the semiconductor device is reduced or avoided.

[0069] Referring to Figure 1 and Figure 3 , in one embodiment, the cross-sectional shape of the active region 120 along the direction perpendicular to the substrate 100 (i.e., the CD direction in Figure 1 ) is a U shape with an opening downward, so as to effectively reduce the area of the active region 120 while matching the topography of the gate 130, and thus effectively reduce the overall size of the semiconductor device.

[0070] Continuing to refer to Figure 1 and Figure 3 , in one embodiment, the isolation layer 110 includes a first isolation layer 112 and a second isolation layer 113. Among them, the first isolation layer 112 is located on the substrate 100 and is provided with an opening 111; the second isolation layer 113 covers the inner wall of the opening 111 and the surface of the first isolation layer 112 away from the substrate 100. Optionally, the material of the first isolation layer 112 includes silicon oxide, and the material of the second isolation layer 113 includes silicon nitride. In other embodiments of the present application, the isolation layer 110 may be a single-layer structure made of an insulating material, or a laminated structure composed of at least two different insulating materials, and the present application does not limit this.

[0071] It should be noted that by providing the isolation layer 110, the risk of short circuit between the gate 130 and the subsequently formed source and drain can be reduced or avoided, and the ion diffusion of the source and drain can be reduced or avoided from having a negative impact on the performance of the semiconductor device. That is, by separating the gate 130 and the substrate 100 through the isolation layer 110, the diffusion layer in the substrate 100 can be reduced or avoided, thereby reducing or avoiding the short-channel effect of the semiconductor device and improving the performance of the semiconductor device.

[0072] In one embodiment, the material of the gate 130 includes a metal material, and the metal material includes at least one of metal copper (Cu), metal aluminum (Al), and metal tungsten (Wu). In other embodiments of the present application, the metal material further includes other commonly used conductive metal materials and alloy materials containing the aforementioned metals.

[0073] It should be noted that by surrounding the gate 130 around the channel region 123, the contact area between the gate 130 and the communication 123 can be increased, the cross-sectional area of current transmission in the channel region 123 can be increased, so that the corresponding resistance is smaller and the current is higher. In one embodiment, the shape of the gate 130 is cylindrical.

[0074] In one embodiment, the material of the gate dielectric layer 140 includes a high-k material. Among them, the high-k material has a dielectric constant of about greater than 7. Optionally, the high-k material can be a hafnium (Hf-based) oxide material. For example, it can be a non-crystalline hafnium silicon oxynitride (HfSiON); a stacked structure formed by stacking nitrides and high-k materials can also be used as the high-k material layer. In other embodiments of the present application, the high-k material layer can include at least one of elements such as hafnium (Hf), silicon (Si), oxygen (O), or nitrogen (N), and can also include tantalum oxide, lanthanum oxide, aluminum oxide, nitrogen oxide, or other commonly used high-k materials, which are well-known common knowledge in the art and will not be elaborated herein.

[0075] It should be noted that when the gate 130 is a metal gate and the gate dielectric layer 140 is a high-k material layer, the gate capacitance can be increased by reducing the thickness of the gate dielectric layer 140 when the gate length is very small, thereby improving the control ability of the gate 130 over the channel and adjusting the threshold voltage at the same time.

[0076] Correspondingly, referring to Figure 4 , one embodiment of the present application also provides a method for manufacturing a semiconductor device, including:

[0077] Step S10: Provide a substrate, form an isolation layer on the substrate, and two parallel openings are formed in the isolation layer;

[0078] Step S20: Form an active region, a gate, and a gate dielectric layer on the isolation layer. Among them, the active region includes a source region, a channel region, and a drain region connected in sequence. The source region and the drain region are respectively formed in one of the openings. The channel region is formed above the isolation layer and is parallel to the surface of the substrate. The gate surrounds the channel region along the extension direction of the channel region, and the gate dielectric layer is formed between the gate and the channel region.

[0079] It can be seen that by using the above method for manufacturing a semiconductor device, the manufacturing process of the semiconductor device described above in the present application can be realized by combining and matching existing process steps without using special processes or complex processes, reducing the manufacturing difficulty and production cost of the semiconductor device.

[0080] Figures 5 to 20 These are schematic diagrams corresponding to different steps in the manufacturing method of the semiconductor device provided by this application. The following will describe in detail the manufacturing method of the semiconductor device provided by this application in conjunction with Figures 5 to 20 the following content.

[0081] First, refer to Figures 5 to 7 , perform step S10 to provide a substrate 100, form an isolation layer 110 on the substrate 100, and two parallel openings 111 are formed in the isolation layer 110. It should be noted that the formation of the isolation layer 110 can avoid the risk of short circuit between the subsequently formed gate and the subsequently formed source and drain, and at the same time reduce or avoid the ion diffusion of the source and drain.

[0082] In one embodiment, the process of forming the isolation layer 110 with the opening 111 on the substrate 100 includes: refer to Figure 5 , form a first isolation layer 112 on the substrate 100; refer to Figure 6 , etch the first isolation layer 112 to form the opening 111 in the first isolation layer 112; refer to Figure 7 , form a second isolation layer 113 on the first isolation layer 112, the second isolation layer 113 covers the inner wall of the opening 111, and the isolation layer 110 includes the first isolation layer 112 and the second isolation layer 113. Optionally, the isolation layer 110 can be formed by methods such as furnace tube, yellow light, and etching processes to prepare the required film layers.

[0083] In one embodiment, the material of the first isolation layer 112 includes silicon oxide, and the material of the second isolation layer 113 includes silicon nitride. In other embodiments of this application, the isolation layer 110 can be a single-layer structure made of an insulating material, or a laminated structure composed of at least two different insulating materials, and this application does not limit this.

[0084] Refer to Figure 8 , in one embodiment, the process of forming the active region, gate, and gate dielectric layer on the isolation layer includes:

[0085] Step S21: Form a source region and a drain region in the opening respectively, and the tops of the source region and the drain region are higher than the surface of the isolation layer;

[0086] Step S22: Form a lower gate on the isolation layer between two adjacent openings, a first trench is formed in the lower gate, and the extending direction of the first trench is parallel to the connecting line direction of two adjacent openings;

[0087] Step S23: Form a lower gate dielectric in the first trench. A second trench is formed in the lower gate dielectric, and the extending direction of the second trench is parallel to that of the first trench.

[0088] Step S24: Form a channel region in the second trench. The channel region connects the source region and the drain region to form the active region of the semiconductor device.

[0089] Step S25: Form an upper gate dielectric on the channel region. The upper gate dielectric is connected to the lower gate dielectric to form a gate dielectric layer surrounding the channel region.

[0090] Step S26: Form an upper gate electrode on the upper gate dielectric. The upper gate electrode is connected to the lower gate electrode to form a gate electrode surrounding the channel region.

[0091] First, refer to Figure 9 , perform Step S21 to form a source region 121 and a drain region 122 in the opening 111 respectively, and the tops of the source region 121 and the drain region 122 are higher than the surface of the isolation layer 110. In one embodiment, the source region 121 and the drain region 122 can be formed by two epitaxy processes (Epitaxy, EPI) respectively.

[0092] Next, refer to Figures 10 to 12 , perform Step S22 to form a lower gate electrode 131 on the isolation layer 110 between two adjacent openings 111. A first trench 131a is formed in the lower gate electrode 131, and the extending direction of the first trench 131a is parallel to the connecting line direction of two adjacent openings 111.

[0093] In one embodiment, the process of forming the lower gate electrode 131 on the isolation layer 110 between two adjacent openings 111 includes: refer to Figure 10 , form the lower gate electrode 131 on the isolation layer 110; perform a planarization process on the lower gate electrode 131 to make the surface of the lower gate electrode 131 flush with the surfaces of the source region 121 and the drain region 122; refer to Figure 11 and Figure 12 , remove a part of the lower gate electrode 131 so that the remaining lower gate electrode 131 is located between two openings 111, and form a first trench 131a in the lower gate electrode 131. Optionally, the lower gate electrode 131 is formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD). Optionally, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) is used for the planarization process. Optionally, processes such as yellow light and etching are used to form the first trench 131a in the lower gate electrode 131.

[0094] Subsequently, refer to Figure 13 and Figure 14 , perform step S23 to form a lower gate dielectric 141 in the first trench 131a. A second trench 141a is formed in the lower gate dielectric 141, and the extending direction of the second trench 141a is parallel to the extending direction of the first trench 131a.

[0095] In one embodiment, the process of forming the lower gate dielectric 141 in the first trench 131a includes: refer to Figure 13 and Figure 14 , form the lower gate dielectric 141 on the inner wall of the first trench 131a. The lower gate dielectric 141 at least extends and covers the lower gate 131, source region 121, and drain region 122 around the first trench 131a; etch the lower gate dielectric 141 so that the remaining lower gate dielectric 141 is located on the inner wall of the first trench 131a, and a second trench 141a is formed in the lower gate dielectric 141. Optionally, the lower gate dielectric 141 is etched through processes such as yellow light and etching.

[0096] In one embodiment, in the case of using the same photomask (not shown in the figure), the lower gate 131 and the lower gate dielectric 141 can be etched respectively by performing positive and negative development. Exemplarily, in the process of performing photolithography and etching on the lower gate 131 using a photomask, for the part of the lower gate 131 located in the first trench 131a, the positive photoresist covering its surface is removed during the development process, thereby forming the first trench 131a in the lower gate 131; while in the process of performing photolithography and etching on the lower gate dielectric 141 using a photomask, for the part of the lower gate dielectric 141 located in the first trench 131a, the negative photoresist covering its surface is not removed during the development process, so that the remaining lower gate dielectric 141 after etching is all located on the inner wall of the first trench 131a. This method can save a photomask, thereby saving production costs.

[0097] Subsequently, refer to Figure 15 and Figure 16 , perform step S24 to form a channel region 123 in the second trench 141a. The channel region 123 connects the source region 121 and the drain region 122 to form an active region 120 of the semiconductor device. It should be noted that the cross-section of the active region 120 along the vertical AB direction forms a U-shaped morphology with an opening downward (for example, refer to Figure 3 ), which can effectively save the planar area of the semiconductor device and help to further reduce the size of the semiconductor device.

[0098] Refer to Figure 17 and Figure 18, perform step S25 to form an upper gate dielectric 142 on the channel region 123. The upper gate dielectric 142 is connected to the lower gate dielectric 141 and forms a gate dielectric layer 140 surrounding the channel region 123.

[0099] In one embodiment, the material of the gate 130 includes a metal material, and the metal material includes at least one of metallic copper (Cu), metallic aluminum (Al), and metallic tungsten (W). In other embodiments of the present application, the metal material further includes other commonly used conductive metal materials and alloy materials containing the foregoing metals.

[0100] Refer to Figure 19 and Figure 20 , perform step S26 to form an upper gate 132 on the upper gate dielectric 142. The upper gate 132 is connected to the lower gate 131 and forms a gate 130 surrounding the channel region 123.

[0101] In one embodiment, the material of the gate dielectric layer 140 includes a high-k material. Among them, the high-k material has a dielectric constant of greater than about 7. Optionally, the high-k material can be a hafnium (Hf-based) oxide material. For example, it can be an amorphous hafnium silicon oxynitride (HfSiON); a stacked structure formed by a nitride and a high-k material can also be used as the high-k material layer. In other embodiments of the present application, the high-k material layer can include at least one of elements such as hafnium (Hf), silicon (Si), oxygen (O), or nitrogen (N), and can also include tantalum oxide, lanthanum oxide, aluminum oxide, nitrogen oxide, or other commonly used high-k materials, which are well-known common knowledge in the art and will not be elaborated herein.

[0102] An unexpected effect of the present application is that by setting a gate surrounding the channel region, the contact area between the gate and the channel region is increased, which is beneficial to increasing the cross-sectional area of current transmission in the channel region, thereby improving the electric field control effect in the channel region; by setting an isolation layer between the gate and the substrate, the influence of the short-channel effect on the performance of semiconductor devices is reduced or avoided.

[0103] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0104] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0105] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, forming an isolation layer on the substrate, and forming two openings parallel to each other in the isolation layer; An active region, a gate and a gate dielectric layer are formed on the isolation layer, wherein the active region is formed with a source region, a channel region and a drain region connected in sequence, the source region and the drain region are respectively formed in one of the openings, the channel region is formed above the isolation layer and is parallel to the surface of the substrate, the gate surrounds the channel region along the extension direction of the channel region, the gate is cylindrical in shape, and the channel region passes through the inside of the cylindrical gate, and the gate dielectric layer is formed between the gate and the channel region; The step of forming an active region, a gate and a gate dielectric layer on the isolation layer comprises: forming a source region and a drain region in the opening respectively, and the tops of the source region and the drain region are higher than the surface of the isolation layer; A lower gate is formed on the isolation layer between two adjacent openings, wherein a first trench is formed in the lower gate, and an extending direction of the first trench is parallel to a connecting direction of the two adjacent openings; forming a lower gate dielectric in the first trench, wherein a second trench is formed in the lower gate dielectric and an extension direction of the second trench is parallel to an extension direction of the first trench; forming a channel region in the second trench, wherein the channel region connects the source region and the drain region to form an active region of the semiconductor device; forming an upper gate dielectric layer on the channel region, wherein the upper gate dielectric layer is connected to the lower gate dielectric layer and forms a gate dielectric layer surrounding the channel region; An upper gate is formed on the upper gate dielectric, and the upper gate is connected to the lower gate to form a gate surrounding the channel region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a lower gate on the isolation layer between two adjacent openings comprises: forming a lower gate on the isolation layer; Performing a planarization process on the lower gate to make the surface of the lower gate flush with the surfaces of the source region and the drain region; A portion of the lower gate is removed so that the remaining lower gate is located between the two openings, and the first trench is formed in the lower gate.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a lower gate dielectric in the first trench comprises: forming the lower gate dielectric on the inner wall of the first trench, wherein the lower gate dielectric at least extends to and covers the lower gate, the source region and the drain region around the first trench; The lower gate dielectric is etched so that the remaining lower gate dielectric is located on the inner wall of the first trench and the second trench is formed in the lower gate dielectric.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The isolation layer includes a first isolation layer and a second isolation layer, and the step of forming the isolation layer on the substrate, wherein two parallel openings are formed in the isolation layer, includes: forming the first isolation layer on the substrate; Etching the first isolation layer to form the opening in the first isolation layer; The second isolation layer is formed on the first isolation layer, and the second isolation layer covers the inner wall of the opening.

5. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that: include: substrate; An isolation layer, located on the substrate, wherein the isolation layer is provided with two openings parallel to each other; an active region, located on the isolation layer, the active region comprising a source region, a channel region and a drain region connected in sequence, wherein the source region and the drain region are respectively arranged in one of the openings, and the channel region is located above the isolation layer and parallel to the surface of the substrate; A gate is disposed around the channel region along the extension direction of the channel region, the gate is cylindrical in shape, and the channel region passes through the inside of the cylindrical gate; The gate dielectric layer is arranged between the gate and the channel region.

6. The semiconductor device according to claim 5, characterized in that The cross-sectional shape of the active region along a direction perpendicular to the substrate is U-shaped with an opening facing downward.

7. The semiconductor device according to claim 5, characterized in that The isolation layer comprises: A first isolation layer, located on the substrate, wherein the first isolation layer is provided with the opening; The second isolation layer covers the inner wall of the opening and the surface of the first isolation layer away from the substrate.

8. The semiconductor device according to claim 7, characterized in that The material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes silicon nitride.

9. The semiconductor device according to claim 5, characterized in that The material of the gate electrode includes a metal material, and the metal material includes at least one of metal copper, metal aluminum, and metal tungsten; the material of the gate dielectric layer includes a high dielectric constant material.

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