Display substrate and display device

Abstract

The invention provides a display substrate. The display substrate comprises a substrate body; the driving circuit layer is located on the substrate, and the driving circuit layer comprises an active layer; the first electrode layer is positioned on one side, far away from the substrate, of the driving circuit layer; the display substrate comprises a plurality of scanning lines and a plurality of data lines, the scanning lines extend in the first direction and are arranged in the second direction, the data lines extend in the second direction and are arranged in the second direction, and the first direction intersects with the second direction; at least one of the scanning line and the data line comprises a transparent conductive section; the active layer comprises a transparent semiconductor material, the first electrode layer comprises a transparent conductive material, and the transparent conductive section is located on at least one of the active layer and the first electrode layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Transparent display technology is an emerging display technology that allows users to see the image on the display screen while also seeing the object behind the screen. This technology has a wide range of application potentials in many fields, including commercial displays, museum exhibitions, architecture and interior design, automotive interiors, advertising and display activities, as well as stage and performing arts performances. How to improve the transparency of transparent display panels is one of the topics that display product developers are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display substrate is provided, comprising:

[0005] substrate substrate;

[0006] A driving circuit layer, located on the base substrate, the driving circuit layer includes an active layer; and

[0007] A first electrode layer is located on a side of the driving circuit layer away from the base substrate;

[0008] Wherein, the display substrate comprises a plurality of scan lines and a plurality of data lines, the plurality of scan lines extend along a first direction and are arranged along a second direction, the plurality of data lines extend along the second direction and are arranged along the second direction, and the first direction intersects with the second direction;

[0009] At least one of the scan line and the data line includes a transparent conductive segment; and

[0010] The active layer includes a transparent semiconductor material, the first electrode layer includes a transparent conductive material, and the transparent conductive segment is located in at least one of the active layer and the first electrode layer.

[0011] According to some exemplary embodiments, the scan line comprises a first transparent conductive segment, and the first transparent conductive segment is located in the active layer; and / or,

[0012] The data line includes a second transparent conductive segment, and the second transparent conductive segment is located in the first electrode layer.

[0013] According to some exemplary embodiments, the scan line includes a plurality of the first transparent conductive segments and a plurality of the first metal segments, the plurality of the first transparent conductive segments and the plurality of the first metal segments are alternately arranged along the first direction and are electrically connected in sequence; and / or,

[0014] The data line includes a plurality of second transparent conductive segments and a plurality of second metal segments, and the plurality of second transparent conductive segments and the plurality of second metal segments are alternately arranged along the second direction and are electrically connected in sequence.

[0015] According to some exemplary embodiments, the first metal segment is located in the driving circuit layer, and / or the second metal segment is located in the driving circuit layer.

[0016] According to some exemplary embodiments, the driving circuit layer includes a light shielding layer located on the base substrate, a buffer layer located on a side of the light shielding layer away from the base substrate, an active layer located on a side of the buffer layer away from the base substrate, a gate insulating layer located on a side of the active layer away from the base substrate, a gate metal layer located on a side of the gate insulating layer away from the base substrate, an interlayer dielectric layer located on a side of the gate metal layer away from the base substrate, and a source-drain metal layer located on a side of the interlayer dielectric layer away from the base substrate;

[0017] The first metal segment is located in the light shielding layer, and / or the second metal segment is located in the source-drain metal layer.

[0018] According to some exemplary embodiments, the scan line further includes a connecting segment located in the source-drain metal layer, and adjacent first transparent conductive segments and first metal segments are electrically connected via the connecting segment.

[0019] According to some exemplary embodiments, the display substrate further comprises a passivation layer located on a side of the source / drain metal layer away from the base substrate and a planarization layer located between the passivation layer and the first electrode layer;

[0020] The passivation layer has a first via hole, the first via hole exposes a portion of the second metal segment, and two ends of the second transparent conductive segment are respectively overlapped with two adjacent second metal segments through at least two of the first via holes; and

[0021] The planarization layer has a first opening, and the orthographic projection of the second transparent conductive segment on the base substrate is located within the orthographic projection of the first opening on the base substrate.

[0022] According to some exemplary embodiments, an orthographic projection of the first metal segment on the base substrate partially overlaps with an orthographic projection of the second transparent conductive segment on the base substrate; and / or,

[0023] An orthographic projection of the first transparent conductive segment on the base substrate is spaced apart from an orthographic projection of the second metal segment on the base substrate.

[0024] According to some exemplary embodiments, an orthographic projection of the first metal segment on the substrate is spaced apart from an orthographic projection of the second metal segment on the substrate; and / or,

[0025] An orthographic projection of the first transparent conductive segment on the base substrate is spaced apart from an orthographic projection of the second transparent conductive segment on the base substrate.

[0026] According to some exemplary embodiments, the length of the first metal segment along the first direction is greater than or equal to the length of the first transparent conductive segment along the first direction; and / or,

[0027] The length of the second metal segment along the second direction is greater than or equal to the length of the second transparent conductive segment along the second direction

[0028] According to some exemplary embodiments, the display substrate includes a display area, and the display area includes a transparent area and a sub-pixel area;

[0029] In at least one first transparent conductive segment adjacent to the transparent region, the first transparent conductive segment includes a first main segment and a first auxiliary segment, the first main segment and the first auxiliary segment are located in the same layer, the first main segment is located between two adjacent first metal segments, the first auxiliary segment is connected to the first main segment along the second direction, and the first auxiliary segment is located in the transparent region; and / or,

[0030] In at least one second transparent conductive segment adjacent to the transparent region, the second transparent conductive segment includes a second main segment and a second auxiliary segment, the second main segment and the second auxiliary segment are located in the same layer, the second main segment is located between two adjacent second metal segments, the second auxiliary segment is connected to the second main segment along the first direction, and the second auxiliary segment is located in the transparent region.

[0031] According to some exemplary embodiments, the length of the first transparent conductive segment along the first direction is smaller than the size of the sub-pixel region along the first direction, and the length of the first metal segment along the first direction is smaller than the size of the sub-pixel region along the first direction; and / or

[0032] The length of the second transparent conductive segment along the second direction is smaller than the size of the sub-pixel region along the second direction, and the length of the second metal segment along the second direction is smaller than the size of the sub-pixel region along the second direction.

[0033] According to some exemplary embodiments, the active layer includes an active portion, the active portion includes a channel portion and conductive portions located on both sides of the channel portion, and a square resistance of the first transparent conductive segment is less than or equal to a square resistance of the conductive portion.

[0034] According to some exemplary embodiments, the first electrode layer includes a first electrode, and a square resistance of the second transparent conductive segment is less than or equal to a square resistance of the first electrode.

[0035] In another aspect, a display device is provided, comprising the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0037] Figure 1 A schematic plan view of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0038] Figure 2 Schematically shows Figure 1 Magnified view of the sub-region shown in .

[0039] Figure 3 A cross-sectional view of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0040] Figure 4 A plan view schematically illustrates scan lines and data lines of a display substrate according to some embodiments of the present disclosure.

[0041] Figure 5 A plan view schematically illustrates scan lines and data lines of a display substrate according to some embodiments of the present disclosure.

[0042] Figure 6A-6C The figure schematically shows a process diagram of preparing a display substrate according to some embodiments of the present disclosure.

[0043] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0045] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0046] When an element is described as "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on another element, directly connected to another element or directly coupled to another element, or there may be an intermediate element. However, when an element is described as "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection, communication connection and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0047] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, a first element may be named a second element, and similarly, a second element may be named a first element.

[0048] Figure 1 A schematic plan view of a display substrate according to some embodiments of the present disclosure is schematically shown. Figure 2 Schematically shows Figure 1 Magnified view of the sub-region shown in .

[0049] Combined with reference Figure 1 and Figure 2 The display substrate includes a display area AA, the display area AA includes a plurality of display sub-areas AA1, and the plurality of display sub-areas AA1 are arranged along a first direction X and a second direction Y. The display sub-area AA1 includes a pixel area PXA and a transparent area TA, the pixel area PXA is an area for emitting light to realize display, and no light-proof structure is provided in the transparent area TA. The portion of the display substrate located in the transparent area TA has a high light transmittance, so that a transparent display effect can be achieved.

[0050] Continue to refer to Figure 2 , the pixel area PXA includes a plurality of sub-pixel areas PXAx, for example, may include a first sub-pixel area PXA1, a second sub-pixel area PXA2, a third sub-pixel area PXA3 and a fourth sub-pixel area PXA4, the first sub-pixel area PXA1 and the second sub-pixel area PXA2 are arranged along the first direction X, the third sub-pixel area PXA3 and the fourth sub-pixel area PXA4 are arranged along the first direction X, the third sub-pixel area PXA3 is located on one side of the first sub-pixel area PXA1 along the second direction Y, and the fourth sub-pixel area PXA4 is located on one side of the second sub-pixel area PXA2 along the second direction Y. The transparent area TA may be located on one side of the pixel area PXA along the first direction X, and the pixel area PXA may include two transparent areas TA, one transparent area TA is located on a side of the first sub-pixel area PXA1 away from the second sub-pixel area PXA2, and the other transparent area TA is located on a side of the third sub-pixel area PXA3 away from the fourth sub-pixel area PXA4. That is, one pixel area PXA may include four sub-pixel areas PXA and two transparent areas TA.

[0051] For example, the first sub-pixel region PXA1 is a region emitting red light, the second sub-pixel region PXA2 is a region emitting green light, the third sub-pixel region PXA3 is a region emitting blue light, and the fourth sub-pixel region PXA4 is a region emitting white light.

[0052] It should be noted that Figure 2 Only a planar structure of the display sub-area AA1 is schematically shown. According to actual display requirements, the shape and arrangement of the pixel area PXA and the transparent area TA, as well as the shape and arrangement of the sub-pixels in the pixel area PXA can be adjusted within the display sub-area AA1, and the embodiments of the present disclosure are not limited to this.

[0053] Figure 3 A cross-sectional view of a display substrate according to some embodiments of the present disclosure is schematically shown, wherein: Figure 3 The schematic diagram shows the display substrate along Figure 2 A cross-sectional view taken along line AA'.

[0054] Reference Figure 3 The display substrate includes a base substrate 100, a driving circuit layer 200 located on the base substrate 100, and a light emitting device layer 300 located on a side of the driving circuit layer 200 away from the base substrate 100. The driving circuit layer 200 includes a plurality of pixel driving circuits, the light emitting device layer 300 includes a plurality of light emitting devices, the plurality of light emitting devices are electrically connected to the plurality of pixel driving circuits, and the plurality of light emitting devices and the plurality of pixel driving circuits are located in a plurality of sub-pixel regions, respectively.

[0055] The driving circuit layer 200 may include a light shielding layer LS located on the base substrate 100, a buffer layer BUF located on the side of the light shielding layer LS away from the base substrate 100, an active layer ACT located on the side of the buffer layer BUF away from the base substrate 100, a gate insulating layer GI located on the side of the active layer ACT away from the base substrate 100, a gate metal layer Gate located on the side of the gate insulating layer GI away from the base substrate 100, an interlayer dielectric layer ILD located on the side of the gate metal layer Gate away from the base substrate 100, and a source-drain metal layer SD located on the side of the interlayer dielectric layer ILD away from the base substrate 100. The light shielding layer LS includes a light shielding portion 210, the active layer ACT includes an active portion 220, the active portion 220 includes a channel portion 221 and a conductive portion 222 connected to both sides of the channel portion 221, and the orthographic projection of the channel portion 221 on the base substrate 100 is located within the orthographic projection of the light shielding portion 210 on the base substrate 100. The gate metal layer Gate includes a gate 230, and the orthographic projection of the gate 230 on the substrate 100 substantially coincides with the orthographic projection of the channel portion 221 on the substrate 100. The source-drain metal layer SD includes a source electrode 241 and a drain electrode 242 that are spaced apart, and the source electrode 241 and the drain electrode 242 are respectively overlapped with the two conductive portions 222 of the active portion 220 through vias located in the interlayer dielectric layer ILD.

[0056] The light emitting device layer 300 includes a first electrode layer 310 located on the side of the driving circuit layer 200 away from the substrate 100, a pixel defining layer PDL located on the side of the first electrode layer 310 away from the substrate 100, a light emitting layer 320 located on the side of the pixel defining layer PDL away from the substrate 100, and a second electrode layer 330 located on the side of the light emitting layer 320 away from the substrate 100. The pixel defining layer PDL has a plurality of second openings KK2, and the light emitting layer 320 contacts the first electrode layer 310 through the plurality of second openings KK2. A passivation layer PVX and a planarization layer PLN located between the passivation layer PVX and the first electrode layer 310 may also be provided between the first electrode layer 310 and the source-drain metal layer SD. The first electrode layer 310 includes a plurality of first electrodes 311, and the first electrodes 311 may be electrically connected to the driving circuit layer 200 through vias located in the planarization layer PLN and the passivation layer PVX.

[0057] Figure 4 The plan view of the scan lines and data lines of the display substrate according to some embodiments of the present disclosure is schematically shown, wherein: Figure 4 A plan view schematically shows data lines and scan lines located around a transparent area.

[0058] Combined with reference Figure 3 and Figure 4 The display substrate includes a plurality of scan lines L1 and a plurality of data lines L2. The scan lines L1 are used to connect scan signals to the pixel driving circuit, and the data lines L2 are used to connect data signals to the pixel driving circuit. The plurality of scan lines L1 extend along a first direction X and are arranged along a second direction Y. The plurality of data lines L2 extend along the second direction Y and are arranged along the first direction X. The first direction X intersects with the second direction Y. At least one of the scan lines L1 and the data lines L2 includes a transparent conductive segment Lx. The active layer ACT includes a transparent semiconductor material. The first electrode layer 310 includes a transparent conductive material. The transparent conductive segment Lx is located in at least one of the active layer ACT and the first electrode layer 310.

[0059] In the display substrate provided by the embodiment of the present disclosure, at least a portion of the data line L2 or the scan line L1 is made transparent, which can effectively improve the transparency of the display substrate and further improve the transparent display effect. At the same time, the transparent conductive segment Lx is located in at least one layer of the active layer ACT and the first electrode layer 310, that is, the transparent conductive segment Lx is formed at the same time as the active layer ACT and the first electrode layer 310 are formed, without the need to add additional manufacturing steps for the display substrate.

[0060] It should be noted that Figure 4 The fill pattern of the middle part structure is Figure 3 The hatch patterns for the same structure in the Figure 4The structure of the scan line L1 and the data line L2 is more clearly illustrated in FIG. Figure 4 and Figure 3 The structures denoted by the same reference numerals are the same structures.

[0061] According to some exemplary embodiments, referring to Figure 3 The material of the active layer ACT may include indium gallium zinc oxide, and the material of the first electrode layer 310 may include indium tin oxide.

[0062] It should be noted that the boundary between the sub-pixel area PXA and the transparent area TA is defined by a plurality of scanning lines L1 and a plurality of data lines L2 arranged in a crisscross pattern. Figure 4 The transparent area TA can be defined by two data lines L2 and two scanning lines L1.

[0063] According to some exemplary embodiments, in combination with reference Figure 3 and Figure 4 , the scan line L1 includes a first transparent conductive segment L11 , and the first transparent conductive segment L11 is located in the active layer ACT.

[0064] According to some exemplary embodiments, in combination with reference Figure 3 and Figure 4 The data line L2 includes a second transparent conductive segment L21, which is located in the first electrode layer 310. The second transparent conductive segment L21 for transmitting data signals and the first transparent conductive segment L11 for transmitting scan signals are located in different layers, which can effectively avoid the problem of mutual interference between data signals and scan signals.

[0065] According to some exemplary embodiments, referring to Figure 4 The scanning line L1 includes a plurality of first transparent conductive segments L11 and a plurality of first metal segments L12, and the plurality of first transparent conductive segments L11 and the plurality of first metal segments L12 are alternately arranged along the first direction X and are electrically connected in sequence. That is to say, the scanning line L1 is formed by alternately connecting the light-transmitting first transparent conductive segments L11 and the first metal segments L12 with low resistance, which can ensure that the scanning line L1 has a low wiring resistance on the basis of improving the transparent display effect.

[0066] According to some exemplary embodiments, referring to Figure 4 The data line L2 includes a plurality of second transparent conductive segments L21 and a plurality of second metal segments L22. The plurality of second transparent conductive segments L21 and the plurality of second metal segments L22 are alternately arranged along the second direction Y and are electrically connected in sequence. That is to say, the data line L2 is formed by alternately connecting the light-transmitting second transparent conductive segments L21 and the second metal segments L21 with low resistance. On the basis of improving the transparent display effect, the data line L2 can be guaranteed to have a lower routing resistance.

[0067] According to some exemplary embodiments, referring to Figure 3 , the first metal segment L12 and the second metal segment L22 may both be located in the driving circuit layer 200 .

[0068] According to some exemplary embodiments, referring to Figure 3 The first metal segment L12 and the second metal segment L22 are located in different layers, which can effectively avoid the problem of mutual interference between the data signal and the scan signal.

[0069] According to some exemplary embodiments, referring to Figure 3 The film layers having metal materials in the driving circuit layer 200 include a light-shielding layer LS, a gate metal layer Gate and a source-drain metal layer SD. Therefore, the first metal segment L12 can be located at any one of the light-shielding layer LS, the gate metal layer Gate and the source-drain metal layer SD, and the second metal segment L22 can be located at any one of the remaining two layers.

[0070] For example, the first metal segment L12 is located in the light shielding layer LS, and the second metal segment L22 is located in the gate metal layer Gate. For another example, the first metal segment L12 is located in the gate metal layer Gate, and the second metal segment L22 is located in the source and drain metal layer SD. For another example, the first metal segment L12 is located in the light shielding layer LS, and the second metal segment L22 is located in the source and drain metal layer SD.

[0071] The inventors have found that when the first metal segment L12 is located in the light shielding layer LS and the second metal segment L22 is located in the source / drain metal layer SD (ie Figure 3 In the illustrated case, there are at least two insulating layers, namely a buffer layer BUF and an interlayer dielectric layer ILD, between the first metal segment L12 and the second metal segment L22, so that the problem of mutual interference between the data signal and the scan signal can be more effectively avoided.

[0072] According to some exemplary embodiments, in combination with reference Figure 3 and Figure 4, the scanning line L1 also includes a connecting segment L13 located in the source-drain metal layer SD, and the adjacent first transparent conductive segment L11 and the first metal segment L12 are electrically connected through the connecting segment L13. The interlayer dielectric layer ILD has a second via hole V02, and the interlayer dielectric layer ILD and the buffer layer BUF have a third via hole V03. The second via hole V02 exposes a portion of the first transparent conductive segment L11, and the third via hole V03 exposes a portion of the first metal segment L12. The two ends of the connecting segment L13 are electrically connected to the first transparent conductive segment L11 and the first metal segment L12 through the second via hole V02 and the third via hole V03, respectively, so as to realize the electrical connection between the first transparent conductive segment L11 and the first metal segment L12. Through such a connection method, the second via hole V02 and the third via hole V03 are both formed in the patterning process of the interlayer dielectric layer ILD, and the buffer layer BUF does not need to use a mask plate for patterning, which is conducive to simplifying the preparation process of the display substrate.

[0073] According to some exemplary embodiments, referring to Figure 3 , the gate 230 is located in the gate metal layer Gate, the scan line L1 is located in the light shielding layer LS and the active layer ACT, the gate 230 is not directly connected to the scan line L1, and the scan line L1 and the gate 230 can be electrically connected through a connection structure located in the source-drain metal layer SD. For example, one end of the connection structure is electrically connected to the gate 230 through a via located in the interlayer dielectric layer ILD, and the other end is electrically connected to the first transparent conductive segment L11 through a via located in the interlayer dielectric layer ILD. For another example, one end of the connection structure is electrically connected to the gate 230 through a via located in the interlayer dielectric layer ILD, and the other end is electrically connected to the first metal segment L12 through a via located in the interlayer dielectric layer ILD and the buffer layer BUF.

[0074] According to some exemplary embodiments, referring to Figure 3The passivation layer PVX has a first via hole V01, the first via hole V01 exposes a portion of the second metal segment L22, and the two ends of the second transparent conductive segment L21 are respectively overlapped with two adjacent second metal segments L22 through at least two first via holes V01. The planarization layer PLN has a first opening KK1, and the orthographic projection of the second transparent conductive segment L21 on the base substrate 100 is located within the orthographic projection of the first opening KK1 on the base substrate 100. By setting a larger first opening KK1 in the planarization layer PLN, the second transparent conductive segment L21 can be completely placed in the first opening KK1, and the first via hole V01 for connecting the second transparent conductive segment L21 and the second metal segment L22 is only located in the passivation layer PVX. The depth of the first via hole V01 is shallow, so that the second transparent conductive segment L21 and the second metal segment L22 can be better connected, thereby improving the connection reliability between the second transparent conductive segment L21 and the second metal segment L22 and reducing the contact resistance between the second transparent conductive segment L21 and the second metal segment L22.

[0075] According to some exemplary embodiments, referring to Figure 4 , the orthographic projection of the first metal segment L12 on the base substrate 100 partially overlaps with the orthographic projection of the second transparent conductive segment L21 on the base substrate 100. Since the scanning line L1 extending along the first direction X and the data line L2 extending along the second direction Y will inevitably overlap, there is a risk of signal interference at the overlapping point. By overlapping the first metal segment L12 in the scanning line L1 and the second transparent conductive segment L21 in the data line L2, at least three insulating layers of a buffer layer BUF, an interlayer dielectric layer ILD and a passivation layer PVX are provided between the first metal segment L12 and the second transparent conductive segment L21, and the total thickness of the insulating layer between the first metal segment L12 and the second transparent conductive segment L21 is relatively thick, so that the problem of mutual interference between the data signal and the scanning signal can be more effectively avoided.

[0076] According to some exemplary embodiments, referring to Figure 4 The orthographic projection of the first transparent conductive segment L11 on the base substrate 100 is spaced from the orthographic projection of the second metal segment L22 on the base substrate 100. On the basis that the orthographic projection of the first metal segment L12 on the base substrate 100 overlaps with the orthographic projection of the second transparent conductive segment L21 on the base substrate 100, the first transparent conductive segment L11 and the second metal segment L22 are arranged to be spaced from each other in projection, thereby further reducing the mutual interference between the data signal and the scan signal.

[0077] According to some exemplary embodiments, referring to Figure 4The orthographic projection of the first metal segment L12 on the base substrate 100 is spaced apart from the orthographic projection of the second metal segment L22 on the base substrate 100. On the basis that the orthographic projection of the first metal segment L12 on the base substrate 100 overlaps with the orthographic projection of the second transparent conductive segment L21 on the base substrate 100, the first metal segment L12 and the second metal segment L22 are arranged to be spaced apart from each other in projection, thereby further reducing mutual interference between the data signal and the scan signal.

[0078] According to some exemplary embodiments, referring to Figure 4 , the orthographic projection of the first transparent conductive segment L11 on the base substrate 100 is spaced from the orthographic projection of the second transparent conductive segment L21 on the base substrate 100, and on the basis that the orthographic projection of the first metal segment L12 on the base substrate 100 overlaps with the orthographic projection of the second transparent conductive segment L21 on the base substrate 100, the first transparent conductive segment L11 and the second transparent conductive segment L21 are arranged to be spaced from each other in projection, thereby further reducing the mutual interference between the data signal and the scan signal.

[0079] According to some exemplary embodiments, referring to Figure 4 , the length of the first metal segment L12 along the first direction X is greater than or equal to the length of the first transparent conductive segment L11 along the first direction X, that is, in the scan line L1, more parts are composed of the first metal segment L12, so that the scan line L1 can be ensured to have a lower wiring resistance. For example, the ratio of the length of the first metal segment L12 along the first direction X to the length of the first transparent conductive segment L11 along the first direction X is greater than or equal to 5.

[0080] According to some exemplary embodiments, the length of the second metal segment L22 along the second direction Y is greater than or equal to the length of the second transparent conductive segment L21 along the second direction Y, that is, in the data line L2, more parts are formed by the second metal segment L22, so that the data line L2 can be ensured to have a lower routing resistance. For example, the ratio of the length of the second metal segment L22 along the second direction Y to the length of the second transparent conductive segment L21 along the second direction Y is greater than or equal to 5.

[0081] According to some exemplary embodiments, referring to Figure 4 In the scanning line L1, the width of the first metal segment L12 along the second direction Y is substantially equal to the width of the first transparent conductive segment L11 along the second direction Y. The scanning line L1 can be set as an equal-width line with substantially uniform width at all locations.

[0082] According to some exemplary embodiments, referring to Figure 4 In the scan line L1, the width of the connecting segment L13 along the second direction Y is substantially equal to the width of the first metal segment L12 along the second direction Y.

[0083] According to some exemplary embodiments, referring to Figure 4 In the data line L2, the width of the second metal segment L22 along the first direction X is substantially equal to the width of the second transparent conductive segment L21 along the first direction X, and the data line L2 can be set to be an equal-width line with substantially uniform width at all locations.

[0084] Figure 5 A plan view schematically illustrates scan lines and data lines of a display substrate according to some embodiments of the present disclosure.

[0085] According to some exemplary embodiments, in combination with reference Figure 2 and Figure 5 , at least a portion of the first transparent conductive segments L11 in the scan line L1 is arranged adjacent to the transparent area TA, in at least one first transparent conductive segment L11 adjacent to the transparent area TA, the first transparent conductive segment L11 includes a first main segment L111 and a first auxiliary segment L112, the first main segment L111 and the first auxiliary segment L112 are both located in the active layer ACT, the first main segment L111 is located between two adjacent first metal segments L12, the first auxiliary segment L112 and the first main segment L111 are connected to form an integral structure along the second direction Y, and the first auxiliary segment L112 is located in the transparent area TA. According to this arrangement, the width of the scan line L1 at the position adjacent to the transparent area TA is increased, which can reduce the routing resistance of the scan line L1 to a certain extent. At the same time, the first auxiliary segment L112 is located in the active layer ACT, and the first auxiliary segment L112 is arranged in the transparent area TA. It will not affect the transparency of the display substrate. In addition, since the first auxiliary segment L112 is located outside the pixel area PXA, it will not occupy the arrangement space of the related structures in the pixel area PXA.

[0086] It should be noted that the first main segment L111 and the first auxiliary segment L112 are connected as an integral structure, the portion having the same width as the adjacent first metal segment L12 is regarded as the first main segment L111, and the portion protruding in the second direction Y compared to the adjacent first metal segment L12 is regarded as the first auxiliary segment L112. When the scan line L1 includes the first auxiliary segment L112, the boundary of the transparent area TA should be understood as being defined by the portion of the scan line L1 other than the first auxiliary segment L112 (i.e., including the first main segment L111, the first metal segment L12, and the connecting segment L13) and the data line L2.

[0087] According to some exemplary embodiments, referring to Figure 5 In at least one first transparent conductive segment L11, the size of the first main segment L111 along the first direction X is equal to the size of the first auxiliary segment L112 along the first direction X. Optionally, the size of the first auxiliary segment L112 along the first direction X may be greater than the size of the first main segment L111 along the first direction X.

[0088] According to some exemplary embodiments, in combination with reference Figure 2 and Figure 5 , at least a portion of the second transparent conductive segments L21 in the data line L2 can be arranged adjacent to the transparent area TA, in at least one second transparent conductive segment L21 adjacent to the transparent area TA, the second transparent conductive segment L21 includes a second main segment L211 and a second auxiliary segment L212, the second main segment L211 and the second auxiliary segment L212 are both located in the first electrode layer 310, the second main segment L211 is located between two adjacent second metal segments L22, the second auxiliary segment L212 and the second main segment L211 are connected to form an integral structure along the first direction X, and the second auxiliary segment L212 is located in the transparent area TA. According to this arrangement, the width of the data line L2 at the position adjacent to the transparent area TA is increased, which can reduce the routing resistance of the data line L2 to a certain extent. At the same time, the second auxiliary segment L212 is located in the first electrode layer 310, and the second auxiliary segment L212 is arranged in the transparent area TA. It will not affect the transparency of the display substrate. In addition, since the second auxiliary segment L212 is located outside the pixel area PXA, it will not occupy the arrangement space of the relevant structure in the pixel area PXA.

[0089] It should be noted that the second main segment L211 and the second auxiliary segment L212 are connected as an integral structure, the portion having the same width as the adjacent second metal segment L22 is regarded as the second main segment L211, and the portion protruding in the first direction X compared with the adjacent second metal segment L22 is regarded as the second auxiliary segment L212. When the scan line L1 includes the second auxiliary segment L212, the boundary of the transparent area TA should be understood to be defined by the portion of the data line L2 other than the second auxiliary segment L212 (i.e., including the second main segment L211 and the first metal segment L12) and the scan line L1.

[0090] According to some exemplary embodiments, referring to Figure 5 The orthographic projection of the first auxiliary segment L112 on the base substrate is spaced from the orthographic projection of the second auxiliary segment L212 on the base substrate, thereby effectively avoiding the problem of mutual interference between the scanning signal transmitted in the first auxiliary segment L112 and the data signal transmitted in the second auxiliary segment L212.

[0091] According to some exemplary embodiments, referring to Figure 5 In at least one second transparent conductive segment L21, the size of the second main segment L211 along the second direction Y is equal to the size of the second auxiliary segment L212 along the second direction Y. Optionally, the size of the second auxiliary segment L212 along the second direction Y may be greater than the size of the second main segment L211 along the second direction Y.

[0092] According to some exemplary embodiments, in combination with reference Figure 2 and Figure 4, the length of the first transparent conductive segment L11 along the first direction X is smaller than the size of the sub-pixel area PXAx along the first direction X, and the length of the first metal segment L12 along the first direction X is smaller than the size of the sub-pixel area PXAx along the first direction X, so that around a sub-pixel area PXAx, there will be alternating first transparent conductive segments L11 and first metal segments L12, avoiding the problem of poor display uniformity caused by the presence of only transparent first transparent conductive segments L11 around some sub-pixel areas PXAx and only opaque first metal segments L12 around other sub-pixel areas PXAx.

[0093] According to some exemplary embodiments, in combination with reference Figure 2 and Figure 4 , the length of the second transparent conductive segment L21 along the second direction Y is less than or equal to the size of the sub-pixel area PXAx along the second direction Y, and the length of the second metal segment L22 along the second direction Y is less than or equal to the size of the sub-pixel area PXAx along the second direction Y, so that around a sub-pixel area PXAx, there will be alternating second transparent conductive segments L21 and second metal segments L22, avoiding the problem of poor display uniformity caused by the presence of only transparent second transparent conductive segments L21 around some sub-pixel areas PXAx and only opaque second metal segments L22 around other sub-pixel areas PXAx.

[0094] According to some exemplary embodiments, referring to Figure 3 The active layer ACT includes an active portion 220, the active portion 220 includes a channel portion 221 and a conductive portion 222 located on both sides of the channel portion 221, and the square resistance of the first transparent conductive segment L11 is less than or equal to the square resistance of the conductive portion 222. That is, in the process of forming the active layer ACT, the square resistance of the first transparent conductive segment L11 can be reduced by increasing the conductive time of the first transparent conductive segment L11, thereby further reducing the resistance of the scanning line L1. In addition, the conductive time of the conductive portion 222 remains unchanged, thereby avoiding the problem of the device performance of the transistor being offset.

[0095] According to some exemplary embodiments, referring to Figure 3 , the first electrode layer 310 includes the first electrode 311, and the square resistance of the second transparent conductive segment L21 is less than or equal to the square resistance of the first electrode 311. That is, in the process of forming the first electrode layer 310, the second transparent conductive segment L21 can be additionally subjected to conductor processing, thereby reducing the square resistance of the second transparent conductive segment L21. In addition, the first electrode 311 does not need to be subjected to conductor processing to avoid affecting the performance of the light-emitting device.

[0096] Figure 6A-6C The figure schematically shows a process diagram of preparing a display substrate according to some embodiments of the present disclosure.

[0097] At least some embodiments of the present disclosure also provide a method for preparing a display substrate, as follows: Figure 6A-6C The preparation method will be described.

[0098] Reference Fig. 6A , a driving circuit layer 200 is formed on the base substrate 100, and the formation of the driving circuit layer 200 may include forming a light shielding layer LS on the base substrate 100, forming a buffer layer BUF on a side of the light shielding layer LS away from the base substrate 100, forming an active layer ACT on a side of the buffer layer BUF away from the base substrate 100, forming a gate insulating layer GI on a side of the active layer ACT away from the base substrate 100, forming a gate metal layer Gate on a side of the gate insulating layer GI away from the base substrate 100, forming an interlayer dielectric layer ILD on a side of the gate metal layer Gate away from the base substrate 100, and forming a source-drain metal layer SD on a side of the interlayer dielectric layer ILD away from the base substrate 100.

[0099] Forming the light shielding layer LS includes forming light shielding portions 210 and first metal segments L12 that are spaced apart from each other. The material of the light shielding layer LS may include copper. The thickness of the light shielding layer LS may be greater than or equal to 5500 angstroms.

[0100] Forming the active layer ACT may include forming an active portion 220 and a first transparent conductive segment L11 that are spaced apart. The active portion 220 includes a channel portion 221 and a conductive portion 222 connected to both sides of the channel portion 221. In the process of forming the active layer ACT, it is necessary to perform conductive processing on the conductive portion 222 and the first transparent conductive segment L11 while shielding the channel portion 221. For example, a dry etching process may be used to reduce the oxygen content in the conductive portion 222 and the first transparent conductive segment L11 through plasma bombardment to increase their conductivity. At the same time, the square resistance of the first transparent conductive segment L11 can be further reduced by additionally extending the conductive time of the first transparent conductive segment L11.

[0101] Forming the gate metal layer Gate includes forming a gate 230 , and an orthographic projection of the gate 230 on the base substrate 100 substantially coincides with an orthographic projection of the channel portion 221 on the base substrate 100 .

[0102] Forming the source-drain metal layer SD includes forming a source electrode 241, a drain electrode 242, a second metal segment L22 and a connecting segment L13 that are spaced apart. The source electrode 241 and the drain electrode 242 are respectively overlapped with the two conductive portions 222 of the active portion 220 through vias located in the interlayer dielectric layer ILD. The two ends of the connecting segment L13 are respectively electrically connected to the first transparent conductive segment L11 and the first metal segment L12 through the second via V02 and the third via V03. The multiple first transparent conductive segments L11, the multiple first metal segments L12 and the multiple connecting segments L13 that are electrically connected in sequence constitute a scanning line L1 for transmitting a scanning signal.

[0103] For example, the material of the source-drain metal layer SD may include copper, and the thickness of the source-drain metal layer SD may be greater than or equal to 5500 angstroms.

[0104] Reference Figure 6B A passivation layer PVX is formed on the side of the driving circuit layer 200 away from the base substrate 100, a planarization layer PLN is formed on the side of the passivation layer PVX away from the base substrate 100, and a first electrode layer 310 is formed on the side of the planarization layer PLN away from the base substrate 100. The first electrode layer 310 includes a first electrode 311 and a second transparent conductive segment L21 which are arranged at intervals. The first electrode 311 is electrically connected to the drain 242 through via holes located in the planarization layer PLN and the passivation layer PVX. The second transparent conductive segment L21 is located in the first opening KK1 of the planarization layer PLN. Two ends of the second transparent conductive segment L21 are respectively overlapped with two adjacent second metal segments L22 through at least two first via holes V01 in the passivation layer PVX. Multiple second transparent conductive segments L21 and multiple second metal segments L22 which are electrically connected in sequence constitute a data line L2 for transmitting data signals.

[0105] For example, in the process of forming the first electrode layer 310, the second transparent conductive segment L21 is subjected to conductor processing while the first electrode 311 is shielded, so that the conductivity of the second transparent conductive segment L21 can be further improved. Exemplarily, the second transparent conductive segment L21 can be further conductorized by bombarding the second transparent conductive segment L21 with plasma through a dry etching process. In addition, since the first electrode 311 is shielded during the conductor processing of the second transparent conductive segment L21, the first electrode 311 is not subjected to additional conductor processing to ensure the relevant performance of the light-emitting device.

[0106] Reference Figure 6CA pixel defining layer PDL is formed on a side of the first metal layer away from the base substrate 100, a light emitting layer 320 is formed on a side of the pixel defining layer PDL away from the base substrate 100, and a second electrode layer 330 is formed on a side of the light emitting layer 320 away from the base substrate 100. The pixel defining layer PDL has a second opening KK2, and the light emitting layer 320 contacts the first electrode 311 through the second opening KK2.

[0107] At least some embodiments of the present disclosure also provide a display device, which includes a display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, a window with an integrated display function, a billboard, and a building curtain wall, etc.

[0108] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate, and these features and advantages can be referred to the above description of the display substrate, which will not be repeated here.

[0109] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0110] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate substrate; A driving circuit layer, located on the base substrate, wherein the driving circuit layer includes an active layer; and A first electrode layer, located on a side of the driving circuit layer away from the base substrate; Wherein, the display substrate comprises a plurality of scan lines and a plurality of data lines, the plurality of scan lines extend along a first direction and are arranged along a second direction, the plurality of data lines extend along the second direction and are arranged along the second direction, and the first direction intersects with the second direction; At least one of the scan line and the data line includes a transparent conductive segment; and The active layer includes a transparent semiconductor material, the first electrode layer includes a transparent conductive material, and the transparent conductive segment is located in at least one of the active layer and the first electrode layer.

2. The display substrate according to claim 1, wherein: The scanning line comprises a first transparent conductive segment, and the first transparent conductive segment is located in the active layer; and / or, The data line includes a second transparent conductive segment, and the second transparent conductive segment is located in the first electrode layer.

3. The display substrate according to claim 2, wherein: The scanning line includes a plurality of the first transparent conductive segments and a plurality of first metal segments, the plurality of first transparent conductive segments and the plurality of first metal segments are alternately arranged along the first direction and are electrically connected in sequence; and / or, The data line includes a plurality of second transparent conductive segments and a plurality of second metal segments, and the plurality of second transparent conductive segments and the plurality of second metal segments are alternately arranged along the second direction and are electrically connected in sequence.

4. The display substrate according to claim 3, wherein: The first metal segment is located in the driving circuit layer, and / or the second metal segment is located in the driving circuit layer.

5. The display substrate according to claim 4, wherein: The driving circuit layer includes a light shielding layer located on the substrate, a buffer layer located on a side of the light shielding layer away from the substrate, an active layer located on a side of the buffer layer away from the substrate, a gate insulating layer located on a side of the active layer away from the substrate, a gate metal layer located on a side of the gate insulating layer away from the substrate, an interlayer dielectric layer located on a side of the gate metal layer away from the substrate, and a source-drain metal layer located on a side of the interlayer dielectric layer away from the substrate; The first metal segment is located in the light shielding layer, and / or the second metal segment is located in the source-drain metal layer.

6. The display substrate according to claim 5, wherein: The scan line further includes a connecting segment located in the source-drain metal layer, and the adjacent first transparent conductive segment and the first metal segment are electrically connected via the connecting segment.

7. The display substrate according to claim 5 or 6, wherein: The display substrate further comprises a passivation layer located on a side of the source / drain metal layer away from the base substrate and a planarization layer located between the passivation layer and the first electrode layer; The passivation layer has a first via hole, the first via hole exposes a portion of the second metal segment, and two ends of the second transparent conductive segment are respectively overlapped with two adjacent second metal segments through at least two of the first via holes; as well as The planarization layer has a first opening, and the orthographic projection of the second transparent conductive segment on the base substrate is located within the orthographic projection of the first opening on the base substrate.

8. The display substrate according to any one of claims 5 to 7, wherein: The orthographic projection of the first metal segment on the base substrate partially overlaps with the orthographic projection of the second transparent conductive segment on the base substrate; and / or, An orthographic projection of the first transparent conductive segment on the base substrate is spaced apart from an orthographic projection of the second metal segment on the base substrate.

9. The display substrate according to claim 8, wherein: The orthographic projection of the first metal segment on the substrate is spaced apart from the orthographic projection of the second metal segment on the substrate; and / or, An orthographic projection of the first transparent conductive segment on the base substrate is spaced apart from an orthographic projection of the second transparent conductive segment on the base substrate.

10. The display substrate according to any one of claims 3 to 9, wherein: The length of the first metal segment along the first direction is greater than or equal to the length of the first transparent conductive segment along the first direction; and / or, A length of the second metal segment along the second direction is greater than or equal to a length of the second transparent conductive segment along the second direction.

11. The display substrate according to any one of claims 3 to 10, wherein: The display substrate comprises a display area, and the display area comprises a transparent area and a sub-pixel area; In at least one first transparent conductive segment adjacent to the transparent region, the first transparent conductive segment includes a first main segment and a first auxiliary segment, the first main segment and the first auxiliary segment are located in the same layer, the first main segment is located between two adjacent first metal segments, the first auxiliary segment is connected to the first main segment along the second direction, and the first auxiliary segment is located in the transparent region; and / or, In at least one second transparent conductive segment adjacent to the transparent region, the second transparent conductive segment includes a second main segment and a second auxiliary segment, the second main segment and the second auxiliary segment are located in the same layer, the second main segment is located between two adjacent second metal segments, the second auxiliary segment is connected to the second main segment along the first direction, and the second auxiliary segment is located in the transparent region.

12. The display substrate according to claim 11, wherein: The length of the first transparent conductive segment along the first direction is smaller than the size of the sub-pixel region along the first direction, and the length of the first metal segment along the first direction is smaller than the size of the sub-pixel region along the first direction; and / or The length of the second transparent conductive segment along the second direction is smaller than the size of the sub-pixel region along the second direction, and the length of the second metal segment along the second direction is smaller than the size of the sub-pixel region along the second direction.

13. The display substrate according to any one of claims 2 to 12, wherein: The active layer includes an active portion, and the active portion includes a channel portion and conductive portions located at two sides of the channel portion. The sheet resistance of the first transparent conductive segment is less than or equal to the sheet resistance of the conductive portion.

14. The display substrate according to any one of claims 2 to 13, wherein: The first electrode layer includes a first electrode, and the square resistance of the second transparent conductive segment is less than or equal to the square resistance of the first electrode.

15. A display device, wherein: The display device comprises the display substrate according to any one of claims 1 to 14.

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