Image sensor structure

Abstract

The invention discloses an image sensor structure. An image sensor structure and a method of forming the same are provided. An image sensor structure according to the present disclosure includes: a semiconductor substrate including a photodiode; a transfer gate transistor disposed over the semiconductor substrate and having a first channel area; a first dielectric layer disposed over the semiconductor substrate; a semiconductor layer disposed on the first dielectric layer; a source follower transistor disposed over the semiconductor layer and having a second channel area; a row selection transistor disposed over the semiconductor layer and having a third channel area; and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is larger than the first channel area, the third channel area or the fourth channel area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to an image sensor structure. Background Art

[0002] Compared with traditional charge coupled devices (CCDs), complementary metal oxide semiconductor (CMOS) image sensors (CIS) are becoming increasingly popular. CMOS image sensors typically include an array of picture elements (pixels) that convert photons into electrons using photosensitive CMOS circuits. The photosensitive CMOS circuits typically may include photodiodes formed in a semiconductor substrate. When the photodiode is exposed to light, a charge is induced in the photodiode. Each pixel may generate electrons proportional to the amount of incident light falling on the pixel. The electrons are converted into a voltage signal in the pixel and further converted into a digital signal, which will be processed by an application specific integrated circuit (ASIC). Although existing image sensor packages are generally adequate for their intended purposes, they are not satisfactory in all aspects. Summary of the invention

[0003] According to a first aspect of the present disclosure, an image sensor structure is disclosed, including: a semiconductor substrate including a photodiode; a transfer gate transistor, arranged on the semiconductor substrate and including a first channel area; a first dielectric layer, arranged on the semiconductor substrate; a semiconductor layer, arranged on the first dielectric layer; a source follower transistor, arranged on the semiconductor layer and including a second channel area; a row selection transistor, arranged on the semiconductor layer and including a third channel area; and a reset transistor, arranged on the semiconductor layer and including a fourth channel area, wherein the second channel area is larger than the first channel area, the third channel area or the fourth channel area.

[0004] According to a second aspect of the present disclosure, a semiconductor device structure is disclosed, comprising: a substrate comprising a plurality of photodiodes; a plurality of transfer gate transistors arranged on the substrate; a first dielectric layer located on the substrate and the plurality of transfer gate transistors; a semiconductor layer arranged on the first dielectric layer; a plurality of source follower transistors, a plurality of row selection transistors and a plurality of reset transistors arranged on the semiconductor layer; a second dielectric layer located on the plurality of source follower transistors, the plurality of row selection transistors and the plurality of reset transistors; and an interconnect structure arranged on the second dielectric layer, wherein each of the plurality of transfer gate transistors comprises a first channel area, each of the plurality of source follower transistors comprises a second channel area, each of the plurality of row selection transistors comprises a third channel area, and each of the plurality of reset transistors comprises a fourth channel area, wherein the second channel area is greater than the first channel area, the third channel area or the fourth channel area.

[0005] According to a third aspect of the present disclosure, a method is disclosed, comprising: receiving a semiconductor substrate including a photodiode; forming a transfer gate transistor on the semiconductor substrate directly above the photodiode; depositing a first dielectric layer on the transfer gate transistor and the semiconductor substrate; depositing a semiconductor layer directly above the first dielectric layer; forming a source follower transistor, a row selection transistor and a reset transistor on the semiconductor layer; forming a second dielectric layer above the source follower transistor, the row selection transistor and the reset transistor; and forming an interconnect structure above the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present invention and, therefore, should not be considered limiting of scope as the present invention may be equally well applied to other embodiments.

[0007] Figure 1 is a schematic diagram of a vertical stacking configuration for increasing the channel area of ​​a source follower transistor for an image sensor according to various aspects of the present disclosure.

[0008] Figure 2-4 Example arrangements for increasing the channel area of ​​a source follower transistor in accordance with various aspects of the present disclosure are shown.

[0009] Figure 5A flow chart of a method for forming an image sensor structure according to various aspects of the present disclosure is shown.

[0010] Figure 6-16 The workpiece experience according to various aspects of the present disclosure is shown Figure 5 Partial cross-sectional views of different steps of the method.

[0011] Fig.17 A flow chart is shown of an alternative method for forming an image sensor structure according to various aspects of the present disclosure.

[0012] Figure 18-29 The workpiece according to various aspects of the present disclosure is shown Fig.17 Partial cross-sectional views of different steps of the method.

[0013] Figure 30-34 is a schematic diagram of various types of transistors that may be implemented to increase the channel area of ​​a source follower transistor in accordance with various aspects of the present disclosure.

[0014] Fig.35 An example layout for increasing the channel area of ​​a source follower transistor according to various aspects of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] In addition, when a number or range of numbers is described using the terms "about," "approximately," etc., the term is intended to encompass numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, a number or range of numbers encompasses a reasonable range including the described number, such as within + / - 10% of the described number, based on known manufacturing tolerances associated with manufacturing features having the properties associated with the number. For example, a layer of material having a thickness of "about 5 nm" may encompass a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the layer of material is known to those of ordinary skill in the art to be + / - 15%.

[0018] In recent years, complementary metal oxide semiconductor (CMOS) image sensors (CIS) have become increasingly popular. In some existing technologies, a CIS image sensor may include a pixel chip stacked on a logic chip. The pixel chip includes a photodiode and a pixel transistor, and the logic chip includes an application-specific integrated circuit (ASIC). In some examples, the pixel transistor may include a transfer gate transistor (TX), a source follower transistor (SF), a reset transistor (RST), and a row select transistor (SEL). As image sensor technology matures, consumers are eager to obtain high-quality images in low-light conditions. To achieve this, the signal-to-noise ratio (SNR) needs to be greatly improved. When the SNR is less than the ideal value, images taken in low-light conditions may be affected by random telegraph signal (RTS) noise.

[0019] The present disclosure provides an image sensor structure to improve the signal-to-noise ratio, thereby reducing RTS noise under low light conditions. The present disclosure also provides an example manufacturing process for implementing the disclosed image sensor structure. In some embodiments where a unit pixel includes a photodiode, a transfer gate transistor, a source follower transistor, a row select transistor, and a reset transistor, the source follower transistor, the row select transistor, and the reset transistor are fabricated on a semiconductor layer or substrate that is different from the substrate that includes the photodiode. In this way, the source follower transistor, the row select transistor, and the reset transistor do not need to compete for space with the photodiode and the transfer gate transistor. In addition, in the source follower transistor, the row select transistor, and the reset transistor, the channel area or channel width of the source follower transistor is maximized by implementing different types of transistors or connecting multiple transistors in parallel. By maximizing the channel area or channel width of the source follower transistor, the image sensor structure of the present disclosure can have reduced RTS noise under low light conditions.

[0020] Figure 1 1 shows a schematic circuit diagram of an image sensor element 10 having a three-chip configuration, wherein the three chips are arranged or stacked vertically one above the other. Figure 1, the image sensor element 10 includes a first chip 12, a second chip 14 disposed on the first chip 12, and a third chip 16 disposed on the second chip 14. In the depicted example, the first chip 12 includes an application specific integrated circuit (ASIC), the second chip 14 includes a source follower transistor (SF), a reset transistor (RST), and a row select transistor (SEL), and the third chip 16 includes a photodiode and a transfer gate transistor (TX). In the depicted embodiment, the first chip 12 may be referred to as a logic chip 12 or an ASIC chip 12, the second chip 14 may be referred to as a pixel device chip 14, and the third chip 16 may be referred to as a pixel chip 16. In some embodiments, the first chip 12, the second chip 14, and the third chip 16 refer to three semiconductor substrates that are manufactured separately before being directly bonded together by using a bonding layer. In some other embodiments, at least the second chip 14 is not manufactured on a separate semiconductor substrate, but is manufactured on a semiconductor layer that is deposited or bonded to the third chip 16. In Figure 1 In the three-chip structure shown, since the source follower transistor (SF), reset transistor (RST) and row select transistor (SEL) in the second chip 14 are located on different substrates or semiconductor layers, they do not compete for space with the photodiode and transfer gate transistor (TX).

[0021] Figure 2-4 An example arrangement is shown in which the channel area or channel width of the source follower transistor (SF) on the second chip 14 is maximized. For ease of illustration, Figure 2-4 The first chip 12 is omitted. Figure 2 , the second chip 14 includes a source follower transistor (SF) 24, a row select transistor (SEL) 26, and a reset transistor (RST) 28, and the third chip 16 includes at least one transfer gate transistor 22 and at least one photodiode 20. In the depicted embodiment, each of the image sensor elements 10 includes four (4) photodiodes 20 and four (4) transfer gate transistors (TX) 22 in the third chip 16. The source follower transistor (SF) 24, the row select transistor (SEL) 26, and the reset transistor (RST) 28 overlap and correspond to the four photodiodes 20 and the four transfer gate transistors (TX) 22. Figure 4As shown, the device area of ​​the source follower transistor (SF) 24 is larger than the device area of ​​the transfer gate transistor (TX) 22, the row select transistor (SEL) 26, or the reset transistor (RST) 28. In some cases, the device area of ​​the source follower transistor (SF) 24 is at least 20% larger than the device area of ​​the transfer gate transistor (TX) 22. The device area of ​​the source follower transistor (SF) 24 is larger than the sum of the device areas of the row select transistor (SEL) 26 or the reset transistor (RST) 28. In some cases, the device area of ​​the source follower transistor (SF) 24 is larger than three times (3X) the sum of the device areas of the row select transistor (SEL) 26 or the reset transistor (RST) 28. Figure 2 In FIG. 1 , the device region of the source follower transistor (SF) 24 is substantially rectangular in shape and is long in the Y direction from a top view. The row selection transistor (SEL) 26 and the reset transistor (RST) 28 are arranged along the long side of the source follower transistor (SF) 24. Figure 3 , the shape of the device region of the source follower transistor (SF) 24 is substantially rectangular and is long in the X direction from a top view. The row selection transistor (SEL) 26 and the reset transistor (RST) 28 are arranged along the long side of the source follower transistor (SF) 24. Figure 4 , the shape of the device region of the source follower transistor (SF) 24 is substantially rectangular. A row select transistor (SEL) 26 is arranged along a first side of the source follower transistor (SF) 24, and a reset transistor (RST) 28 is arranged along a second side of the source follower transistor (SF) 24.

[0022] Figure 2-4 The vertical arrangement shown can be used Figure 5 Method 100 or Fig.17 Methods 100 and 300 are merely examples and are not intended to limit the present disclosure to what is explicitly shown in method 100 or method 300. Additional steps may be provided before, during, and after method 100 or method 300, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Figure 6-16 Describing method 100, Figure 6-16 2 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages according to an embodiment of the method 100. Figure 18-29 Describing method 300, Figure 18-29300 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages according to an embodiment of the method 300. Because the workpiece 200 will be manufactured into a semiconductor device 200 at the end of the manufacturing process, the workpiece 200 may be referred to as a semiconductor device 200 as the context requires. In addition, throughout the present application and across different embodiments, the same reference numerals represent similar features with similar structures and compositions unless otherwise specified. (One or more) source / drain regions may be referred to individually or collectively as a source or a drain, depending on the context.

[0023] refer to Figure 5 and Figure 6 , the method 100 includes block 102, where a photodiode 204 and a transfer gate transistor 208 are formed on a substrate 202. The substrate 202 may be a bulk silicon (Si) substrate. Alternatively, the substrate 202 may include an elemental semiconductor, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or a combination thereof. At block 102, a photodiode 204 is formed on the substrate 202. To form the photodiode 204 in the substrate 202, the substrate 202 may include various doped regions. In one embodiment, the substrate 202 may include an n-type dopant, such as phosphorus (P), arsenic (As), or other n-type dopants. At box 102, a transfer gate transistor 208 is formed on the photodiode 204. In some embodiments, each transfer gate transistor 208 includes a vertical portion 210 extending into the photodiode 204. The vertical portion 210 may include a gate dielectric layer in direct contact with the substrate 202 and the photodiode 2-4, and an electrode layer separated from the substrate 202 and the photodiode 2-4 by a gate dielectric layer. The electrode layer may include heavily doped polysilicon, copper (Cu), tungsten (W), or aluminum (Al). In Figure 6In some embodiments shown, the photodiodes 204 are spaced apart from each other by deep trench isolation (DTI) features 206. To form the DTI features 206, deep trenches are formed in the back side of the substrate 202. A liner and a fill material may then be deposited into the deep trenches to form the DTI features 206. Because the DTI features 206 are formed on the back side, the DTI features 204 may also be referred to as backside DTI (BDTI) features 206. In some embodiments, the liner may include a metal, such as aluminum (Al), tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu), and the fill material may include a dielectric material, such as silicon oxide, aluminum oxide, hafnium oxide, titanium oxide, barium titanate, zirconium oxide, lanthanum oxide, barium oxide, strontium oxide, yttrium oxide, or a combination thereof.

[0024] refer to Figure 5 , Figure 6 and Figure 7 , the method 100 includes block 104, in which a first passivation layer 212 is formed over the substrate 202. After forming the transfer gate transistor (TX) 208, the first passivation layer 212 is deposited on the substrate 202. In some embodiments, the first passivation layer 212 includes a dielectric material, such as silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicate glass, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. At block 104, the first passivation layer 212 may be deposited using spin coating, flowable chemical vapor deposition (FCVD), or CVD.

[0025] refer to Figure 5 , 89, the method 100 includes a block 106, wherein a semiconductor layer 214 is deposited on top of the first passivation layer 212. In an exemplary process, a seed semiconductor layer is first deposited on the first passivation layer 212 using CVD or a suitable method, and then the semiconductor layer 214 is epitaxially deposited on the seed semiconductor layer. The epitaxial deposition of the semiconductor layer 214 may be performed using vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable epitaxial deposition processes. In some implementations, the seed semiconductor layer and the semiconductor layer 214 include silicon (Si). In some implementations, the semiconductor layer 214 is deposited so that the crystal plane facing the top is a (100) plane or a (110) plane. The semiconductor layer 214 is much thinner than a commercially available silicon substrate having a thickness between about 400 μm and about 500 μm. In some embodiments, the semiconductor layer 214 may have a first thickness T1 between about 2 μm and about 20 μm. This thickness range is not insignificant. When the thickness is less than 2 μm, semiconductor layer 214 may have too many defects due to its formation from first passivation layer 212. When the thickness is greater than 20 μm, it is unnecessary for transistors, and epitaxial deposition to such a thickness may take too long, resulting in smaller production volume and higher cost.

[0026] refer to Figure 5 and Fig.10 , the method 100 includes a block 108, in which an isolation structure 216 is formed in the semiconductor layer 214. The isolation structure 216 can be used to divide the semiconductor layer 214 into different isolated device regions. In an example process, an isolation trench is formed that at least partially passes through the semiconductor layer 214. Because the semiconductor layer 214 has a thickness between about 2 μm and about 20 μm, the isolation trench can extend completely through the semiconductor layer 214 to terminate in the first passivation layer 212. After the isolation trench is formed, a dielectric material for the isolation structure 216 is deposited on the workpiece 200, including the isolation trench, using CVD, sub-atmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized to form the isolation structure 216. The dielectric material for the isolation structure 216 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0027] refer to Figure 5 and Fig.11, method 100 includes block 110, where a source follower transistor (SF) 220, a row select transistor (SEL) 222, and a reset transistor (RST) 224 are formed on semiconductor layer 214. Source follower transistor (SF) 220, row select transistor (SEL) 222, and reset transistor (RST) 224 may be implemented using planar transistors or multi-gate transistors. An example planar transistor 400 is shown in FIG. Fig.30 As shown. The planar transistor 400 includes an active region 402 disposed in the isolation structure 216. It can be seen that the patterning of the semiconductor layer 214 to form the active region 402 can be achieved by forming the isolation structure 216. After forming the isolation structure 216, a gate dielectric layer 406 is deposited on the active region 402 and the isolation structure 216. The gate dielectric layer 406 may include an interface layer ( Fig.28 404 and 405. The interfacial layer 404 may include silicon oxide and may be deposited during a cleaning process in which the active area 402 is oxidized. The high-k dielectric layer may include hafnium oxide, zinc oxide, zirconium oxide, aluminum oxide, or a combination thereof. The high-k dielectric layer may be deposited using atomic layer deposition (ALD) or CVD. In some alternative embodiments, the gate dielectric layer 406 includes silicon oxide and is deposited using ALD or CVD. A gate electrode layer 408 is then deposited on the gate dielectric layer 406. The gate electrode layer 408 may include titanium nitride (TiN), ruthenium (Ru), aluminum (Al), or tungsten (W). The gate dielectric layer 406 and the gate electrode layer 408 may be referred to as a gate structure 404. As shown in FIG. Fig.30 As shown, the gate structure 404 of the planar transistor 400 only engages the top surface of the active region 402. A channel region is formed only near the interface between the gate structure 404 and the active region 402.

[0028] Fig.31 , 32 , 33 and 34 show four exemplary multi-gate transistors. Fig.31 An L-type gate transistor 500 is shown. Fig.32 A fin transistor 600 is shown. Fig.33 A linear gate all around (GAA) transistor 700 is shown. Fig.34 A sheet-type GAA transistor 800 is shown. As the name implies, Fig.31The L-gate transistor 500 in FIG. 4 includes an L-gate structure 504 that interfaces with at least a portion of a top surface and a sidewall of an active region 502. Note that the active region 502 of the L-gate transistor 500 can be similar to the active region 402 of the planar transistor 400. The L-gate structure 504 includes a gate dielectric layer 506 and a gate electrode layer 508. The composition of the gate dielectric layer 506 can be similar to the gate dielectric layer 406 of the planar transistor 400. The composition of the gate electrode layer 508 can be similar to the gate electrode layer 408 of the planar transistor 400. Fig.32 The fin transistor 600 in FIG. 1 includes a gate structure 604 covering a fin-shaped active region 602. Fig.32 As shown, the lower portion of the fin-shaped active region 602 is buried in and surrounded by the isolation structure 216, but the upper portion of the fin-shaped active region 602 is higher than the isolation structure 216. The gate structure 604 of the fin-shaped transistor 600 engages the top surface and two sidewalls of the fin-shaped active region 602. The gate structure 604 includes a gate dielectric layer 606 and a gate electrode layer 608 on the gate dielectric layer 608. The composition of the gate dielectric layer 606 can be similar to the gate dielectric layer 406 of the planar transistor 400. The composition of the gate electrode layer 608 can be similar to the gate electrode layer 408 of the planar transistor 400. Fig.33 The linear GAA transistor 700 and Fig.34 The sheet-type GAA transistor 800 in FIG. 8 is a GAA transistor in which a gate structure surrounds at least one channel member among a plurality of channel members. Fig.33 , the active area of ​​the linear GAA transistor 700 includes at least one linear channel member 702, whose cross-sectional area is substantially square or circular. Compared with the linear channel member 702 in the linear GAA transistor 700, the channel member 802 of the sheet-like GAA transistor 800 is similar to a sheet. The cross-section of each sheet-like channel member 802 is characterized in that the height is significantly less than the width. The gate structure 704 of the linear GAA transistor 700 includes a gate dielectric layer 706 and a gate electrode layer 708. The gate structure 804 of the sheet-like GAA transistor 800 includes a gate dielectric layer 806 and a gate electrode layer 808. The composition of the gate dielectric layers 706 and 806 can be similar to the gate dielectric layer 406 of the planar transistor. The composition of the gate electrode layer 708 and the gate electrode layer 808 can be similar to the gate electrode layer 408 of the planar transistor.

[0029] When the source follower transistor (SF) 220, the row select transistor (SEL) 222, and the reset transistor (RST) 224 are implemented with multi-gate transistors, a gate-first process or a gate-last process can be used. When the gate-first process is used, the gate structure (e.g., gate structures 504, 604, 704, and 804) is formed before the source / drain features are formed on either side of the gate structure. When the gate-last process is used, the gate structure (e.g., gate structures 504, 604, 704, and 804) is formed after the source / drain features are formed on either side of the gate structure. In the example gate-first process, a mask layer is deposited on the active area. The mask layer is patterned to form a gate trench that exposes the channel region of the active area, while the source / drain region of the active area is still covered by the mask layer. The gate structure (e.g., gate structures 504, 604, 704, and 804) is formed in the gate trench. When it comes to GAA transistors such as linear GAA transistor 700 and sheet GAA transistor 800, after forming the gate trench, the sacrificial layer is selectively removed to release the channel layer as the channel member 702 or 802. The gate structure 704 is deposited to surround each linear channel member 702. The gate structure 804 is deposited to surround each sheet channel member 802. After forming the gate structure, the mask layer covering the source / drain region is removed. In some embodiments, the source / drain region is recessed to form a source / drain recess, and the source / drain feature is formed in the source / drain recess so that the source / drain feature contacts the termination sidewall of the channel member 702 or 802. In some alternative embodiments, the mask layer on the source / drain region is removed, and the sacrificial layer is at least partially recessed. The source / drain feature is then deposited to surround the source / drain region.

[0030] Given the same footprint, the channel width of a multi-gate transistor is generally larger than that of a planar transistor. Fig.30 , the active region 402 extends longitudinally along a direction CL representing a channel length direction. The gate structure 404 extends along a direction CW representing a channel width direction. The directions CL and CW may correspond to the X direction or the Y direction, or vice versa. The planar transistor 400 has a first channel width W1 along the direction CW. Now referring to Fig.31 The L-type gate structure 504 of the L-type gate transistor 500 intersects the top surface and a portion of the sidewall of the active region 502. When the width of the active region 502 is the same as the first channel width W1 to have the same device footprint and the channel length remains constant, the L-type gate transistor 500 has a second channel width W2 that is greater than Fig.29 The first channel width W1 of the mid-plane transistor 400 is shown in FIG. Fig.32, the gate structure 604 of the fin transistor 600 intersects with the top surface and two sidewalls of the fin-shaped active region 602. When the top surface of the fin-shaped active region 602 has the same width as the first channel width W1 and the channel length remains constant, the fin transistor 600 has a third channel width W3, which is greater than the second channel width W2 of the L-type gate transistor 500. Fig.33 , when the top surface of the linear channel member 702 has the first channel width W1 and the channel length remains constant, each linear channel member 702 provides a fourth channel width W4 that is about 2.5 times to about 3 times the first channel width W1. Fig.32 As shown, when the linear GAA transistor 700 includes three (3) vertically stacked linear channel members 702, the total channel width of the linear GAA transistor 700 is approximately three times the fourth channel width W4 (ie, W4×3). The total channel width of the linear GAA transistor 700 is greater than the third channel width W3 of the fin transistor 600. Fig.34 , when the top surface of the sheet-like channel member 802 has a first channel width W1 and the channel length remains constant, each sheet-like channel member provides a fifth channel width W5, which is more than twice the first channel width W2. Fig.34 As shown, when the sheet GAA transistor 800 includes three (3) vertically stacked linear channel members 702 , the total channel width of the sheet GAA transistor 800 is approximately three times the fifth channel width W5 (ie, W5×3). The total channel width of the sheet GAA transistor 800 is greater than the third channel width W3 of the fin transistor 600 .

[0031] According to the present disclosure, the channel width of the source follower transistor (SF) 220 is maximized, while the channel width of the row select transistor (SEL) 222 and the channel width of the reset transistor (RST) 224 are minimized. In some embodiments, the source follower transistor (SF) 220, the row select transistor (SEL) 222, and the reset transistor (RST) 224 may use Figure 30-34 For example, source follower transistor (SF) 220, row select transistor (SEL) 222, and reset transistor (RST) 224 may all be implemented using transistors of the same type as those shown in FIG. Fig.30 In this example, in order to increase the channel width of the source follower transistor (SF) 220, more than one planar transistor 400 may be connected in parallel to increase the effective channel width. Fig.35 , which is a schematic top view of the layout of the source follower transistor (SF) 220. Fig.35The gate structures 24G are included, each of which is disposed between a source contact 24S and a drain contact 24D. Fig.35 As shown, when the first metal line 30 electrically couples the two source contacts 24S through the first via 30V, the second metal line 32 electrically couples the two gate structures 24G through the second via 32V, and the third metal line 34 electrically couples the two drain contacts 24D through the third via 34V, the effective channel length can be increased from one times (1X) the first channel width W1 to two times (2X) the first channel width W1. That is, when the source follower transistor (SF) 220, the row selection transistor (SEL) 222, and the reset transistor (RST) 224 are all implemented using the same type of transistors, the effective channel width of the source follower transistor (SF) 220 can be increased by connecting more transistors in parallel, as shown in FIG. Fig.35 shown.

[0032] Based on experimental data and simulation results, in order to effectively reduce random telegraph signal (RTS) noise, the effective channel width of the source follower transistor (SF) 220 should be greater than the channel width of the row select transistor (SEL) 222 or the channel width of the reset transistor (RST) 224. In some embodiments, the effective channel width of the source follower transistor (SF) 220 is greater than about 1 to about 3 times the sum of the channel widths of the row select transistor (SEL) 222 and the reset transistor (RST) 224. When the source follower transistor (SF) 220, the row select transistor (SEL) 222, and the reset transistor (RST) 224 are all implemented using the same type of transistors, the above comparison of channel widths can be directly converted into device areas.

[0033] In some other embodiments, the source follower transistor (SF) 220 is implemented with a multi-gate transistor, such as Figure 31-34 As shown, the row selection transistor (SEL) 222 and the reset transistor (RST) 224 are used Fig.30 In addition, the source follower transistor (SF) 220 can be implemented with multiple multi-gate transistors connected in parallel, such as Fig.35 shown.

[0034] refer to Figure 5 and Fig.12, the method 100 includes block 112, where a second passivation layer 230 is formed over the semiconductor layer 214. After forming the source follower transistor (SF) 220, the row select transistor (SEL) 222, and the reset transistor (RST) 224, the second passivation layer 230 is deposited on the semiconductor layer 214. In some embodiments, the second passivation layer 230 includes a dielectric material such as silicon oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicate glass such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass, boron-doped silicate glass (BSG), and / or other suitable dielectric materials. At block 112, the second passivation layer 230 may be deposited using spin coating, flowable chemical vapor deposition (FCVD), or CVD.

[0035] refer to Figure 5 and 13 , method 100 includes block 114, where deep contacts 234 are formed. After depositing second passivation layer 230, contact features 232 are formed to electrically couple to source follower transistor (SF) 220, row select transistor (SEL) 222, and reset transistor (RST) 224, and deep contacts 234 are formed to electrically couple to photodiode 204. In an example process, contact openings for contact features 232 and deep contact openings for deep contacts 234 are formed using a photolithography process and an etching process. In some cases, a dry etching process, such as a reactive ion etching (RIE) process, is used to form the contact openings and the deep contact openings. As shown in FIG. Fig.13 As shown, the contact opening for contact feature 232 extends through the second passivation layer 230, and the deep contact opening for deep contact 234 extends through the second passivation layer 230, the isolation structure 216 and the first passivation layer 212 to reach the floating diffusion node. Due to the different depths, in some embodiments, the deep contact opening is formed in two steps. First, a guide opening is formed, and the area for the contact opening is covered with a mask layer. Then the mask layer is removed. The guide opening extends downward to form a deep contact opening while forming the contact opening. After forming the contact opening and the deep contact opening, a barrier layer is deposited in the contact opening and the deep contact opening, and a metal filling layer is deposited on the barrier layer. After a planarization process (e.g., a chemical mechanical polishing (CMP) process), contact features 232 and deep contacts 234 are formed. In some cases, the barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, cobalt, cobalt nitride, nickel or nickel nitride, and the metal filling layer may include copper (Cu).

[0036] refer to Figure 5 , 1415, the method 100 includes a block 116, wherein an interconnect structure 240 is formed on top of the second passivation layer 230. In some embodiments, the interconnect structure 240 includes 2 to 10 metal layers (or metallization layers). Each metal layer includes contact vias and metal lines disposed in at least one etch stop layer and at least one intermetallic dielectric (IMD) layer. The contact vias and metal lines may include copper (Cu) and a barrier layer formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, cobalt nitride, nickel, or nickel nitride. The etch stop layer in the interconnect structure 240 may include silicon nitride or silicon oxynitride. The IMD layer may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass, boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The interconnect structure 240 may be formed layer by layer. In an example process, an etch stop layer and an IMD layer are deposited on the second passivation layer 230. Then, contact vias and metal lines in the etch stop layer and the IMD layer are formed using a single or dual damascene process. This process can be repeated multiple times to form multiple metal layers in the interconnect structure 240.

[0037] refer to Figure 5 and Fig.16 , the method 100 includes a block 118, in which further processing is performed. These further processings include manufacturing a logic device on the third substrate 250, forming an interconnect structure 252 on the third substrate 250, bonding the interconnect structure 252 to the interconnect structure 240, forming a color filter layer 260, and forming a microlens 262. The logic device on the third substrate 250 may include an application-specific integrated circuit (ASIC) device, which is implemented using various multi-gate devices such as fin transistors or GAA transistors. The interconnect structure 252 may include more metallization layers than the interconnect structure 240. In some embodiments, the interconnect structure 252 may include 8 to 20 metallization layers. The interconnect structure 252 may be bonded to the interconnect structure 240 through a first bonding layer 254 and a second bonding layer 256. Each of the first bonding layer 254 and the second bonding layer 256 includes a plurality of bonding pads disposed in a dielectric layer. The plurality of bonding pads in the first bonding layer 254 are configured to be aligned in a vertical direction with the plurality of bonding pads in the second bonding layer 256. A first bonding layer 254 is formed over the interconnect structure 254, and a second bonding layer 256 is formed over the interconnect structure 240. The interconnect structure 252 and the third substrate 250 are bonded to the interconnect structure 240 by bonding a plurality of bonding pads in the first bonding layer 254 and the second bonding layer 256 and bonding a dielectric surface in the first bonding layer 254 to a dielectric surface in the second bonding layer 256.

[0038] The color filter layer 260 may be formed of a polymer material or resin including a color pigment. At block 118, the color filter layer 260 is formed over the photodiode 204 in the first substrate 202. The color filter layer 260 includes a plurality of color filters, each of which allows the transmission of radiation (e.g., light) having a specific wavelength range while blocking light of wavelengths outside the specific range. Microlenses 262 are formed over the color filter layer 260. The microlenses 262 may be formed of any material that can be patterned and formed into microlenses, such as a high-transmittance acrylic polymer.

[0039] refer to Fig.16 . Combined with the above Figure 2-4 In accordance with the description, the third substrate 250 and the interconnect structure 252 are used as a first chip that performs logic or ASIC functions. The second substrate 214 and the interconnect structure 240 are used as a second chip including pixel transistors such as a source follower transistor (SF) 220, a reset transistor (RST) 224, and a row select transistor (SEL) 222. The first substrate 202 is used as a third chip including a photodiode 204 and a transfer gate transistor (TX) 208. The first chip may also be referred to as a logic chip. The second chip may also be referred to as a pixel device chip. The third chip may also be referred to as a pixel chip. As described above, this three-chip structure allows the device area of ​​the source follower transistor (SF) to be maximized to reduce random telegraph signal (RTS) noise.

[0040] In method 100, semiconductor layer 214 is deposited on first passivation layer 212 using an epitaxial deposition process. In alternative method 300, substrate 202 is a first substrate and a second substrate is bonded to first passivation layer 212. After bonding, source follower transistor (SF) 220, row select transistor (SEL) 222, and reset transistor (RST) 224 are fabricated on the second substrate instead of semiconductor layer 214. Figure 18-29 Describing the operation of method 300, Figure 18-29 is a partial cross-sectional view of the workpiece 200. Some operations in the method 300 are similar to those in the method 100. Detailed descriptions of similar operations in the method 300 may be simplified to avoid repetition.

[0041] refer to Fig.17 and 18 , the method 300 includes a block 302, in which a photodiode 204 and a transfer gate transistor 208 are formed on a first substrate 202. Note that the first substrate 202 may be Figure 6-16The illustrated substrate 202 is no different. Because the method 300 includes two semiconductor substrates, for ease of description, the substrate 202 is referred to as the first substrate 202. The operations at block 302 are substantially similar to the operations in block 102 of the method 100. For the sake of brevity, a detailed description of block 302 is omitted.

[0042] refer to Fig.17 , Fig.18 and Fig.19 , the method 300 includes block 304, where a first passivation layer 212 is formed over the substrate 202. The operations at block 304 are substantially similar to the operations in block 104 of the method 100. For the sake of brevity, a detailed description of block 304 is omitted.

[0043] refer to Fig.17 and 20 -22, method 300 includes box 306, where the second substrate 2140 is bonded to the first passivation layer 212. To ensure performance bonding, a cleaning process can be performed on the first passivation layer 212. In some embodiments, the cleaning process can include the use of ammonium hydroxide, hydrogen peroxide, and deionized water. After cleaning, the first passivation layer 212 can be plasma treated 280 to activate its top surface for bonding. The plasma treatment 280 can include the use of oxygen, argon, nitrogen, or hydrogen. In one embodiment, the plasma treatment 280 can include the use of hydrogen plasma. After the plasma treatment 280, the first passivation layer 212 and the second substrate 2140 are bonded together by bringing the top surface of the first passivation layer 212 into contact with the bottom surface of the second substrate 2140 at room temperature. As Fig. 22 As shown, after bonding, the second substrate 2140 is bonded to the top surface of the first passivation layer 212 and has a second thickness T2. In some cases, the second thickness T2 of the second substrate 2140 is greater than Fig. 9 The semiconductor layer 214 is shown to have a first thickness T1. In some embodiments, the second thickness T2 may be between about 2 μm and about 50 μm.

[0044] refer to Fig.17 and 23 , method 300 includes block 308, where an isolation structure 216 is formed in the second substrate 2140. The operations at block 308 are substantially similar to the operations in block 108 of method 100, except that the isolation structure 216 is formed in the second substrate 2140 at block 308. Because the second substrate 2140 is thicker than the semiconductor layer 214, in at least some embodiments, the isolation structure 216 does not extend completely through the second substrate 2140. That is, in these embodiments, the bottom surface of the isolation structure 216 terminates at the second substrate 2140. For the sake of brevity, a detailed description of block 308 is omitted.

[0045] refer to Fig.17 and 24 The method 300 includes a block 310 in which a source follower transistor (SF) 220, a row select transistor (SEL) 222, and a reset transistor (RST) 224 are formed on a second substrate 2140. The operations at block 310 are substantially similar to the operations in block 108 of the method 100, except that the source follower transistor (SF) 220, the row select transistor (SEL) 222, and the reset transistor (RST) 224 are formed on the second substrate 2140 at block 310. For the sake of brevity, a detailed description of block 308 is omitted.

[0046] refer to Fig.17 and 25 , the method 300 includes block 312, where a second passivation layer 230 is formed over the second substrate 2140. The operations at block 312 are substantially similar to the operations in block 114 of the method 100. For the sake of brevity, a detailed description of block 312 is omitted.

[0047] refer to Fig.17 and 26 , the method 300 includes block 314, in which a deep contact 234 is formed. The operations at block 314 are substantially similar to the operations in block 114 of the method 100, except that at block 314 the deep contact 234 extends through the second passivation layer 230, the isolation structure 216, the second substrate 2140, and the first passivation layer 212 to reach the floating diffusion node.

[0048] refer to Fig.17 and Fig.29, the method 300 includes a block 318, in which further processing is performed. These further processings include: manufacturing a logic device on the third substrate 250, forming an interconnect structure 252 on the third substrate 250, bonding the interconnect structure 252 to the interconnect structure 240, forming a color filter layer 260, and forming a microlens 262. The logic device on the third substrate 250 may include an application-specific integrated circuit (ASIC) device, which is implemented using various multi-gate devices such as fin transistors or GAA transistors. The interconnect structure 252 may include more metallization layers than the interconnect structure 240. In some embodiments, the interconnect structure 252 may include 8 to 20 metallization layers, each of which includes a plurality of metal lines and contact vias. The interconnect structure 252 may be bonded to the interconnect structure 240 through a first bonding layer 254 and a second bonding layer 256. Each of the first bonding layer 254 and the second bonding layer 256 includes a plurality of bonding pads disposed in a dielectric layer. The plurality of bonding pads in the first bonding layer 254 are configured to be aligned in a vertical direction with the plurality of bonding pads in the second bonding layer 256. A first bonding layer 254 is formed over the interconnect structure 254, and a second bonding layer 256 is formed over the interconnect structure 240. The interconnect structure 252 and the third substrate 250 are bonded to the interconnect structure 240 by bonding a plurality of bonding pads in the first bonding layer 254 and the second bonding layer 256 and bonding a dielectric surface in the first bonding layer 254 to a dielectric surface in the second bonding layer 256.

[0049] The color filter layer 260 may be formed of a polymer material or resin including a color pigment. At block 318, the color filter layer 260 is formed over the photodiode 204 in the first substrate 202. The color filter layer 260 includes a plurality of color filters, each of which allows the transmission of radiation (e.g., light) having a specific wavelength range while blocking light of wavelengths outside the specific range. Microlenses 262 are formed over the color filter layer 260. The microlenses 262 may be formed of any material that can be patterned and formed into microlenses, such as a high-transmittance acrylic polymer.

[0050] refer to Fig.29 . Combined with the above Figure 2-4In accordance with the description, the third substrate 250 and the interconnect structure 252 are used as a first chip that performs logic or ASIC functions. The second substrate 2140 and the interconnect structure 240 are used as a second chip including a source follower transistor (SF) 220, a reset transistor (RST) 224, and a row select transistor 222. The first substrate 202 is used as a third chip including a photodiode 204 and a transfer gate transistor (TX) 208. The first chip can also be referred to as a logic chip. The second chip can also be referred to as a pixel device chip. The third chip can also be referred to as a pixel chip. As described above, this three-chip structure allows the device area of ​​the source follower transistor (SF) to be maximized to reduce random telegraph signal (RTS) noise.

[0051] Therefore, in one aspect, the present disclosure provides an image sensor structure. The image sensor structure includes: a semiconductor substrate, the semiconductor substrate including a photodiode; a transfer gate transistor disposed on the semiconductor substrate and including a first channel area; a first dielectric layer disposed on the semiconductor substrate; a semiconductor layer disposed on the first dielectric layer; a source follower transistor disposed on the semiconductor layer and including a second channel area; a row select transistor disposed on the semiconductor layer and including a third channel area; and a reset transistor disposed on the semiconductor layer and including a fourth channel area. The second channel area is greater than the first channel area, the third channel area, or the fourth channel area.

[0052] In some embodiments, a ratio of the second channel area to the first channel area is greater than 1.2. In some embodiments, the second channel area is greater than the sum of the third channel area and the fourth channel area. In some embodiments, the image sensor structure further comprises: a second dielectric layer over the source follower transistor, the row select transistor, and the reset transistor; and an interconnect structure over the second dielectric layer. In some cases, the image sensor structure further comprises: a deep contact extending from the interconnect structure and through the semiconductor substrate and the first dielectric layer. In some embodiments, the image sensor structure further comprises: a deep trench isolation feature disposed adjacent to the photodiode. In some embodiments, the source follower transistor, the row select transistor, and the reset transistor are planar transistors. In some cases, the row select transistor and the reset transistor comprise planar transistors, and the source follower transistor comprises a multi-gate transistor. In some embodiments, the source follower transistor comprises a channel region and a gate structure, and the gate structure comprises more than one side of the channel region.

[0053] Another aspect of the present disclosure relates to a semiconductor device structure. The semiconductor device structure includes: a substrate, the substrate including a plurality of photodiodes; a plurality of transfer gate transistors disposed on the substrate; a first dielectric layer disposed on the substrate and the plurality of transfer gate transistors; a semiconductor layer disposed on the first dielectric layer; a plurality of source follower transistors, a plurality of row select transistors, and a plurality of reset transistors disposed on the semiconductor layer; a second dielectric layer disposed on the plurality of source follower transistors, the plurality of row select transistors, and the plurality of reset transistors; and an interconnect structure disposed on the second dielectric layer. Each of the plurality of transfer gate transistors includes a first channel area, each of the plurality of source follower transistors includes a second channel area, each of the plurality of row select transistors includes a third channel area, and each of the plurality of reset transistors includes a fourth channel area, and the second channel area is greater than the first channel area, the third channel area, or the fourth channel area.

[0054] In some embodiments, a ratio of the second channel area to the first channel area is greater than 1.2. In some embodiments, the semiconductor device structure further comprises: a plurality of deep contacts extending continuously through the first dielectric layer, the semiconductor layer, and the second dielectric layer. In some embodiments, the plurality of photodiodes are at least partially separated from each other by deep trench isolation features. In some embodiments, the deep trench isolation features include a metal liner and a dielectric fill material.

[0055] Another aspect of the present disclosure relates to a method. The method includes: receiving a semiconductor substrate having a photodiode; forming a transfer gate transistor on the semiconductor substrate directly above the photodiode, depositing a first dielectric layer over the transfer gate transistor and the semiconductor substrate; depositing a semiconductor layer directly over the first dielectric layer; forming a source follower transistor, a row select transistor, and a reset transistor over the semiconductor layer; forming a second dielectric layer over the source follower transistor, the row select transistor, and the reset transistor; and forming an interconnect structure over the second dielectric layer.

[0056] In some embodiments, the first dielectric layer and the second dielectric layer include silicon oxide. In some embodiments, the semiconductor layer includes silicon. In some embodiments, the method further includes: before forming the interconnect structure, forming a deep contact structure extending through the second dielectric layer, the semiconductor layer, and the first dielectric layer. In some embodiments, the semiconductor layer includes a thickness between about 2 μm and about 20 μm. In some embodiments, the source follower transistor includes a first channel area, the row select transistor includes a second channel area, the reset transistor includes a third channel area, and the second channel area is greater than the first channel area or the third channel area.

[0057] The features of several embodiments are summarized above so that those skilled in the art can better understand the detailed description. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0058] Example

[0059] Example 1. An image sensor structure, comprising: a semiconductor substrate including a photodiode; a transfer gate transistor disposed on the semiconductor substrate and including a first channel area; a first dielectric layer disposed on the semiconductor substrate; a semiconductor layer disposed on the first dielectric layer; a source follower transistor disposed on the semiconductor layer and including a second channel area; a row selection transistor disposed on the semiconductor layer and including a third channel area; and a reset transistor disposed on the semiconductor layer and including a fourth channel area, wherein the second channel area is greater than the first channel area, the third channel area or the fourth channel area.

[0060] Example 2. An image sensor structure according to Example 1, wherein a ratio of the second channel area to the first channel area is greater than 1.2.

[0061] Example 3. An image sensor structure according to Example 1, wherein the second channel area is greater than the sum of the third channel area and the fourth channel area.

[0062] Example 4. The image sensor structure of Example 1 further includes: a second dielectric layer located above the source follower transistor, the row select transistor, and the reset transistor; and an interconnect structure located above the second dielectric layer.

[0063] Example 5. The image sensor structure of Example 4, further comprising: a deep contact extending from the interconnect structure and through the semiconductor substrate and the first dielectric layer.

[0064] Example 6. The image sensor structure of Example 1, further comprising: a deep trench isolation feature disposed adjacent to the photodiode.

[0065] Example 7. An image sensor structure according to Example 1, wherein the source follower transistor, the row select transistor and the reset transistor are planar transistors.

[0066] Example 8. An image sensor structure according to Example 1, wherein the row select transistor and the reset transistor include planar transistors, and wherein the source follower transistor includes a multi-gate transistor.

[0067] Example 9. The image sensor structure of Example 8, wherein the source follower transistor comprises a channel region and a gate structure, wherein the gate structure interfaces with one or more sidewalls of the channel region.

[0068] Example 10. A semiconductor device structure, comprising: a substrate comprising a plurality of photodiodes; a plurality of transfer gate transistors disposed on the substrate; a first dielectric layer disposed on the substrate and the plurality of transfer gate transistors; a semiconductor layer disposed on the first dielectric layer; a plurality of source follower transistors, a plurality of row selection transistors, and a plurality of reset transistors disposed on the semiconductor layer; a second dielectric layer disposed on the plurality of source follower transistors, the plurality of row selection transistors, and the plurality of reset transistors; and an interconnect structure disposed on the second dielectric layer, wherein each of the plurality of transfer gate transistors comprises a first channel area, each of the plurality of source follower transistors comprises a second channel area, each of the plurality of row selection transistors comprises a third channel area, and each of the plurality of reset transistors comprises a fourth channel area, wherein the second channel area is greater than the first channel area, the third channel area, or the fourth channel area.

[0069] Example 11. The semiconductor device structure of Example 10, wherein a ratio of the second channel area to the first channel area is greater than 1.2.

[0070] Example 12. The semiconductor device structure of Example 10, further comprising: a plurality of deep contacts extending continuously through the first dielectric layer, the semiconductor layer, and the second dielectric layer.

[0071] Example 13. The semiconductor device structure of Example 10, wherein the plurality of photodiodes are at least partially separated from one another by deep trench isolation features.

[0072] Example 14. The semiconductor device structure of Example 13, wherein the deep trench isolation feature comprises a metal liner and a dielectric fill material.

[0073] Example 15. A method comprising: receiving a semiconductor substrate including a photodiode; forming a transfer gate transistor on the semiconductor substrate directly above the photodiode; depositing a first dielectric layer on the transfer gate transistor and the semiconductor substrate; depositing a semiconductor layer directly above the first dielectric layer; forming a source follower transistor, a row select transistor, and a reset transistor on the semiconductor layer; forming a second dielectric layer above the source follower transistor, the row select transistor, and the reset transistor; and forming an interconnect structure above the second dielectric layer.

[0074] Example 16. The method of Example 15, wherein the first dielectric layer and the second dielectric layer include silicon oxide.

[0075] Example 17. The method of Example 15, wherein the semiconductor layer comprises silicon.

[0076] Example 18. The method of Example 15, further comprising: before forming the interconnect structure, forming a deep contact structure extending through the second dielectric layer, the semiconductor layer, and the first dielectric layer.

[0077] Example 19. The method of Example 15, wherein the semiconductor layer comprises a thickness between 2 μm and 20 μm.

[0078] Example 20. A method according to Example 15, wherein the source follower transistor includes a first channel area, wherein the row select transistor includes a second channel area, wherein the reset transistor includes a third channel area, and wherein the second channel area is greater than the first channel area or the third channel area.

Claims

1. An image sensor structure, comprising: a semiconductor substrate including a photodiode; a transfer gate transistor disposed on the semiconductor substrate and comprising a first channel area; A first dielectric layer, disposed on the semiconductor substrate; A semiconductor layer, disposed on the first dielectric layer; a source follower transistor disposed on the semiconductor layer and including a second channel area; a row selection transistor disposed on the semiconductor layer and including a third channel area; and a reset transistor disposed on the semiconductor layer and comprising a fourth channel area, The second channel area is larger than the first channel area, the third channel area or the fourth channel area.

2. The image sensor structure according to claim 1, wherein: A ratio of the second channel area to the first channel area is greater than 1.

2.

3. The image sensor structure according to claim 1, wherein: The second channel area is greater than the sum of the third channel area and the fourth channel area.

4. The image sensor structure according to claim 1, further comprising: a second dielectric layer over the source follower transistor, the row select transistor, and the reset transistor; and The interconnect structure is located on the second dielectric layer.

5. The image sensor structure according to claim 4, further comprising: A deep contact extends from the interconnect structure and through the semiconductor substrate and the first dielectric layer.

6. The image sensor structure according to claim 1, further comprising: A deep trench isolation feature is disposed adjacent to the photodiode.

7. The image sensor structure according to claim 1, wherein: The source follower transistor, the row select transistor and the reset transistor are planar transistors.

8. The image sensor structure according to claim 1, in, The row selection transistor and the reset transistor include planar transistors, Wherein, the source follower transistor comprises a multi-gate transistor.

9. A semiconductor device structure, comprising: a substrate comprising a plurality of photodiodes; A plurality of transfer gate transistors are disposed on the substrate; a first dielectric layer disposed over the substrate and the plurality of transfer gate transistors; A semiconductor layer, disposed on the first dielectric layer; a plurality of source follower transistors, a plurality of row selection transistors and a plurality of reset transistors disposed on the semiconductor layer; a second dielectric layer over the plurality of source follower transistors, the plurality of row select transistors, and the plurality of reset transistors; and an interconnect structure disposed on the second dielectric layer, wherein each of the plurality of transfer gate transistors comprises a first channel area, each of the plurality of source follower transistors comprises a second channel area, each of the plurality of row select transistors comprises a third channel area, and each of the plurality of reset transistors comprises a fourth channel area, The second channel area is larger than the first channel area, the third channel area or the fourth channel area.

10. A method for forming a semiconductor device structure, comprising: receiving a semiconductor substrate including a photodiode; forming a transfer gate transistor on the semiconductor substrate directly above the photodiode; depositing a first dielectric layer over the transfer gate transistor and the semiconductor substrate; depositing a semiconductor layer directly above the first dielectric layer; forming a source follower transistor, a row select transistor, and a reset transistor over the semiconductor layer; forming a second dielectric layer over the source follower transistor, the row select transistor, and the reset transistor; as well as An interconnect structure is formed over the second dielectric layer.

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