Preparation method of TBC solar cell with double cross contact structure

Abstract

The invention relates to the field of solar cells, and discloses a preparation method of a TBC solar cell with a double-cross contact structure. The TBC solar cell prepared by the invention has a (p-p-n-n-p-p-n-n) or (p-p-n-p-p-n) or (p-n-n-p-n-n) double cross contact structure, and the structure can enlarge the width of a p region or an n region during initial graphical design, reduce the number of auxiliary grids designed on the surface of an initial silicon wafer, and reduce the complexity and difficulty of graphical design. Besides, even if an isolation region between subsequent auxiliary grids of the same doping type (between p-p or n-n) is narrow or partially conducted, the influence of short circuit can be neglected, the short circuit risk of the p region and the n region is reduced, and the battery performance is improved.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a method for preparing a double cross-contact structure TBC solar cell. Background Art

[0002] IBC cell is an interdigitated back contact solar cell. It is a structural technology that is compatible with various interface passivation technologies to form TBC, HBC, HPBC and other solar cells. Its biggest feature is that the metal cell contacts are placed on the back of the cell, and there is no metal electrode blocking the front, so it has a higher short-circuit current J sc , while the back side can allow wider metal grid lines to reduce the series resistance R s This improves the fill factor FF, so BC-type solar cells often have higher conversion efficiency. In addition, IBC battery module packaging is more convenient and flexible, changing from conventional "Z"-shaped welding to full-back "I"-shaped welding, avoiding the conventional complex packaging process and effectively improving the module's ability to resist hidden cracks. As TOPCon+ technology, TBC cells combine the excellent tunneling silicon oxide / doped amorphous silicon interface passivation technology of TOPCon cells, have higher conversion efficiency potential, and are expected to become the next generation of mass-produced solar cells.

[0003] The most critical process for preparing TBC solar cells is the back-side graphic design. The rationality of the graphic design is directly related to the subsequent battery performance. The back electrode contact form of traditional TBC solar cells is a conventional pnpnpn single cross contact structure. In order to maximize the current extraction and improve the FF of the battery, the entire sub-grid graphic design is very tight. Among them, the width of the p-region (boron diffusion layer region) and the n-region (phosphorus diffusion layer region) is generally 100-600μm, and the width of the isolation region is generally 40-300μm. Due to the small spacing of the graphic design, the p-region and the n-region are very easy to conduct, causing the entire battery to short-circuit, which makes the back-side graphic design process of TBC solar cells very complicated and requires high precision.

[0004] In view of this, how to reduce the difficulty of graphic design of TBC solar cells and reduce the risk of short circuit between the p-region and the n-region is an urgent problem to be solved. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a TBC solar cell with a double cross-contact structure. The TBC solar cell prepared by the present invention has a double cross-contact structure of (ppnnppnn) or (ppnppn) or (pnnpnn), which can expand the width of the p region or n region during the initial graphic design, reduce the number of secondary grids designed on the initial silicon wafer surface, and thus reduce the complexity and difficulty of graphic design. In addition, even if the isolation area between the subsequent secondary grids of the same doping type (between pp or between nn) is narrow or partially turned on, the influence of the short circuit can be ignored, reducing the risk of short circuit between the p region and the n region, and improving the battery performance. At the same time, since the width of the isolation area between the secondary grids of the same doping type (between pp or between nn) (10 to 100 μm) is narrower than the width of the isolation area between the conventional secondary grids of different doping types (between pn) (40 to 300 μm), the poly-Si carrier collection area of ​​the entire silicon substrate is also larger, which helps to improve the values ​​of FF and so on.

[0006] The specific technical solution of the present invention is: a method for preparing a double cross-contact structure TBC solar cell, which specifically includes the following steps: S1. Double-sided polishing of silicon wafers.

[0007] S2. Forming a tunneling oxide layer, an intrinsic polysilicon layer, and a mask layer in sequence on the back side of the silicon wafer.

[0008] The purpose of setting the mask layer is to block the doping atoms from entering the intrinsic polysilicon layer at the bottom thereof during the subsequent boron diffusion and phosphorus diffusion processes.

[0009] S3. Laser one-time patterning and grooving to remove the mask layer in the designed area of ​​the boron diffusion layer region (p region).

[0010] S4. Alkaline cleaning is performed to remove the residual mask layer in the grooved area to expose the intrinsic polysilicon layer.

[0011] S5. Boron diffusion converts the inner layer and the surface layer of the intrinsic polysilicon layer in the grooved area into a boron diffusion layer and a BSG layer respectively.

[0012] In the above boron diffusion process, the ungrooved area of ​​S3 can effectively block boron atoms from entering the intrinsic polysilicon layer due to the protection of the mask layer, and only the inner layer and the surface layer of the exposed intrinsic polysilicon layer are converted into a boron diffusion layer and a BSG layer respectively.

[0013] S6, laser secondary patterning and grooving the remaining mask layer area.

[0014] The purpose of removing the remaining mask layer area by trenching is to cooperate with the subsequent alkaline cleaning to expose the surface of the remaining intrinsic polysilicon layer.

[0015] S7, alkaline cleaning removes the residual mask layer in the grooved area of ​​S6, so that the surface of the remaining intrinsic polysilicon layer is exposed, and the boron diffusion layer is protected from corrosion under the protection of the BSG layer on its surface.

[0016] S8. Phosphorus diffusion, so that the inner layer and the surface layer of the remaining intrinsic polysilicon layer are converted into a phosphorus diffusion layer and a PSG layer respectively.

[0017] In the phosphorus diffusion process, since the surface of the boron diffusion layer is protected by the BSG layer, phosphorus atoms cannot effectively diffuse into the boron diffusion layer, and only the inner layer and the surface layer of the exposed remaining intrinsic polysilicon layer are converted into the phosphorus diffusion layer and the PSG layer respectively.

[0018] S9. Laser patterning is performed three times to open grooves at the interface between the BSG layer and the PSG layer (ie, the isolation region between the n region and the p region), and the BSG layer and the PSG layer in the opening region are removed.

[0019] A groove is formed at the interface between the BSG layer (ie, the boron diffusion layer region) and the PSG layer (ie, the phosphorus diffusion layer region) to pave the way for the subsequent formation of an insulating isolation region.

[0020] S10, laser patterning and slotting each remaining BSG layer and the middle area of ​​the PSG layer (ie, the isolation area designed between the n-region or the p-region) four times to form a prototype of a double-symmetric double-crossed ppnnppnn contact structure.

[0021] Alternatively, the middle region of each remaining BSG layer (i.e., the isolation region design region between the n-region or the p-region) is laser patterned and grooved four times to form a prototype of a single symmetrical double cross ppnppn contact structure.

[0022] Alternatively, the middle region of each remaining PSG layer (i.e., the isolation region design region between the n-region or the p-region) is laser patterned and grooved four times to form a prototype of a single symmetrical double cross pnnpnn contact structure.

[0023] Through the above three slotting methods, three different double cross contact structure prototypes can be obtained respectively.

[0024] S11, removing the coating on the front and side surfaces of the silicon wafer.

[0025] S12, cleaning and velveting.

[0026] First, the front and back laser slotted areas of the silicon wafer are wet cleaned and texturized in an integrated manner in an alkaline solution. Since the front side of the silicon wafer has been completely stripped of the coating and there is no oxidation area, an effective light-trapping velvet surface (i.e., pyramid velvet surface) can be formed during the texturizing process; and in the back laser triple-patterned slotted area, the alkaline solution can effectively corrode the bottom deposition layer, thereby forming an insulating isolation area, and a pyramid velvet surface is also generated on the surface of the isolation area. The non-laser area can further block alkaline corrosion due to the presence of the PSG layer / BSG layer. For the middle slotted area of ​​the BSG layer and the middle slotted area of ​​the PSG layer of the laser quadruple-patterned slotting, the boron diffusion layer and the phosphorus diffusion layer of the corresponding area can also be removed during the alkaline texturizing process, so that the initial boron diffusion layer and the phosphorus diffusion layer are equally spaced and divided into two, and three different double cross-contact structures can be formed according to different slotting methods. Then, the subsequent acid cleaning tank of the texturizing tank body can further remove the PSG layer and BSG layer remaining on the surface of the silicon wafer.

[0027] S13, double-sided coating. After double-sided coating, a passivation anti-reflection layer is generated on the front and back sides of the silicon wafer.

[0028] S14, screen printing, sintering, and light injection to obtain a double cross-contact structure TBC solar cell.

[0029] As described in the background technology section of the present application, the back electrode contact form of the traditional TBC solar cell is a conventional pnpnpn single cross contact structure. In order to maximize the current extraction and improve the FF of the battery, the entire sub-grid graphic design is very tight. The width of the p-region and the n-region is generally 100 to 600 μm, and the width of the isolation region is generally 40 to 300 μm. Due to the small spacing of the graphic design, the p-region and the n-region are very easy to conduct, causing the entire battery to short-circuit, which makes the TBC solar cell back graphic design process very complicated and requires high precision. In order to reduce the difficulty of TBC solar cell graphic design and reduce the risk of short circuit between the p-region and the n-region, the present invention can obtain new TBC solar cells (such as ppnnppnn or ppnppn or pnnpnn) with three different double cross contact structures according to the above method. Figure 1 (bd) shows that this new structure can expand the width of the p-region or n-region during the initial graphic design and reduce the number of secondary gates designed on the initial silicon wafer surface, thereby reducing the complexity and difficulty of graphic design. In addition, even if the isolation area between the subsequent secondary gates of the same doping type (between pp or between nn) is narrow or partially conductive, the impact of the short circuit can be ignored, reducing the risk of short circuit between the p-region and the n-region and improving battery performance.

[0030] Preferably, in the prototype of the double-symmetric double-crossed ppnnppnn contact structure, the width of a single p region is 600-2000 μm, and the width of a single n region is 600-2000 μm; the width of a single isolation region between a p region and a p region or between an n region and an n region is 10-100 μm, and the width of a single isolation region between a p region and an n region is 40-300 μm.

[0031] Preferably, in the single symmetrical double crossed ppnppn contact structure prototype, the width of a single p region is 600-2000 μm, and the width of a single n region is ≤600 μm; the width of a single isolation region between a p region and a p region or between an n region and an n region is 10-100 μm, and the width of a single isolation region between a p region and an n region is 40-300 μm.

[0032] Preferably, in the single symmetrical double cross pnnpnn contact structure prototype, the width of a single p region is ≤600μm, and the width of a single n region is 600-2000μm; the width of a single isolation region between a p region and a p region or an n region and an n region is 10-100μm, and the width of a single isolation region between a p region and an n region is 40-300μm.

[0033] In the above three different schemes of the present invention, the width of the isolation region between the same doping type sub-gates (between pp or between nn) (10 to 100 μm) is narrower than the conventional width of the isolation region between different doping types (between pn) (40 to 300 μm), so that the poly-Si carrier collection area of ​​the entire silicon substrate is also larger, which is helpful to improve the values ​​such as FF.

[0034] Preferably, in S2, the mask layer is formed by ultraviolet oxidation laser treatment: first, a mask layer prototype is generated under the conditions of an oxygen concentration of 20-30% (volume concentration) and an ultraviolet laser wavelength of 300-400nm; and then a denser mask layer is formed under the conditions of an oxygen concentration of 30-80% (volume concentration) and an ultraviolet laser wavelength of 200-300nm.

[0035] The present invention has found in previous experiments that the density of the mask layer obtained by the conventional one-step ultraviolet laser oxidation process is not ideal, which will increase the risk of boron atoms and phosphorus atoms diffusing into the intrinsic polysilicon layer during the subsequent boron diffusion and phosphorus diffusion, thereby causing battery leakage or performance degradation. To this end, the present invention has designed the above-mentioned special distributed differentiated ultraviolet laser oxidation process, the principle of which is: different laser wavelengths penetrate into the silicon interior at different depths. In the first step of the above process of the present invention, the wavelength is larger and the penetration depth is deeper, which can initially form a thicker mask layer prototype; the second step has a shorter wavelength and a shallower penetration depth, which can make the mask layer prototype denser in texture while the thickness remains almost unchanged; at the same time, with different oxygen concentration processing environments, the formed mask layer can more effectively block the internal expansion of boron atoms and phosphorus atoms.

[0036] Further preferably, in S2, the conditions of the ultraviolet oxidation laser treatment are specifically: First, a mask layer prototype is generated under the conditions of an O2 flow rate of 10 to 100 sccm, an ambient oxygen concentration of 20 to 30% (volume concentration), an ultraviolet laser wavelength of 300 to 400 nm, a power of 10 to 500 W, and a processing time of 1 to 20 seconds; Then, under the conditions of O2 flow rate of 100-500sccm, ambient oxygen concentration of 30-80% (volume concentration), ultraviolet laser wavelength of 200-300nm, power of 2-50W, and processing time of 1-20s, a denser mask layer is formed.

[0037] Preferably, in S2, the thickness of the mask layer is 20-300 nm.

[0038] Preferably, in S2, the deposition conditions of the tunnel oxide layer are: O2 flow rate 10000-80000 sccm, reaction temperature 400-800°C, time 200-1000s, and tunnel oxide layer thickness 2-10nm.

[0039] Preferably, in S2, the deposition conditions of the intrinsic polysilicon layer are: Sim4 flow rate 300-2000sccm, reaction temperature 500-700°C, time 2-4h, working pressure 100-500mTorr, intrinsic polysilicon layer thickness 100-300nm. Preferably, in S3, S6, S9 and S10, the grooving conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / S, power 10-50W, processing time 1-5s.

[0040] Preferably, in S5, the boron diffusion conditions are: temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min.

[0041] Preferably, in S5, the thickness of the BSG layer is 30-70 nm.

[0042] Preferably, in S8, the conditions for phosphorus diffusion are: temperature 750-850°C, diffusion time 5-30 min, POCl3 is carried by nitrogen with a flow rate of 500-1200 sccm, and O2 flow rate 500-1000 sccm; oxidation advancement temperature 850-950°C, O2 flow rate 1000-10000 sccm, and advancement time 20-60 min.

[0043] Preferably, in S8, the thickness of the PSG layer is 30-70 nm.

[0044] Compared with the prior art, the beneficial effects of the present invention are: (1) The TBC solar cell prepared by the present invention has three different double cross contact structures of ppnnppnn or ppnppn or pnnpnn. This new structure can expand the width of the p region or n region during the initial graphic design, reduce the number of sub-grids designed on the initial silicon wafer surface, and thus reduce the complexity and difficulty of graphic design. In addition, even if the isolation area between the subsequent sub-grids of the same doping type (between pp or between nn) is narrow or partially conductive, the impact of the short circuit can be ignored, reducing the risk of short circuit between the p region and the n region, and improving the battery performance. At the same time, since the width of the isolation area between the sub-grids of the same doping type (between pp or between nn) (10 to 100 μm) is narrower than the conventional width of the isolation area between the sub-grids of different doping types (between pn) (40 to 300 μm), the poly-Si carrier collection area of ​​the entire silicon substrate is also larger, which helps to improve the values ​​of FF and so on.

[0045] (2) The present invention adopts an ultraviolet laser oxidation process to construct a mask layer on the surface of the intrinsic polysilicon layer. Compared with conventional LPCVD deposition processes, the mask layer construction time can be greatly shortened, and the mask layer preparation efficiency and preparation accuracy can be improved. In addition, the ultraviolet laser oxidation process of the present invention has a distributed differentiation characteristic. Compared with the one-step process, the obtained mask layer has a higher density and can more effectively block the inward expansion of boron atoms and phosphorus atoms, thereby improving battery performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 11. A structural comparison diagram of a conventional single cross TBC solar cell (a: pnpnpn structure) and three different double cross contact structure TBC solar cells of the present invention (b: ppnnppnn structure, c: ppnppn structure, d: pnnpnn structure).

[0047] Figure 2 Schematic diagram of the structure of the silicon wafer after double-sided polishing.

[0048] Figure 3 Schematic diagram of the structure after forming a tunnel oxide layer, an intrinsic polysilicon layer and a mask layer for a silicon wafer.

[0049] Figure 4 This is a schematic diagram of the structure of the silicon wafer after one-time laser grooving and cleaning.

[0050] Figure 5 Schematic diagram of the structure after boron diffusion of silicon wafer.

[0051] Figure 6 This is a schematic diagram of the structure of the silicon wafer after laser secondary patterning grooving + cleaning.

[0052] Figure 7 Schematic diagram of the structure of the silicon wafer after phosphorus diffusion.

[0053] Figure 8 This is a schematic diagram of the silicon wafer structure after laser triple patterning grooving and laser quadruple patterning grooving + cleaning and texturing.

[0054] Fig. 9 Schematic diagram of the structure of a double cross-contact TBC solar cell.

[0055] The reference numerals are: N-type single crystal silicon wafer 1, tunneling oxide layer 2, intrinsic polysilicon layer 3, mask layer 4, boron diffusion layer 5, BSG layer 6, phosphorus diffusion layer 7, PSG layer 8, pyramid velvet surface 9, passivation anti-reflection layer 10, electrode layer 11. DETAILED DESCRIPTION

[0056] The present invention will be further described below in conjunction with the embodiments.

[0057] A method for preparing a double cross-contact structure TBC solar cell specifically comprises the following steps: S1, double-sided polishing of a silicon wafer.

[0058] In some specific implementation cases, an N-type single crystal silicon wafer 1 after diamond wire cutting is selected, with a thickness of 150 μm. The silicon wafer is placed in an alkaline polishing tank, the temperature is maintained at 75-85°C, and the time is 6-8 minutes for double-sided polishing, the polishing thickness is 3-7 μm, and the thinning amount is 0.35-0.45g. Figure 2 shown.

[0059] S2, forming a tunneling oxide layer 2 (using LPCVD), an intrinsic polysilicon layer 3 (using LPCVD), and a mask layer 4 in sequence on the back side of the N-type single crystal silicon wafer 1, such as Figure 3 shown.

[0060] The purpose of setting the mask layer is to block the doping atoms from entering the intrinsic polysilicon layer at the bottom thereof during the subsequent boron diffusion and phosphorus diffusion processes.

[0061] In some specific implementation cases, the thickness of the mask layer is 20 to 300 nm.

[0062] In some specific implementation cases, the deposition conditions of the tunnel oxide layer are: O2 flow rate 10000-80000 sccm, reaction temperature 400-800°C, time 200-1000s, and tunnel oxide layer thickness 2-10nm.

[0063] In some specific implementation cases, the deposition conditions of the intrinsic polysilicon layer are: Sim4 flow rate 300-2000sccm, reaction temperature 500-700°C, time 2-4h, working gas pressure 100-500mTorr, and intrinsic polysilicon layer thickness 100-300nm.

[0064] In some specific implementation cases, the mask layer is formed by ultraviolet oxidation laser processing: first, a mask layer prototype is generated under the conditions of an oxygen concentration of 20-30% (volume concentration) and an ultraviolet laser wavelength of 300-400nm; then, a denser mask layer is formed under the conditions of an oxygen concentration of 30-80% (volume concentration) and an ultraviolet laser wavelength of 200-300nm.

[0065] In some more preferred implementation cases, in S2, the conditions of the ultraviolet oxidation laser treatment are specifically as follows: first, a mask layer prototype is generated under the conditions of an O2 flow rate of 10 to 100 sccm, an ambient oxygen concentration of 20 to 30% (volume concentration), an ultraviolet laser wavelength of 300 to 400 nm, a power of 10 to 500 W, and a processing time of 1 to 20 s; then, a denser mask layer is formed under the conditions of an O2 flow rate of 100 to 500 sccm, an ambient oxygen concentration of 30 to 80% (volume concentration), an ultraviolet laser wavelength of 200 to 300 nm, a power of 2 to 50 W, and a processing time of 1 to 20 s.

[0066] S3. Laser one-time patterning and grooving to remove the mask layer in the designed area of ​​the boron diffusion layer region (p region).

[0067] In some specific implementation cases, the grooving conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0068] S4, alkaline cleaning to remove the residual mask layer 4 in the groove area, so that the intrinsic polysilicon layer 3 is exposed, such as Figure 4 shown.

[0069] In some specific implementation cases, the silicon wafer is placed in an alkaline solution for cleaning at a temperature of 75 to 85°C. During the experiment, by adjusting different parameters such as cleaning time and using an ellipsometer to test the thickness of the mask layer after cleaning, the mask layer in the patterned area can be accurately removed to prevent excessive removal of the bottom intrinsic polysilicon layer during the alkaline cleaning process.

[0070] S5, boron diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the grooved area are respectively converted into a boron diffusion layer 5 and a BSG layer 6. In the above boron diffusion process, the S3 ungrooved area can effectively block the boron atoms from entering the intrinsic polysilicon layer 3 due to the protection of the mask layer 4, and only the inner layer and the surface layer of the exposed intrinsic polysilicon layer 3 are respectively converted into a boron diffusion layer 5 and a BSG layer 6. Figure 5 shown.

[0071] In some specific implementation cases, the boron diffusion conditions are: temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min. The thickness of the resulting BSG layer is 30-70 nm.

[0072] S6, laser secondary patterning and grooving the remaining mask layer 4 region. The purpose of grooving the remaining mask layer 4 region is to cooperate with the subsequent alkaline cleaning to expose the surface of the remaining intrinsic polysilicon layer 3.

[0073] In some specific implementation cases, the grooving conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0074] S7, alkaline cleaning removes the residual mask layer 4 in the groove area S6, so that the surface of the remaining intrinsic polysilicon layer 3 is exposed, and the boron diffusion layer 5 is protected from corrosion under the protection of the BSG layer 6 on its surface, such as Figure 6 shown.

[0075] In some specific implementation cases, the silicon wafer is placed in an alkaline solution for cleaning at a temperature of 75 to 85°C. During the experiment, by adjusting different parameters such as cleaning time and using an ellipsometer to test the thickness of the mask layer after cleaning, the mask layer in the patterned area can be accurately removed to prevent excessive removal of the bottom intrinsic polysilicon layer during the alkaline cleaning process.

[0076] S8, phosphorus diffusion, so that the inner layer and the surface layer of the remaining intrinsic polysilicon layer 3 are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8. In the above phosphorus diffusion process, since the surface of the boron diffusion layer 5 is protected by the BSG layer 6, the phosphorus atoms cannot effectively diffuse into the boron diffusion layer 5, and only the inner layer and the surface layer of the exposed remaining intrinsic polysilicon layer 3 are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8. Figure 7 shown.

[0077] In some specific implementation cases, the phosphorus diffusion conditions are: temperature 750-850°C, diffusion time 5-30 min, POCl3 carried by nitrogen with a flow rate of 500-1200 sccm, O2 flow rate 500-1000 sccm; oxidation advancement temperature 850-950°C, O2 flow rate 1000-10000 sccm, advancement time 20-60 min. The thickness of the obtained PSG layer is 30-70 nm.

[0078] S9, laser patterning is performed three times to groove the interface between the BSG layer 6 and the PSG layer 8, and the BSG layer 6 and the PSG layer 8 in the grooved area are removed. Grooving at the interface between the BSG layer 6 (i.e., the boron diffusion layer 5) and the PSG layer 8 (i.e., the phosphorus diffusion layer 7) can pave the way for the subsequent formation of an insulating isolation area.

[0079] In some specific implementation cases, the grooving conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0080] S10, laser patterning and slotting each remaining BSG layer and the middle area of ​​the PSG layer (ie, the isolation area designed between the n-region or the p-region) four times to form a prototype of a double-symmetric double-crossed ppnnppnn contact structure.

[0081] In some specific implementation cases, in the prototype of the double-symmetric double-crossed ppnnppnn contact structure, the width of a single p-region is 600-2000 μm, and the width of a single n-region is 600-2000 μm; the width of a single isolation region between a p-region and a p-region or between an n-region and an n-region is 10-100 μm, and the width of a single isolation region between a p-region and an n-region is 40-300 μm.

[0082] Alternatively, the middle region of each remaining BSG layer (i.e., the isolation region design region between the n-region or the p-region) is laser patterned and grooved four times to form a prototype of a single symmetrical double cross ppnppn contact structure.

[0083] In some specific implementation cases, in the single symmetrical double cross ppnppn contact structure prototype, the width of a single p region is 600 to 2000 μm, and the width of a single n region is ≤ 600 μm; the width of a single isolation region between a p region and a p region or between an n region and an n region is 10 to 100 μm, and the width of a single isolation region between a p region and an n region is 40 to 300 μm.

[0084] Alternatively, the middle region of each remaining PSG layer (i.e., the isolation region design region between the n-region or the p-region) is laser patterned and grooved four times to form a prototype of a single symmetrical double cross pnnpnn contact structure.

[0085] In some specific implementation cases, in the single symmetrical double cross pnnpnn contact structure prototype, the width of a single p region is ≤600μm, and the width of a single n region is 600-2000μm; the width of a single isolation region between a p region and a p region or an n region and an n region is 10-100μm, and the width of a single isolation region between a p region and an n region is 40-300μm.

[0086] In some specific implementation cases, the grooving conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0087] S11, removing the coating on the front and side surfaces of the silicon wafer.

[0088] In some specific implementation cases, a chain machine (acid etching) is used to remove the boron diffusion layer and phosphorus diffusion layer and other coating layers on the front and side surfaces of the silicon wafer.

[0089] S12, cleaning and texturing, removing the BSG layer and the PSG layer.

[0090] In some specific implementation cases, the front and back laser grooved areas of the silicon wafer are first wet cleaned and texturized in an integrated manner in an alkaline solution. Since the plating layer on the front side of the silicon wafer has been completely removed and there is no oxidation area, an effective light-trapping velvet surface (i.e., pyramid velvet surface 9) can be formed during the texturizing process; and in the back laser three-time patterned grooved area, the alkaline solution can effectively corrode the bottom deposition layer, thereby forming an isolation area, and a pyramid velvet surface 9 is formed on the surface of the isolation area, and the non-laser area can further block alkaline corrosion due to the presence of the PSG layer / BSG layer. For the middle grooved area of ​​the BSG layer and the middle grooved area of ​​the PSG layer that are laser four-time patterned, the boron diffusion layer and the phosphorus diffusion layer of the corresponding area can be washed away during the alkaline texturizing process, so that the initial boron diffusion layer and the phosphorus diffusion layer are equally spaced and divided into two, forming three different contact structures. The subsequent acid (HF / HCl) cleaning tank of the texturizing tank body can further remove the PSG layer and the BSG layer remaining on the surface of the silicon wafer, such as Figure 8 shown.

[0091] S13, double-sided coating: After double-sided coating, a passivation anti-reflection layer 10 is formed on the front and back sides of the silicon wafer.

[0092] S14, screen printing, sintering to form electrode layer 11, light injection, to obtain a double cross contact structure TBC solar cell, such as Figure 1 (b) and Fig. 9 shown.

[0093] Specific examples and comparative examples.

[0094] Example 1 (double symmetric double cross ppnnppnn contact structure) A method for preparing a double cross-contact structure TBC solar cell specifically comprises the following steps: S1. Double-sided polishing of silicon wafer: Select N-type single crystal silicon wafer 1 after diamond wire cutting, with a thickness of 150μm. Put the silicon wafer into the alkaline polishing tank, maintain the temperature at 75℃, and perform double-sided polishing for 6 minutes. The polishing thickness is 4μm, and the thinning amount is 0.42g. Figure 2 shown.

[0095] S2, forming a tunneling oxide layer 2 (using LPCVD), an intrinsic polysilicon layer 3 (using LPCVD), and a mask layer 4 in sequence on the back side of the N-type single crystal silicon wafer 1, such as Figure 3 As shown. Among them: The deposition conditions of the tunnel oxide layer are: O2 flow rate 40000sccm, reaction temperature 600°C, time 600s, and the thickness of the tunnel oxide layer is about 3nm.

[0096] The deposition conditions of the intrinsic polysilicon layer are: SiHH4 flow rate 920sccm, reaction temperature 550°C, time 3.3h, working gas pressure 300mTorr, and the thickness of the intrinsic polysilicon layer is about 290nm.

[0097] The mask layer is formed by ultraviolet oxidation laser treatment: first, a mask layer prototype is generated under the conditions of O2 flow rate 50sccm, ambient oxygen concentration 25% (volume concentration), ultraviolet laser wavelength 355nm, power 11W, and processing time 10s; then, a denser mask layer (thickness of about 50nm) is formed under the conditions of O2 flow rate 200sccm, ambient oxygen concentration 50% (volume concentration), ultraviolet laser wavelength 266nm, power 3W, and processing time 17s.

[0098] S3, laser one-time patterning groove to remove the mask layer in the designed area of ​​the boron diffusion layer. The groove conditions are: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / S, power 25W, processing time 2.7s.

[0099] S4, alkaline cleaning to remove the residual mask layer 4 in the groove area, so that the intrinsic polysilicon layer 3 is exposed, such as Figure 4 The specific steps are as follows: put the silicon wafer into an alkaline solution for cleaning at a temperature of 75°C. During the experiment, by adjusting different parameters such as cleaning time, and using an ellipsometer to test the thickness of the mask layer after cleaning, the mask layer in the patterned area can be accurately removed, so that the bottom intrinsic polysilicon layer will not be removed too much during the alkaline cleaning process.

[0100] S5, boron diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the grooved area are converted into a boron diffusion layer 5 and a BSG layer 6 respectively. The conditions for boron diffusion are: temperature 850°C, diffusion time 10min, BCl3 flow rate 200sccm, O2 flow rate 1200sccm; oxidation advancement temperature 950°C, O2 flow rate 7000sccm, advancement time 30min. The thickness of the BSG layer is about 45nm. In the above-mentioned boron diffusion process, the S3 ungrooved area can effectively block boron atoms from entering the intrinsic polysilicon layer 3 due to the protection of the mask layer 4, and only the inner layer and the surface layer of the exposed intrinsic polysilicon layer 3 are converted into a boron diffusion layer 5 and a BSG layer 6 respectively, as shown in FIG. Figure 5 shown.

[0101] S6. Laser secondary patterning grooves are formed in the remaining mask layer 4 area. The purpose of groove forming in the remaining mask layer 4 area is to cooperate with the subsequent alkali cleaning to expose the surface of the remaining intrinsic polysilicon layer 3. The groove forming conditions are: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / s, power 25W, and processing time 2.7s.

[0102] S7, alkaline cleaning removes the residual mask layer 4 in the groove area S6, so that the surface of the remaining intrinsic polysilicon layer 3 is exposed, and the boron diffusion layer 5 is protected from corrosion under the protection of the BSG layer 6 on its surface, such as Figure 6 The specific steps are as follows: put the silicon wafer into an alkaline solution for cleaning at a temperature of 75°C. During the experiment, by adjusting different parameters such as cleaning time, and using an ellipsometer to test the thickness of the mask layer after cleaning, the mask layer in the patterned area can be accurately removed, so that the bottom intrinsic polysilicon layer will not be removed too much during the alkaline cleaning process.

[0103] S8, phosphorus diffusion, so that the inner layer and the surface layer of the remaining intrinsic polysilicon layer 3 are converted into the phosphorus diffusion layer 7 and the PSG layer 8 respectively. The conditions for phosphorus diffusion are: temperature 790°C, diffusion time 20min, POCl3 carried by nitrogen with a flow rate of 1100sccm, O2 flow rate 700sccm; oxidation advancement temperature 890°C, O2 flow rate 3000sccm, advancement time 40min. The thickness of the PSG layer is about 42nm. In the above-mentioned phosphorus diffusion process, since the surface of the boron diffusion layer 5 is protected by the BSG layer 6, the phosphorus atoms cannot diffuse into the boron diffusion layer 5, and only the inner layer and the surface layer of the exposed remaining intrinsic polysilicon layer 3 are converted into the phosphorus diffusion layer 7 and the PSG layer 8 respectively, as shown Figure 7 shown.

[0104] S9, laser patterning grooves are made three times at the junction of BSG layer 6 and PSG layer 8 to remove the BSG layer 6 and PSG layer 8 in the grooved area, and the groove width is 80μm. Grooving at the junction of BSG layer 6 (i.e., boron diffusion layer 5) and PSG layer 8 (i.e., phosphorus diffusion layer 7) can pave the way for the subsequent formation of an insulating isolation area. The groove conditions are: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / S, power 50W, and processing time 3s.

[0105] S10, laser patterning grooves are made four times in the middle area of ​​each remaining BSG layer 6 and PSG layer 8 (i.e., the isolation area design area between the n-region or p-region) to form a double symmetrical double cross ppnnppnn contact structure prototype. Among them, the width of a single p-region in the double symmetrical double cross ppnnppnn contact structure prototype is 800μm, and the width of a single n-region is 800μm; the width of a single isolation area between a p-region and a p-region or an n-region and an n-region is 30μm, and the width of a single isolation area between a p-region and an n-region is 80μm. The groove conditions are: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / s, power 50W, and processing time 3s.

[0106] S11. Removing the coating on the front and side surfaces of the silicon wafer: using a chain machine (acid etching) to remove the coatings such as the boron diffusion layer and the phosphorus diffusion layer on the front and side surfaces of the silicon wafer.

[0107] S12, cleaning and texturing, removing the BSG layer and the PSG layer.

[0108] In some specific implementation cases, the front and back laser grooved areas of the silicon wafer are first wet cleaned and texturized in an integrated manner in an alkaline solution. Since the plating layer on the front side of the silicon wafer has been completely removed and there is no oxidation area, an effective light-trapping velvet surface (i.e., pyramid velvet surface 9) can be formed during the texturizing process; and in the back laser triple-patterned grooved area, the alkaline solution can effectively corrode the bottom deposition layer, thereby forming an insulating isolation area velvet surface (i.e., pyramid velvet surface 9) area, and the non-laser area can further block alkaline corrosion due to the presence of the PSG layer / BSG layer. For the middle grooved area of ​​the BSG layer and the middle grooved area of ​​the PSG layer that are laser-patterned four times, the boron diffusion layer and the phosphorus diffusion layer of the corresponding area can be washed away during the alkaline texturizing process, so that the initial boron diffusion layer and the phosphorus diffusion layer are equally spaced and divided into two, forming a double-symmetric double-crossed ppnnppnn contact structure. The subsequent acid (HF / HCl) cleaning tank of the texturizing tank body can further remove the PSG layer and BSG layer remaining on the surface of the silicon wafer, such as Figure 8 shown.

[0109] S13, double-sided coating. After double-sided coating, a passivation anti-reflection layer 10 is formed on the front and back sides of the silicon wafer, specifically comprising: using atomic layer deposition ALD to first deposit AlO on the front and back sides of the processed silicon wafer; x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8nm, and the process temperature is controlled at 250℃. Then SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x Thin film, SiN x The thickness of the film is about 90nm and the refractive index is 2.0. x During thin film deposition, the reaction gases in the tubular chamber are SiH4 and NH3, the working pressure is 1600mTorr, the power is 12000W, the temperature is 440℃, the flow rate of Sim4 gas is 980sccm, the flow rate of NH3 gas is 8000sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10min.

[0110] S14, screen printing, sintering to form electrode layer 11, light injection: the coated silicon wafer is screen printed on the back to form a metal contact, then sintered at 770°C to form an Ag-Si ohmic contact (i.e., electrode layer 11), and finally repaired by light injection to obtain a double cross contact structure TBC solar cell, such as Figure 1 (b) and Fig. 9 shown.

[0111] Example 2 (Single Symmetric Double Cross PPnPPn Contact Structure) The difference between Example 2 and Example 1 is that in S10, the laser is patterned and grooved four times in the middle area of ​​each remaining BSG layer (i.e., the isolation area between the n-region or the p-region) to form a single symmetrical double cross ppnppn contact structure prototype (such as Figure 1 (c)). In the prototype of the single symmetrical double cross ppnppn contact structure, the width of a single p region is 800 μm, the width of a single n region is 400 μm; the width of a single isolation region is 30 μm, and the width of a single isolation region between the p region and the n region is 80 μm.

[0112] Example 3 (Prototype of a single symmetrical double cross pnnpnn contact structure) The difference between Example 3 and Example 1 is that in S10, the middle region of each remaining PSG layer (i.e., the isolation region between the n-region or the p-region) is patterned by laser four times to form a single symmetrical double cross pnnpnn contact structure prototype (such as Figure 1 (d)). In the prototype of the single symmetrical double cross pnnpnn contact structure, the width of a single p region is 400 μm, and the width of a single n region is 800 μm; the width of a single isolation region between a p region and a p region or between an n region and an n region is 30 μm, and the width of a single isolation region between a p region and an n region is 80 μm.

[0113] Comparative Example 1 The structure of the TBC solar cell of Comparative Example 1 is as follows Figure 1 (a) shows a conventional single cross-structure TBC solar cell, specifically a pnpnpnpn contact structure, in which the width of a single p region is 400 μm, the width of a single n region is 400 μm, and the width of all isolation regions is 80 μm.

[0114] Example 4 The only difference between Example 4 and Example 1 is that in S2, the mask layer is generated by conventional LPCVD method: O2 flow rate is 50000sccm, temperature is 650°C, time is 2800s, and the thickness of the deposited mask layer is about 50nm.

[0115] Example 5 The only difference between Example 5 and Example 1 is that in S2, the mask layer is generated by a one-step ultraviolet laser oxidation process: the wavelength of the ultraviolet laser used is 355nm, the power is 11W, the O2 flow rate through the tube is 50sccm, the oxygen concentration in the environment is 25% (volume ratio), the oxidation treatment time is 10s, and a mask layer with a thickness of about 50nm is formed.

[0116] Performance Testing The TBC solar cells obtained in the above-mentioned embodiments and comparative examples were tested for various properties, and the results are shown in the following table: Table 1: Electrical performance data of different batteries Serial number η(%) <![CDATA[V oc (mV)]]> <![CDATA[J sc (mA / cm 2 )]]> FF(%) Irev(A) Example 1 26.85 744.6 42.57 84.71 0.27 Comparative Example 1 26.43 743.5 42.35 83.94 1.23 Example 2 26.79 744.3 42.55 84.59 0.43 Example 3 26.72 744.2 42.51 84.46 0.45 Example 4 26.57 743.8 42.39 84.27 0.56 Example 5 26.63 743.9 42.44 84.35 0.51 From the comparison of the data in the above table, we can see that: First, Examples 1-5 use three different forms of double cross-contact structures. Compared with Comparative Example 1, the number of isolation regions between the p-region and the n-region in the embodiments is smaller, and the risk of short-circuit leakage between sub-gates of the same doping type (between pp or between nn) is negligible, so that the short-circuit leakage value of the battery in the overall embodiment is lower and the electrical performance is better.

[0117] Secondly, compared with Examples 2-3, Example 1 adopts a double symmetrical double cross contact structure, so the number of isolation regions between the p-region and the n-region is smaller, the number of initial patterned sub-gates is also smaller, and the design technology complexity and difficulty are lower; in addition, since the width of the isolation region between sub-gates of the same doping type (between pp or between nn) (10-100 μm) is narrower than the width of the isolation region between conventional sub-gates of different doping types (between pn) (40-300 μm), the poly-Si carrier collection area of ​​the entire silicon substrate of Example 1 is larger than that of Examples 2-3, so the J of the battery is sc , FF and other values ​​are higher.

[0118] As for Examples 2 and 3, since the gold / semi-contact performance of the p-region is often weaker than that of the n-region, increasing the proportion of the initial p-region is more beneficial to the overall battery carrier collection probability; therefore, compared with Example 3, Example 2 has a higher p-region proportion, thereby better contact performance, making the overall battery performance better.

[0119] For Example 4, compared with Example 1, the process of forming the mask layer by LPCVD has a longer process time and a higher temperature, making it difficult to accurately control the process stability. In addition, the front-side plating problem caused by the LPCVD method also exists, resulting in low battery electrical performance.

[0120] For Example 5, since the differentiation of the mask layer generated by the one-step UV laser oxidation process is not obvious compared with Example 1, some mask layers are not dense enough, resulting in the inevitable risk of excessive internal expansion of some doping atoms during the high-temperature process, which also reduces the electrical performance (but overall it is still better than Example 4).

[0121] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0122] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a double cross-contact structure TBC solar cell, characterized in that include: S1, silicon wafer polishing; S2, forming a tunneling oxide layer, an intrinsic polysilicon layer, and a mask layer on the back side; S3, laser slotting boron diffusion layer area design area mask layer; S4, alkali cleaning; S5, boron diffusion, so that the intrinsic polysilicon layer in the groove area is converted into a boron diffusion layer and a BSG layer; S6, laser grooving to remove the remaining mask layer; S7, alkali cleaning; S8, phosphorus diffusion, so that the remaining intrinsic polysilicon layer is converted into a phosphorus diffusion layer and a PSG layer; S9, laser grooving the interface between the BSG layer and the PSG layer; S10, laser grooving the middle region of the BSG layer and / or the PSG layer to form a double cross contact structure prototype; S11, go around the plating; S12, cleaning and velveting; S13, double-sided coating; S14, screen printing, sintering, light injection.

2. The preparation method according to claim 1, characterized in that: In S10, laser grooves are formed in the middle area of ​​each remaining BSG layer and PSG layer to form a prototype of a double-symmetric double-crossed ppnnppnn contact structure, in which the width of a single p-region is 600~2000 μm, and the width of a single n-region is 600~2000 μm; the width of a single isolation region located between a p-region and a p-region or an n-region and an n-region is 10~100 μm, and the width of a single isolation region located between a p-region and an n-region is 40~300 μm.

3. The preparation method according to claim 1, characterized in that: In S10, a laser groove is formed in the middle area of ​​each remaining BSG layer to form a prototype of a monosymmetrical double cross ppnppn contact structure, wherein the width of a single p region is 600~2000 μm, and the width of a single n region is ≤600 μm; the width of a single isolation region located between a p region and a p region or an n region and an n region is 10~100 μm, and the width of a single isolation region located between a p region and an n region is 40~300 μm.

4. The preparation method according to claim 1, characterized in that: S10. Laser groove the middle area of ​​each remaining PSG layer to form a prototype of a single symmetrical double cross pnnpnn contact structure, in which the width of a single p region is ≤600 μm, and the width of a single n region is 600~2000 μm; the width of a single isolation region between a p region and a p region or an n region and an n region is 10~100 μm, and the width of a single isolation region between a p region and an n region is 40~300 μm.

5. The preparation method according to claim 1, characterized in that: In S2, the mask layer is formed by ultraviolet laser oxidation treatment: First, a mask layer prototype is generated under the conditions of an oxygen concentration of 20-30% and an ultraviolet laser wavelength of 300-400 nm; Then, a denser mask layer is formed under the conditions of an oxygen concentration of 30-80% and an ultraviolet laser wavelength of 200-300 nm.

6. The preparation method according to claim 5, characterized in that: In S2, the conditions of the ultraviolet oxidation laser treatment are specifically: First, a mask layer prototype is generated under the conditions of an O2 flow rate of 10-100 sccm, an ambient oxygen concentration of 20-30%, an ultraviolet laser wavelength of 300-400 nm, a power of 10-500 W, and a processing time of 1-20 s; Then, under the conditions of O2 flow rate of 100~500 sccm, ambient oxygen concentration of 30~80%, UV laser wavelength of 200~300 nm, power of 2~50 W, and processing time of 1~20 s, a denser mask layer is formed.

7. The preparation method according to claim 1, characterized in that: In S2, the deposition conditions of the tunnel oxide layer are: O2 flow rate 10000~80000 sccm, reaction temperature 400~800°C, time 200~1000 s, and tunnel oxide layer thickness 2~10 nm.

8. The preparation method according to claim 1, characterized in that: In S2, the deposition conditions of the intrinsic polysilicon layer are: SiH4 flow rate 300~2000 sccm, reaction temperature 500~700°C, time 2~4 h, working gas pressure 100~500 mTorr, and intrinsic polysilicon layer thickness 100~300 nm.

9. The preparation method according to claim 1, characterized in that: In S5, the conditions for boron diffusion are: temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min; the thickness of the BSG layer is 30-70 nm.

10. The preparation method according to claim 1, characterized in that: In S8, the conditions for the phosphorus diffusion are: temperature 750-850°C, diffusion time 5-30 min, POCl3 is carried by nitrogen with a flow rate of 500-1200 sccm, and O2 flow rate 500-1000 sccm; oxidation advancement temperature 850-950°C, O2 flow rate 1000-10000 sccm, advancement time 20-60 min; the thickness of the PSG layer is 30-70 nm.

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