Deep ultraviolet Micro-LED array chip and preparation method thereof

Abstract

The invention discloses a deep ultraviolet Micro-LED array chip and a preparation method, and belongs to the technical field of semiconductors. The deep ultraviolet Micro-LED array chip comprises: an electron providing layer; each array unit comprises a multi-quantum well active layer, an electron blocking layer and a hole providing layer which are sequentially arranged on the electron providing layer in a stacked mode in the longitudinal direction, through holes longitudinally penetrating through the array units are formed in the array units, and the transverse sections of the array units and the transverse sections of the through holes are hexagonal; the plurality of first electrodes are positioned on the corresponding array units and are connected with the hole providing layers in the corresponding array units; the plurality of second electrodes are positioned in the through holes of the corresponding array units and are connected with the electron providing layer; the transverse section of each second electrode is hexagonal, and the first electrodes are arranged around the corresponding second electrodes; the first interconnection layer is connected with the plurality of first electrodes; and the second interconnection layer is connected with the plurality of second electrodes. According to the invention, absorption loss can be reduced, light extraction efficiency is improved, and chip reliability is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a deep ultraviolet Micro-LED array chip and a preparation method thereof. Background Art

[0002] AlGaN-based deep ultraviolet light-emitting diodes (LEDs) are considered to be a new generation of deep ultraviolet light sources due to their non-toxicity, low power consumption, small size and long life. Deep ultraviolet LEDs have potential application value in sterilization, sewage treatment, day-blind communication and medical phototherapy.

[0003] At present, the external quantum efficiency and electro-optical conversion efficiency of deep ultraviolet LEDs are low, which limits their widespread application. The epitaxial layer of deep ultraviolet LEDs has a reabsorption effect on deep ultraviolet emission light, and a large number of laterally propagating photons are absorbed before being extracted from the chip. This not only limits the light output power of deep ultraviolet LED chips, but the heat energy converted after the photons are absorbed also causes the chip temperature to rise, which in turn reduces the chip reliability. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a deep ultraviolet Micro-LED array chip and a preparation method, which can reduce absorption loss, improve light extraction efficiency, and improve chip reliability.

[0005] In a first aspect, the present application provides a deep ultraviolet Micro-LED array chip, comprising:

[0006] Electron supply layer;

[0007] A plurality of array units are arranged in an array at intervals, wherein the array unit comprises a multi-quantum well active layer, an electron blocking layer and a hole supplying layer which are sequentially stacked on the electron supplying layer in a longitudinal direction, wherein the array unit has a through hole which passes through the array unit in a longitudinal direction, and the transverse cross-sections of the array unit and the through hole are respectively hexagonal;

[0008] A plurality of first electrodes are arranged corresponding to the plurality of array units one by one, wherein the first electrodes are located on corresponding array units and connected to the hole supply layer in the corresponding array units;

[0009] A plurality of second electrodes are arranged corresponding to the plurality of array units one by one, the second electrodes are located in the through holes of the corresponding array units and connected to the electron supply layer; the transverse cross-section of the second electrodes is hexagonal, and the first electrodes are arranged around the corresponding second electrodes;

[0010] A first interconnection layer, located between the plurality of array units and connected to the plurality of first electrodes;

[0011] The second interconnection layer is located at a side of the second electrode away from the electron supply layer and is connected to the plurality of second electrodes.

[0012] According to the deep ultraviolet Micro-LED array chip of the present application, the chip is pixelated into a plurality of array units distributed at array intervals, and the lateral cross-section of the array unit is hexagonal, thereby reducing the absorption of lateral deep ultraviolet light by the epitaxial material, reducing absorption losses, and improving light extraction efficiency. A second electrode is arranged in the array unit to form an array-distributed second electrode, and the lateral cross-section of the second electrode is hexagonal, thereby alleviating the current concentration effect, improving the current distribution performance, and improving the chip reliability.

[0013] According to one embodiment of the present application, the deep ultraviolet Micro-LED array chip further includes:

[0014] A reflector is located on the side wall of the through hole and the side wall of the array unit.

[0015] According to an embodiment of the present application, the reflector includes a plurality of refractive layers stacked together, the plurality of refractive layers include first refractive layers and second refractive layers that are alternately distributed, and the first refractive layers and the second refractive layers have different refractive indices.

[0016] According to one embodiment of the present application, the thickness of the refractive layer is Wherein, λ is the central wavelength of the excitation light, and n is the refractive index of the refractive layer.

[0017] According to one embodiment of the present application, the deep ultraviolet Micro-LED array chip further includes:

[0018] A first insulating layer covers the first interconnection layer and the plurality of second electrodes, wherein the second interconnection layer is located on the first insulating layer and vertically penetrates the first insulating layer to be connected to the second electrodes;

[0019] a second insulating layer, covering the second interconnect layer and the first insulating layer;

[0020] a first pad, longitudinally penetrating the first insulating layer and the second insulating layer and connected to the first interconnection layer;

[0021] The second pad vertically penetrates the second insulating layer and is connected to the second interconnection layer.

[0022] According to an embodiment of the present application, the spacing between adjacent array units is smaller than the lateral dimension of the array unit.

[0023] According to one embodiment of the present application, the lateral dimension of the array unit is 110-210 μm; and / or,

[0024] The lateral dimension of the through hole is 20-40 μm; and / or,

[0025] The angle between the side wall of the array unit and the upper surface of the electron supply layer is 40°-50°, and the upper surface of the electron supply layer is parallel to the transverse direction and perpendicular to the longitudinal direction; and / or,

[0026] The angle between the side wall of the through hole and the upper surface of the electron supply layer is 40°-50°.

[0027] In a second aspect, the present application provides a method for preparing a deep ultraviolet Micro-LED array chip, comprising:

[0028] Providing an epitaxial structure, the epitaxial structure comprising an electron supply layer, a multi-quantum well active layer, an electron blocking layer and a hole supply layer stacked in sequence along the longitudinal direction;

[0029] A plurality of array units are formed in the epitaxial structure and are distributed in an array, wherein the array unit comprises the multi-quantum well active layer, the electron blocking layer and the hole supply layer, and the array unit has a through hole that penetrates the array unit longitudinally, and the transverse cross-sections of the array unit and the through hole are respectively hexagonal;

[0030] A first electrode connected to the hole supply layer is formed on the array unit, and a second electrode connected to the electron supply layer is formed in the through hole; the second electrode has a hexagonal cross section, and the first electrode is arranged around the corresponding second electrode;

[0031] forming a first interconnection layer between the plurality of array units, wherein the first interconnection layer is connected to first electrodes on the plurality of array units;

[0032] A second interconnection layer is formed on a side of the second electrode away from the electron supply layer, and the second interconnection layer is connected to the second electrodes in the plurality of array units.

[0033] According to an embodiment of the present application, before forming a first electrode connected to the hole supply layer on the array unit and forming a second electrode connected to the electron supply layer in the through hole, the method further includes:

[0034] A reflector is formed on the outer surface of the array unit and the inner surface of the through hole, the first electrode is located on the side of the reflector away from the array unit, and vertically penetrates the reflector to be connected to the hole supply layer, and the second electrode is located in the through hole, and vertically penetrates the reflector to be connected to the electron supply layer.

[0035] According to one embodiment of the present application, before forming the second interconnect layer on the side of the second electrode facing away from the electron supply layer, the method further includes:

[0036] forming a first insulating layer covering the first interconnection layer and the second electrode, wherein the second interconnection layer is located on the first insulating layer and vertically penetrates the first insulating layer to be connected to the second electrodes in the plurality of array units;

[0037] The method further comprises:

[0038] forming a second insulating layer covering the second interconnect layer and the first insulating layer;

[0039] A first pad is formed that vertically penetrates the first insulating layer and the second insulating layer and is connected to the first interconnection layer, and a second pad is formed that vertically penetrates the second insulating layer and is connected to the second interconnection layer.

[0040] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0041] By pixelating the chip into a plurality of array units distributed at array intervals, and the lateral cross-section of the array unit is hexagonal, the absorption of lateral deep ultraviolet light by the epitaxial material is reduced, the absorption loss is reduced, and the light extraction efficiency is improved. A second electrode is arranged in the array unit to form an array-distributed second electrode, and the lateral cross-section of the second electrode is hexagonal, so as to alleviate the current concentration effect, improve the current distribution performance, and improve the chip reliability.

[0042] Reflectors are formed on the side walls of the array unit and the side walls of the through hole. The laterally propagating deep ultraviolet light is reflected by the reflectors and redirected to the top of the chip, further improving the light extraction efficiency of the deep ultraviolet Micro-LED array chip. The reflectors can also serve as a passivation layer to suppress leakage current and non-radiative recombination caused by sidewall etching damage, thereby improving the performance stability and reliability of the device.

[0043] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0045] Figure 1 It is a schematic diagram of a process for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0046] Figure 2This is one of the structural schematic diagrams of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0047] Figure 3 This is the second structural schematic diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0048] Figure 4 This is the third structural schematic diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0049] Figure 5 This is the fourth structural schematic diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0050] Figure 6 This is the fifth structural schematic diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0051] Figure 7 This is the sixth structural schematic diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0052] Figure 8 Schematic diagram of the structure of the reflector in the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0053] Fig. 9 This is the seventh structural schematic diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0054] Fig.10 This is the eighth structural schematic diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0055] Fig.11 This is the ninth structural diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0056] Fig.12 This is the tenth structural diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0057] Fig.13 This is the eleventh structural diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0058] Fig.14 This is the twelfth structural diagram of the method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application;

[0059] Fig.15 Schematic diagram of the structure of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0060] Fig.16 This is one of the microscope images of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0061] Fig.17 This is the second microscope image of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0062] Fig.18 This is the third microscope image of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0063] Fig.19 This is the fourth microscope image of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0064] Fig. 20 This is the fifth microscope image of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0065] Fig.21 This is the sixth microscope image of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application;

[0066] Fig. 22 This is a comparison chart of the light output power of the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application and the related technology.

[0067] Description of reference numerals:

[0068] 101. substrate; 102. buffer layer; 103. electron supply layer; 104. multi-quantum well active layer; 105. electron blocking layer; 106. hole supply layer; 107. through hole; 108. groove; 109. reflector; 110. second electrode; 111. first electrode; 112. first interconnect layer; 113. first insulating layer; 114. third opening; 115. second interconnect layer; 116. second insulating layer; 117. first contact hole; 118. second contact hole; 119. first pad; 120. second pad; 11. epitaxial structure; 12. array unit; 13a. first refractive layer; 13b. second refractive layer; 14. first opening; 15. second opening. DETAILED DESCRIPTION

[0069] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0070] The deep ultraviolet Micro-LED array chip and preparation method provided in the embodiments of the present application are described below with reference to the accompanying drawings.

[0071] Figure 1 A schematic flow chart of a method for preparing a deep ultraviolet Micro-LED array chip provided in an embodiment of the present application.

[0072] like Figure 1 As shown, the method for preparing a deep ultraviolet Micro-LED array chip provided in the embodiment of the present application includes steps 110 to 150.

[0073] Step 110 , providing an epitaxial structure, wherein the epitaxial structure includes an electron supply layer, a multi-quantum well active layer, an electron blocking layer and a hole supply layer which are stacked in sequence along the longitudinal direction.

[0074] Combination Figure 2 As shown, the epitaxial structure 11 may be formed on a substrate 101. In some embodiments, a substrate 101 is provided first, and then the epitaxial structure 11 is formed on the substrate 101. The substrate 101 may include a sapphire substrate or the like.

[0075] The epitaxial structure 11 includes an electron supply layer 103 , a multi-quantum well active layer 104 , an electron blocking layer 105 and a hole supply layer 106 stacked in sequence along the longitudinal direction X. In some embodiments, the epitaxial structure 11 may further include a buffer layer 102 , which is located between the substrate 101 and the electron supply layer 103 .

[0076] First, a buffer layer 102 is formed on a substrate 101 by a thin film deposition process. The thin film deposition process includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, etc. Then, an electron supply layer 103 is formed on the buffer layer 102 by a thin film deposition process, a multi-quantum well active layer 104 is formed on the electron supply layer 103, an electron blocking layer 105 is formed on the multi-quantum well active layer 104, and a hole supply layer 106 is formed on the electron blocking layer 105.

[0077] The buffer layer 102 may include AlN, the electron supply layer 103 may include n-AlGaN, the multi-quantum well active layer 104 may include AlGaN, the electron blocking layer 105 may include p-AlGaN, and the hole supply layer 106 may include p-GaN.

[0078] Step 120, forming a plurality of array units distributed in an array in the epitaxial structure, wherein the array unit comprises a multi-quantum well active layer, an electron blocking layer and a hole supply layer, and the array unit has a through hole that penetrates the array unit longitudinally, and the transverse cross-sections of the array unit and the through hole are respectively hexagonal.

[0079] Combination Figure 3 As shown, the epitaxial structure 11 is etched by photolithography and etching until the electron supply layer 103 is exposed, and a plurality of through holes 107 are formed, that is, the through holes 107 vertically penetrate the hole supply layer 106, the electron blocking layer 105 and the multi-quantum well active layer 104 in the direction X. The etching process includes an inductively coupled plasma etching process (ICP etching).

[0080] Figure 4 FIG. 1 is a top view of the epitaxial structure 11 and the through hole 107. Figure 4 As shown, a plurality of through holes 107 are distributed in an array. The transverse Y-section of the through hole 107 is a hexagon, which can be a regular hexagon. In some embodiments, the transverse Y-dimension of the through hole 107 is 20-40 μm. The transverse Y-dimension of the through hole 107 refers to the distance between two opposite vertices of the transverse Y-section (hexagon) of the through hole 107, that is, the diameter of the circumscribed circle of the hexagon.

[0081] In some embodiments, the longitudinal X-section of the through hole 107 is inverted trapezoidal, that is, the side wall of the through hole 107 is inclined in the direction away from the center of the through hole 107. The angle between the side wall of the through hole 107 and the upper surface of the electron supply layer 103 (the surface of the electron supply layer 103 close to the array unit 12) is 40°-50°. The upper surface of the electron supply layer 103 is parallel to the transverse direction Y and perpendicular to the longitudinal direction X.

[0082] Combination Figure 5 As shown, an etching process is used to etch the epitaxial structure 11 between the plurality of through holes 107 until the electron supply layer 103 is exposed, and a groove 108 is formed, that is, the groove 108 penetrates the hole supply layer 106, the electron blocking layer 105 and the multi-quantum well active layer 104 in the longitudinal direction X. The epitaxial structure 11 is divided into a plurality of array units 12 distributed in an array by the groove 108, that is, the array unit 12 includes the multi-quantum well active layer 104, the electron blocking layer 105 and the hole supply layer 106 which are sequentially stacked on the electron supply layer 103 along the longitudinal direction X.

[0083] Figure 6 FIG. 1 is a top view of the array unit 12, the through hole 107 and the groove 108. Figure 6As shown, a plurality of through holes 107 are located in a plurality of array units 12 in a one-to-one correspondence, and the through hole 107 is located at the center of the corresponding array unit 12. The transverse Y-section of the array unit 12 is a hexagon, and the hexagon may be a regular hexagon. The six sides of the transverse Y-section of the array unit 12 and the six sides of the transverse Y-section of its through hole 107 may be arranged in parallel in a one-to-one correspondence. In some embodiments, the transverse Y-dimension of the array unit 12 is 110-210 μm. The transverse Y-dimension of the array unit 12 refers to the distance between two opposite vertices of the transverse Y-section (hexagon) of the array unit 12, that is, the diameter of the circumscribed circle of the hexagon.

[0084] In some embodiments, the longitudinal X-section of the array unit 12 is a regular trapezoid, that is, the side wall of the array unit 12 is inclined toward the center of the array unit 12. The angle between the side wall of the array unit 12 and the upper surface of the electron supply layer 103 (the surface of the electron supply layer 103 close to the array unit 12) is 40°-50°.

[0085] In some embodiments, the spacing between adjacent array units 12 is smaller than the lateral dimension of the array unit 12 to prevent the spacing between the array units 12 from being too large and affecting the light emitting effect of the chip.

[0086] It should be noted that the order of forming the through hole 107 and the groove 108 is not specifically limited. The through hole 107 can be formed first and then the groove 108 in the epitaxial structure 11, or the groove 108 can be formed first and then the through hole 107 in the epitaxial structure 11, or the through hole 107 and the groove 108 can be formed simultaneously in the epitaxial structure 11.

[0087] In some embodiments, before forming a first electrode connected to the hole supply layer on the array unit and forming a second electrode connected to the electron supply layer in the through hole in step 130, the method further includes:

[0088] A reflector is formed on the outer surface of the array unit and the inner surface of the through hole. The first electrode is located on the side of the reflector away from the array unit and vertically penetrates the reflector to connect with the hole supply layer. The second electrode is located in the through hole and vertically penetrates the reflector to connect with the electron supply layer.

[0089] Combination Figure 7 As shown, a thin film deposition process (such as plasma enhanced chemical vapor deposition (PECVD)) is used to form a reflector 109 on the outer surface of the array unit 12 and the inner surface of the through hole 107, that is, the reflector 109 is located on the side wall and upper surface of the array unit 12 and the side wall and bottom surface of the through hole 107. The reflector 109 is also located on the electron supply layer 103 between multiple array units 12, that is, the reflector 109 is also located on the bottom surface of the groove 108. Among them, the reflector 109 can be a distributed Bragg reflector (DBR).

[0090] In some embodiments, in combination Figure 8 As shown, the reflector 109 includes a plurality of refractive layers stacked and arranged, and the plurality of refractive layers include first refractive layers 13a and second refractive layers 13b that are alternately distributed, and the refractive indexes of the first refractive layers 13a and the second refractive layers 13b are different. For example, the refractive index of the first refractive layer 13a is greater than the refractive index of the second refractive layer 13b, and the refractive layer of the bottom layer of the reflector 109 may be the first refractive layer 13a, and the refractive layer of the top layer may be the second refractive layer 13b. The first refractive layer 13a may include MgF2 or HfO2, and the second refractive layer 13b may include Al2O3, HfO2, or SiO2. For example, the reflector 109 may include MgF2 / Al2O3, MgF2 / HfO2, HfO2 / SiO2, or HfO2 / SiO2. It should be noted that the materials of different first refractive layers 13a may be the same or different. The materials of different second refractive layers 13b may be the same or different.

[0091] In some embodiments, the thickness of the refractive layer is determined by Wherein, d is the thickness of the refractive layer, λ is the central wavelength of the emitted deep ultraviolet light, and n is the refractive index of the refractive layer. For example, the reflector 109 is formed by alternatingly stacking four 25 nm thick HfO2 refractive layers and four 46 nm thick SiO2 refractive layers.

[0092] Then, combine Fig. 9 As shown, an etching process is used to etch the reflector 109 to form a plurality of first openings 14 and a plurality of second openings 15 in the reflector 109. The plurality of first openings 14 are arranged in one-to-one correspondence with the plurality of array units 12, and the first openings 14 are located above the corresponding array units 12 and penetrate the reflector 109 in the longitudinal direction X to expose the hole supply layer 106 in the corresponding array units 12. The plurality of second openings 15 are arranged in one-to-one correspondence with the through holes 107 of the plurality of array units 12, and the second openings 15 are located at the bottom of the corresponding through holes 107 and are connected to the corresponding through holes 107. The second openings 15 penetrate the reflector 109 in the longitudinal direction X to expose the electron supply layer 103 at the bottom of the through holes 107. The transverse Y section of the second openings 15 is hexagonal, and the first openings 14 are arranged around the corresponding second openings 15.

[0093] In this embodiment, a reflector 109 is formed on the sidewalls of the array unit 12 and the sidewalls of the through hole 107. The laterally propagating deep ultraviolet light is reflected by the reflector and redirected to the top of the chip, further improving the light extraction efficiency of the deep ultraviolet Micro-LED array chip. In addition, the reflector 109 can also serve as a passivation layer to suppress leakage current and non-radiative recombination caused by sidewall etching damage, thereby improving the performance stability and reliability of the device.

[0094] Step 130: forming a first electrode connected to the hole supply layer on the array unit, and forming a second electrode connected to the electron supply layer in the through hole; the transverse cross section of the second electrode is hexagonal, and the first electrode is arranged around the corresponding second electrode.

[0095] Combination Fig.10 As shown, a plurality of first electrodes 111 and a plurality of second electrodes 110 are formed by a thin film deposition process. The plurality of first electrodes 111 are arranged one-to-one with the plurality of array units 12, and are arranged one-to-one with the plurality of first openings 14. The first electrode 111 is filled in the corresponding first opening 14, and is connected to the hole supply layer 106 exposed by the corresponding first opening 14 (i.e., the hole supply layer 106 in the corresponding array unit 12). The second electrode 110 is arranged one-to-one with the through holes 107 of the plurality of array units 12, and is arranged one-to-one with the plurality of second openings 15. The second electrode 110 is filled in the corresponding through hole 107 and the corresponding second opening 15, and is connected to the electron supply layer 103 exposed by the corresponding second opening 15 (i.e., the electron supply layer 103 in the corresponding array unit 12). After the first electrode 111 and the second electrode 110 are formed, high temperature annealing is performed to form an ohmic contact.

[0096] Each array unit 12 corresponds to a first electrode 111 and a second electrode 110. The second electrode 110 is located at the center of the corresponding array unit 12, and the transverse Y-section of the second electrode 110 is hexagonal, and the longitudinal X-section of the second electrode 110 may be inverted trapezoidal. The first electrode 111 is arranged around the corresponding second electrode 110, and the first electrode 111 and the second electrode 110 are arranged at intervals. Among them, the first electrode 111 may be a p-electrode, and the second electrode 110 may be an n-electrode.

[0097] In this embodiment, the LED chip is pixelated into a hexagonal array unit 12 of appropriate size, which reduces the absorption of lateral deep ultraviolet light by the epitaxial material, reduces absorption damage, and improves light extraction efficiency.

[0098] Step 140: forming a first interconnection layer between the plurality of array units, and the first interconnection layer is connected to the first electrodes on the plurality of array units.

[0099] Combination Fig.11 As shown, a first interconnection layer 112 is formed between the plurality of array units 12 by using a thin film deposition process, and the first interconnection layer 112 covers the reflectors 109 between the plurality of array units 12 (i.e., the reflectors 109 on the sidewalls and bottom of the groove 108) and the first electrodes 111 on the plurality of array units 12, so that all the first electrodes 111 are connected through the first interconnection layer 112. The first interconnection layer 112 may be a p-interconnection layer.

[0100] In some embodiments, before forming the second interconnect layer on the side of the second electrode facing away from the electron supply layer in step 150, the method further includes:

[0101] A first insulating layer is formed covering the first interconnect layer and the second electrode.

[0102] Combination Fig.12 As shown, a thin film deposition process is used to form a first insulating layer 113 covering the first interconnect layer 112 and the second electrode 110. The first insulating layer 113 fills the groove 108, and the upper surface of the first insulating layer 113 (i.e., the surface of the first insulating layer 113 away from the electron supply layer 103) is a plane.

[0103] Then, an etching process is used to form a plurality of third openings 114 distributed in an array in the first insulating layer 113. The plurality of third openings 114 are arranged one-to-one corresponding to the plurality of second electrodes 110, and the third openings 114 penetrate the first insulating layer 113 in a longitudinal direction X to expose the corresponding second electrodes 110.

[0104] Step 150: forming a second interconnection layer on a side of the second electrode facing away from the electron supply layer, and the second interconnection layer is connected to the second electrodes in the plurality of array units.

[0105] When the first insulating layer 113 is formed, the second interconnection layer is located on the first insulating layer and vertically penetrates the first insulating layer to be connected to the second electrodes in the plurality of array units.

[0106] Combination Fig.13 As shown, a second interconnection layer 115 is formed on the first insulating layer 113 by a thin film deposition process, and the second interconnection layer 115 fills the plurality of third openings 114 to connect with the plurality of second electrodes 110. All second electrodes 110 are connected through the second interconnection layer 115. The second interconnection layer 115 may be an n interconnection layer.

[0107] It should be noted that the second interconnect layer 115 does not completely cover the first insulating layer 113 , that is, the second interconnect layer 115 covers part of the first insulating layer 113 , such as the edge area of ​​the first insulating layer 113 is not covered by the second interconnect layer 115 , and the other areas of the first insulating layer 113 are covered by the second interconnect layer 115 .

[0108] In some embodiments, the method further comprises:

[0109] forming a second insulating layer covering the second interconnect layer and the first insulating layer;

[0110] A first pad is formed that vertically penetrates the first insulating layer and the second insulating layer and is connected to the first interconnection layer, and a second pad is formed that vertically penetrates the second insulating layer and is connected to the second interconnection layer.

[0111] Combination Fig.14 As shown, a second insulating layer 116 is formed by a thin film deposition process, and the second insulating layer 116 covers the second interconnection layer 115 and part of the first insulating layer 113 (i.e., the part of the first insulating layer 113 not covered by the second interconnection layer 115). The surface of the second insulating layer 116 facing away from the electron supply layer 103 is a plane.

[0112] Combination Fig.14 As shown, an etching process is used to form a first contact hole 117 and a second contact hole 118. The first contact hole 117 penetrates the second insulating layer 116 and the first insulating layer 113 in the longitudinal direction X to expose the first interconnection layer 112. The second contact hole 118 penetrates the second insulating layer 116 in the longitudinal direction X to expose the second interconnection layer 115. The number of the first contact hole 117 and the number of the second contact hole 118 can be one or more.

[0113] Then, combine Fig.15 As shown, a first pad 119 and a second pad 120 are formed on the second insulating layer 116 by a thin film deposition process. The first pad 119 fills the first contact hole 117 and is connected to the first interconnection layer 112. The first pad 119 is connected to all the first electrodes 111 through the first interconnection layer 112. The second pad 120 fills the second contact hole 118 and is connected to the second interconnection layer 115. The second pad 120 is connected to all the second electrodes 110 through the second interconnection layer 112. The first pad 119 may be a p-pad, and the second pad 120 may be an n-pad.

[0114] The output power of the LED chips in this embodiment and the related art was tested. The LED chips in the related art are not provided with array units and reflectors. The lateral dimensions of the array units 12 of the LED chips in this embodiment are 130 μm (Example 1), 110 μm (Example 2), 150 μm (Example 3), 170 μm (Example 4), 190 μm (Example 5) and 210 μm (Example 6). The microscope images of the LED chips in Examples 1 to 6 are shown as follows: Figures 16 to 21 The output power test results of the related technology and embodiments 1 to 6 are shown in Fig. 22 As shown, it can be seen that compared with the related art, the present embodiments 1 to 6 can effectively improve the light output power. Moreover, by reasonably setting the lateral size of the array unit 12, more transversely transmitted photons are redirected to the top of the chip by the reflector, and embodiment 1 (the lateral size of the array unit 12 is 130 μm) shows the maximum light output power.

[0115] In summary, according to the method for preparing a deep ultraviolet Micro-LED array chip provided in the embodiment of the present application, the chip is pixelated into a plurality of array units 12 distributed at intervals in an array, and the lateral cross-section of the array unit 12 is hexagonal, the absorption of lateral deep ultraviolet light by the epitaxial material is reduced, the absorption loss is reduced, and the light extraction efficiency is improved. A second electrode 110 is provided in the array unit 12 to form an array-distributed second electrode 110, and the lateral cross-section of the second electrode 110 is hexagonal, which alleviates the current concentration effect, improves the current distribution performance, and improves the chip reliability. A reflector 109 is provided on the side wall of the through hole 107 and the side wall of the array unit 12 to further enhance the light extraction efficiency and improve the side wall damage.

[0116] Correspondingly, the embodiment of the present application also provides a deep ultraviolet Micro-LED array chip, which can be prepared using the preparation method of the deep ultraviolet Micro-LED array chip in the above embodiment.

[0117] Fig.15 This is a schematic diagram of the structure of the deep ultraviolet Micro-LED array chip provided in an embodiment of the present application.

[0118] like Fig.15 As shown, the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application includes an electron supply layer 103, a plurality of array units 11, a plurality of first electrodes 111, a plurality of second electrodes 110, a first interconnection layer and a second interconnection layer.

[0119] The electron supply layer 103 is used to supply electrons and may include n-AlGaN or the like.

[0120] In some embodiments, the deep ultraviolet Micro-LED array chip further includes a buffer layer 102, and the electron supply layer 103 is located on the buffer layer 102. The buffer layer 102 may include AlN or the like.

[0121] In some embodiments, the deep ultraviolet Micro-LED array chip further includes a substrate 101, and the buffer layer 102 is located between the substrate 101 and the electron supply layer 103. The substrate 101 may include a sapphire substrate or the like.

[0122] The plurality of array units 11 are distributed in an array at intervals, and the array unit 11 comprises a multi-quantum well active layer 104, an electron blocking layer 105 and a hole supply layer 106 which are sequentially stacked on the electron supply layer 103 along the longitudinal direction X. The multi-quantum well active layer 104 may comprise AlGaN or the like, the electron blocking layer 105 may comprise p-AlGaN or the like, and the hole supply layer 106 may comprise p-GaN or the like.

[0123] The array unit 11 has a through hole 107 that penetrates the array unit 11 in the longitudinal direction X, that is, the through hole 107 penetrates the hole supply layer 106, the electron blocking layer 105 and the multi-quantum well active layer 104 in the longitudinal direction X. The through hole 107 is located at the center of the corresponding array unit 12. The through holes 107 in the plurality of array units 11 (i.e., the plurality of through holes 107) are distributed in an array.

[0124] The transverse Y-section of the array unit 12 is a hexagon, which can be a regular hexagon. In some embodiments, the transverse Y-dimension of the array unit 12 is 110-210 μm. The transverse Y-dimension of the array unit 12 refers to the distance between two opposite vertices of the transverse Y-section (hexagon) of the array unit 12, that is, the diameter of the circumscribed circle of the hexagon.

[0125] In some embodiments, the longitudinal X-section of the array unit 12 is a regular trapezoid, that is, the side wall of the array unit 12 is inclined toward the center of the array unit 12. The angle between the side wall of the array unit 12 and the upper surface of the electron supply layer 103 (the surface of the electron supply layer 103 close to the array unit 12) is 40°-50°.

[0126] In some embodiments, the spacing between adjacent array units 12 is smaller than the lateral dimension of the array unit 12 to prevent the spacing between the array units 12 from being too large and affecting the light emitting effect of the chip.

[0127] The transverse Y-section of the through hole 107 is a hexagon, which can be a regular hexagon. The six sides of the transverse Y-section of the array unit 12 and the six sides of the transverse Y-section of its through hole 107 can be arranged in parallel in a one-to-one correspondence. In some embodiments, the transverse Y-dimension of the through hole 107 is 20-40 μm. The transverse Y-dimension of the through hole 107 refers to the distance between two opposite vertices of the transverse Y-section (hexagon) of the through hole 107, that is, the diameter of the circumscribed circle of the hexagon.

[0128] In some embodiments, the longitudinal X-section of the through hole 107 is inverted trapezoidal, that is, the side wall of the through hole 107 is inclined in the direction away from the center of the through hole 107. The angle between the side wall of the through hole 107 and the upper surface of the electron supply layer 103 (the surface of the electron supply layer 103 close to the array unit 12) is 40°-50°. The upper surface of the electron supply layer 103 is parallel to the transverse direction Y and perpendicular to the longitudinal direction X.

[0129] The plurality of first electrodes 111 are arranged in one-to-one correspondence with the plurality of array units 12. The first electrode 111 is located on the corresponding array unit 12 and connected to the hole supply layer 106 in the corresponding array unit 12. The first electrode 111 may be a p-electrode.

[0130] The plurality of second electrodes 110 are arranged in one-to-one correspondence with the plurality of array units 12. The second electrodes 110 are located in the through holes 107 of the corresponding array units 12 and connected to the electron supply layer 103. The second electrodes 110 may be n-electrodes.

[0131] The second electrode 110 is located at the center of the corresponding array unit 12. The transverse Y section of the second electrode 110 is hexagonal, and the longitudinal X section of the second electrode 110 may be inverted trapezoidal. The first electrode 111 is arranged around the corresponding second electrode 110, and the first electrode 111 and the second electrode 110 are arranged at intervals.

[0132] In this embodiment, the LED chip is pixelated into a hexagonal array unit 12 of appropriate size, which reduces the absorption of lateral deep ultraviolet light by the epitaxial material, reduces absorption damage, and improves light extraction efficiency.

[0133] The first interconnection layer 112 is located between the plurality of array units 12 and is connected to the plurality of first electrodes 111. The first interconnection layer 112 is located between the plurality of array units 12 and extends along the sidewalls of the array units 12 to the upper surface of the first electrode 111 to be connected to the first electrode 111. All the first electrodes 111 are connected through the first interconnection layer 112. The first interconnection layer 112 may be a p-interconnection layer.

[0134] The second interconnection layer 115 is located on a side of the second electrode 110 away from the electron supply layer 103 and is connected to the plurality of second electrodes 110. All second electrodes 110 are connected via the second interconnection layer 115. The second interconnection layer 115 may be an n-interconnection layer.

[0135] In some embodiments, the deep ultraviolet Micro-LED array chip further includes a reflector 109, which is located on the sidewalls of the through hole 107 and the sidewalls of the array unit 12. The reflector 109 may also be located on the electron supply layer 103 between the plurality of array units 12, and the first interconnect layer 112 covers the reflectors 109 between the plurality of array units 12 and covers the reflectors 109 on the sidewalls of the array unit 12. The reflector 109 may be a distributed Bragg reflector (DBR).

[0136] Combination Figure 8As shown, the reflector 109 includes a plurality of refractive layers stacked and arranged, and the plurality of refractive layers include first refractive layers 13a and second refractive layers 13b that are alternately distributed, and the refractive indexes of the first refractive layers 13a and the second refractive layers 13b are different. For example, the refractive index of the first refractive layer 13a is greater than the refractive index of the second refractive layer 13b. The refractive layer at the bottom layer of the reflector 109 may be the first refractive layer 13a, and the refractive layer at the top layer may be the second refractive layer 13b. The first refractive layer 13a may include MgF2 or HfO2, and the second refractive layer 13b may include Al2O3, HfO2, or SiO2. For example, the reflector 109 may include MgF2 / Al2O3, MgF2 / HfO2, HfO2 / SiO2, or HfO2 / SiO2. It should be noted that the materials of different first refractive layers 13a may be the same or different. The materials of different second refractive layers 13b may be the same or different.

[0137] In some embodiments, the thickness of the refractive layer is determined by Wherein, d is the thickness of the refractive layer, λ is the central wavelength of the emitted deep ultraviolet light, and n is the refractive index of the refractive layer. For example, the reflector 109 is formed by alternatingly stacking four 25 nm thick HfO2 refractive layers and four 46 nm thick SiO2 refractive layers.

[0138] In this embodiment, a reflector 109 is disposed on the side wall of the array unit 12 and the side wall of the through hole 107. The laterally propagating deep ultraviolet light is reflected by the reflector and redirected to the top of the chip, further improving the light extraction efficiency of the deep ultraviolet Micro-LED array chip. Moreover, the reflector 109 can also serve as a passivation layer to suppress the leakage current and non-radiative recombination phenomenon caused by the sidewall etching damage, thereby improving the performance stability and reliability of the device.

[0139] In some embodiments, the deep ultraviolet Micro-LED array chip further includes a first insulating layer 113 , a second insulating layer 116 , a first solder pad 119 and a second solder pad 120 .

[0140] The first insulating layer 113 covers the first interconnection layer 112 and the plurality of second electrodes 110, and the upper surface of the first insulating layer 113 (i.e., the surface of the first insulating layer 113 on the side away from the electron supply layer 103) is a plane. The second interconnection layer 112 is located on the first insulating layer 113, and penetrates the first insulating layer 113 in the longitudinal direction X to connect with the second electrode 110. The second interconnection layer 115 does not completely cover the first insulating layer 113, that is, the second interconnection layer 115 covers part of the first insulating layer 113, such as the edge area of ​​the first insulating layer 113 is not covered by the second interconnection layer 115, and the other areas of the first insulating layer 113 are covered by the second interconnection layer 115.

[0141] The second insulating layer 116 covers the second interconnect layer 115 and the first insulating layer 113. The surface of the second insulating layer 116 facing away from the electron supply layer 103 is a plane.

[0142] The first pad 119 penetrates the first insulating layer 113 and the second insulating layer 116 in the longitudinal direction X and is connected to the first interconnection layer 112. The first pad 119 is connected to all the first electrodes 111 through the first interconnection layer 112. The first pad 119 may be a p-pad.

[0143] The second pad 120 penetrates the second insulating layer 116 in the longitudinal direction X and is connected to the second interconnection layer 115. The second pad 120 is connected to all the second electrodes 110 through the second interconnection layer 112. The second pad 120 may be an n pad.

[0144] In summary, according to the deep ultraviolet Micro-LED array chip provided in the embodiment of the present application, the chip is pixelated into a plurality of array units 12 distributed at intervals in an array, and the lateral cross-section of the array unit 12 is hexagonal, so as to reduce the absorption of lateral deep ultraviolet light by the epitaxial material, reduce the absorption loss, and improve the light extraction efficiency. A second electrode 110 is provided in the array unit 12 to form an array-distributed second electrode 110, and the lateral cross-section of the second electrode 110 is hexagonal, so as to alleviate the current concentration effect, improve the current distribution performance, and improve the chip reliability. A reflector 109 is provided on the side wall of the through hole 107 and the side wall of the array unit 12 to further enhance the light extraction efficiency and improve the side wall damage.

[0145] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0146] In the description of the present application, “plurality” means two or more.

[0147] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0148] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A deep ultraviolet Micro-LED array chip, characterized in that: include: Electron supply layer; A plurality of array units are arranged in an array at intervals, wherein the array unit comprises a multi-quantum well active layer, an electron blocking layer and a hole supplying layer which are sequentially stacked on the electron supplying layer in a longitudinal direction, wherein the array unit has a through hole which passes through the array unit in a longitudinal direction, and the transverse cross-sections of the array unit and the through hole are respectively hexagonal; A plurality of first electrodes are arranged corresponding to the plurality of array units one by one, wherein the first electrodes are located on corresponding array units and connected to the hole supply layer in the corresponding array units; A plurality of second electrodes are arranged corresponding to the plurality of array units one by one, the second electrodes are located in the through holes of the corresponding array units and connected to the electron supply layer; the transverse cross-section of the second electrodes is hexagonal, and the first electrodes are arranged around the corresponding second electrodes; A first interconnection layer, located between the plurality of array units and connected to the plurality of first electrodes; The second interconnection layer is located at a side of the second electrode away from the electron supply layer and is connected to the plurality of second electrodes.

2. The deep ultraviolet Micro-LED array chip according to claim 1, characterized in that: The deep ultraviolet Micro-LED array chip also includes: A reflector is located on the side wall of the through hole and the side wall of the array unit.

3. The deep ultraviolet Micro-LED array chip according to claim 2, characterized in that: The reflector includes a plurality of refractive layers stacked in layers, wherein the plurality of refractive layers include first refractive layers and second refractive layers that are alternately distributed, and the first refractive layers have different refractive indices from the second refractive layers.

4. The deep ultraviolet Micro-LED array chip according to claim 3, characterized in that: The thickness of the refractive layer Wherein, λ is the central wavelength of the excitation light, and n is the refractive index of the refractive layer.

5. The deep ultraviolet Micro-LED array chip according to claim 1, characterized in that: The deep ultraviolet Micro-LED array chip also includes: A first insulating layer covers the first interconnection layer and the plurality of second electrodes, wherein the second interconnection layer is located on the first insulating layer and vertically penetrates the first insulating layer to be connected to the second electrodes; a second insulating layer, covering the second interconnect layer and the first insulating layer; a first pad, longitudinally penetrating the first insulating layer and the second insulating layer and connected to the first interconnection layer; The second pad vertically penetrates the second insulating layer and is connected to the second interconnection layer.

6. The deep ultraviolet Micro-LED array chip according to claim 1, characterized in that: The spacing between adjacent array units is smaller than the lateral dimension of the array unit.

7. The deep ultraviolet Micro-LED array chip according to any one of claims 1 to 6, characterized in that: The lateral dimension of the array unit is 110-210 μm; and / or, The lateral dimension of the through hole is 20-40 μm; and / or, The angle between the side wall of the array unit and the upper surface of the electron supply layer is 40°-50°, and the upper surface of the electron supply layer is parallel to the transverse direction and perpendicular to the longitudinal direction; and / or, The angle between the side wall of the through hole and the upper surface of the electron supply layer is 40°-50°.

8. A method for preparing a deep ultraviolet Micro-LED array chip, characterized in that: include: Providing an epitaxial structure, the epitaxial structure comprising an electron supply layer, a multi-quantum well active layer, an electron blocking layer and a hole supply layer stacked in sequence along the longitudinal direction; A plurality of array units are formed in the epitaxial structure and are distributed in an array, wherein the array unit comprises the multi-quantum well active layer, the electron blocking layer and the hole supply layer, and the array unit has a through hole that penetrates the array unit longitudinally, and the transverse cross-sections of the array unit and the through hole are respectively hexagonal; A first electrode connected to the hole supply layer is formed on the array unit, and a second electrode connected to the electron supply layer is formed in the through hole; the second electrode has a hexagonal cross section, and the first electrode is arranged around the corresponding second electrode; forming a first interconnection layer between the plurality of array units, wherein the first interconnection layer is connected to first electrodes on the plurality of array units; A second interconnection layer is formed on a side of the second electrode away from the electron supply layer, and the second interconnection layer is connected to the second electrodes in the plurality of array units.

9. The method for preparing a deep ultraviolet Micro-LED array chip according to claim 8, characterized in that: Before forming a first electrode connected to the hole supply layer on the array unit and forming a second electrode connected to the electron supply layer in the through hole, the method further comprises: A reflector is formed on the outer surface of the array unit and the inner surface of the through hole, the first electrode is located on the side of the reflector away from the array unit, and vertically penetrates the reflector to be connected to the hole supply layer, and the second electrode is located in the through hole, and vertically penetrates the reflector to be connected to the electron supply layer.

10. The method for preparing a deep ultraviolet Micro-LED array chip according to claim 8 or 9, characterized in that: Before forming the second interconnect layer on the side of the second electrode facing away from the electron supply layer, the method further comprises: forming a first insulating layer covering the first interconnection layer and the second electrode, wherein the second interconnection layer is located on the first insulating layer and vertically penetrates the first insulating layer to be connected to the second electrodes in the plurality of array units; The method further comprises: forming a second insulating layer covering the second interconnect layer and the first insulating layer; A first pad is formed that vertically penetrates the first insulating layer and the second insulating layer and is connected to the first interconnection layer, and a second pad is formed that vertically penetrates the second insulating layer and is connected to the second interconnection layer.

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