Display device

Abstract

There is provided a display device including: a substrate having a display area and a peripheral area adjacent to the display area; a first wiring in the peripheral region on the substrate; an insulating layer on the first wiring and covering at least a portion of the first wiring; a second wiring on the insulating layer, overlapping at least a portion of the insulating layer in a plan view, and having an opening pattern exposing at least a portion of the insulating layer; a first cover portion on the insulating layer and the second wiring to fill the opening pattern and expose at least a portion of the second wiring; and a second covering portion on the second wiring and covering at least a portion of the second wiring exposed from the first covering portion.

Description

Technical Field

[0001] An aspect of some embodiments of the present disclosure relates to a display device. Background Art

[0002] With the development of information technology, the importance of display devices that provide a connection medium between users and information is becoming prominent. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), plasma display devices (PDPs), and quantum dot display devices is increasing.

[0003] The display device may include an insulating layer to insulate between stacked conductive layers. The insulating layer may generate gas due to short-term or long-term chemical decomposition of organic matter contained in the insulating layer.

[0004] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some embodiments include a display device having relatively improved display quality and durability.

[0006] According to some embodiments, a display device includes: a substrate having a display area and a peripheral area adjacent to the display area; a first wiring in the peripheral area on the substrate; an insulating layer on the first wiring and covering at least a portion of the first wiring; a second wiring on the insulating layer, overlapping at least a portion of the insulating layer in a plan view, and having an opening pattern exposing at least a portion of the insulating layer; a first covering portion on the insulating layer and the second wiring to fill the opening pattern and expose at least a portion of the second wiring; and a second covering portion on the second wiring and covering at least a portion of the second wiring exposed from the first covering portion.

[0007] According to some embodiments, a thickness of the second covering portion may be smaller than a thickness of the first covering portion.

[0008] According to some embodiments, a height from an upper surface of the insulating layer to an upper surface of the second covering part may be smaller than a height from an upper surface of the insulating layer to an upper surface of the first covering part.

[0009] According to some embodiments, the second covering portion may contact the first covering portion.

[0010] According to some embodiments, the first cover portion may be connected by the second cover portion.

[0011] According to some embodiments, the second covering portion may be spaced apart from the opening pattern in a plan view.

[0012] According to some embodiments, the first covering portion may contact the insulating layer.

[0013] According to some embodiments, the first cover portion and the second cover portion may be integrated into one body without a separate interface.

[0014] According to some embodiments, the first covering portion and the second covering portion may include an organic material.

[0015] According to some embodiments, the first wiring and the second wiring may contact each other to form a power voltage line, and the power voltage line may transmit the power voltage to the light emitting element in the display area.

[0016] According to some embodiments, a display device includes: a substrate having a display area and a peripheral area adjacent to the display area; a first wiring in the peripheral area on the substrate; an insulating layer on the first wiring and covering at least a portion of the first wiring; a second wiring on the insulating layer, overlapping at least a portion of the insulating layer in a plan view, and having an opening pattern exposing at least a portion of the insulating layer; a covering film on the insulating layer and the second wiring and covering the second wiring defining the opening pattern, wherein at least a portion of the covering film is located in the opening pattern; and a covering portion on the covering film and covering at least a portion of the covering film, wherein at least a portion of the covering portion is located in the opening pattern.

[0017] According to some embodiments, the covering portion may expose at least a portion of the covering film.

[0018] According to some embodiments, the thickness of the cover film may be smaller than the thickness of the cover portion.

[0019] According to some embodiments, a height from an upper surface of the insulating layer to an upper surface of the cover film may be smaller than a height from an upper surface of the insulating layer to an upper surface of the cover portion.

[0020] According to some embodiments, the cover portion may contact the cover film.

[0021] According to some embodiments, the cover portion may be out of contact with the insulating layer by the cover film.

[0022] According to some embodiments, the cover film may contact the insulating layer in the opening pattern.

[0023] According to some embodiments, the cover film may include an inorganic material, and the cover portion may include an organic material.

[0024] According to some embodiments, the first wiring and the second wiring contact each other to form a power voltage line.

[0025] According to some embodiments, the power voltage line may transmit the power voltage to the light emitting elements in the display area.

[0026] In the display device according to some embodiments, the wiring having the opening pattern may be located on the insulating layer that generates gas by chemical decomposition, etc. Therefore, the gas generated from the insulating layer may be exhausted through the opening pattern.

[0027] In addition, in the display device according to some embodiments, the first covering portion and the second covering portion may be on the wiring having the opening pattern. In this case, the first covering portion may fill the opening pattern, and the second covering portion may cover the portion of the wiring exposed in the space between the openings not covered by the first covering portion.

[0028] Therefore, in the area defining the opening pattern, the wiring can be substantially completely covered by the first covering portion and the second covering portion. Therefore, in the area defining the opening pattern, the film peeling phenomenon in which the first covering portion is peeled off from the insulating layer can be reduced or prevented, compared with the case where the wiring is only partially covered by the first covering portion corresponding to the opening pattern.

[0029] In addition, in the display device according to some embodiments, the wiring having the opening pattern can be doubly covered by the cover film and the cover portion. Therefore, even if the film peeling phenomenon occurs in which the cover portion peels off from the cover film, the wiring can be covered by the cover film in the area defining the opening pattern.

[0030] Therefore, in the display device according to some embodiments, in the subsequent process (for example, an etching process for forming a pixel electrode, etc.), the etchant can be reduced or prevented from penetrating into the wiring due to the peeling phenomenon. Therefore, the problem of the wiring being damaged due to the reaction with the etchant can be reduced or prevented. In addition, the problem of the material included in the wiring reacting with the etchant to form particles can be reduced or prevented. Therefore, the display quality and durability of the display device can be relatively improved.

[0031] It will be understood that the above general description and the following detailed description are illustrative and explanatory, and are intended to provide further explanation of the claimed invention, but are not intended to be limiting. As will be appreciated by those of ordinary skill in the art, various modifications and changes may be made to the disclosed embodiments without departing from the spirit and scope of the embodiments according to the present disclosure as defined in the appended claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0033] Figure 1 is a plan view showing a display device according to some embodiments.

[0034] Figure 2 It is shown Figure 1A circuit diagram of one of the pixels included in a display device.

[0035] Figure 3 is a diagram showing some embodiments of the present invention. Figure 1 A cross-sectional view of a display area of ​​a display device.

[0036] Figures 4 to 7 is a diagram showing some embodiments of the present invention. Figure 1 Layout diagram of the enlarged area A.

[0037] Figure 8 It is along Figure 7 A cross-sectional view taken along line II'.

[0038] Fig. 9 and Fig.10 is a diagram showing a method according to some embodiments Figure 1 Layout diagram of the enlarged area A.

[0039] Fig.11 It is along Fig.10 A cross-sectional view taken along line II-II'.

[0040] Fig.12 and Fig.13 is a diagram showing some embodiments of the present invention. Figure 1 Layout diagram of the enlarged area A.

[0041] Fig.14 It is along Fig.13 A cross-sectional view taken along line III-III'. DETAILED DESCRIPTION

[0042] Aspects of some embodiments of the present disclosure will now be more fully described below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will more fully convey the scope aspects of some embodiments of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0043] Figure 1 is a plan view showing a display device according to some embodiments.

[0044] Reference Figure 1 , the display device DD (eg, substrate SUB) may include a display area DA and a peripheral area PA adjacent to the display area DA (eg, in the periphery of the display area DA or outside the footprint).

[0045] The display area DA may be an area for displaying an image by generating light. A plurality of pixels PX that emit light may be located in the display area DA, and therefore, an image may be displayed in the display area DA. The pixels PX may be arranged in a matrix form or arrangement (e.g., columns and rows of pixels PX) along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. Each of the pixels PX may include a light emitting element and a pixel circuit for driving the light emitting element. According to some embodiments, the light emitting element may include an organic light emitting diode, and the pixel circuit may include at least one thin film transistor.

[0046] Lines for supplying signals or power to the pixels PX may be located in the display area DA. For example, a plurality of data signal lines, a plurality of gate signal lines, and a plurality of power lines PL may be located in the display area DA.

[0047] According to some embodiments, each of the power lines PL may extend along the first direction DR1 and may be arranged along the second direction DR2. However, embodiments according to the present invention are not necessarily limited thereto. The power lines PL may supply a power voltage to the pixels PX.

[0048] The peripheral area PA may surround at least a portion of the display area DA. For example, the peripheral area PA may completely surround the display area DA. According to some embodiments, the peripheral area PA may be an area where an image is not displayed. However, embodiments according to the present invention are not necessarily limited thereto, and an image may be displayed in at least a portion of the peripheral area PA.

[0049] Drivers and lines for image display may be located in the peripheral area PA. For example, a first power voltage line VL1 and a second power voltage line VL2 may be located in the peripheral area PA. The first power voltage line VL1 and the second power voltage line VL2 may provide a power voltage to at least one of the pixels PX.

[0050] For example, the first power voltage line VL1 may provide a common power voltage to the pixel PX, and the second power voltage line VL2 may provide a driving power voltage to the pixel PX. That is, the first power voltage line VL1 may be a common power voltage line, and the second power voltage line VL2 may be a driving power voltage line.

[0051] For example, the second power voltage line VL2 may provide the driving power voltage to the power line PL, and the power line PL may provide the driving power voltage to the pixel PX. Meanwhile, according to some embodiments, the driving power voltage may be higher than the common power voltage.

[0052] Figure 2 It is shown Figure 1 A circuit diagram of one of the pixels included in a display device.

[0053] Reference Figure 2 , each of the pixels PX included in the display device DD may include a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor CST, and a light emitting element LED.

[0054] The first transistor T1 may include a source electrode, a drain electrode, and a gate electrode. The first transistor T1 may adjust a current flowing from a driving power voltage line ELVDL supplied with a driving power voltage to the light emitting element LED according to a voltage difference between the gate electrode and the source electrode.

[0055] For example, the first transistor T1 may be a driving transistor for driving the light emitting element LED. The gate electrode of the first transistor T1 may be connected to the first node N1. The source electrode of the first transistor T1 may be connected to the first electrode of the light emitting element LED. The drain electrode of the first transistor T1 may be connected to a driving power voltage line ELVDL to which a driving power voltage is applied.

[0056] The second transistor T2 may include a source electrode, a drain electrode, and a gate electrode. The second transistor T2 may be turned on by a gate signal of a gate signal line GSL to connect the data signal line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the gate signal line GSL. The source electrode of the second transistor T2 may be connected to the first node N1. The drain electrode of the second transistor T2 may be connected to the data signal line DTL.

[0057] The third transistor T3 may include a source electrode, a drain electrode, and a gate electrode. The third transistor T3 may be turned on by a sensing signal of the sensing signal line SSL to connect the initialization voltage line VIL to one end of the light emitting element LED. The gate electrode of the third transistor T3 may be connected to the sensing signal line SSL. The source electrode of the third transistor T3 may be connected to the second node N2. The drain electrode of the third transistor T3 may be connected to the initialization voltage line VIL to which the initialization voltage is applied.

[0058] However, the source electrode and the drain electrode of each of the first transistor T1 , the second transistor T2 , and the third transistor T3 are not limited thereto, and vice versa. In addition, each of the first transistor T1 , the second transistor T2 , and the third transistor T3 may be formed as a thin film transistor.

[0059] The storage capacitor CST may include a first electrode and a second electrode. The first electrode of the storage capacitor CST may be connected to the first node N1. The second electrode of the storage capacitor CST may be connected to the second node N2. The storage capacitor CST may store a voltage corresponding to a voltage difference between a gate voltage and a source voltage of the first transistor T1.

[0060] The light emitting element LED may emit light according to the current supplied by the first transistor T1. The light emitting element LED may be an organic light emitting diode including a first electrode (e.g., an anode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode). However, the embodiments of the present invention are not limited thereto, and the light emitting element LED may be an inorganic light emitting diode including an inorganic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, or the like. In addition, the light emitting element LED may be a micro LED. The first electrode of the light emitting element LED may be connected to the source electrode of the first transistor T1, and the second electrode of the light emitting element LED may be connected to a common power voltage line ELVSL, to which a common power voltage lower than a driving power voltage is applied.

[0061] At the same time, Figure 2 In the embodiment, the case where each of the pixels PX includes three transistors, one storage capacitor, and one light emitting element has been described. However, the number of transistors, the number of storage capacitors, and the number of light emitting elements included in each of the pixels PX are not limited thereto. For example, according to some embodiments, the pixel PX may include additional components or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0062] Figure 3 is a diagram showing some embodiments of the present invention. Figure 1 A cross-sectional view of a display area of ​​a display device.

[0063] Reference Figure 1 and Figure 3 The display device DD may include a substrate SUB, a buffer layer BFR, an active pattern ACT, a first gate electrode GE1, a second gate electrode GE2, a source electrode SE, a drain electrode DE, a connecting electrode CNE, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, a third interlayer insulating layer IL3, a first via insulating layer VIA1, a second via insulating layer VIA2, a pixel defining layer PDL, a pixel electrode PE, a light emitting layer EL, a common electrode CE and an encapsulation layer ENC.

[0064] The substrate SUB may include a transparent material or an opaque material. According to some embodiments, examples of materials that may be used as the substrate SUB may include glass, quartz, plastic, etc. These may be used alone or in combination with each other.

[0065] The buffer layer BFR may be located on the substrate SUB. The buffer layer BFR may prevent metal atoms or impurities from diffusing from the substrate SUB to the active pattern ACT. According to some embodiments, the buffer layer BFR may be formed of an insulating material. Examples of insulating materials that may be used as the buffer layer BFR may include silicon oxide, silicon nitride, and silicon oxynitride.

[0066] The active pattern ACT may be located on the buffer layer BFR. According to some embodiments, the active pattern ACT may be formed of a silicon semiconductor material, an oxide semiconductor material, or an organic semiconductor material.

[0067] The first interlayer insulating layer IL1 may be located on the active pattern ACT. The first interlayer insulating layer IL1 may cover the active pattern ACT. According to some embodiments, the first interlayer insulating layer IL1 may be formed of an insulating material. Examples of insulating materials that may be used as the first interlayer insulating layer IL1 may include silicon oxide, silicon nitride, and silicon oxynitride. These may be used alone or in combination with each other.

[0068] The first gate electrode GE1 may be located on the first interlayer insulating layer IL1. The first gate electrode GE1 may overlap the active pattern ACT. According to some embodiments, the first gate electrode GE1 may be formed of metal, alloy, conductive metal oxide, transparent conductive material, or the like.

[0069] The second interlayer insulating layer IL2 may be located on the first gate electrode GE1. The second interlayer insulating layer IL2 may cover the first gate electrode GE1. According to some embodiments, the second interlayer insulating layer IL2 may be formed of an insulating material. Examples of insulating materials that may be used as the second interlayer insulating layer IL2 may include silicon oxide, silicon nitride, and silicon oxynitride. These may be used alone or in combination with each other.

[0070] The second gate electrode GE2 may be located on the second interlayer insulating layer IL2. The second gate electrode GE2 may overlap the first gate electrode GE1. According to some embodiments, the second gate electrode GE2 may be formed of metal, alloy, conductive metal oxide, transparent conductive material, or the like.

[0071] The third interlayer insulating layer IL3 may be located on the second gate electrode GE2. The third interlayer insulating layer IL3 may cover the second gate electrode GE2. According to some embodiments, the third interlayer insulating layer IL3 may be formed of an insulating material. Examples of insulating materials that may be used as the third interlayer insulating layer IL3 may include silicon oxide, silicon nitride, and silicon oxynitride. These may be used alone or in combination with each other.

[0072] The source electrode SE and the drain electrode DE may be located on the third interlayer insulating layer IL3. The source electrode SE and the drain electrode DE may contact the active pattern ACT. According to some embodiments, the source electrode SE and the drain electrode DE may be formed of metal, alloy, conductive metal oxide, transparent conductive material, etc.

[0073] The active pattern ACT, the first gate electrode GE1, the source electrode SE, and the drain electrode DE may form a transistor. For example, the active pattern ACT, the first gate electrode GE1, the source electrode SE, and the drain electrode DE may form a transistor. Figure 2The first gate electrode GE1 and the second gate electrode GE2 may form a capacitor. For example, the first gate electrode GE1 and the second gate electrode GE2 may form a Figure 2 The storage capacitor CST.

[0074] The first via insulating layer VIA1 may be located on the source electrode SE and the drain electrode DE. The first via insulating layer VIA1 may cover the source electrode SE and the drain electrode DE. The first via insulating layer VIA1 may be formed of an organic insulating material. Examples of organic insulating materials that may be used as the first via insulating layer VIA1 may include photoresists, polyimide resins, polyamide resins, acrylic resins (e.g., polyacrylic resins), and epoxy resins. These may be used alone or in combination with each other.

[0075] The connection electrode CNE may be located on the first via insulating layer VIA1. The connection electrode CNE may contact at least one of the source electrode SE and the drain electrode DE. For example, the connection electrode CNE may contact the drain electrode DE. The connection electrode CNE may connect the pixel electrode PE and the transistor. The connection electrode CNE may be formed of a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0076] The second via insulating layer VIA2 may be located on the connection electrode CNE. The second via insulating layer VIA2 may cover the connection electrode CNE. The second via insulating layer VIA2 may be formed of an organic insulating material. Examples of organic insulating materials that may be used as the second via insulating layer VIA2 may include photoresists, polyimide resins, polyamide resins, acrylic resins (e.g., polyacrylic resins), and epoxy resins. These may be used alone or in combination with each other.

[0077] The pixel electrode PE may be located on the second via insulating layer VIA2. The pixel electrode PE may be used as an anode electrode or a cathode electrode. For example, the pixel electrode PE may be used as an anode electrode. The pixel electrode PE may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material. The pixel electrode PE may have a single-layer structure or a multi-layer structure including a plurality of conductive layers.

[0078] The pixel defining layer PDL may be located on the second via insulating layer VIA2 and the pixel electrode PE. The pixel defining layer PDL may be formed of an insulating material. Examples of insulating materials that may be used as the pixel defining layer PDL may include photoresists, polyimide resins, polyamide resins, siloxane resins, acrylic resins (e.g., polyacrylic resins), and epoxy resins. These may be used alone or in combination with one another. The pixel defining layer PDL may define a pixel opening that exposes at least a portion of the pixel electrode PE.

[0079] The light emitting layer EL may be located on the pixel electrode PE exposed by the pixel opening of the pixel defining layer PDL. According to some embodiments, the light emitting layer EL may have a multi-layer structure including a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0080] The common electrode CE may be located on the pixel defining layer PDL and the light emitting layer EL. The common electrode CE may be used as a cathode electrode or an anode electrode. For example, the common electrode CE may be used as a cathode electrode. The common electrode CE may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material. The common electrode CE may have a single-layer structure or a multilayer structure including a plurality of conductive layers. The pixel electrode PE, the light emitting layer EL, and the common electrode CE may form a light emitting element LED.

[0081] The encapsulation layer ENC may be located on the light emitting element LED. The encapsulation layer ENC may prevent or reduce the penetration of impurities or contaminants into the light emitting element LED. The encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. According to some embodiments, the encapsulation layer ENC may include a first inorganic encapsulation layer IEL1, an organic encapsulation layer OEL, and a second inorganic encapsulation layer IEL2. The first inorganic encapsulation layer IEL1 may be located on the common electrode CE. The organic encapsulation layer OEL may be located on the first inorganic encapsulation layer IEL1. The second inorganic encapsulation layer IEL2 may be located on the organic encapsulation layer OEL.

[0082] Figures 4 to 7 is a diagram showing some embodiments of the present invention. Figure 1 Layout diagram of the enlarged area A. For example, Figures 4 to 7 may be an enlarged layout diagram of the first power voltage line VL1 and the second power voltage line VL2 in the peripheral area PA.

[0083] First, refer to Figure 1 , Figure 3 and Figure 4 , the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the third interlayer insulating layer IL3 may be sequentially arranged on the substrate SUB. In addition, the first wiring WR1 and the second wiring WR2 may be located on the third interlayer insulating layer IL3. The description of the substrate SUB, the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the third interlayer insulating layer IL3 is similar to that of the reference Figure 3 The descriptions overlap and are omitted.

[0084] The first wiring WR1 and the second wiring WR2 may extend in the first direction DR1 and / or the second direction DR2. The first wiring WR1 and the second wiring WR2 may include a conductive material. Examples of conductive materials that may be used as the first wiring WR1 and the second wiring WR2 may include aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, lithium, calcium, molybdenum, titanium, tungsten, or copper, etc. These may be used alone or in combination with each other. According to some embodiments, the first wiring WR1 and the second wiring WR2 may be formed in the same process as the source electrode SE and the drain electrode DE. That is, the first wiring WR1 and the second wiring WR2 may include the same material as the source electrode SE and the drain electrode DE.

[0085] Further references Figure 5 , the first via insulating layer VIA1 may be located on the first wiring WR1 and the second wiring WR2. According to some embodiments, the first via insulating layer VIA1 may cover at least a portion of the first wiring WR1 and at least a portion of the second wiring WR2. In addition, the first via insulating layer VIA1 may expose at least a portion of the first wiring WR1 and at least a portion of the second wiring WR2. The first via insulating layer VIA1 may contact at least a portion of the third interlayer insulating layer IL3. As described above, the first via insulating layer VIA1 may include an organic insulating material.

[0086] Further references Figure 6 , the third wiring WR3 and the fourth wiring WR4 may be located on the first via insulating layer VIA1.

[0087] In a plan view, the third wiring WR3 and the fourth wiring WR4 may overlap with at least a portion of the first via insulating layer VIA1. The third wiring WR3 and the fourth wiring WR4 may have an opening pattern OPP exposing at least a portion of the first via insulating layer VIA1 in a region overlapping with the first via insulating layer VIA1. That is, the opening pattern OPP of each of the third wiring WR3 and the fourth wiring WR4 may expose at least a portion of the first via insulating layer VIA1. For example, the opening pattern OPP may be defined by a plurality of openings repeatedly arranged along the first direction DR1 and the second direction DR2.

[0088] Since the first via insulating layer VIA1 includes an organic insulating material, gas may be generated from the first via insulating layer VIA1 due to short-term or long-term chemical decomposition. If the gas is not properly exhausted, the light emitting element LED located in the display area DA may be damaged by the gas, resulting in pixel shrinkage and shortening the life of the light emitting element LED.

[0089] According to the embodiment, since each of the third and fourth wirings WR3 and WR4 located on the first via insulating layer VIA1 includes the opening pattern OPP, gas generated from the first via insulating layer VIA1 may be exhausted through the opening pattern OPP.

[0090] The third wiring WR3 and the fourth wiring WR4 may include a conductive material. Examples of conductive materials that can be used as the third wiring WR3 and the fourth wiring WR4 may include aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, lithium, calcium, molybdenum, titanium, tungsten or copper, etc. These may be used alone or in combination with each other. According to some embodiments, the third wiring WR3 and the fourth wiring WR4 may be formed in the same process as the connection electrode CNE. That is, the third wiring WR3 and the fourth wiring WR4 may include the same material as the connection electrode CNE.

[0091] Meanwhile, the third wiring WR3 may overlap at least a portion of the first wiring WR1, and the fourth wiring WR4 may overlap at least a portion of the second wiring WR2. For example, the third wiring WR3 may contact the first wiring WR1 exposed from the first via insulating layer VIA1, and the fourth wiring WR4 may contact the second wiring WR2 exposed from the first via insulating layer VIA1.

[0092] The first and third wirings WR1 and WR3 may contact each other to form a first power voltage line VL1 , and the second and fourth wirings WR2 and WR4 may contact each other to form a second power voltage line VL2 .

[0093] Further references Figure 7 , the first cover portion CDP1 and the second cover portion CDP2 may be located on the first via insulating layer VIA1, the third wiring WR3, and the fourth wiring WR4.

[0094] The first covering portion CDP1 may fill the opening pattern OPP of each of the third wiring WR3 and the fourth wiring WR4. That is, the first covering portion CDP1 may be arranged to correspond to the opening pattern OPP. Therefore, the first covering portion CDP1 may contact the first via insulating layer VIA1 at the opening pattern OPP. According to some embodiments, the first covering portion CDP1 may cover a portion of each of the third wiring WR3 and the fourth wiring WR4.

[0095] The first cover portion CDP1 may include an organic insulating material. Examples of the organic insulating material that may be used as the first cover portion CDP1 may include photoresist, polyimide resin, polyamide resin, acrylic resin (eg, polyacrylic resin), and epoxy resin. These may be used alone or in combination with each other.

[0096] According to some embodiments, the first cover portion CDP1 may be formed in the same process as the second via insulating layer VIA2. That is, the first cover portion CDP1 may include the same material as the second via insulating layer VIA2. For example, the first cover portion CDP1 and the second via insulating layer VIA2 may be formed simultaneously by laying a preliminary layer including an organic insulating material on the first via insulating layer VIA1, the third wiring WR3, the fourth wiring WR4, and the connection electrode CNE, and exposing and developing the preliminary layer.

[0097] The second covering portion CDP2 may cover at least a portion of each of the third wiring WR3 and the fourth wiring WR4 that is exposed from the first covering portion CDP1. For example, in a plan view, the second covering portion CDP2 may be spaced apart from the opening pattern OPP. That is, the second covering portion CDP2 may be located in a space between openings that define the opening pattern OPP. In other words, the second covering portion CDP2 may cover a portion of each of the third wiring WR3 and the fourth wiring WR4 that is exposed in the space between openings that define the opening pattern OPP. Specifically, the second covering portion CDP2 may cover a portion of the third wiring WR3 and the fourth wiring WR4 that is exposed in the space not covered by the first covering portion CDP1.

[0098] According to some embodiments, the second cover portion CDP2 may contact the first cover portion CDP1. For example, the second cover portion CDP2 may contact the side surface of the first cover portion CDP1. Therefore, the first cover portion CDP1 may be connected by the second cover portion CDP2. In other words, the first cover portion CDP1 arranged to correspond to the opening pattern OPP may be connected by the second cover portion CDP2.

[0099] The second cover portion CDP2 may include an organic insulating material. Examples of the organic insulating material that may be used as the second cover portion CDP2 may include photoresist, polyimide resin, polyamide resin, acrylic resin (eg, polyacrylic resin), and epoxy resin. These may be used alone or in combination with each other.

[0100] According to some embodiments, the second covering portion CDP2 may be formed in the same process as the first covering portion CDP1. That is, the second covering portion CDP2 may include the same material as the first covering portion CDP1. For example, the first covering portion CDP1 and the second covering portion CDP2 may be integrated into one body without a separate interface. For example, the first covering portion CDP1 and the second covering portion CDP2 may be simultaneously formed by laying a preparatory layer including an organic insulating material on the first via insulating layer VIA1, the third wiring WR3, and the fourth wiring WR4, and exposing and developing the preparatory layer.

[0101] According to some embodiments, the first covering portion CDP1, the second covering portion CDP2, and the second via insulating layer VIA2 may be formed together in the same process. That is, the first covering portion CDP1, the second covering portion CDP2, and the second via insulating layer VIA2 may include the same material. Also in this case, the first covering portion CDP1 and the second covering portion CDP2 may be integrated into one without a separate interface. For example, the first covering portion CDP1, the second covering portion CDP2, and the second via insulating layer VIA2 may be formed simultaneously by laying a preparatory layer containing an organic insulating material on the first via insulating layer VIA1, the third wiring WR3, and the fourth wiring WR4, and exposing and developing the preparatory layer.

[0102] In the display device DD according to the embodiment, the second cover portion CDP2 may be located on the third wiring WR3 and the fourth wiring WR4 having the opening pattern OPP. In addition, the second cover portion CDP2 may cover the portions of the third wiring WR3 and the fourth wiring WR4 that are exposed in the space between the openings and are not covered by the first cover portion CDP1. Therefore, in the region defining the opening pattern OPP, the third wiring WR3 and the fourth wiring WR4 may be substantially completely covered by the first cover portion CDP1 and the second cover portion CDP2.

[0103] Therefore, in the area defining the opening pattern OPP, compared with the case where the third wiring WR3 and the fourth wiring WR4 are only partially covered by the first covering portion CDP1 positioned corresponding to the opening pattern OPP, the film lifting phenomenon of the first covering portion CDP1 peeling off from the first via insulation layer VIA1 can be reduced or prevented.

[0104] Therefore, in the subsequent process (for example, an etching process for forming the pixel electrode PE, etc.), the etchant can be reduced or prevented from penetrating into the third wiring WR3 and / or the fourth wiring WR4 due to the peeling phenomenon of the first covering portion CDP1. Therefore, the problem of the third wiring WR3 and / or the fourth wiring WR4 being damaged due to the reaction with the etchant can be reduced or prevented. In addition, the problem of the material included in the third wiring WR3 and / or the fourth wiring WR4 reacting with the etchant to form particles can be reduced or prevented. Therefore, the display quality and durability of the display device DD can be improved.

[0105] Figure 8 It is along Figure 7 A cross-sectional view taken along line II'.

[0106] exist Figure 8In the figure, for the convenience of description, only the cross-sectional structure of the region where the opening pattern OPP defined in the third wiring WR3 and the first cover portion CDP1 and the second cover portion CDP2 corresponding to the third wiring WR3 are positioned is shown. The cross-sectional structure of the region where the opening pattern OPP defined in the fourth wiring WR4 and the first cover portion CDP1 and the second cover portion CDP2 corresponding to the fourth wiring WR4 can be similar to that of FIG. Figure 8 The cross-sectional structures are basically the same.

[0107] Further references Figure 8 According to some embodiments, the thickness of the second cover part CDP2 may be different from the thickness of the first cover part CDP1. That is, the upper surface of the first cover part CDP1 and the upper surface of the second cover part CDP2 may be located at different levels. Specifically, the thickness of the second cover part CDP2 may be less than the thickness of the first cover part CDP1. That is, the upper surface of the second cover part CDP2 may be located at a lower level than the upper surface of the first cover part CDP1. For example, the height from the upper surface of the first via insulation layer VIA1 to the upper surface of the second cover part CDP2 may be less than the height from the upper surface of the first via insulation layer VIA1 to the upper surface of the first cover part CDP1.

[0108] For example, when the first covering part CDP1 and the second covering part CDP2 are integrated into one, the first covering part CDP1 and the second covering part CDP2 having different thicknesses can be simultaneously formed by laying a preparatory layer containing an organic insulating material on the first via insulation layer VIA1, the third wiring WR3 and the fourth wiring WR4, and exposing and developing the preparatory layer through a half-tone mask or the like.

[0109] For example, the full-tone area of ​​the half-tone mask may correspond to a portion corresponding to the first covering portion CDP1 of the preliminary layer, and the half-tone area of ​​the half-tone mask may correspond to a portion corresponding to the second covering portion CDP2 of the preliminary layer. Therefore, the amount of light irradiated to the portion corresponding to the second covering portion CDP2 of the preliminary layer may be less than the amount of light irradiated to the portion corresponding to the first covering portion CDP1 of the preliminary layer. According to the difference in the amount of light irradiation, in a subsequent development process, the portion of the preliminary layer corresponding to the full-tone area may remain as the first covering portion CDP1, and the portion of the preliminary layer corresponding to the half-tone area may remain as the second covering portion CDP2 having a thickness smaller than that of the first covering portion CDP1.

[0110] Meanwhile, in another example, according to the type of photosensitive material included in the preliminary layer, the amount of light irradiated to a portion of the preliminary layer corresponding to the second cover part CDP2 may be greater than that irradiated to a portion of the preliminary layer corresponding to the first cover part CDP1.

[0111] Since the second cover portion CDP2 has a thickness smaller than that of the first cover portion CDP1, the path of the gas generated from the first via insulating layer VIA1 and discharged through the opening pattern OPP is not blocked (for example, a space where the first cover portion CDP1 is not positioned on the third wiring WR3 and the fourth wiring WR4). That is, even when the second cover portion CDP2 is located on the third wiring WR3 and the fourth wiring WR4, the discharge of the gas through the opening pattern OPP is not reduced or suppressed.

[0112] Fig. 9 and Fig.10 is a diagram showing some embodiments of the present invention. Figure 1 Layout diagram of the enlarged area A.

[0113] For example, except that the first covering portion CDP1′ and the second covering portion CDP2′ are included instead of the first covering portion CDP1 and the second covering portion CDP2, Fig. 9 and Fig.10 The described embodiments can be compared with Figures 4 to 7 In addition, the first cover portion CDP1' and the second cover portion CDP2' are separate structures that are not integrally formed with each other, and the first cover portion CDP1' and the second cover portion CDP2' are similar to the embodiment described above. Figure 7 The first cover portion CDP1 and the second cover portion CDP2 are described as being substantially the same, and therefore, overlapping descriptions are omitted or simplified.

[0114] As reference Figure 6 As described, the third and fourth wirings WR3 and WR4 may have the opening pattern OPP exposing at least a portion of the first via insulating layer VIA1 .

[0115] Further references Fig. 9 and Fig.10 , the first cover portion CDP1′ and the second cover portion CDP2′ may be located on the first via insulating layer VIA1, the third wiring WR3, and the fourth wiring WR4.

[0116] For example, Fig. 9 As shown in , the first cover portion CDP1' may be arranged to fill the opening pattern OPP of each of the third wiring WR3 and the fourth wiring WR4. That is, the first cover portion CDP1' may be arranged to correspond to the opening pattern OPP. Therefore, the first cover portion CDP1' may contact the first via insulating layer VIA1 at the opening pattern OPP.

[0117] The first cover portion CDP1' may include an organic insulating material. Examples of the organic insulating material that may be used as the first cover portion CDP1' may include photoresist, polyimide resin, polyamide resin, acrylic resin (eg, polyacrylic resin), and epoxy resin. These may be used alone or in combination with each other.

[0118] According to some embodiments, the first cover portion CDP1' may be formed in the same process as the second via insulating layer VIA2. That is, the first cover portion CDP1' may include the same material as the second via insulating layer VIA2. For example, the first cover portion CDP1' and the second via insulating layer VIA2 may be formed simultaneously by laying a preparatory layer including an organic insulating material on the first via insulating layer VIA1, the third wiring WR3, the fourth wiring WR4, and the connection electrode CNE, and exposing and developing the preparatory layer.

[0119] like Fig.10 As shown in , the second covering portion CDP2' may cover at least a portion of each of the third wiring WR3 and the fourth wiring WR4 that is exposed from the first covering portion CDP1'. For example, in a plan view, the second covering portion CDP2' may be arranged to be spaced apart from the opening pattern OPP. That is, the second covering portion CDP2' may be located in a space between the openings that define the opening pattern OPP. In other words, the second covering portion CDP2' may cover a portion of each of the third wiring WR3 and the fourth wiring WR4 that is exposed in the space between the openings that define the opening pattern OPP. Specifically, the second covering portion CDP2' may cover a portion of the third wiring WR3 and the fourth wiring WR4 that is exposed in the space not covered by the first covering portion CDP1'.

[0120] According to some embodiments, the second cover portion CDP2' may contact the first cover portion CDP1'. For example, the second cover portion CDP2' may contact the side surface of the first cover portion CDP1'. Therefore, the first cover portion CDP1' may be connected by the second cover portion CDP2'. In other words, the first cover portion CDP1' arranged to correspond to the opening pattern OPP may be connected by the second cover portion CDP2'.

[0121] According to some embodiments, the second cover portion CDP2' may be formed in a separate process from the first cover portion CDP1'. For example, the second cover portion CDP2' may be formed after forming the first cover portion CDP1'. For example, the second cover portion CDP2' may be formed by laying a preliminary layer including an organic insulating material on the third wiring WR3, the fourth wiring WR4, and the first cover portion CDP1', and exposing and developing the preliminary layer.

[0122] According to some embodiments, the second cover portion CDP2' may include an organic insulating material. Examples of organic insulating materials that may be used as the second cover portion CDP2' may include photoresists, polyimide resins, polyamide resins, acrylic resins (eg, polyacrylic resins), and epoxy resins. These may be used alone or in combination with each other.

[0123] According to some embodiments, the second cover portion CDP2' may include an inorganic insulating material. Examples of the inorganic insulating material that may be used as the second cover portion CDP2' may include silicon oxide, silicon nitride, and silicon oxynitride. These may be used alone or in combination with each other.

[0124] Fig.11 It is along Fig.10 A cross-sectional view taken along line II-II'.

[0125] exist Fig.11 In the figure, for the convenience of description, only the cross-sectional structure of the region where the opening pattern OPP defined in the third wiring WR3 and the first cover portion CDP1' and the second cover portion CDP2' corresponding to the third wiring WR3 are positioned is shown. The cross-sectional structure of the region where the opening pattern OPP defined in the fourth wiring WR4 and the first cover portion CDP1' and the second cover portion CDP2' corresponding to the fourth wiring WR4 can be similar to that of FIG. Fig.11 The cross-sectional structures are basically the same.

[0126] Further references Fig.11 According to some embodiments, the thickness of the second cover part CDP2' may be different from the thickness of the first cover part CDP1'. That is, the upper surface of the first cover part CDP1' and the upper surface of the second cover part CDP2' may be located at different levels. Specifically, the thickness of the second cover part CDP2' may be less than the thickness of the first cover part CDP1'. That is, the upper surface of the second cover part CDP2' may be located at a lower level than the upper surface of the first cover part CDP1'. For example, the height from the upper surface of the first via insulation layer VIA1 to the upper surface of the second cover part CDP2' may be less than the height from the upper surface of the first via insulation layer VIA1 to the upper surface of the first cover part CDP1'.

[0127] That is, even in the case where the first cover portion CDP1' and the second cover portion CDP2' are not integrally formed and have separate configurations, the thickness of the second cover portion CDP2' may be smaller than the thickness of the first cover portion CDP1'.

[0128] Fig.12 and Fig.13 is a diagram showing some embodiments of the present invention. Figure 1Layout diagram of the enlarged area A.

[0129] For example, except that the cover film CDF and the cover part CDP are included instead of the first cover part CDP1 and the second cover part CDP2, refer to Fig.12 and Fig.13 The described embodiments can be compared with Figures 4 to 7 The described embodiments are substantially the same, and therefore, overlapping descriptions are omitted or simplified.

[0130] As reference Figure 6 As described, the third and fourth wirings WR3 and WR4 may have the opening pattern OPP exposing at least a portion of the first via insulating layer VIA1 .

[0131] Further references Fig.12 and Fig.13 , the cover film CDF and the cover portion CDP may be located on the first via insulating layer VIA1 , the third wiring WR3 , and the fourth wiring WR4 .

[0132] like Fig.12 As shown in , at least a portion of the cover film CDF may be located in the opening pattern OPP of each of the third wiring WR3 and the fourth wiring WR4. Therefore, the cover film CDF may contact the first via insulating layer VIA1 at the opening pattern OPP. At the same time, in the area defined with the opening pattern OPP, the third wiring WR3 and the fourth wiring WR4 may be substantially completely covered by the cover film CDF.

[0133] The cover film CDF may include an inorganic insulating material. Examples of inorganic insulating materials that can be used as the cover film CDF may include silicon oxide, silicon nitride, and silicon oxynitride. These may be used alone or in combination with each other.

[0134] like Fig.13 As shown in , the covering portion CDP may be located on the covering film CDF. For example, the covering portion CDP may contact the covering film CDF. Specifically, the covering portion CDP may cover at least a portion of the covering film CDF. For example, the covering portion CDP may cover a portion of the covering film CDF and expose another portion of the covering film CDF.

[0135] At least a portion of the cover portion CDP may be located in the opening pattern OPP. For example, the cover portion CDP may be arranged to fill the excess space of the opening pattern OPP that is not filled by the cover film CDF. That is, the cover portion CDP may be arranged to correspond to the opening pattern OPP. Therefore, the cover portion CDP may contact the cover film CDF in the opening pattern OPP.

[0136] The covering portion CDP may include an organic insulating material. Examples of organic insulating materials that may be used as the covering portion CDP may include photoresists, polyimide resins, polyamide resins, acrylic resins (eg, polyacrylic resins), and epoxy resins. These may be used alone or in combination with one another.

[0137] According to some embodiments, the cover portion CDP may be formed in the same process as the second via insulating layer VIA2. That is, the cover portion CDP may include the same material as the second via insulating layer VIA2. For example, the cover portion CDP and the second via insulating layer VIA2 may be formed simultaneously by laying a preparatory layer including an organic insulating material on the first via insulating layer VIA1, the third wiring WR3, the fourth wiring WR4, and the connection electrode CNE, and exposing and developing the preparatory layer.

[0138] According to some embodiments, the cover portion CDP may not contact the first via insulating layer VIA1. That is, since the cover film CDF is located on the first via insulating layer VIA1 in the opening pattern OPP and the cover portion CDP is formed on the cover film CDF, the cover portion CDP may not contact the first via insulating layer VIA1.

[0139] In the area defining the opening pattern OPP, the third wiring WR3 and the fourth wiring WR4 can be doubly covered by the cover film CDF and the cover part CDP. Therefore, even if a film peeling phenomenon occurs in which the cover part CDP peels off from the cover film CDF, the third wiring WR3 and the fourth wiring WR4 can be covered by the cover film CDF in the area defining the opening pattern OPP.

[0140] Therefore, in the subsequent process (for example, an etching process for forming the pixel electrode PE, etc.), the etching agent can be reduced or prevented from penetrating into the third wiring WR3 and / or the fourth wiring WR4 due to the peeling phenomenon of the covering portion CDP. Therefore, the problem of the third wiring WR3 and / or the fourth wiring WR4 being damaged due to the reaction with the etching agent can be reduced or prevented. In addition, the problem of the material included in the third wiring WR3 and / or the fourth wiring WR4 reacting with the etching agent to form particles can be reduced or prevented. Therefore, the display quality and durability of the display device DD can be improved.

[0141] Fig.14 It is along Fig.13 A cross-sectional view taken along line III-III'.

[0142] exist Fig.14In the figure, for the convenience of description, only the cross-sectional structure of the region where the opening pattern OPP defined in the third wiring WR3 and the cover film CDF corresponding to the third wiring WR3 and the cover portion CDP is positioned and defined is shown. The cross-sectional structure of the region where the opening pattern OPP defined in the third wiring WR3 and the cover film CDF corresponding to the fourth wiring WR4 and the cover portion CDP can be similar to that of FIG. Fig.14 The cross-sectional structures are basically the same.

[0143] Further references Fig.14 According to some embodiments, the thickness of the cover film CDF may be different from the thickness of the cover portion CDP. That is, the upper surface of the cover film CDF and the upper surface of the cover portion CDP may be located at different levels. Specifically, the thickness of the cover film CDF may be less than the thickness of the cover portion CDP. That is, the upper surface of the cover film CDF may be located at a lower level than the upper surface of the cover portion CDP. For example, the height from the upper surface of the first via insulating layer VIA1 to the upper surface of the cover film CDF may be less than the height from the upper surface of the first via insulating layer VIA1 to the upper surface of the cover portion CDP.

[0144] Since the cover film CDF has a thickness smaller than that of the cover portion CDP, the path of the gas generated from the first via insulating layer VIA1 and discharged through the opening pattern OPP (for example, a space where the cover portion CDP is not located on the third wiring WR3 and the fourth wiring WR4) may not be blocked. That is, even when the cover film CDF is located on the third wiring WR3 and the fourth wiring WR4, the discharge of the gas through the opening pattern OPP is not reduced or suppressed.

[0145] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate having a display area and a peripheral area adjacent to the display area; a first wiring in the peripheral region on the substrate; an insulating layer on the first wiring and covering at least a portion of the first wiring; a second wiring on the insulating layer, overlapping at least a portion of the insulating layer in a plan view, and having an opening pattern exposing at least a portion of the insulating layer; a first covering portion on the insulating layer and the second wiring to fill the opening pattern and expose at least a portion of the second wiring; as well as A second covering portion is on the second wiring and covers at least a portion of the second wiring exposed from the first covering portion.

2. The display device according to claim 1, wherein: The thickness of the second covering portion is smaller than the thickness of the first covering portion.

3. The display device according to claim 1, wherein: A height from an upper surface of the insulating layer to an upper surface of the second covering portion is smaller than a height from the upper surface of the insulating layer to an upper surface of the first covering portion.

4. The display device according to claim 1, wherein: The second covering portion contacts the first covering portion.

5. The display device according to claim 1, wherein: The first covering parts are connected by the second covering parts.

6. The display device according to claim 1, wherein: The second covering portion is spaced apart from the opening pattern in a plan view.

7. The display device according to claim 1, wherein: The first covering portion contacts the insulating layer.

8. The display device according to claim 1, wherein: The first cover portion and the second cover portion are integrated into one body without a separate interface.

9. The display device according to claim 8, wherein: The first covering portion and the second covering portion include an organic material.

10. The display device according to claim 1, wherein: The first wiring and the second wiring are in contact with each other to form a power voltage line, and The power voltage line transmits a power voltage to the light emitting elements in the display area.

11. A display device, comprising: A substrate having a display area and a peripheral area adjacent to the display area; a first wiring in the peripheral region on the substrate; an insulating layer on the first wiring and covering at least a portion of the first wiring; a second wiring on the insulating layer, overlapping at least a portion of the insulating layer in a plan view, and having an opening pattern exposing at least a portion of the insulating layer; a cover film on the insulating layer and the second wiring and covering the second wiring defining the opening pattern, wherein at least a portion of the cover film is in the opening pattern; and A covering portion is on the cover film and covers at least a portion of the cover film, wherein at least a portion of the covering portion is in the opening pattern.

12. The display device according to claim 11, wherein: The covering portion exposes at least a portion of the covering film.

13. The display device according to claim 11, wherein: The thickness of the cover film is smaller than the thickness of the cover portion.

14. The display device according to claim 11, wherein: A height from an upper surface of the insulating layer to an upper surface of the cover film is smaller than a height from the upper surface of the insulating layer to an upper surface of the cover portion.

15. The display device according to claim 11, wherein: The cover portion contacts the cover film.

16. The display device according to claim 11, wherein: The cover portion is not in contact with the insulating layer by the cover film.

17. The display device according to claim 11, wherein: The cover film contacts the insulating layer in the opening pattern.

18. The display device according to claim 11, wherein: The cover film includes an inorganic material, and The covering portion includes an organic material.

19. The display device according to claim 11, wherein: The first wiring and the second wiring are in contact with each other to form a power voltage line.

20. The display device according to claim 19, wherein: The power voltage line is configured to transmit a power voltage to the light emitting elements in the display area.

Images