Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. In the array substrate, a first reference signal is used to provide a pixel unit in a display area, and a second reference signal is used to provide a pixel unit in an aperture area. Different reference signals can be provided for the pixel unit in the display area and the pixel unit in the aperture area, thereby effectively improving the poor display effect of the aperture area. Meanwhile, the first reference signal is input into the display area through a second sub-reference signal line, and the second sub-reference signal line is connected into a mesh shape through a first sub-reference signal line, so that the display uniformity of the display area can be further improved. The second reference signal is input into the display area through a third sub-reference signal line, and the third sub-reference signal line is connected into a mesh shape through a fourth sub-reference signal line, so that the display uniformity of the aperture area can be further improved, thereby effectively improving the display effect of the product.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and flat display devices based on light emitting diode (LED) technology have been widely used in mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] However, the use performance of the current OLED display product needs to be improved. SUMMARY

[0004] Therefore, the present application aims to provide an array substrate, a display panel and a display device, which can provide different reference signals for the display area and the opening area, thereby improving the display effect of the product.

[0005] To achieve the above purpose, the present application provides an array substrate, which comprises:

[0006] a display area and an opening area located in the display area;

[0007] a reference signal line, the reference signal line comprising a first reference signal line and a second reference signal line;

[0008] the first reference signal line comprises a plurality of first sub-reference signal lines arranged along a first direction and extending along a second direction, and a plurality of second sub-reference signal lines arranged along the second direction and extending along the first direction; the first sub-reference signal lines are partially located in the display area and partially located in the opening area; the second sub-reference signal lines are located in the display area; the first sub-reference signal lines and the second sub-reference signal lines are located in different layers and are connected by a dielectric layer via hole at the intersection;

[0009] the second reference signal line comprises a plurality of third sub-reference signal lines arranged along a first direction and extending along a second direction, and a plurality of fourth sub-reference signal lines arranged along the second direction and extending along the first direction; the third sub-reference signal lines are partially located in the display area and partially located in the opening area; the fourth sub-reference signal lines are located in the opening area; the third sub-reference signal lines and the fourth sub-reference signal lines are located in different layers and are connected by a dielectric layer via hole at the intersection;

[0010] The signal input module configures a first reference signal on the second sub-reference signal line and a second reference signal on the third sub-reference signal line.

[0011] In one embodiment, the signal input module includes a first reference signal input module and a second reference signal input module.

[0012] The first reference signal input module is connected to the second sub-reference signal line and configures a first reference signal on the second sub-reference signal line.

[0013] The second reference signal input module is connected to the third sub-reference signal line and configures a second reference signal on the third sub-reference signal line.

[0014] In one embodiment, the array substrate further includes:

[0015] A frame region at least partially surrounding the display region, the frame region including a first frame region, a second frame region, and a third frame region, the first frame region, the display region, and the second frame region being arranged along the first direction, and the display region and the third frame region being arranged along the second direction.

[0016] The first frame region and the second frame region are each provided with the first reference signal input module, and both ends of the second sub-reference signal line are connected to the first reference signal input module in the first frame region and the second frame region, respectively.

[0017] The third frame region is provided with the second reference signal input module, and one end of the third sub-reference signal line close to the third frame region is connected to the second reference signal input module.

[0018] In one embodiment, the array substrate further includes:

[0019] A plurality of pixel units, part of which is located in the display region and part of which is located in the aperture region, the pixel unit including a pixel circuit, the pixel circuit including a driving module for driving a light emitting device to emit light, a first reset module for resetting a gate of the driving module, and a second reset module for resetting an anode of the light emitting module, the reference signal line including a gate reset signal line connected to the first reset module and an anode reset signal line connected to the second reset module.

[0020] In one embodiment, the first sub-reference signal line in the gate reset signal line, the third sub-reference signal line in the gate reset signal line, the first sub-reference signal line in the anode reset signal line, and the third sub-reference signal line in the anode reset signal line are arranged in the same layer.

[0021] In one embodiment, the pixel unit further comprises a third reset module for resetting the source of the driving module, and the reference signal line comprises a source reset signal line connected to the third reset module.

[0022] In one embodiment, the first sub-reference signal line in the gate reset signal line, the third sub-reference signal line in the gate reset signal line, the first sub-reference signal line in the anode reset signal line, and the third sub-reference signal line in the anode reset signal line are arranged in the same layer, and the first sub-reference signal line in the source reset signal line and the third sub-reference signal line in the source reset signal line are arranged in the same layer.

[0023] In one embodiment, the first sub-reference signal line and the third sub-reference signal line are arranged in the same layer and are alternately arranged in the first direction.

[0024] Preferably, the second sub-reference signal lines are continuously arranged in the second direction.

[0025] Preferably, part of the second sub-reference signal lines are disconnected in the aperture region.

[0026] Preferably, the fourth sub-reference signal lines are continuously arranged in the second direction and are located in the disconnected region of the second sub-reference signal lines.

[0027] Preferably, the second sub-reference signal lines and the fourth sub-reference signal lines are arranged in the same layer.

[0028] Based on the same inventive concept, the present application further discloses a display panel comprising the array substrate as described above.

[0029] Based on the same inventive concept, the present application further discloses a display device comprising the display panel as described above.

[0030] Compared with the prior art, the array substrate provided by the present application can provide different reference signals for the pixel units in the display region and the aperture region, which can effectively improve the problem of poor display effect in the aperture region. At the same time, connecting the reference signal lines into a network can further improve the uniformity of display and effectively improve the display effect of the product. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present application or the related art, the accompanying drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute part of the present application, and for those skilled in the art, other drawings can also be obtained without creative work based on these drawings.

[0032] Figure 1 A schematic diagram of an array substrate;

[0033] Figure 2 A schematic diagram of an array substrate provided by an embodiment of the present application;

[0034] Figure 3 A schematic diagram of an array substrate; Figure 2 A schematic diagram of an array substrate;

[0035] Figure 4 A schematic diagram of an array substrate; Figure 2 A schematic diagram of an array substrate;

[0036] Figure 5 A schematic diagram of an array substrate provided by another embodiment of the present application;

[0037] Figure 6 A schematic diagram of an array substrate provided by another embodiment of the present application;

[0038] Figure 7 A schematic diagram of a pixel circuit provided by another embodiment of the present application;

[0039] Figure 8 A circuit diagram of a pixel circuit provided by another embodiment of the present application.

[0040] Label explanation:

[0041] 100, array substrate; 110, display area; 120, aperture area; 130, frame area; 131, first frame area; 132, second frame area; 133, third frame area; 134, fourth frame area;

[0042] 2, first reference signal line; 21, first sub-reference signal line; 22, second sub-reference signal line;

[0043] 3, second reference signal line; 31, third sub-reference signal line; 32, fourth sub-reference signal line;

[0044] 4, first reference signal input module;

[0045] 5, second reference signal input module;

[0046] 200, pixel circuit. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0048] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as their common meanings to those having ordinary skills in the art to which the present application belongs. The terms "first", "second" and similar terms used in the embodiments of the present application do not represent any order, number or importance, but are only used to distinguish different components. The terms "include", "contain" and similar terms mean that the components or objects before the terms cover the components or objects listed after the terms and their equivalents, and do not exclude other components or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0049] Referring to Figure 1 As shown in FIG. 1, an array substrate 100 is provided, which includes a display area 110 and an aperture area 120 in the display area 110, and the aperture area 120 is usually used to accommodate a camera or the like.

[0050] Among them, due to the requirements of light transmittance and the like, the pixel units in the aperture area 120 are usually designed differently from the pixel units in the display area 110, for example, the pixel units in the aperture area 120 are usually smaller. Therefore, under the same driving signal, the display effects of the pixel units in the aperture area 120 and the pixel units in the display area 110 have differences, the display effect of the aperture area 120 is poor, which leads to the phenomenon of Mura (display unevenness).

[0051] Based on this, the present application provides an array substrate scheme to solve the above problems, which will be described in detail with reference to the following embodiments.

[0052] Referring to Figures 2-4 As shown in FIG. 1, an array substrate 100 is provided, which includes a display area 110 and an aperture area 120 in the display area 110, and the aperture area 120 is usually used to accommodate a camera or the like.

[0053] The array substrate 100 further includes a reference signal line and a signal input module, and the reference signal line includes a first reference signal line 2 and a second reference signal line 3.

[0054] The first reference signal line 2 includes a plurality of first sub-reference signal lines 21 arranged along a first direction (e.g., the X direction in the figure) and extending along a second direction (e.g., the Y direction in the figure), and a plurality of second sub-reference signal lines 22 arranged along the second direction and extending along the first direction; the first sub-reference signal lines 21 are partially located in the display area 110 and partially located in the aperture area 120; the second sub-reference signal lines 22 are located in the display area 110; the first sub-reference signal lines 21 and the second sub-reference signal lines 22 are located in different layers and connected by a via in the medium layer at the intersection.

[0055] The second reference signal line 3 includes a plurality of third sub-reference signal lines 31 arranged along the first direction and extending along the second direction, and a plurality of fourth sub-reference signal lines 32 arranged along the second direction and extending along the first direction; the third sub-reference signal lines 31 are partially located in the display area 110 and partially located in the aperture area 120; the fourth sub-reference signal lines 32 are located in the aperture area 120; the third sub-reference signal lines 31 and the fourth sub-reference signal lines 32 are located in different layers and connected by a via in the medium layer at the intersection.

[0056] The signal input module is configured to input a first reference signal on the second sub-reference signal line 22 and a second reference signal on the third sub-reference signal line 31.

[0057] The pixel units in the aperture area 120 are different from the pixel units in the display area 110, the first reference signal is used to provide the pixel units in the display area 110, and the second reference signal is used to provide the pixel units in the aperture area 120, so that different reference signals can be provided for the pixel units in the display area 110 and the pixel units in the aperture area 120, thereby effectively improving the poor display effect of the aperture area 120.

[0058] Meanwhile, the first reference signal is input into the display area 110 through the second sub-reference signal line 22, and the second sub-reference signal line 22 is connected into a mesh shape through the first sub-reference signal line 21, which can further improve the display uniformity of the display area 110; the second reference signal is input into the display area 110 through the third sub-reference signal line 31, and the third sub-reference signal line 31 is connected into a mesh shape through the fourth sub-reference signal line 32, which can further improve the display uniformity of the aperture area 120, thereby effectively improving the display effect of the product.

[0059] In one embodiment, the first sub-reference signal lines 21 and the third sub-reference signal lines 31 are arranged in the same layer and alternately arranged along the first direction. Because the first sub-reference signal lines 21 and the third sub-reference signal lines 31 are both wired along the second direction and continuous along the second direction, they only need to be spaced apart along the first direction to achieve the same layer arrangement without interfering with each other.

[0060] Preferably, the second sub-reference signal lines 22 are arranged continuously in the second direction; further, part of the second sub-reference signal lines 22 are disconnected in the aperture region 120, i.e. the second sub-reference signal lines 22 do not pass through the aperture region 120.

[0061] Preferably, the fourth sub-reference signal lines 32 are arranged continuously in the second direction and are located in the disconnected region of the second sub-reference signal lines 22, i.e. in the aperture region 120, so as to realize the disconnection between the second sub-reference signal lines 22 and the fourth sub-reference signal lines 32.

[0062] In one embodiment, the second sub-reference signal lines 22 and the fourth sub-reference signal lines 32 are arranged in the same layer, so as to facilitate the simultaneous preparation and breaking of the second sub-reference signal lines 22 and the fourth sub-reference signal lines 32. In another embodiment, the second sub-reference signal lines 22 and the fourth sub-reference signal lines 32 are located in different layers.

[0063] Please continue to refer to Figure 2 In one embodiment, the signal input module includes a first reference signal input module 4 and a second reference signal input module 5; the first reference signal input module 4 is connected with the second sub-reference signal lines 22, and the first reference signal input module 4 configures a first reference signal on the second sub-reference signal lines 22; the second reference signal input module 5 is connected with the third sub-reference signal lines 31, and the second reference signal input module 5 configures a second reference signal on the third sub-reference signal lines 31.

[0064] By arranging two kinds of reference signal input modules, two different reference signals can be provided for the display region 110 and the aperture region 120 respectively, so as to effectively improve the poor display effect of the aperture region 120. In another embodiment, one reference signal input module can be used to provide two different reference signals in a time-division driving manner.

[0065] Please refer to Figure 5 and 6 In one embodiment, the array substrate 100 further includes a frame region 130, which is arranged at least partially around the display region 110, and the frame region 130 includes a first frame region 131, a second frame region 132 and a third frame region 133; the first frame region 131, the display region 110 and the second frame region 132 are arranged in the first direction, and the display region 110 and the third frame region 133 are arranged in the second direction.

[0066] The first frame area 131 and the second frame area 132 are each provided with a first reference signal input module 4, and two ends of the second sub-reference signal line 22 are connected with the first reference signal input modules 4 in the first frame area 131 and the second frame area 132 respectively; the third frame area 133 is provided with a second reference signal input module 5, and one end of the third sub-reference signal line 31 close to the third frame area 133 is connected with the second reference signal input module 5.

[0067] In the first direction, the second sub-reference signal line 22 and the fourth sub-reference signal line 32 are both continuous, and in the second direction, the second sub-reference signal line 22 is not continuous due to the existence of the aperture area 120. Therefore, the first reference signal input module 4 is arranged in the first frame area 131 and the second frame area 132 to input the first reference signal to the second sub-reference signal line 22 on both sides of the aperture area 120 respectively.

[0068] Further, the frame area 130 further includes a fourth frame area 134, and the fourth frame area 134 is located at one end of the display area 110 away from the third frame area 133, i.e., the fourth frame area 134, the display area 110 and the third frame area 133 are arranged in the second direction. In the embodiment, the third frame area 133 is usually a lower frame, and the fourth frame area 134 is usually an upper frame.

[0069] In one embodiment, the array substrate 100 further includes a plurality of pixel units, part of the pixel units are located in the display area 110, and part of the pixel units are located in the aperture area 120. The pixel unit includes a pixel circuit 200, the pixel circuit 200 includes a driving module for driving a light emitting device to emit light, a first reset module for resetting a gate of the driving module, and a second reset module for resetting an anode of the light emitting module. The reference signal line includes a gate reset signal line Vref1 connected with the first reset module, and an anode reset signal line Vref2 connected with the second reset module, as shown in the following figure. Figure 7

[0070] In the embodiment, before the light emitting module emits light, the gate of the driving module needs to be reset by the first reset module to improve the driving effect of the driving module, and then the anode of the light emitting module is reset by the second reset module to improve the light emitting effect of the light emitting module.

[0071] ​It should be noted that the pixel units in the display area 110 and the pixel units in the aperture area are different in size, but the driving circuit structures of the two are the same.

[0072] In one embodiment, the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2, and the third sub-reference signal line 31 in the anode reset signal line Vref2 are arranged on the same layer.

[0073] Specifically, the gate reset signal line Vref1 includes the first reference signal line 2 and the second reference signal line 3, and the anode reset signal line Vref2 also includes the first reference signal line 2 and the second reference signal line 3. Because the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2, and the third sub-reference signal line 31 in the anode reset signal line Vref2 are all wired along the second direction and are continuous along the second direction. Therefore, they only need to be spaced apart one by one along the first direction to achieve the same layer arrangement and mutual non-interference.

[0074] Please continue to refer to Figure 7 As shown in FIG. 2, in one embodiment, the pixel circuit 200 further includes a third reset module for resetting the source of the driving module, and the reference signal line includes a source reset signal line Vref3 connected with the third reset module. Wherein, before the first reset module resets the gate of the driving module, the signal on the source reset signal line Vref3 resets the source of the driving module.

[0075] In one embodiment, the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2, and the third sub-reference signal line 31 in the anode reset signal line Vref2 are arranged on the same layer, and the first sub-reference signal line 21 in the source reset signal line Vref3 and the third sub-reference signal line 31 in the source reset signal line Vref3 are arranged on the same layer.

[0076] Specifically, the gate reset signal line Vref1 includes the first reference signal line 2 and the second reference signal line 3, the anode reset signal line Vref2 also includes the first reference signal line 2 and the second reference signal line 3, and the source reset signal line Vref3 also includes the first reference signal line 2 and the second reference signal line 3. Since the first sub-reference signal line 21 in the gate reset signal line Vref1, the third sub-reference signal line 31 in the gate reset signal line Vref1, the first sub-reference signal line 21 in the anode reset signal line Vref2, the third sub-reference signal line 31 in the anode reset signal line Vref2, the first sub-reference signal line 21 in the source reset signal line Vref3, and the third sub-reference signal line 31 in the source reset signal line Vref3 are all routed along the second direction and are continuous along the second direction. Therefore, they only need to be spaced apart one by one along the first direction to achieve the same layer setting and mutual non-interference, which is convenient for preparation.

[0077] Further, the control end of the first reset module is connected with the scanning signal SN1, and the control end of the second reset module and the control end of the third reset module are connected with the scanning signal SP2.

[0078] Further, the pixel circuit 200 further includes a data writing module, the control end of the data writing module is connected with the scanning signal line SP1, the first end of the data writing module is connected with the data line Vdata, and the second end of the data writing module is connected with the first end of the driving module. The data writing module is used for writing a voltage related to the data voltage on the data line Vdata to the control end of the driving module in a data writing stage in response to the signal on the scanning signal line SP1, so as to facilitate the driving module to generate a driving current according to the data voltage in a light emitting stage, so as to drive the light emitting module to emit light.

[0079] Further, the pixel circuit 200 further includes a storage module, the storage module is connected with the control end of the driving module and is used for storing the voltage of the control end of the driving module; further, the storage module includes a storage capacitor, the first end of the storage capacitor is connected with the control end of the driving module, and the second end of the storage capacitor is connected with the first end of the driving module.

[0080] Further, the pixel circuit 200 further includes a compensation module, the control end of the compensation module is connected with the fourth scanning signal line SN2, the first end of the compensation module is connected with the control end of the driving module, the second end of the compensation module is connected with the second end of the driving module, and the compensation module is used for compensating the threshold voltage of the driving module.

[0081] Reference Figure 8As shown, in a specific embodiment, the pixel circuit 200 is taken as an example of an 8T1C circuit. Among them, the driving module includes transistor T1, the light-emitting module includes OLED or AMOLED, the data writing module includes transistor T2, the compensation module includes transistor T3, the first reset module includes transistor T4, the first light-emitting control module includes transistor T6, the second light-emitting control module includes transistor T5, the second reset module includes transistor T7, and the third reset module includes transistor T8. Among them, transistor T3 and transistor T4 are NMOS tubes, and transistor T1, transistor T2, transistor T5, transistor T6, transistor T7 and transistor T8 are PMOS tubes.

[0082] Another embodiment of the present application discloses a display panel, which comprises the array substrate 100 in the above-mentioned embodiments.

[0083] The display panel provided by the embodiment can provide different reference signals for the pixel units in the display area 110 and the aperture area 120, which can effectively improve the problem of poor display effect of the aperture area 120. Meanwhile, the reference signal lines are connected into a mesh shape, which can further improve the uniformity of display and is beneficial to improving the display performance of the display panel.

[0084] Another embodiment of the present application discloses a display device, which comprises the display panel in the above-mentioned embodiments. The display device can be mounted on a smart device (such as a mobile phone, a VR device, a computer, a television, a vehicle-mounted display, etc.).

[0085] The display device provided by the embodiment can provide different reference signals for the pixel units in the display area 110 and the aperture area 120 in the array substrate 100 in the display panel, which can effectively improve the problem of poor display effect of the aperture area 120. Meanwhile, the reference signal lines are connected into a mesh shape, which can further improve the uniformity of display and is beneficial to improving the display performance of the display device.

[0086] Although the present application has been described in conjunction with the specific embodiments thereof, it is obvious to those skilled in the art that many alternatives, modifications and variations to the specific embodiments will be apparent in light of the foregoing description.

[0087] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims can be performed in a different order than those described above and still achieve desirable results. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0088] Embodiments of the present application are intended to embrace all such alterations, modifications, and variations that fall within the broad scope of the appended claims. Accordingly, any one or more features of a given embodiment are intended to be illustrative only and not limiting of the scope of the application.

Claims

1. An array substrate, characterized in that, include: Display area and opening area located in the display area; A reference signal line, wherein the reference signal line includes a first reference signal line and a second reference signal line; The first reference signal line includes multiple first sub-reference signal lines arranged along a first direction and extending along a second direction, and multiple second sub-reference signal lines arranged along the second direction and extending along the first direction; the first sub-reference signal lines are partially located in the display area and partially located in the aperture area; the second sub-reference signal lines are located in the display area; the first sub-reference signal lines and the second sub-reference signal lines are located in different layers and are connected at their intersections through dielectric layer vias; The second reference signal line includes multiple third sub-reference signal lines arranged along a first direction and extending along a second direction, and multiple fourth sub-reference signal lines arranged along the second direction and extending along the first direction; the third sub-reference signal lines are partially located in the display area and partially located in the aperture area; the fourth sub-reference signal lines are located in the aperture area; the third sub-reference signal lines and the fourth sub-reference signal lines are located in different layers and are connected at their intersections through dielectric layer vias; A signal input module, wherein a first reference signal is configured on the second sub-reference signal line and a second reference signal is configured on the third sub-reference signal line; The signal input module includes a first reference signal input module and a second reference signal input module; The first reference signal input module is connected to the second sub-reference signal line, and the first reference signal input module configures a first reference signal on the second sub-reference signal line; The second reference signal input module is connected to the third sub-reference signal line, and the second reference signal input module is configured on the third sub-reference signal line; Multiple pixel units are located, partly in the display area and partly in the aperture area; each pixel unit includes a pixel circuit, the pixel circuit including a driving module for driving the light-emitting device to emit light, a first reset module for resetting the gate of the driving module, and a second reset module for resetting the anode of the light-emitting device; the reference signal line includes a gate reset signal line connected to the first reset module and an anode reset signal line connected to the second reset module. The first sub-reference signal line, the third sub-reference signal line, the first sub-reference signal line, and the third sub-reference signal line in the gate reset signal line are arranged in the same layer.

2. The array substrate as described in claim 1, characterized in that, The array substrate further includes: A border area, which at least partially surrounds the display area, includes a first border area, a second border area, and a third border area. The first border area, the display area, and the second border area are arranged along a first direction, and the display area and the third border area are arranged along a second direction. Both the first border area and the second border area are provided with the first reference signal input module, and the two ends of the second sub-reference signal line are respectively connected to the first reference signal input module in the first border area and the second border area; The third border area is provided with the second reference signal input module, and the end of the third sub-reference signal line near the third border area is connected to the second reference signal input module.

3. The array substrate as described in claim 1, characterized in that, The pixel unit further includes a third reset module for resetting the source of the driving module, and the reference signal line includes a source reset signal line connected to the third reset module.

4. The array substrate as described in claim 3, characterized in that, The first sub-reference signal line, the third sub-reference signal line, the first sub-reference signal line, and the third sub-reference signal line in the anode reset signal line are arranged on the same layer, and the first sub-reference signal line and the third sub-reference signal line in the source reset signal line are arranged on the same layer.

5. The array substrate as described in claim 1, characterized in that, The first sub-reference signal line and the third sub-reference signal line are disposed on the same layer and are arranged alternately in the first direction.

6. The array substrate as claimed in claim 1, characterized in that, The second sub-reference signal lines are arranged continuously in the second direction.

7. The array substrate as claimed in claim 1, characterized in that, Part of the second sub-reference signal line is disconnected in the aperture area.

8. The array substrate as claimed in claim 1, characterized in that, The fourth sub-reference signal line is arranged continuously in the second direction and is located in the disconnected area of ​​the second sub-reference signal line.

9. The array substrate as claimed in claim 1, characterized in that, The second sub-reference signal line is disposed on the same layer as the fourth sub-reference signal line.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

11. A display device, characterized in that, Includes the display panel as described in claim 10.

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