Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a node contact structure array which comprises a plurality of node contact structures which are arranged at intervals in multiple rows and multiple columns; the plurality of node contact structures located in the same row are arranged at intervals along a first direction, and the plurality of node contact structures located in the same column are arranged at intervals along a second direction; orthographic projections of the plurality of node contact structures in the same row in a plane perpendicular to the first direction are overlapped, and orthographic projections of the plurality of node contact structures in the same column in a plane perpendicular to the second direction are overlapped; the first direction intersects with the second direction; the capacitor contact pads are located on the upper surfaces of the node contact structures and are arranged in one-to-one correspondence with the node contact structures; the orthographic projections of the plurality of capacitor contact pads in the same column in a plane perpendicular to the second direction are partially overlapped or not overlapped. According to the invention, short circuit between adjacent capacitor contact pads and adjacent capacitors can be avoided, so that the performance of the device is ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Each capacitor in the capacitor array needs to be electrically connected to other device structures in the substrate by means of a capacitor contact structure; the capacitor contact structure includes a node contact structure and a capacitor contact pad located on the upper surface of the node contact structure.

[0003] As process nodes continue to shrink, the spacing between adjacent capacitor contact structures is getting smaller and smaller. Since capacitors and capacitor contact structures are set one-to-one, the spacing between adjacent capacitors is also getting smaller and smaller, which can easily lead to a short circuit between adjacent capacitor contact pads or a short circuit between adjacent capacitors, thereby affecting the performance of the device. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same to address the problem that as the process nodes continue to shrink, the spacing between adjacent capacitor contact structures and the spacing between adjacent capacitors are smaller, which can easily lead to short circuits between adjacent capacitor contact pads or between adjacent capacitors, thereby affecting the performance of the device.

[0005] In order to achieve the above objectives, in a first aspect, the present disclosure provides a semiconductor structure, comprising:

[0006] A node contact structure array, comprising a plurality of node contact structures spaced in multiple rows and columns; the plurality of node contact structures in the same row are spaced along a first direction, and the plurality of node contact structures in the same column are spaced along a second direction; the orthographic projections of the plurality of node contact structures in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of node contact structures in the same column in a plane perpendicular to the second direction overlap; the first direction intersects with the second direction;

[0007] A plurality of capacitor contact pads are located on the upper surface of the node contact structure and are arranged one-to-one corresponding to the node contact structure; the orthographic projections of the plurality of capacitor contact pads located in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

[0008] In one embodiment, the semiconductor structure further comprises:

[0009] substrate;

[0010] A dielectric layer, located on the substrate;

[0011] A plurality of node contact holes are located in the dielectric layer; and the node contact structures are located in the node contact holes.

[0012] In one embodiment, the plurality of capacitor contact pads include:

[0013] A plurality of first capacitor contact pads are arranged in a plurality of rows and columns at intervals; the plurality of first capacitor contact pads in the same row are arranged at intervals along the first direction and are arranged in a one-to-one correspondence with the node contact structures;

[0014] A plurality of second capacitor contact pads are arranged in a plurality of rows and columns at intervals; a plurality of the second capacitor contact pads in the same row are arranged at intervals along the first direction and are arranged in a one-to-one correspondence with the node contact structures;

[0015] Multiple rows of the first capacitor contact pads and multiple rows of the second capacitor contact pads are alternately arranged along the second direction, and the orthographic projections of the first capacitor contact pads and the adjacent second capacitor contact pads in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

[0016] In one embodiment, the orthographic projection of each of the first capacitor contact pads on the upper surface of the substrate partially overlaps with the orthographic projection of the corresponding node contact structure on the upper surface of the substrate, and the first capacitor contact pad is offset toward the first side of the corresponding node contact structure along the first direction;

[0017] The orthographic projection of each second capacitor contact pad on the upper surface of the substrate partially overlaps with the orthographic projection of the corresponding node contact structure on the upper surface of the substrate, and the second capacitor contact pad is offset toward the second side of the corresponding node contact structure along the first direction; the second side is opposite to the first side.

[0018] In one embodiment, the cross-sectional shape of the first capacitor contact pad and the cross-sectional shape of the second capacitor contact pad are both rectangular.

[0019] In one embodiment, the upper surface of the node contact structure is lower than the top surface of the node contact hole; the first capacitor contact pad and the second capacitor contact pad both include:

[0020] A metal barrier layer, located on the sidewalls of the node contact hole, the upper surface of the node contact structure and the upper surface of the dielectric layer;

[0021] The metal conductive layer is located on the surface of the metal barrier layer.

[0022] In one embodiment, the semiconductor structure further comprises:

[0023] A capacitor array, the capacitor array comprising a plurality of capacitors arranged in a plurality of rows and columns, the capacitors being arranged in one-to-one correspondence with the capacitor contact pads; the orthographic projections of the plurality of capacitors in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of capacitors in the same column in a plane perpendicular to the second direction overlap.

[0024] In a second aspect, the present disclosure further provides a method for preparing a semiconductor structure, comprising:

[0025] A node contact structure array is formed, wherein the node contact structure array includes a plurality of node contact structures arranged in multiple rows and columns; the plurality of node contact structures in the same row are arranged in a first direction, and the plurality of node contact structures in the same column are arranged in a second direction; the orthographic projections of the plurality of node contact structures in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of node contact structures in the same column in a plane perpendicular to the second direction overlap; the first direction intersects with the second direction;

[0026] A plurality of capacitor contact pads are formed on the node contact structure array and are arranged in multiple rows and columns; the plurality of capacitor contact pads are arranged one-to-one corresponding to the node contact structures; and the orthographic projections of the plurality of capacitor contact pads in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

[0027] In one embodiment, before forming the node contact structure array, the method further includes:

[0028] providing a substrate;

[0029] forming a dielectric layer on the substrate;

[0030] A plurality of node contact holes arranged in multiple rows and columns are formed in the dielectric layer; the node contact structure is formed in the node contact holes.

[0031] In one embodiment, the upper surface of the node contact structure is lower than the upper surface of the node contact hole; the plurality of capacitor contact pads include a plurality of first capacitor contact pads and a plurality of second capacitor contact pads; the plurality of capacitor contact pads arranged in multiple rows and columns are formed on the node contact structure array, including:

[0032] A capacitor contact material layer is formed in the node contact hole and on the upper surface of the dielectric layer; the capacitor contact material layer located on the upper surface of the dielectric layer is in the form of a plurality of strip structures extending along a first direction and arranged at intervals along a second direction; the strip structures include a first strip structure and a second strip structure arranged alternately at intervals along the second direction;

[0033] forming a first patterned etching mask layer on the dielectric layer, wherein the first patterned etching mask layer has a plurality of first etching opening patterns arranged at intervals along the first direction, and the first etching opening patterns expose a portion of the first strip-shaped structure;

[0034] Etching the capacitor contact material layer based on the first patterned etching mask layer to obtain the first capacitor contact pad;

[0035] removing the first patterned etching mask layer;

[0036] forming a second patterned etching mask layer on the dielectric layer, wherein the second patterned etching mask layer has a plurality of second etching opening patterns arranged at intervals along the first direction, and the second etching opening patterns expose a portion of the second strip-shaped structure;

[0037] The capacitor contact material layer is etched based on the second patterned etching mask layer to obtain the second capacitor contact pad.

[0038] In one embodiment, forming a first patterned etching mask layer on the dielectric layer includes:

[0039] forming a first mask stack on the dielectric layer, wherein the first mask stack covers the strip structure;

[0040] forming a first patterned mask layer on the upper surface of the first mask stack, wherein the first patterned mask layer comprises a plurality of first mask patterns extending along the first direction and arranged at intervals along the second direction; the orthographic projection of the first mask pattern on the upper surface of the dielectric layer covers the second strip structure;

[0041] forming a second mask stack on the first mask stack, wherein the second mask stack covers the first mask pattern;

[0042] forming a second patterned mask layer on the upper surface of the second mask stack, wherein the second patterned mask layer comprises a plurality of second mask patterns extending along the second direction and arranged at intervals along the first direction;

[0043] forming a first sacrificial mask layer, wherein the first sacrificial mask layer covers the second mask pattern;

[0044] forming a first covering mask layer, wherein the first covering mask layer covers the first sacrificial mask layer and fills the gaps between the second mask patterns;

[0045] removing the first sacrificial mask layer to form a third patterned mask layer, wherein the third patterned mask layer includes a third mask pattern, and the third mask pattern includes a first opening pattern;

[0046] Based on the third patterned mask layer, the second mask stack and the first patterned mask layer are etched to obtain a fourth patterned mask layer, wherein the fourth patterned mask layer includes a fourth mask pattern, and the fourth mask pattern includes a second opening pattern;

[0047] The first mask stack is etched based on the fourth patterned mask layer to obtain the first patterned etching mask layer.

[0048] In one of the embodiments, an orthographic projection of the first etched opening pattern on the upper surface of the dielectric layer partially overlaps with the node contact hole, and the first etched opening pattern is offset toward a second side of the node contact hole along the first direction; an orthographic projection of the second etched opening pattern on the upper surface of the dielectric layer partially overlaps with the node contact hole, and the second etched opening pattern is offset toward a first side of the node contact hole along the first direction, and the first side and the second side are opposite sides.

[0049] In one embodiment, forming a second patterned etching mask layer on the dielectric layer includes:

[0050] forming a third mask stack on the dielectric layer, wherein the third mask stack covers the first capacitor contact pad and the second strip structure;

[0051] forming a fifth patterned mask layer on the upper surface of the third mask stack, wherein the fifth patterned mask layer comprises a plurality of fifth mask patterns extending along the first direction and arranged at intervals along the second direction; the orthographic projection of the fifth mask pattern on the upper surface of the dielectric layer covers the first capacitor contact pad;

[0052] forming a fourth mask stack on the third mask stack, wherein the fourth mask stack covers the fifth patterned mask layer;

[0053] forming a sixth patterned mask layer on the upper surface of the fourth mask stack, wherein the sixth patterned mask layer comprises a plurality of sixth mask patterns extending along the second direction and arranged at intervals along the first direction;

[0054] forming a second sacrificial mask layer, wherein the second sacrificial mask layer covers the sixth mask pattern;

[0055] forming a second covering mask layer, wherein the second covering mask layer covers the second sacrificial mask layer and fills the gaps between the sixth mask patterns;

[0056] removing the second sacrificial mask layer to form a seventh patterned mask layer, wherein the seventh patterned mask layer includes a seventh mask pattern, and the seventh mask pattern includes a third opening pattern;

[0057] Based on the seventh patterned mask layer, the fourth mask stack and the fifth patterned mask layer are etched to obtain an eighth patterned mask layer, wherein the eighth patterned mask layer includes an eighth mask pattern, and the eighth mask pattern includes a fourth opening pattern;

[0058] The third mask stack is etched based on the eighth patterned mask layer to obtain the second patterned etching mask layer.

[0059] In one embodiment, forming a capacitor contact material layer in the node contact hole and on the upper surface of the dielectric layer includes:

[0060] forming a metal barrier material layer on the sidewalls of the node contact hole, the upper surface of the node contact structure and the upper surface of the dielectric layer;

[0061] forming a metal conductive material layer on the surface of the metal barrier material layer;

[0062] The metal conductive material layer and the metal barrier material layer are patterned to obtain the capacitor contact material layer.

[0063] In one embodiment, after forming a plurality of capacitor contact pads arranged in multiple rows and columns on the node contact structure array, the method further comprises:

[0064] A capacitor array is formed, wherein the capacitor array includes a plurality of capacitors arranged in a plurality of rows and columns, and the capacitors are arranged in a one-to-one correspondence with the capacitor contact pads; the orthographic projections of the plurality of capacitors located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of capacitors located in the same column in a plane perpendicular to the second direction overlap.

[0065] The present disclosure has the following beneficial effects:

[0066] The semiconductor structure disclosed in the present invention can avoid short circuits between adjacent capacitor contact pads and adjacent capacitors by arranging multiple capacitor contact pads located in the same column so that their orthographic projections in a plane perpendicular to the second direction partially overlap or do not overlap, so that adjacent capacitor contact pads in the same column are staggered. This can ensure the performance of the device by avoiding short circuits between adjacent capacitor contact pads and adjacent capacitors.

[0067] The method for preparing a semiconductor structure disclosed in the present invention can avoid short circuits between adjacent capacitor contact pads and adjacent capacitors by arranging multiple capacitor contact pads located in the same column so that their orthographic projections in a plane perpendicular to the second direction partially overlap or do not overlap, so that adjacent capacitor contact pads in the same column are staggered. This can ensure the performance of the device by avoiding short circuits between adjacent capacitor contact pads and between adjacent capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0069] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0070] Figure 2 A schematic diagram of a top view of a structure obtained in step S10 in a method for preparing a semiconductor structure provided in an embodiment;

[0071] Figure 3 For along Figure 2 Schematic diagram of the cross-sectional structure along the AA direction;

[0072] Figure 4 is a flow chart of step S11 in a method for preparing a semiconductor structure provided in an embodiment;

[0073] Figure 5 A schematic diagram of a top view of a structure obtained in step S111 of a method for preparing a semiconductor structure provided in an embodiment;

[0074] Figure 6 For along Figure 5 Schematic diagram of the cross-sectional structure along the AA direction;

[0075] Figure 7 For along Figure 6 Schematic diagram of the cross-sectional structure along the BB direction;

[0076] Figure 8 is a flow chart of step S112 in a method for preparing a semiconductor structure provided in an embodiment;

[0077] Fig. 9 It is a schematic diagram of a top view of a structure obtained after forming a first patterned photoresist layer in step S1122 of a method for preparing a semiconductor structure provided in an embodiment;

[0078] Fig.10 For along Fig. 9 Schematic diagram of the cross-sectional structure in the CC direction;

[0079] Fig.11 A schematic diagram of a top view of a structure obtained in step S1122 of a method for preparing a semiconductor structure provided in an embodiment;

[0080] Fig.12 For along Fig.11 Schematic diagram of the cross-sectional structure in the CC direction;

[0081] Fig.13 It is a schematic diagram of a top view of a structure obtained after forming a second patterned photoresist layer in step S1124 of a method for preparing a semiconductor structure provided in an embodiment;

[0082] Fig.14 For along Fig.13 Schematic diagram of the cross-sectional structure in the middle DD direction;

[0083] Fig.15 A schematic diagram of a top view of a structure obtained in step S1124 in a method for preparing a semiconductor structure provided in an embodiment;

[0084] Fig.16 For along Fig.15 Schematic diagram of the cross-sectional structure in the middle DD direction;

[0085] Fig.17 It is a schematic diagram of a top view of a structure obtained after forming a first covering dielectric layer in step S1126 of a method for preparing a semiconductor structure provided in an embodiment;

[0086] Fig.18 For along Fig.17 Schematic diagram of the cross-sectional structure along the EE direction;

[0087] Fig.19 A schematic diagram of a top view of a structure obtained in step S1128 in a method for preparing a semiconductor structure provided in an embodiment;

[0088] Fig. 20 For along Fig.19 Schematic diagram of the cross-sectional structure in the FF direction;

[0089] Fig.21 A schematic diagram of a cross-sectional structure of a structure obtained in step S1129 in a method for preparing a semiconductor structure provided in an embodiment;

[0090] Fig. 22 A schematic diagram of a top view of a structure obtained in step S113 of a method for preparing a semiconductor structure provided in an embodiment;

[0091] Fig.23 For along Fig. 22 Schematic diagram of the cross-sectional structure along the GG direction;

[0092] Fig.24 A schematic diagram of a top view of a structure obtained in step S116 of a method for preparing a semiconductor structure provided in an embodiment;

[0093] Fig.25 For along Fig.24 Schematic diagram of the cross-sectional structure along the HH direction;

[0094] Fig.26 A schematic diagram of a top view of a structure obtained after a capacitor array is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0095] Fig. 27 For along Fig.26 Schematic diagram of the cross-sectional structure along the II direction.

[0096] Description of reference numerals:

[0097] 10. dielectric layer; 11. node contact hole; 12. node contact structure; 13. capacitor contact pad; 131. first capacitor contact pad; 132. second capacitor contact pad; 133. metal barrier layer; 1331. metal barrier material layer; 134. metal conductive layer; 1341. metal conductive material layer; 135. capacitor contact material layer; 1351. first strip structure; 1352. second strip structure; 14. capacitor; 15. first patterned etching mask layer; 151. first etching opening pattern; 16. first mask stack; 161. amorphous carbon layer; 162. first silicon oxynitride layer; 17. first pattern , a first silicon oxide layer; 1711, a first mask pattern; 172, a first spin-on carbon layer; 173, a second silicon oxynitride layer; 174, a first patterned photoresist layer; 175, a fourth patterned mask layer; 1751, a second opening pattern; 18, a second mask stack; 181, a second silicon oxide layer; 182, a second spin-on carbon layer; 183, a third silicon oxide layer; 19, a second patterned mask layer; 191, a third spin-on carbon layer; 192, a third silicon oxynitride layer; 193, a second mask pattern; 20, a second patterned photoresist layer; 21, a first sacrificial mask layer; 22, a first covering mask layer. DETAILED DESCRIPTION

[0098] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0099] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0100] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0101] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0102] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0103] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0104] Each capacitor in the capacitor array needs to be electrically connected to other device structures in the substrate by means of a capacitor contact structure; the capacitor contact structure includes a node contact structure and a capacitor contact pad located on the upper surface of the node contact structure.

[0105] As process nodes continue to shrink, the spacing between adjacent capacitor contact structures is getting smaller and smaller. Since capacitors and capacitor contact structures are set one-to-one, the spacing between adjacent capacitors is also getting smaller and smaller, which can easily lead to a short circuit between adjacent capacitor contact pads or a short circuit between adjacent capacitors, thereby affecting the performance of the device.

[0106] In the existing process, when forming a capacitor contact pad, if the capacitor contact pad is offset relative to the node contact structure, it is easy to cause a small contact area between the capacitor contact pad and the node contact structure, resulting in a large contact resistance, thereby affecting signal transmission.

[0107] In order to solve the above problems, the present disclosure provides a method for preparing a semiconductor structure, such as Figure 1 As shown, the method for preparing a semiconductor structure may include the following steps:

[0108] S10: forming a node contact structure array, the node contact structure array comprising a plurality of node contact structures arranged in multiple rows and columns; the plurality of node contact structures in the same row are arranged in a first direction, and the plurality of node contact structures in the same column are arranged in a second direction; the orthographic projections of the plurality of node contact structures in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of node contact structures in the same column in a plane perpendicular to the second direction overlap; the first direction intersects the second direction;

[0109] S11: forming a plurality of capacitor contact pads arranged in multiple rows and columns on the node contact structure array; the plurality of capacitor contact pads are arranged one-to-one corresponding to the node contact structures; the orthographic projections of the plurality of capacitor contact pads in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

[0110] The method for preparing the above-mentioned semiconductor structure can avoid short circuits between adjacent capacitor contact pads and adjacent capacitors by arranging multiple capacitor contact pads located in the same column so that their orthographic projections in a plane perpendicular to the second direction partially overlap or do not overlap, so that adjacent capacitor contact pads in the same column are staggered. This can ensure the performance of the device by avoiding short circuits between adjacent capacitor contact pads and adjacent capacitors.

[0111] As an example, see Figure 2 and Figure 3 Before step S10, the following steps may also be included:

[0112] providing a substrate (not shown);

[0113] forming a dielectric layer 10 on a substrate;

[0114] A plurality of node contact holes 11 are formed in the dielectric layer 10 and are arranged in a plurality of rows and columns.

[0115] As examples, the substrate may include but is not limited to a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate; in this embodiment, the substrate may be a silicon substrate.

[0116] As an example, the dielectric layer 10 may be formed on the substrate by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0117] As an example, the dielectric layer 10 may include but is not limited to a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.

[0118] As an example, multiple node contact holes 11 located in the same row can be arranged at intervals along the first direction, and multiple node contact holes 11 located in the same column can be arranged at intervals along the second direction; the orthographic projections of the multiple node contact holes 11 located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the multiple node contact holes 11 located in the same column in a plane perpendicular to the second direction overlap.

[0119] As an example, the node contact hole 11 may be formed in the dielectric layer 10 by using, but not limited to, a photolithography and etching process.

[0120] Specifically, the node contact hole 11 may penetrate the dielectric layer 10 along the thickness direction to expose the substrate below the dielectric layer 10 .

[0121] As an example, before forming the dielectric layer 10 on the substrate, the following steps may also be included:

[0122] A plurality of bit lines (not shown) arranged in parallel and spaced apart are formed on the substrate; the dielectric layer 10 fills the gaps between adjacent bit lines and covers the bit lines; and the node contact holes 11 are located between adjacent bit lines.

[0123] Specifically, the specific structure of the bit line is known to those skilled in the art and will not be described again here.

[0124] In step S10, refer to Figure 1 S10 steps in Figures 2 to 3 , forming a node contact structure array, the node contact structure array includes a plurality of node contact structures 12 arranged in multiple rows and columns; the plurality of node contact structures 12 located in the same row are arranged in a first direction, and the plurality of node contact structures 12 located in the same column are arranged in a second direction; the orthographic projections of the plurality of node contact structures 12 located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of node contact structures 12 located in the same column in a plane perpendicular to the second direction overlap; the first direction intersects with the second direction.

[0125] As an example, each node contact structure 12 is located in the node contact hole 11 and is arranged in a one-to-one correspondence with the node contact hole 11 .

[0126] As an example, forming the node contact structure 12 in the node contact hole 11 may include the following steps:

[0127] S101: forming a node contact material layer (not shown), the node contact material layer fills the node contact hole 11 and covers the upper surface of the dielectric layer 10;

[0128] S102: removing the node contact material layer located on the upper surface of the dielectric layer 10; the node contact material layer located on the upper surface of the dielectric layer 10 may be removed by, but is not limited to, a chemical mechanical polishing (CMP) process;

[0129] S103: etching back to remove part of the node contact material layer in the node contact hole 11, and the node contact material layer remaining in the node contact hole 11 is the node contact structure 12; specifically, the dry etching process may be used but is not limited to etching back to remove part of the node contact material layer in the node contact hole 11.

[0130] Specifically, the upper surface of the node contact structure 12 obtained after the back etching is lower than the upper surface of the node contact hole 12. Figure 3 shown.

[0131] In step S11, refer to Figure 1 Step S11 in Figures 4 to 25 , a plurality of capacitor contact pads 13 are formed on the node contact structure array and are arranged in multiple rows and columns; the plurality of capacitor contact pads 13 are arranged one-to-one corresponding to the node contact structures 12; the orthographic projections of the plurality of capacitor contact pads 13 located in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

[0132] As an example, see Fig.24 The plurality of capacitor contact pads 13 may include a plurality of first capacitor contact pads 131 and a plurality of second capacitor contact pads 132 .

[0133] As an example, see Figure 4 , step S11 may include the following steps:

[0134] S111: forming a capacitor contact material layer in the node contact hole and on the upper surface of the dielectric layer; the capacitor contact material layer on the upper surface of the dielectric layer is in the form of a plurality of strip structures extending along a first direction and arranged at intervals along a second direction; the strip structures include a first strip structure and a second strip structure arranged alternately at intervals along the second direction;

[0135] S112: forming a first patterned etching mask layer on the dielectric layer, wherein the first patterned etching mask layer has a plurality of first etching opening patterns arranged at intervals along a first direction, and the first etching opening patterns expose a portion of the first strip structure;

[0136] S113: etching the capacitor contact material layer based on the first patterned etching mask layer to obtain a first capacitor contact pad;

[0137] S114: removing the first patterned etching mask layer;

[0138] S115: forming a second patterned etching mask layer on the dielectric layer, wherein the second patterned etching mask layer has a plurality of second etching opening patterns arranged at intervals along the first direction, and the second etching opening patterns expose a portion of the second strip-shaped structure;

[0139] S116: etching the capacitor contact material layer based on the second patterned etching mask layer to obtain a second capacitor contact pad.

[0140] In step S111, refer to Figure 4 Step S111 in Figures 5 to 7 A capacitor contact material layer 135 is formed in the node contact hole 11 and on the upper surface of the dielectric layer 10; the capacitor contact material layer 135 located on the upper surface of the dielectric layer 10 is in the form of a plurality of strip structures extending along a first direction and arranged at intervals along a second direction; the strip structures include a first strip structure 1351 and a second strip structure 1352 arranged alternately at intervals along the second direction.

[0141] As an example, step S111 may include the following steps:

[0142] S1111: forming a metal barrier material layer 1331 on the sidewall of the node contact hole 11, the upper surface of the node contact structure 12 and the upper surface of the dielectric layer 10; specifically, the metal barrier material layer 1331 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process;

[0143] S1112: forming a metal conductive material layer 1341 on the upper surface of the metal barrier material layer 1331; specifically, the metal conductive material layer 1341 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the metal conductive material layer 1341 fills the node contact hole 11;

[0144] S1113: patterning the metal conductive material layer 1341 to obtain the capacitor contact material layer 135; specifically, the metal conductive material layer 1341 may be patterned by using a photolithography and etching process.

[0145] As an example, in step S1112, after forming the metal conductive material layer 1341 on the upper surface of the metal barrier material layer 1331, a step of planarizing the metal conductive material layer 1341 using a chemical mechanical polishing process is also included to make the upper surface of the metal conductive material layer 1341 flat.

[0146] As an example, the metal barrier material layer 1331 may include a titanium nitride layer, a titanium layer, or a stacked structure of a titanium layer and a titanium nitride layer; the metal conductive material layer 1341 may include but is not limited to a tungsten layer.

[0147] In step S112, refer to Figure 4 Step S112 in Figures 8 to 21 A first patterned etching mask layer 15 is formed on the dielectric layer 10 , wherein the first patterned etching mask layer 15 has a plurality of first etching opening patterns 151 arranged at intervals along a first direction, and the first etching opening patterns 151 expose a portion of the first strip structure 1351 .

[0148] As an example, Figure 8 As shown, step S112 may include the following steps:

[0149] S1121: forming a first mask stack on the dielectric layer, wherein the first mask stack covers the strip structure;

[0150] S1122: forming a first patterned mask layer on the upper surface of the first mask stack, wherein the first patterned mask layer includes a plurality of first mask patterns extending along the first direction and arranged at intervals along the second direction; an orthographic projection of the first mask pattern on the upper surface of the dielectric layer covers the second strip structure;

[0151] S1123: forming a second mask stack on the first mask stack, wherein the second mask stack covers the first mask pattern;

[0152] S1124: forming a second patterned mask layer on the upper surface of the second mask stack, wherein the second patterned mask layer includes a plurality of second mask patterns extending along the second direction and arranged at intervals along the first direction;

[0153] S1125: forming a first sacrificial mask layer, wherein the first sacrificial mask layer covers the second mask pattern;

[0154] S1126: forming a first covering mask layer, wherein the first covering mask layer covers the first sacrificial mask layer and fills the gaps between the second mask patterns;

[0155] S1127: removing the first sacrificial mask layer to form a third patterned mask layer, wherein the third patterned mask layer includes a third mask pattern, and the third mask pattern includes the first opening pattern;

[0156] S1128: etching the second mask stack and the first patterned mask layer based on the third patterned mask layer to obtain a fourth patterned mask layer, wherein the fourth patterned mask layer includes a fourth mask pattern, and the fourth mask pattern includes a second opening pattern;

[0157] S1129: etching the first mask stack based on the fourth patterned mask layer to obtain a first patterned etching mask layer.

[0158] In step S1121, refer to Figure 8 S1121 steps and Figures 9 and 10 , a first mask stack 16 is formed on the dielectric layer 10, and the first mask stack 16 covers the strip structure.

[0159] As an example, step S1121 may include the following steps:

[0160] S1121a: forming an amorphous carbon layer (ACL) 161 on the dielectric layer 10, wherein the amorphous carbon layer 161 covers the strip structure; specifically, the amorphous carbon layer 161 may be formed by, but is not limited to, a spin coating process;

[0161] S1121b: forming a first silicon oxynitride layer 162 on the upper surface of the amorphous carbon layer 161; specifically, the first silicon oxynitride layer 162 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0162] In step S1122, refer to Figure 8 Step S1122 in Figures 9 to 12 A first patterned mask layer 17 is formed on the upper surface of the first mask stack 16, and the first patterned mask layer 17 includes a plurality of first mask patterns 1711 extending along the first direction and arranged at intervals along the second direction; the orthographic projection of the first mask pattern 1711 on the upper surface of the dielectric layer 10 covers the second strip structure 1352.

[0163] As an example, step S1122 may include the following steps:

[0164] S1122a: forming a first silicon oxide layer 171 on the upper surface of the first mask stack 16; specifically, the first silicon oxide layer 171 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;

[0165] S1122b: forming a first spin-on hard mask (SOH) 172 on the upper surface of the first silicon oxide layer 171; specifically, the first spin-on carbon layer 172 may be formed by, but is not limited to, a spin coating process;

[0166] S1122c: forming a second silicon oxynitride layer 173 on the upper surface of the first spin-on carbon layer 172; specifically, the second silicon oxynitride layer 173 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;

[0167] S1122d: forming a first patterned photoresist layer 174 on the upper surface of the second silicon oxynitride layer 173, such as Fig. 9 and Fig.10 As shown; specifically, the first patterned photoresist layer 174 may be formed by, but not limited to, spin coating, curing and photolithography processes; the first patterned photoresist layer 174 defines the shape and position of the first mask pattern 1711;

[0168] S1122e: etching the second silicon oxynitride layer 173, the first spin-on carbon layer 172 and the first silicon oxide layer 171 based on the first patterned photoresist layer 174; specifically, the second silicon oxynitride layer 173, the first spin-on carbon layer 172 and the first silicon oxide layer 171 may be etched by, but not limited to, a dry etching process;

[0169] S1122f: removing the first patterned photoresist layer 174, the second silicon oxynitride layer 173 and the first spin-on carbon layer 172, so as to obtain the first patterned mask layer 17. Fig.11 and Fig.12 Specifically, the first patterned photoresist layer 174 may be removed by an ashing process, and the second silicon oxynitride layer 173 and the first spin-on carbon layer 172 may be removed by a chemical mechanical polishing process or an etching process.

[0170] In step S1123, refer to Figure 8 Step S1123 in Figure 13 to Figure 14 , a second mask stack 18 is formed on the first mask stack 16 , and the second mask stack 18 covers the first mask pattern 1711 .

[0171] As an example, step S1123 may include the following steps:

[0172] S1123a: forming a second silicon oxide layer 181 on the first mask stack 16, wherein the second silicon oxide layer 181 covers the first mask pattern 1711; specifically, the second silicon oxide layer 181 may be formed by, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;

[0173] S1123b: forming a second spin-on carbon layer 182 on the upper surface of the second silicon oxide layer 181; specifically, the second spin-on carbon layer 182 may be formed by, but is not limited to, a spin coating process;

[0174] S1123c: forming a third silicon oxide layer 183 on the upper surface of the second spin-on carbon layer 182; specifically, the third silicon oxide layer 183 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.

[0175] In step S1124, refer to Figure 8 Step S1124 in Figure 15 to Figure 16 A second patterned mask layer 19 is formed on the upper surface of the second mask stack 18. The second patterned mask layer 19 includes a plurality of second mask patterns 193 extending along the second direction and arranged at intervals along the first direction.

[0176] As an example, step S1124 may include the following steps:

[0177] S1124a: forming a third spin-on carbon layer 191 on the upper surface of the second mask stack 18; specifically, the third spin-on carbon layer 191 may be formed by, but is not limited to, a spin coating process;

[0178] S1124b: forming a third silicon oxynitride layer 192 on the upper surface of the third spin-on carbon layer 191; specifically, the third silicon oxynitride layer 192 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;

[0179] S1124c: forming a second patterned photoresist layer 20 on the upper surface of the third silicon oxynitride layer 192;

[0180] S1124d: Etch the third silicon oxynitride layer 192 and the third spin-on carbon layer 191 using a photolithography and etching process to obtain a second patterned mask layer 19.

[0181] In step S1125, refer to Figure 8 Step S1125 and Fig.18 , forming a first sacrificial mask layer 21 , the first sacrificial mask layer 21 covers the second mask pattern 193 .

[0182] Specifically, the first sacrificial mask layer 21 may be formed by, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.

[0183] In step S1126, refer to Figure 8 Step S1126 in Fig.17 and Fig.18 , forming a first covering mask layer 22 , the first covering mask layer 22 covers the first sacrificial mask layer 21 and fills the gaps between the second mask patterns 193 .

[0184] As an example, the first cover mask layer 22 may include but is not limited to a spin-on carbon layer; the first cover mask layer 22 may be formed by, but is not limited to, a spin coating process.

[0185] As an example, in step S1127, the first sacrificial mask layer 21 may be removed by, but not limited to, a dry etching process to form a third patterned mask layer (not shown).

[0186] It should be noted that when the upper surface of the first covering mask layer 22 is higher than the upper surface of the first sacrificial mask layer 21, it is necessary to first use a process such as chemical mechanical polishing to remove the first covering mask layer 22 located on the first sacrificial mask layer 21 to expose the first sacrificial mask layer 21, and then use but not limited to a dry etching process to remove the first sacrificial mask layer 21.

[0187] As an example, in step S1128, the second mask stack 18 and the first patterned mask layer 17 may be etched based on the third patterned mask layer using a dry etching process to obtain a fourth patterned mask layer 175. The fourth mask pattern 175 may include a plurality of second opening patterns 1751. The shape and number of the second opening patterns 1751 may be set according to actual needs. In this embodiment, the shape of the second opening pattern 1751 may be a rectangle, such as Fig.19 and Fig. 20 shown.

[0188] As an example, in step S1129, the first mask stack 16 may be etched based on the fourth patterned mask layer 175 using, but not limited to, a dry etching process to obtain a first patterned etching mask layer 15; the first patterned etching mask layer 15 may include an amorphous carbon layer 161 and a first silicon oxynitride layer 162 stacked sequentially from bottom to top, such as Fig.21 shown.

[0189] Specifically, the orthographic projection of the first etched opening pattern 151 on the upper surface of the dielectric layer 10 partially overlaps with the node contact hole 11, and the first etched opening pattern 151 is etched along the first direction toward the second side of the node contact hole 11 (ie, Fig. 22 to the right of the .

[0190] In step S113, refer to Figure 4 Step S113 in Figure 22 to Figure 23 , the capacitor contact material layer 35 is etched based on the first patterned etching mask layer 15 to obtain a first capacitor contact pad 131 .

[0191] As an example, a dry etching process may be used but is not limited thereto to etch the capacitor contact material layer 135 based on the first patterned etching mask layer to obtain the first capacitor contact pad 131 .

[0192] Specifically, the first capacitor contact pad 131 extends from the node contact hole 11 to the upper surface of the dielectric layer 10 on the first side of the node contact hole 11, that is, the orthographic projection of the first capacitor contact pad 131 on the upper surface of the substrate and the orthographic projection of the corresponding node contact structure 12 (that is, the node contact structure 12 located below the first capacitor contact pad 131) on the upper surface of the substrate partially overlap, and the first capacitor contact pad 131 is offset toward the first side of the corresponding node contact structure 12 along the first direction, that is, the orthographic projection of the first capacitor contact pad 131 on the upper surface of the dielectric layer 10 is offset toward the first side of the node contact hole 11 where the first capacitor contact pad 131 is located.

[0193] As an example, in step S114 , the first patterned etching mask layer 15 may be removed by, but is not limited to, a grinding process or an etching process.

[0194] As an example, step S115 may include the following steps: forming a second patterned etching mask layer on the dielectric layer, including:

[0195] S1151: forming a third mask stack (not shown) on the dielectric layer 10, the third mask stack covering the first capacitor contact pad 131 and the second strip structure 1352;

[0196] S1152: forming a fifth patterned mask layer (not shown) on the upper surface of the third mask stack, wherein the fifth patterned mask layer includes a plurality of fifth mask patterns (not shown) extending along the first direction and arranged at intervals along the second direction; the orthographic projection of the fifth mask pattern on the upper surface of the dielectric layer 10 covers the first capacitor contact pad 131;

[0197] S1153: forming a fourth mask stack (not shown) on the third mask stack, wherein the fourth mask stack covers the fifth patterned mask layer;

[0198] S1154: forming a sixth patterned mask layer (not shown) on the upper surface of the fourth mask stack, wherein the sixth patterned mask layer includes a plurality of sixth mask patterns (not shown) extending along the second direction and arranged at intervals along the first direction;

[0199] S1155: forming a second sacrificial mask layer (not shown), the second sacrificial mask layer covering the sixth mask pattern;

[0200] S1156: forming a second covering mask layer (not shown), the second covering mask layer covers the second sacrificial mask layer and fills the gaps between the sixth mask patterns;

[0201] S1157: removing the second sacrificial mask layer to form a seventh patterned mask layer (not shown), the seventh patterned mask layer including a seventh mask pattern (not shown), the seventh mask pattern including a third opening pattern (not shown);

[0202] S1158: etching the fourth mask stack and the fifth patterned mask layer based on the seventh patterned mask layer to obtain an eighth patterned mask layer (not shown), wherein the eighth patterned mask layer includes an eighth mask pattern (not shown), and the eighth mask pattern includes a fourth opening pattern (not shown);

[0203] S1159: etching the third mask stack (not shown) based on the eighth patterned mask layer to obtain a second patterned etching mask layer.

[0204] As an example, the specific method in steps S1151 to S1159 is substantially the same as the specific method for forming the first patterned etching mask layer 15 in steps S1121 to S1129. For details, please refer to the aforementioned method for forming the first patterned etching mask layer 15, which will not be repeated here.

[0205] As an example, the orthographic projection of the second etched opening pattern on the upper surface of the dielectric layer 10 partially overlaps with the node contact hole 11, and the second etched opening pattern is etched toward the first side of the node contact hole 11 (ie, Fig.24 and Fig.25 ), the first side and the second side are opposite sides.

[0206] As an example, in step S116 , a dry etching process may be used but is not limited thereto to etch the capacitor contact material layer 135 based on the second patterned etching mask layer to obtain the second capacitor contact pad 132 .

[0207] Specifically, the second capacitor contact pad 132 extends from the node contact hole 11 to the upper surface of the dielectric layer 10 on the second side of the node contact hole 11, that is, the orthographic projection of the second capacitor contact pad 132 on the upper surface of the substrate and the orthographic projection of the corresponding node contact structure 12 (that is, the node contact structure 12 located below the second capacitor contact pad 132) on the upper surface of the substrate partially overlap, and the second capacitor contact pad 132 is offset toward the second side of the corresponding node contact structure 12 along the first direction, that is, the orthographic projection of the second capacitor contact pad 132 on the upper surface of the dielectric layer 10 is offset toward the second side of the node contact hole 11 where the first capacitor contact pad 132 is located.

[0208] For example, see Fig.26 and Fig. 27 After step S11, the following steps may also be included:

[0209] S12: forming a capacitor array, wherein the capacitor array comprises a plurality of capacitors 14 arranged in a plurality of rows and columns, and the capacitors 14 are arranged in a one-to-one correspondence with the capacitor contact pads; the orthographic projections of the plurality of capacitors 14 located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of capacitors 14 located in the same column in a plane perpendicular to the second direction overlap.

[0210] Specifically, the capacitor 14 may include a lower electrode (not shown), a capacitor dielectric layer (not shown) and an upper electrode (not shown); the lower electrode is in contact with the capacitor contact pad; the capacitor dielectric layer is located on the upper surface of the lower electrode; and the upper electrode is located on the upper surface of the capacitor dielectric layer.

[0211] In another embodiment, please continue to refer to Figures 1 to 27 The present disclosure also provides a semiconductor structure, the semiconductor structure comprising:

[0212] A node contact structure array, the node contact structure array includes a plurality of node contact structures 12 spaced in multiple rows and columns; the plurality of node contact structures 12 located in the same row are spaced along a first direction, and the plurality of node contact structures 12 located in the same column are spaced along a second direction; the orthographic projections of the plurality of node contact structures 12 located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of node contact structures 12 located in the same column in a plane perpendicular to the second direction overlap; the first direction intersects with the second direction;

[0213] A plurality of capacitor contact pads are located on the upper surface of the node contact structure 12 and are arranged one-to-one with the node contact structure 12; the orthographic projections of the plurality of capacitor contact pads located in the same column in the plane perpendicular to the second direction partially overlap or do not overlap.

[0214] In the above semiconductor structure, by arranging multiple capacitor contact pads located in the same column so that their orthographic projections in the plane of the second direction partially overlap or do not overlap, adjacent capacitor contact pads in the same column are staggered, which can avoid short circuits between adjacent capacitor contact pads and adjacent capacitors, thereby ensuring the performance of the device.

[0215] In one embodiment, the semiconductor structure may further include: a substrate (not shown); a dielectric layer 10 located on the substrate; a plurality of node contact holes 11 located in the dielectric layer 10; and a node contact structure 12 located in the node contact holes 11.

[0216] As examples, the substrate may include but is not limited to a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate; in this embodiment, the substrate may be a silicon substrate.

[0217] As an example, the dielectric layer 10 may include but is not limited to a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.

[0218] As an example, multiple node contact holes 11 located in the same row can be arranged at intervals along the first direction, and multiple node contact holes 11 located in the same column can be arranged at intervals along the second direction; the orthographic projections of the multiple node contact holes 11 located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the multiple node contact holes 11 located in the same column in a plane perpendicular to the second direction overlap.

[0219] Specifically, the node contact hole 11 may penetrate the dielectric layer 10 along the thickness direction to expose the substrate below the dielectric layer 10 .

[0220] As an example, the semiconductor structure may further include: a plurality of bit lines (not shown) arranged in parallel and spaced apart; a dielectric layer 10 filling the gaps between adjacent bit lines and covering the bit lines; and a node contact structure 12 located between adjacent bit lines.

[0221] As an example, Figure 22 to Figure 25 As shown, the multiple capacitor contact pads may include: multiple first capacitor contact pads 131, the multiple first capacitor contact pads 131 are arranged in multiple rows and columns; the multiple first capacitor contact pads 131 located in the same row are arranged in a first direction and are arranged one-to-one with the node contact structure 12; multiple second capacitor contact pads 132, the second capacitor contact pads 132 are arranged in multiple rows and columns; the multiple second capacitor contact pads 132 located in the same row are arranged in a first direction and are arranged one-to-one with the node contact structure 12; multiple rows of first capacitor contact pads 131 and multiple rows of second capacitor contact pads 132 are alternately arranged in the second direction, and the orthographic projection of each first capacitor contact pad 131 and the adjacent second capacitor contact pad 132 in the same column in a plane perpendicular to the second direction partially overlap or do not overlap; that is, the adjacent first capacitor contact pads 131 and second capacitor contact pads 132 located in the same column are staggered.

[0222] As an example, the orthographic projection of each first capacitor contact pad 131 on the upper surface of the substrate partially overlaps with the orthographic projection of the corresponding node contact structure 12 on the upper surface of the substrate, and the first capacitor contact pad 131 is extended toward the first side of the corresponding node contact structure 12 along the first direction (i.e., Fig.24 The orthographic projection of each second capacitor contact pad 132 on the upper surface of the substrate partially overlaps with the orthographic projection of the corresponding node contact structure 12 on the upper surface of the substrate, and the second capacitor contact pad 132 is offset along the first direction to the second side of the corresponding node contact structure 12 (i.e., Fig.24 The second side is offset to the right side of the first side.

[0223] As an example, the cross-sectional shape of the first capacitor contact pad 131 and the cross-sectional shape of the second capacitor contact pad 132 are both rectangular. In the case where the first capacitor contact pad 131 and the second capacitor contact pad 132 are both offset from the node contact structure 12, the cross-sectional shape of the first capacitor contact pad 131 and the cross-sectional shape of the second capacitor contact pad 132 are both set to be rectangular, compared with the solution in which the cross-sectional shape of the first capacitor contact pad 131 and the cross-sectional shape of the second capacitor contact pad 132 are both rhombus-shaped, it can ensure that the first capacitor contact pad 131 and the second capacitor contact pad 132 have a larger contact area with the node contact structure 12, reduce the contact resistance, and thus ensure the transmission of the signal.

[0224] As an example, the upper surface of the node contact structure 12 is lower than the top surface of the node contact hole 11; the first capacitor contact pad 131 and the second capacitor contact pad 132 both include: a metal barrier layer 133, the metal barrier layer 133 is located on the side wall of the node contact hole 11, the upper surface of the node contact structure 12 and the upper surface of the dielectric layer 10; a metal conductive layer 134, the metal conductive layer 134 is located on the surface of the metal barrier layer 133.

[0225] Specifically, the first capacitor contact pad 131 extends from the node contact hole 11 to the upper surface of the dielectric layer 10 on the first side of the node contact hole 11, that is, the orthographic projection of the first capacitor contact pad 131 on the upper surface of the substrate and the orthographic projection of the corresponding node contact structure 12 on the upper surface of the substrate partially overlap, and the first capacitor contact pad 131 is offset toward the first side of the corresponding node contact structure 12 along the first direction, that is, the orthographic projection of the first capacitor contact pad 131 on the upper surface of the dielectric layer 10 is offset toward the first side of the node contact hole 11 where the first capacitor contact pad 131 is located. The second capacitor contact pad 132 extends from the node contact hole 11 to the upper surface of the dielectric layer 10 on the second side of the node contact hole 11, that is, the orthographic projection of the second capacitor contact pad 132 on the upper surface of the substrate partially overlaps with the orthographic projection of the corresponding node contact structure 12 on the upper surface of the substrate, and the second capacitor contact pad 132 is offset toward the second side of the corresponding node contact structure 12 along the first direction, that is, the orthographic projection of the second capacitor contact pad 132 on the upper surface of the dielectric layer 10 is offset toward the second side of the node contact hole 11 where the first capacitor contact pad 132 is located.

[0226] As an example, the metal barrier layer 133 may include a titanium nitride layer, a titanium layer, or a stacked structure of a titanium layer and a titanium nitride layer; the metal conductive layer 1341 may include but is not limited to a tungsten layer.

[0227] As an example, Fig.26 and Fig. 27 As shown, the semiconductor structure may also include: a capacitor array, the capacitor array includes a plurality of capacitors 14 arranged in multiple rows and columns, and the capacitors 14 are arranged in a one-to-one correspondence with the capacitor contact pads 12; the orthographic projections of the plurality of capacitors 14 located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of capacitors 14 located in the same column in a plane perpendicular to the second direction overlap.

[0228] Specifically, the capacitor 14 may include a lower electrode (not shown), a capacitor dielectric layer (not shown) and an upper electrode (not shown); the lower electrode is in contact with the capacitor contact pad; the capacitor dielectric layer is located on the upper surface of the lower electrode; and the upper electrode is located on the upper surface of the capacitor dielectric layer.

[0229] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0230] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A node contact structure array, comprising a plurality of node contact structures spaced in multiple rows and columns; The plurality of node contact structures in the same row are arranged at intervals along the first direction, and the plurality of node contact structures in the same column are arranged at intervals along the second direction; the orthographic projections of the plurality of node contact structures in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of node contact structures in the same column in a plane perpendicular to the second direction overlap; The first direction intersects the second direction; A plurality of capacitor contact pads are located on the upper surface of the node contact structure and are arranged one-to-one corresponding to the node contact structure; the orthographic projections of the plurality of capacitor contact pads located in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: substrate; A dielectric layer, located on the substrate; A plurality of node contact holes are located in the dielectric layer; The node contact structure is located in the node contact hole.

3. The semiconductor structure according to claim 2, characterized in that: The plurality of capacitor contact pads include: A plurality of first capacitor contact pads are arranged in a plurality of rows and columns at intervals; the plurality of first capacitor contact pads in the same row are arranged at intervals along the first direction and are arranged in a one-to-one correspondence with the node contact structures; A plurality of second capacitor contact pads are arranged in a plurality of rows and columns at intervals; a plurality of the second capacitor contact pads in the same row are arranged at intervals along the first direction and are arranged in a one-to-one correspondence with the node contact structures; Multiple rows of the first capacitor contact pads and multiple rows of the second capacitor contact pads are alternately arranged along the second direction, and the orthographic projections of the first capacitor contact pads and the adjacent second capacitor contact pads in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

4. The semiconductor structure according to claim 3, characterized in that: The orthographic projection of each of the first capacitor contact pads on the upper surface of the substrate partially overlaps with the orthographic projection of the corresponding node contact structure on the upper surface of the substrate, and the first capacitor contact pad is offset toward a first side of the corresponding node contact structure along the first direction; The orthographic projection of each second capacitor contact pad on the upper surface of the substrate partially overlaps with the orthographic projection of the corresponding node contact structure on the upper surface of the substrate, and the second capacitor contact pad is offset toward the second side of the corresponding node contact structure along the first direction; the second side is opposite to the first side.

5. The semiconductor structure according to claim 3, characterized in that: The cross-sectional shape of the first capacitor contact pad and the cross-sectional shape of the second capacitor contact pad are both rectangular.

6. The semiconductor structure according to claim 2, characterized in that: The upper surface of the node contact structure is lower than the top surface of the node contact hole; the first capacitor contact pad and the second capacitor contact pad both include: A metal barrier layer, located on the sidewalls of the node contact hole, the upper surface of the node contact structure and the upper surface of the dielectric layer; The metal conductive layer is located on the surface of the metal barrier layer.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: Also includes: A capacitor array, the capacitor array comprising a plurality of capacitors arranged in a plurality of rows and columns, wherein the capacitors are arranged in a one-to-one correspondence with the capacitor contact pads; The orthographic projections of the plurality of capacitors in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of capacitors in the same column in a plane perpendicular to the second direction overlap.

8. A method for preparing a semiconductor structure, characterized in that: include: forming a node contact structure array, wherein the node contact structure array comprises a plurality of node contact structures arranged in multiple rows and columns; The plurality of node contact structures in the same row are arranged at intervals along the first direction, and the plurality of node contact structures in the same column are arranged at intervals along the second direction; the orthographic projections of the plurality of node contact structures in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of node contact structures in the same column in a plane perpendicular to the second direction overlap; The first direction intersects the second direction; Forming a plurality of capacitor contact pads arranged in multiple rows and columns on the node contact structure array; The plurality of capacitor contact pads are arranged in one-to-one correspondence with the node contact structures; the orthographic projections of the plurality of capacitor contact pads in the same column in a plane perpendicular to the second direction partially overlap or do not overlap.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: Before forming the node contact structure array, the method further includes: providing a substrate; forming a dielectric layer on the substrate; A plurality of node contact holes arranged in multiple rows and columns are formed in the dielectric layer; the node contact structure is formed in the node contact holes.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The upper surface of the node contact structure is lower than the upper surface of the node contact hole; the plurality of capacitor contact pads include a plurality of first capacitor contact pads and a plurality of second capacitor contact pads; The method comprises forming a plurality of capacitor contact pads arranged in multiple rows and columns on the node contact structure array, comprising: A capacitor contact material layer is formed in the node contact hole and on the upper surface of the dielectric layer; the capacitor contact material layer located on the upper surface of the dielectric layer is in the form of a plurality of strip structures extending along a first direction and arranged at intervals along a second direction; the strip structures include a first strip structure and a second strip structure arranged alternately at intervals along the second direction; forming a first patterned etching mask layer on the dielectric layer, wherein the first patterned etching mask layer has a plurality of first etching opening patterns arranged at intervals along the first direction, and the first etching opening patterns expose a portion of the first strip-shaped structure; Etching the capacitor contact material layer based on the first patterned etching mask layer to obtain the first capacitor contact pad; removing the first patterned etching mask layer; forming a second patterned etching mask layer on the dielectric layer, wherein the second patterned etching mask layer has a plurality of second etching opening patterns arranged at intervals along the first direction, and the second etching opening patterns expose a portion of the second strip-shaped structure; The capacitor contact material layer is etched based on the second patterned etching mask layer to obtain the second capacitor contact pad.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The step of forming a first patterned etching mask layer on the dielectric layer comprises: forming a first mask stack on the dielectric layer, wherein the first mask stack covers the strip structure; forming a first patterned mask layer on the upper surface of the first mask stack, wherein the first patterned mask layer comprises a plurality of first mask patterns extending along the first direction and arranged at intervals along the second direction; the orthographic projection of the first mask pattern on the upper surface of the dielectric layer covers the second strip structure; forming a second mask stack on the first mask stack, wherein the second mask stack covers the first mask pattern; forming a second patterned mask layer on the upper surface of the second mask stack, wherein the second patterned mask layer comprises a plurality of second mask patterns extending along the second direction and arranged at intervals along the first direction; forming a first sacrificial mask layer, wherein the first sacrificial mask layer covers the second mask pattern; forming a first covering mask layer, wherein the first covering mask layer covers the first sacrificial mask layer and fills the gaps between the second mask patterns; removing the first sacrificial mask layer to form a third patterned mask layer, wherein the third patterned mask layer includes a third mask pattern, and the third mask pattern includes a first opening pattern; Based on the third patterned mask layer, the second mask stack and the first patterned mask layer are etched to obtain a fourth patterned mask layer, wherein the fourth patterned mask layer includes a fourth mask pattern, and the fourth mask pattern includes a second opening pattern; The first mask stack is etched based on the fourth patterned mask layer to obtain the first patterned etching mask layer.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that: The orthographic projection of the first etching opening pattern on the upper surface of the dielectric layer partially overlaps with the node contact hole, and the first etching opening pattern is offset toward the second side of the node contact hole along the first direction; The orthographic projection of the second etched opening pattern on the upper surface of the dielectric layer partially overlaps with the node contact hole, and the second etched opening pattern is offset toward a first side of the node contact hole along the first direction, and the first side and the second side are opposite sides.

13. The method for preparing a semiconductor structure according to claim 10, characterized in that: The forming of a second patterned etching mask layer on the dielectric layer comprises: forming a third mask stack on the dielectric layer, wherein the third mask stack covers the first capacitor contact pad and the second strip structure; forming a fifth patterned mask layer on the upper surface of the third mask stack, wherein the fifth patterned mask layer comprises a plurality of fifth mask patterns extending along the first direction and arranged at intervals along the second direction; the orthographic projection of the fifth mask pattern on the upper surface of the dielectric layer covers the first capacitor contact pad; forming a fourth mask stack on the third mask stack, wherein the fourth mask stack covers the fifth patterned mask layer; forming a sixth patterned mask layer on the upper surface of the fourth mask stack, wherein the sixth patterned mask layer comprises a plurality of sixth mask patterns extending along the second direction and arranged at intervals along the first direction; forming a second sacrificial mask layer, wherein the second sacrificial mask layer covers the sixth mask pattern; forming a second covering mask layer, wherein the second covering mask layer covers the second sacrificial mask layer and fills the gaps between the sixth mask patterns; removing the second sacrificial mask layer to form a seventh patterned mask layer, wherein the seventh patterned mask layer includes a seventh mask pattern, and the seventh mask pattern includes a third opening pattern; Based on the seventh patterned mask layer, the fourth mask stack and the fifth patterned mask layer are etched to obtain an eighth patterned mask layer, wherein the eighth patterned mask layer includes an eighth mask pattern, and the eighth mask pattern includes a fourth opening pattern; The third mask stack is etched based on the eighth patterned mask layer to obtain the second patterned etching mask layer.

14. The method for preparing a semiconductor structure according to claim 10, characterized in that: The forming of a capacitor contact material layer in the node contact hole and on the upper surface of the dielectric layer comprises: forming a metal barrier material layer on the sidewalls of the node contact hole, the upper surface of the node contact structure and the upper surface of the dielectric layer; forming a metal conductive material layer on the surface of the metal barrier material layer; The metal conductive material layer and the metal barrier material layer are patterned to obtain the capacitor contact material layer.

15. The method for preparing a semiconductor structure according to any one of claims 8 to 14, characterized in that: After forming a plurality of capacitor contact pads arranged in multiple rows and columns on the node contact structure array, the method further comprises: A capacitor array is formed, wherein the capacitor array includes a plurality of capacitors arranged in a plurality of rows and columns, and the capacitors are arranged in a one-to-one correspondence with the capacitor contact pads; the orthographic projections of the plurality of capacitors located in the same row in a plane perpendicular to the first direction overlap, and the orthographic projections of the plurality of capacitors located in the same column in a plane perpendicular to the second direction overlap.

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