Semiconductor structure and preparation method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a preparation method of the semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure comprises a substrate which is provided with a first surface and a second surface which are opposite to each other and comprises a first area and a second area; the first conductive column is located in the first area of the substrate and penetrates through the substrate; the through hole capacitor is positioned in the second area of the substrate; the through hole capacitor comprises a second conductive column which penetrates through the substrate; the stacking layer comprises an upper electrode layer, a dielectric layer and a lower electrode layer; the stacking layer surrounds the second conductive column and further covers the first surface of the first area of the substrate, and the upper electrode layer covers the side wall of the second conductive column. According to the embodiment of the invention, the suppression effect of the semiconductor structure on high-frequency power supply noise can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Art

[0002] With the rapid development of high-performance computing applications such as artificial intelligence (AI), the power demand of chips has increased dramatically, and the current change rate has also become faster, which has put forward higher requirements for power stability and noise suppression. Although traditional deep trench capacitors (DTCs) perform well in suppressing high-frequency power noise, they cannot effectively meet the power management challenges of current and future high-performance computing chips due to their relatively small capacitance.

[0003] Therefore, there is an urgent need for a technical solution to effectively suppress high-frequency power supply noise to meet the needs of high-performance computing for low latency, high bandwidth and stable power management.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure, which can improve the suppression effect of the semiconductor structure on high-frequency power supply noise.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a semiconductor structure is provided.

[0008] include:

[0009] A substrate having a first surface and a second surface opposite to each other, the substrate comprising a first region and a second region;

[0010] A first conductive column, the first conductive column is located in the first region of the substrate and penetrates the substrate;

[0011] A through-hole capacitor, the through-hole capacitor is located in the second region of the substrate;

[0012] Among them, the through-hole capacitor includes: a second conductive column, the second conductive column passes through the substrate; a stacked layer, the stacked layer includes an upper electrode layer, a dielectric layer, and a lower electrode layer; the stacked layer surrounds the second conductive column and also covers the first surface of the first area of ​​the substrate, and the upper electrode layer covers the side wall of the second conductive column.

[0013] In one embodiment, the second conductive pillar and the upper electrode layer are made of different materials, and the upper electrode layer and the lower electrode layer are made of the same material.

[0014] In one embodiment, a top surface of the second conductive pillar is substantially flush with a top surface of the stacked layer on the first surface.

[0015] In one embodiment, a diameter of the first conductive pillar is greater than a diameter of the second conductive pillar.

[0016] In one embodiment, the semiconductor structure further includes: an insulating layer, which covers the through-hole capacitor; a first contact plug, which is located in the insulating layer and electrically connected to the second conductive column; and a second contact plug, which passes through the upper electrode layer and the dielectric layer and is electrically connected to the lower electrode layer.

[0017] In one embodiment, the semiconductor structure further includes: a redistribution layer, the redistribution layer covers the insulating layer, and the first contact plug is electrically connected to the power pad through the redistribution layer, and the second contact plug is electrically connected to the ground pad.

[0018] In one embodiment, the semiconductor structure further includes: a trench capacitor, the trench capacitor is in the second region of the substrate, and the trench capacitor and the through-hole capacitor share a stacking layer.

[0019] In one embodiment, the semiconductor structure further includes: a third contact plug located in the insulating layer and electrically connected to the upper electrode layer; and a fourth contact plug penetrating the upper electrode layer and the dielectric layer and electrically connected to the lower electrode layer.

[0020] In one embodiment, the ratio of the depth of the trench capacitor to the height of the second conductive pillar is 1 / 4-2 / 3.

[0021] In one embodiment, the semiconductor structure further includes: a first isolation layer, the first isolation layer covers the second surface of the substrate; and a bottom metal layer, the bottom metal layer penetrates the first isolation layer and is electrically connected to the first conductive column and the second conductive column respectively.

[0022] According to another aspect of the present disclosure, there is provided a method for preparing a semiconductor structure, comprising:

[0023] Providing a substrate, the substrate comprising a first surface, the substrate comprising a first region and a second region;

[0024] forming a first groove in a first region of the substrate and simultaneously forming a second groove in a second region of the substrate;

[0025] forming a first conductive column in the first groove;

[0026] A lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially conformally formed in the second groove, and a third groove is formed, wherein the lower electrode layer, the dielectric layer, and the upper electrode layer form a stacked layer, and the stacked layer also covers the first surface of the first region of the substrate;

[0027] A second conductive column is formed in the third groove, and the stacked layer and the second conductive column form a through-hole capacitor;

[0028] The surface of the substrate opposite to the first surface is thinned to expose the first conductive pillar and the second conductive pillar, thereby forming a second surface of the substrate opposite to the first surface.

[0029] In one embodiment, after forming a first groove in a first area of ​​the substrate and forming a second groove in a second area of ​​the substrate, the preparation method further includes forming a groove in the second area of ​​the substrate; while sequentially forming stacked layers in the second groove, the stacked layers are also formed in the groove, and the groove and the stacked layers constitute a groove capacitor.

[0030] In one embodiment, after forming the second conductive column in the third groove, the preparation method further includes forming an insulating layer, the insulating layer covers the through-hole capacitor, forming a first contact plug and a second contact plug in the insulating layer, the first contact plug is electrically connected to the second conductive column; the second contact plug is electrically connected to the lower electrode layer.

[0031] In one embodiment, the preparation method further includes forming a redistribution layer, the redistribution layer covers the insulating layer, and the first contact plug is electrically connected to the power pad and the second contact plug is electrically connected to the ground pad through the redistribution layer.

[0032] In one embodiment, the preparation method further includes forming a first isolation layer on the second surface, and forming a bottom metal layer on the first isolation layer, wherein the bottom metal layer penetrates the first isolation layer and is electrically connected to the first conductive column and the second conductive column respectively.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0035] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown; Figure 2 A top view of a substrate provided for an embodiment of the present disclosure; Figure 3-14 A schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown; DETAILED DESCRIPTION

[0036] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0037] In the three-dimensional integrated circuit (3DIC) packaging technology, the packaging structure consists of multiple key components, including system-on-chip, high-bandwidth memory, silicon interposer and substrate. This packaging method tightly integrates different chips and memory components to improve the performance and efficiency of the overall system while reducing signal delay and power consumption.

[0038] In early 3D integrated circuit packaging designs, high-frequency capacitance was mainly provided by deep trench capacitors on silicon interposers. Deep trench capacitors can effectively suppress power supply noise, especially under high-frequency operating conditions, due to their high capacitance density and low equivalent series resistance (ESR) characteristics. However, with the development of high-performance computing, such as the rise of AI applications, the power demand and current change rate of chips have increased dramatically, which has put higher requirements on power supply stability and noise suppression. Traditional deep trench capacitors cannot meet the more stringent power management requirements.

[0039] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for preparing the semiconductor structure. By setting a through-hole capacitor, the capacitance value of the semiconductor structure can be increased, and the through-hole capacitor can also be used as a part of the power path PDN (Power Delivery Network) to improve the performance of the power network, thereby improving the semiconductor structure's suppression effect on high-frequency power noise.

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown;

[0042] Reference Figure 1As shown, in one embodiment, a semiconductor structure 100,

[0043] include:

[0044] A substrate 110, wherein the substrate 110 has a first surface and a second surface opposite to each other, and the substrate 110 includes a first region I and a second region II;

[0045] A first conductive column 120 , wherein the first conductive column 120 is located in the first region I of the substrate 110 and penetrates the substrate 110 ;

[0046] A through-hole capacitor 130 , wherein the through-hole capacitor 130 is located in the second region II of the substrate 110 ;

[0047] Among them, the through-hole capacitor 130 includes: a second conductive column 131, the second conductive column 131 passes through the substrate 110; a stacked layer 135, the stacked layer 135 includes an upper electrode layer 132, a dielectric layer 133, and a lower electrode layer 134; the stacked layer 135 surrounds the second conductive column 131 and also covers the first surface of the first region I of the substrate 110, and the upper electrode layer 132 covers the side wall of the second conductive column 131.

[0048] Reference Figure 1-Figure 2 , the semiconductor structure 100 is described in detail.

[0049] The material of the substrate 110 can be silicon, germanium, silicon germanium, silicon carbide and other materials. In some embodiments, the substrate 110 can be a silicon interposer, which is usually made of silicon material and has a high-density wiring layer, which can achieve high-speed, low-latency interconnection between chips and provide efficient distribution of power and signals. At the same time, the silicon interposer can integrate various functions, including power management circuits, capacitors, resistors, etc., to optimize the power network, reduce power noise, and improve signal integrity and overall system performance.

[0050] The substrate 110 includes a first region I and a second region II. Figure 2 As shown, the first region I can be located in the middle area of ​​the substrate 110, which is a key area for signal transmission and is used to set silicon through vias for signal transmission. The second region II can be located in the corner area of ​​the substrate 110 and is used to set a capacitor structure for suppressing power supply noise. Since the capacitor structure is crucial to power management but has little effect on signal transmission, setting it in the corner area can avoid interfering with high-speed signal transmission in the middle area, while making full use of the space of the substrate and optimizing the overall performance.

[0051] The first conductive column 120 is located in the first region I of the substrate 110 and penetrates the substrate 110; the first conductive column 120 is used to transmit signals. The first conductive column 120 penetrates the entire substrate 110, so that the upper and lower chips or packaging components can be directly electrically connected, thereby significantly reducing signal delay and power consumption, and improving data transmission speed and efficiency. The process used by the first conductive column 120 is through silicon via (TSV, Through Silicon Via) technology, which is a high-density packaging technology. Through silicon via technology realizes vertical electrical interconnection by filling conductive materials such as copper, polysilicon and tungsten. In some embodiments, the material of the first conductive column 120 can be copper.

[0052] The through-hole capacitor 130 is located in the second region II of the substrate 110; wherein the through-hole capacitor 130 includes: a second conductive column 131, the second conductive column 131 penetrates the substrate 110; a stacked layer 135, the stacked layer 135 includes an upper electrode layer 132, a dielectric layer 133, and a lower electrode layer 134; the stacked layer 135 surrounds the second conductive column 131 and also covers the first surface of the first region I of the substrate 110, and the upper electrode layer 132 covers the sidewall of the second conductive column 131. The process used for the second conductive column 131 is through silicon via (TSV, Through Silicon Via) technology, and vertical electrical interconnection is achieved by filling conductive materials such as copper, polysilicon and tungsten. In some embodiments, the material of the second conductive column 131 can be copper. The second conductive column 131 penetrates the entire substrate 110 to achieve electrical connection in the vertical direction, which is used for the distribution of power or grounding to provide a stable power supply and reduce power noise. The upper electrode layer 132 covers the side wall of the second conductive column 131, that is, the close contact between the upper electrode layer 132 and the side wall of the second conductive column 131 forms a part of the capacitor structure, that is, it also acts as an upper electrode. In this way, by integrating the stacked layer 135 with the second conductive column 131, the through-hole capacitor 130 can achieve high capacitance density and low equivalent series resistance (ESR) in a limited space, effectively suppress power supply noise, and improve the stability and efficiency of the power supply network.

[0053] In one embodiment, the second conductive pillar 131 is made of a different material from the upper electrode layer 132, and the upper electrode layer 132 and the lower electrode layer 134 are made of the same material. The material of the second conductive pillar 131 may be a conductive material such as copper, polysilicon, and tungsten. In some embodiments, the material of the second conductive pillar 131 may be copper. The materials of the upper electrode layer 132 and the lower electrode layer 134 may be titanium nitride, tantalum, tantalum nitride, or a combination thereof, and may be formed using plating, physical vapor deposition, atomic layer deposition, or chemical vapor deposition. The dielectric layer 133 material includes silicon dioxide, silicon nitride, hafnium silicate, hafnium oxide, zirconium oxide, hafnium oxide, aluminum oxide, aluminum nitride, and a combination thereof. The material of the upper electrode layer 132, such as titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., has good barrier properties and can prevent the material of the second conductive pillar 131 (such as copper) from diffusing into the dielectric layer or other layers. Such diffusion may result in a decrease in electrical performance, such as increasing the equivalent series resistance (ESR) or causing a short circuit. In addition, during the formation of the second conductive pillars 131, a chemical mechanical polishing (CMP) process is usually used to flatten the surface and control the height of the second conductive pillars 131. The upper electrode layer 132 can serve as a grinding stop layer during the CMP process, that is, when the grinding process reaches the upper electrode layer 132, the grinding process stops to avoid excessive grinding that causes damage or excessive thinning of the second conductive pillars 131. The material of the upper electrode layer 132 usually has high hardness and chemical stability, and can withstand the grinding process without excessive wear, thereby ensuring the precise control of the second conductive pillars 131 and the integrity of the capacitor structure.

[0054] In one embodiment, the top surface of the second conductive pillar 131 is substantially flush with the top surface of the stacked layer 135 on the first surface. In other words, the height of the second conductive pillar 131 cannot be too high or too low. If the height of the second conductive pillar 131 is too high, the upper electrode layer 132 may not be able to completely cover the sidewall of the second conductive pillar 131, resulting in a weakened blocking effect of the upper electrode layer 132. If the height of the second conductive pillar 131 is too low, the capacitance value of the through-hole capacitor 130 will be reduced, directly affecting the stability of the power supply network and the ability to suppress power supply noise.

[0055] In one embodiment, the diameter of the first conductive pillar 120 is greater than the diameter of the second conductive pillar 131. The first conductive pillar 120 is mainly used for signal transmission, and its diameter is greater than the diameter of the second conductive pillar 131. The larger diameter can provide lower resistance, thereby reducing the energy loss of the signal during transmission, so as to ensure the stability of signal transmission and reduce signal attenuation. The second conductive pillar 131 is used for grounding or connecting to a power source. Considering that the second conductive pillar 131 is formed in the second region of the substrate 110, the diameter of the second conductive pillar 131 is smaller than the diameter of the first conductive pillar 120.

[0056] In one embodiment, the height of the first conductive pillar 120 is smaller than the height of the second conductive pillar 131. The first conductive pillar 120 is used for signal transmission, while the second conductive pillar 131, as a part of the through-hole capacitor 130, needs a greater height to provide a sufficient capacitance value.

[0057] In one embodiment, the semiconductor structure 100 further includes: an insulating layer 140, the insulating layer 140 covers the through-hole capacitor 130; a first contact plug 151, the first contact plug 151 is located in the insulating layer 140 and is electrically connected to the second conductive column 131; a second contact plug 152, the second contact plug 152 penetrates the upper electrode layer 132 and the dielectric layer 133, and is electrically connected to the lower electrode layer 134. The insulating layer 140 is mainly used to provide electrical isolation to prevent short circuits between different conductive structures, and can also play a supporting and protective role. The insulating layer 140 is made of an insulating material with a high dielectric constant, such as silicon dioxide, silicon nitride or other high-k materials. The first contact plug 151 and the second contact plug 152 are used to connect the metal wiring of the upper layer with the conductive column of the lower layer (such as the first conductive column 120 or the second conductive column 131), and are made of conductive materials, such as copper, aluminum or tungsten, to ensure good conductive performance. The orthographic projection of the first contact plug 151 in the direction perpendicular to the substrate 110 is larger than the orthographic projection of the second conductive pillar 131 in the direction perpendicular to the substrate 110. That is, due to the close contact between the upper electrode layer 132 and the side wall of the second conductive pillar 131, the first contact plug 151 does not need to be completely landed on the second conductive pillar 131, thereby reducing the processing difficulty of the first contact plug 151.

[0058] In one embodiment, the semiconductor structure 100 further includes: a redistribution layer 160, the redistribution layer 160 covers the insulating layer 140, and the first contact plug 151 is electrically connected to the power pad 171 through the redistribution layer 160, and the second contact plug 152 is electrically connected to the ground pad 172. In other words, the second conductive column 131 is electrically connected to the power pad 171, and the lower electrode layer 134 is electrically connected to the ground pad 172. In this way, the semiconductor structure 100 forms a ground network (GND net) that wraps the positive electrode of the power supply. The ground network (GNDnet) can provide a shielding layer to reduce power crosstalk and electromagnetic interference (EMI) radiation between the positive electrode of the power supply and other signal lines, and at the same time, through the low-impedance GND path, it helps to quickly absorb and disperse transient currents in the power network, thereby reducing power noise.

[0059] In one embodiment, the semiconductor structure 100 further includes: a trench capacitor 136, the trench capacitor 136 is in the second region II of the substrate 110, and the trench capacitor 136 and the through-hole capacitor 130 share a stacking layer 135. That is, the trench capacitor 136 and the through-hole capacitor 130 are jointly arranged in the second region II of the substrate 110, which can achieve a more compact and higher performance power supply noise suppression solution. In addition, the trench capacitor 136 and the through-hole capacitor 130 share the stacking layer 135, which means that they share the upper electrode layer 132, the dielectric layer 133 and the lower electrode layer 134. This can not only simplify the packaging structure, reduce the number of packaging layers, and reduce the packaging complexity, but also achieve more effective power supply noise suppression through the shared stacking layer 135.

[0060] In one embodiment, the semiconductor structure 100 further includes: a third contact plug 153, the third contact plug 153 is located in the insulating layer 140 and is electrically connected to the upper electrode layer 132; and a fourth contact plug 154, the fourth contact plug 154 penetrates the upper electrode layer 132 and the dielectric layer 133, and is electrically connected to the lower electrode layer 134. The third contact plug 153 electrically connects the upper electrode layer 132 to an external circuit or a higher-level metal wiring layer (such as M1, M2, etc.). The fourth contact plug 154 enables the lower electrode layer 134 to be electrically connected to an external circuit or a higher-level metal wiring layer. Through the design of the third contact plug 153 and the fourth contact plug 154, the trench capacitor 136 can be effectively connected to other electrical components and networks of the package or chip to suppress power supply noise.

[0061] In one embodiment, the semiconductor structure 100 also includes: a fifth contact plug 155, which is located in the insulating layer 140 and electrically connected to the first conductive column 120; the fifth contact plug 155 electrically connects the first conductive column 120 to an external circuit or a higher-level metal wiring layer (such as M1, M2, etc.) for transmitting signals.

[0062] In one embodiment, the third contact plug 151 and the fourth contact plug 154 are electrically connected to different contact arrays 173 through the redistribution layer 160. The contact array 173 generally refers to a plurality of contact points on the surface of the package, which are used for electrical connection with an external circuit board or a package substrate. The fifth contact plug 155 is electrically connected to the signal pad 174 to achieve efficient signal transmission.

[0063] In one embodiment, the ratio of the depth of the trench capacitor 136 to the height of the second conductive pillar 131 is 1 / 4-2 / 3. The selection of this ratio is based on the comprehensive consideration of optimizing the capacitor performance and the packaging structure. If the ratio is too small, that is, the depth of the trench capacitor 136 is too small, the suppression of the power supply noise will be worse; if the ratio is too large, that is, the depth of the trench capacitor 136 is too large, the too deep trench will increase the difficulty of the process and may cause process defects, such as incomplete filling or defects in the trench wall, thereby affecting the reliability and performance of the capacitor.

[0064] In one embodiment, the semiconductor structure 100 further includes: a first isolation layer 180, the first isolation layer 180 covers the second surface of the substrate 110; and a bottom metal layer 190, the bottom metal layer 190 penetrates the first isolation layer 180 and is electrically connected to the first conductive pillar 120 and the second conductive pillar 131, respectively. The first isolation layer 180 is usually made of an insulating material, such as silicon dioxide, silicon nitride or other materials with a high dielectric constant to ensure good electrical isolation performance. The material of the bottom metal layer 190 is usually copper or other metals with good electrical conductivity to ensure low-impedance electrical connection. The addition of the first isolation layer 180 and the bottom metal layer 190 not only enhances the electrical isolation and mechanical protection of the package, but also realizes efficient and low-latency interconnection between the internal and external circuits of the package through optimized electrical connection design.

[0065] In one embodiment, the semiconductor structure 100 also includes: a second isolation layer 121, which isolates the substrate 110 from the first conductive column 120, the through-hole capacitor 130, the trench capacitor 136 and the insulating layer 140. The second isolation layer 121 provides additional electrical isolation and mechanical protection to ensure electrical independence and structural stability between components inside the package.

[0066] The embodiment of the present disclosure sets through-hole capacitors in specific areas to increase the capacitance value of the semiconductor structure. At the same time, the through-hole capacitors can also be used as part of the power delivery network (PDN) to improve the performance of the power network, thereby enhancing the semiconductor structure's suppression effect on high-frequency power noise.

[0067] On the basis of the above-mentioned embodiments, the present disclosure also provides a method for preparing a semiconductor structure. The following is a detailed description of the method for preparing a semiconductor structure.

[0068] Figure 3-14 A schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown;

[0069] In one embodiment, a method for preparing a semiconductor structure is provided, comprising:

[0070] See also Figure 3 As shown, a substrate 110 is provided, the substrate comprising a first surface, a first region I and a second region II of the substrate;

[0071] See also Figure 4 As shown, a first groove 1201 is formed in the first region I of the substrate 110, and a second groove 1310 is formed in the second region II of the substrate 110;

[0072] See also Figure 6 As shown, a first conductive column 120 is formed in the first groove 1201; the specific method may be, first, using photoresist to completely cover the second region II of the substrate 110 to ensure that the region will not be affected during the subsequent deposition and grinding process; then, depositing a conductive material, such as copper (Cu), in the first region I not covered by the photoresist. The deposition process can be achieved by physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating; after the deposition is completed, the first region I is subjected to chemical mechanical grinding, the purpose of which is to remove the conductive material covering the surface of the first region I, and only retain the conductive material located in the first groove 1201, thereby forming the first conductive column 120.

[0073] See also Figure 7-9 As shown, a lower electrode layer 134, a dielectric layer 133, and an upper electrode layer 132 are conformally formed in the second groove 1310 in sequence, and a third groove 1311 is formed. The lower electrode layer 134, the dielectric layer 133, and the upper electrode layer 132 form a stacked layer 135, and the stacked layer 135 also covers the first surface of the first region I of the substrate;

[0074] See also Fig.10As shown, a second conductive column 131 is formed in the third groove 1310, and the stacked layer 135 and the second conductive column 131 form a through-hole capacitor 130; that is, the side wall of the second conductive column 131 contacts the upper electrode layer 132, and together constitutes a part of the capacitor structure, that is, it also acts as an upper electrode. In this way, by integrating the stacked layer 135 with the second conductive column 131, the through-hole capacitor 130 can achieve high capacitance density and low equivalent series resistance (ESR) in a limited space, effectively suppress power supply noise, and improve the stability and efficiency of the power supply network. The second conductive column 131 is formed in the third groove 1310. The specific method can be to completely cover the first area I of the substrate 110 with a photoresist to ensure that the first area I will not be affected during the subsequent deposition and grinding process. At this time, the third groove 1310 of the second area II should remain uncovered; then, a conductive material, such as copper (Cu), is deposited in the second area II not covered by the photoresist, specifically in the third groove 1310. The deposition process can be achieved by physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating; after the deposition is completed, the second region II is subjected to chemical mechanical polishing, the purpose of which is to remove the conductive material covering the surface of the second region II, and only retain the conductive material located in the third groove 1310, thereby forming the second conductive pillar 131. In this process, the second conductive pillar 131 is made of a different material from the upper electrode layer 132, and the upper electrode layer 132 can be used as a polishing stop layer in the CMP process, that is, when the polishing process reaches the upper electrode layer 132, the polishing process stops to avoid damage or excessive thinning of the second conductive pillar 131 caused by excessive polishing; after the polishing is completed, the residual photoresist is removed to expose the surface of the first region I of the substrate.

[0075] See also Fig.14 As shown, the surface of the substrate 110 opposite to the first surface is thinned to expose the first conductive pillars 120 and the second conductive pillars 131 , thereby forming a second surface of the substrate opposite to the first surface.

[0076] In the embodiment of the present disclosure, a first conductive column 120 is formed in the first region I, and a through-hole capacitor 130 is formed in the second region II, which can increase the capacitance value of the semiconductor structure. Meanwhile, the through-hole capacitor 130 can also be used as a part of the power delivery network (PDN) to improve the performance of the power network, thereby enhancing the semiconductor structure's suppression effect on high-frequency power noise.

[0077] In one embodiment, the opening diameters of the first groove 1201 and the second groove 1310 are substantially the same, so the same photolithography mask and etching parameters can be used, which not only simplifies the process flow but also improves the repeatability and consistency of the process.

[0078] In one embodiment, after forming the first groove 1201 in the first region I of the substrate 110 and forming the second groove 1310 in the second region II of the substrate 110, the preparation method further includes: Figure 4 As shown, a groove 1360 is formed in the second region II of the substrate 110; a specific step may be to uniformly coat a layer of photoresist on the substrate 110 to ensure that the first groove 1201 and the second groove 1310 are completely covered. The photoresist is exposed using a mask, and a pattern of the groove 1360 is designed on the mask. After exposure, the portion of the photoresist irradiated by light is removed by a developer, and the portion not irradiated is retained. In this way, a pattern corresponding to the mask pattern, i.e., a mask of the groove 1360, is formed on the photoresist. Using the photoresist mask as a protective layer, the substrate 110 is etched to form the groove 1360. Etching may be dry etching or wet etching. After etching is completed, the residual photoresist needs to be removed to expose the substrate surface. The removal of the photoresist is usually achieved by methods such as plasma etching or solvent cleaning. See Figure 7-9 As shown, while the stacked layer 135 is sequentially formed in the second groove 1310, the stacked layer 135 is also formed in the trench 1360, and the trench 1360 and the stacked layer 135 form a trench capacitor 136. In this way, the process flow is simplified.

[0079] In one embodiment, after forming the first groove 1201, the second groove 1310 and the trench 1360 on the substrate 110, the preparation method further includes: Figure 5 As shown, a second isolation layer 121 is deposited and conformally formed in the first recess 1201, the second recess 1310 and the trench 1360, and covers the first surface of the substrate 110. The second isolation layer 121 provides additional electrical isolation and mechanical protection, ensuring electrical independence and structural stability between components within the package.

[0080] In one embodiment, after forming the second conductive pillar 131 in the third groove 1310, the preparation method further includes: Figure 11-12 As shown, an insulating layer 140 is formed, and the insulating layer 140 covers the through-hole capacitor 130. At the same time, the insulating layer also fills the trench capacitor 136, and a first contact plug 151 and a second contact plug 152 are formed in the insulating layer 140. The first contact plug 151 is electrically connected to the second conductive column 131; the second contact plug 152 is electrically connected to the lower electrode layer 134.

[0081] In one embodiment, a third contact plug 153 and a fourth contact plug 154 are also formed in the insulating layer 140, and the third contact plug 153 is electrically connected to the upper electrode layer 132; the fourth contact plug 154 penetrates the upper electrode layer 132 and the dielectric layer 133, and is electrically connected to the lower electrode layer 134. Through the design of the third contact plug 153 and the fourth contact plug 154, the trench capacitor 136 can be effectively connected to other electrical components and networks of the package or chip to achieve power supply noise suppression. A fifth contact plug 155 is also formed in the insulating layer 140, and the fifth contact plug 155 is electrically connected to the first conductive column 120; the fifth contact plug 155 electrically connects the first conductive column 120 to an external circuit or a higher-level metal wiring layer (such as M1, M2, etc.) for signal transmission.

[0082] In one embodiment, the preparation method further comprises: Fig.13 As shown, a redistribution layer 160 is formed, and the redistribution layer 160 covers the insulating layer 140. Through the redistribution layer 160, the first contact plug 151 is electrically connected to the power pad 171, and the second contact plug 152 is electrically connected to the ground pad 172. In other words, the second conductive column 131 is electrically connected to the power pad 171, and the lower electrode layer 134 is electrically connected to the ground pad 172. In this way, the semiconductor structure 100 forms a ground network (GND net) that wraps the positive electrode of the power supply. The ground network (GND net) can provide a shielding layer to reduce the power crosstalk and electromagnetic interference (EMI) radiation between the positive electrode of the power supply and other signal lines. At the same time, through the low-impedance GND path, it helps to quickly absorb and disperse the transient current in the power network, thereby reducing power noise.

[0083] In one embodiment, the preparation method further comprises: Fig.13 As shown, the third contact plug 151 and the fourth contact plug 154 are electrically connected to different contact arrays 173 through the redistribution layer 160. The contact array 173 generally refers to a plurality of contact points on the surface of the package, which are used for electrical connection with an external circuit board or a package substrate. The fifth contact plug 155 is electrically connected to the signal pad 174 through the redistribution layer 160 to achieve efficient signal transmission.

[0084] In one embodiment, the preparation method further comprises: Figure 1 As shown, a first isolation layer 180 is formed on the second surface, and a bottom metal layer 190 is formed on the first isolation layer 180. The bottom metal layer 190 penetrates the first isolation layer 180 and is respectively electrically connected to the first conductive pillar 120 and the second conductive pillar 131. The addition of the first isolation layer 180 and the bottom metal layer 190 not only enhances the electrical isolation and mechanical protection of the package, but also realizes efficient and low-latency interconnection between the internal and external circuits of the package through an optimized electrical connection design.

[0085] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0086] In the description of the present disclosure, it should be understood that the terms "including" and "having" and any variations thereof used herein are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0087] Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, and it can make the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate having a first surface and a second surface opposite to each other, the substrate comprising a first region and a second region; a first conductive column, the first conductive column is located in the first region of the substrate and penetrates the substrate; a through-hole capacitor, wherein the through-hole capacitor is located in the second region of the substrate; Among them, the through-hole capacitor includes: a second conductive column, the second conductive column passes through the substrate; a stacked layer, the stacked layer includes an upper electrode layer, a dielectric layer, and a lower electrode layer; the stacked layer surrounds the second conductive column and also covers the first surface of the first area of ​​the substrate, and the upper electrode layer covers the side wall of the second conductive column.

2. The semiconductor structure according to claim 1, characterized in that: The second conductive pillar and the upper electrode layer are made of different materials, and the upper electrode layer and the lower electrode layer are made of the same material.

3. The semiconductor structure according to claim 1, characterized in that: The top surface of the second conductive pillar is substantially flush with the top surface of the stacked layer on the first surface.

4. The semiconductor structure according to claim 1, characterized in that: A diameter of the first conductive pillar is greater than a diameter of the second conductive pillar.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure also includes: an insulating layer, which covers the through-hole capacitor; a first contact plug, which is located in the insulating layer and electrically connected to the second conductive column; and a second contact plug, which passes through the upper electrode layer and the dielectric layer and is electrically connected to the lower electrode layer.

6. The semiconductor structure according to claim 5, characterized in that: The semiconductor structure further includes a redistribution layer, the redistribution layer covers the insulating layer, and the first contact plug is electrically connected to the power pad through the redistribution layer, and the second contact plug is electrically connected to the ground pad.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a trench capacitor, wherein the trench capacitor is located in the second region of the substrate, and the trench capacitor and the through-hole capacitor share the stacked layer.

8. The semiconductor structure according to claim 5, characterized in that: The semiconductor structure further includes: a third contact plug, which is located in the insulating layer and electrically connected to the upper electrode layer; and a fourth contact plug, which passes through the upper electrode layer and the dielectric layer and is electrically connected to the lower electrode layer.

9. The semiconductor structure according to claim 7, characterized in that: The ratio of the depth of the trench capacitor to the height of the second conductive pillar is 1 / 4-2 / 3.

10. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a first isolation layer, which covers the second surface of the substrate; and a bottom metal layer, which penetrates the first isolation layer and is electrically connected to the first conductive column and the second conductive column respectively.

11. A method for preparing a semiconductor structure, characterized in that: include, Providing a substrate, the substrate comprising a first surface, the substrate comprising a first region and a second region; forming a first groove in the first region of the substrate and forming a second groove in the second region of the substrate; forming a first conductive column in the first groove; Conformally forming a lower electrode layer, a dielectric layer, and an upper electrode layer in the second groove in sequence, and forming a third groove, wherein the lower electrode layer, the dielectric layer, and the upper electrode layer constitute a stacked layer, and the stacked layer also covers the first surface of the first region of the substrate; forming a second conductive column in the third groove, wherein the stacked layer and the second conductive column constitute a through-hole capacitor; The surface of the substrate opposite to the first surface is thinned to expose the first conductive pillar and the second conductive pillar, thereby forming a second surface of the substrate opposite to the first surface.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: After forming a first groove in the first region of the substrate and forming a second groove in the second region of the substrate, the preparation method further includes forming a trench in the second region of the substrate; While the stacked layers are sequentially formed in the second groove, the stacked layers are also formed in the trench, and the trench and the stacked layers constitute a trench capacitor.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that: After forming the second conductive column in the third groove, the preparation method further includes forming an insulating layer, the insulating layer covering the through-hole capacitor, forming a first contact plug and a second contact plug in the insulating layer, the first contact plug being electrically connected to the second conductive column; and the second contact plug being electrically connected to the lower electrode layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: The preparation method further includes forming a redistribution layer, wherein the redistribution layer covers the insulating layer, and the first contact plug is electrically connected to the power pad and the second contact plug is electrically connected to the ground pad through the redistribution layer.

15. The method for preparing a semiconductor structure according to claim 11, characterized in that: The preparation method further includes forming a first isolation layer on the second surface, and forming a bottom metal layer on the first isolation layer, wherein the bottom metal layer penetrates the first isolation layer and is electrically connected to the first conductive column and the second conductive column respectively.

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