Integrated device, package, and method for manufacturing an integrated device

Abstract

An integrated device includes a die portion including a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, where the plurality of under bump metallization interconnects includes a first under bump metallization interconnect. The integrated device includes a plurality of solder stud interconnects coupled to the plurality of under bump metallization interconnects, wherein the plurality of solder stud interconnects includes a first solder stud interconnect. The first solder stud interconnect includes a first width corresponding to a widest portion of the first solder stud interconnect and a second width corresponding to a portion of the first solder stud interconnect farthest from the first under bump metallization interconnect, wherein the second width is less than the first width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 855,189 filed in the U.S. Patent Office on June 30, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes.

[0003] field

[0004] Various features are directed to integrated devices.

[0005] background

[0006] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various functions. The performance of a package and its components may depend on the quality of the joints between the various components of the package. There is a continuing need to provide a package that includes robust and reliable joints between the various components.

[0007] Overview

[0008] Various features are directed to integrated devices.

[0009] An example provides an integrated device including a die portion, the die portion including a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, wherein the plurality of under bump metallization interconnects include a first under bump metallization interconnect. The integrated device includes a plurality of solder pillar interconnects coupled to the plurality of under bump metallization interconnects, wherein the plurality of solder pillar interconnects include a first solder pillar interconnect. The first solder pillar interconnect includes a first width corresponding to a widest portion of the first solder pillar interconnect and a second width corresponding to a portion of the first solder pillar interconnect that is the farthest vertically from the first under bump metallization interconnect, wherein the second width is less than the first width.

[0010] Another example provides a package including a substrate and an integrated device. The integrated device includes a plurality of under bump metallization interconnects including a first under bump metallization interconnect, and a plurality of solder pillar interconnects including a first solder pillar interconnect. The first solder pillar interconnect is coupled to the first under bump metallization interconnect. The first solder pillar interconnect includes a first width corresponding to the widest portion of the first solder pillar interconnect and a second width corresponding to a portion of the first solder pillar interconnect that is the farthest vertically from the first under bump metallization interconnect, wherein the second width is less than the first width. The integrated device is coupled to the substrate via the plurality of solder pillar interconnects and the plurality of solder interconnects.

[0011] Another example provides a method for manufacturing an integrated device. The method provides a tube core portion including a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads. The method forms a plurality of solder pillar interconnects on the plurality of under bump metallization interconnects. Forming the plurality of solder pillar interconnects includes: forming a first solder pillar interconnect so that the first solder pillar interconnect includes a first width corresponding to the widest portion of the first solder pillar interconnect and a second width corresponding to a portion of the first solder pillar interconnect that is the farthest vertically from the first under bump metallization interconnect, wherein the second width is less than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0014] Figure 1 A cross-sectional profile view of an exemplary integrated device including solder pillar interconnects is illustrated.

[0015] Figure 2 An exemplary solder pillar interconnect is illustrated.

[0016] Figure 3 A cross-sectional profile view of an exemplary solder pillar interconnect is illustrated.

[0017] Figure 4 Another exemplary solder pillar interconnect is illustrated.

[0018] Figure 5 A cross-sectional profile view of an exemplary solder pillar interconnect is illustrated.

[0019] Figure 6 Another exemplary solder pillar interconnect is illustrated.

[0020] Figure 7 A cross-sectional profile view of an exemplary solder pillar interconnect is illustrated.

[0021] Figure 8 A cross-sectional profile view of an exemplary package including an integrated device including solder pillar interconnects is illustrated, wherein the integrated device is coupled to a substrate.

[0022] Fig. 9 A close-up view of an exemplary package including an integrated device including solder pillar interconnects is illustrated, where the integrated device is coupled to a substrate.

[0023] Figures 10A-10C An exemplary process for fabricating an integrated device including solder pillar interconnects is illustrated.

[0024] Fig.11 An exemplary flow chart of a method for fabricating an integrated device including solder pillar interconnects is illustrated.

[0025] Figures 12A-12D An exemplary process for fabricating an integrated device including solder pillar interconnects is illustrated.

[0026] Fig.13 An exemplary flow chart of a method for fabricating an integrated device including solder pillar interconnects is illustrated.

[0027] Fig.14 An exemplary flow chart of a method for fabricating an integrated device including solder pillar interconnects is illustrated.

[0028] Fig.15 An exemplary process for fabricating a package including an integrated device including solder pillar interconnects is illustrated.

[0029] Fig.16 An exemplary flow chart of a method for fabricating a package including an integrated device including solder pillar interconnects is illustrated.

[0030] Fig.17 Various electronic devices are illustrated into which the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein may be integrated.

[0031] Detailed Description

[0032] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0033] The present disclosure describes a package, which includes a substrate and an integrated device. The integrated device includes a plurality of under-bump metallization interconnects including a first under-bump metallization interconnect, and a plurality of solder pillar interconnects including a first solder pillar interconnect. The first solder pillar interconnect is coupled to the first under-bump metallization interconnect. The first solder pillar interconnect includes a first width corresponding to the widest part of the first solder pillar interconnect and a second width corresponding to the part of the first solder pillar interconnect that is the farthest from the vertical distance of the first under-bump metallization interconnect, wherein the second width is less than the first width. The integrated device is coupled to the substrate via a plurality of solder pillar interconnects and a plurality of solder interconnects. Different and / or varying widths can allow the solder interconnects to be coupled to a larger surface area, thereby providing a more robust and reliable joint between the integrated device and the substrate. The increased surface area can also allow more solder interconnects to be located between the first solder pillar interconnect and the substrate without causing a short circuit between adjacent interconnects of the substrate. Using solder pillar interconnects of different widths also helps to reduce stress on the dielectric layer near the solder pillar interconnect, which reduces the possibility of dielectric layer delamination. More robust and reliable joints help provide a more reliable electrical path for current and / or signal travel between the integrated device and the substrate, which can lead to improved performance of the integrated device and package.

[0034] Exemplary integrated device including solder pillar interconnects

[0035] Figure 1 A cross-sectional view of an integrated device 100 including a solder pillar interconnect with a variable width is illustrated. The integrated device 100 includes a tube core portion 102, a plurality of solder pillar interconnects 104, and a plurality of solder interconnects 106. A plurality of solder pillar interconnects 104 are coupled to the tube core portion 102. A plurality of solder interconnects 106 are coupled to a plurality of solder pillar interconnects 104. At least one solder pillar interconnect in the plurality of solder pillar interconnects 104 includes a variable width (e.g., a cross-sectional shape with a variable width). For example, at least one solder pillar interconnect in the plurality of solder pillar interconnects 104 includes a first portion having a first width and a second portion having a second width. The second width may be less than the first width. As will be further described below, the portion of the solder pillar interconnect coupled to the solder interconnect may have a width less than the portion of the solder pillar interconnect coupled to the under-bump metallization interconnect. Different widths create additional surface areas for solder interconnect coupling. Different widths also create more space to accommodate more solder interconnects while reducing the possibility of shorting with nearby interconnects. The additional surface area of ​​the solder pillar interconnects and / or the additional amount of solder interconnects helps provide a more robust and reliable joint for the integrated device, thereby providing a more robust and reliable electrical path for the current(s) in and out of the integrated device. Using variable widths of the solder pillar interconnects helps reduce stress (e.g., reduces stress in the dielectric layer), which helps reduce the risk of delamination (e.g., helps reduce the risk of dielectric layer delamination). The integrated device 100 may include a flip chip.

[0036] The die portion 102 includes a die substrate 120, an interconnection portion 122, a passivation layer 105, a passivation layer 108, a plurality of pads 107, a passivation layer 108, and a plurality of under-bump metallization interconnects 109. The die substrate 120 may include silicon (Si). A plurality of cells (e.g., logic cells) and / or a plurality of transistors (not shown) may be formed in and / or on the die substrate 120. Different implementations may use different types of transistors, such as field effect transistors (FETs), planar FETs, fin FETs, and surround gate FETs. In some implementations, a front-end process (FEOL) process may be used to manufacture the plurality of cells (e.g., logic cells) and / or transistors in and / or on the die substrate 120. The interconnection portion 122 is located on and coupled to the die substrate 120. The interconnection portion 122 may be coupled to the plurality of cells and / or transistors located in and / or on the die substrate 120. The interconnect portion 122 (eg, die interconnect portion) may include a plurality of die interconnects (not shown) coupled to a plurality of cells and / or transistors. In some implementations, a back-end of line (BEOL) process may be used to fabricate the interconnect portion 122 .

[0037] The passivation layer 105 is located on and coupled to the interconnection portion 122. The passivation layer 105 may be a hard passivation layer. The passivation layer 108 is located on the passivation layer 105. The passivation layer 108 may include a polymer passivation layer. A plurality of pads 107 are located on the interconnection portion 122. The plurality of pads 107 may be coupled to the die interconnect of the interconnection portion 122. In some implementations, the passivation layer 105, the passivation layer 108, and / or the plurality of pads 107 may be considered as part of the interconnection portion 122. In some implementations, the passivation layer 105, the passivation layer 108, and the plurality of pads 107 may be manufactured using a back-end-of-line (BEOL) process. A plurality of under-bump metallization interconnects 109 are coupled to the plurality of pads 107. The plurality of under-bump metallization interconnects 109 may be located on the plurality of pads 107. In some implementations, additional interconnects may exist between the plurality of pads 107 and the plurality of under-bump metallization interconnects 109. For example, there may be a metallization interconnect between the plurality of pads 107 and the plurality of under bump metallization interconnects 109. Examples of metallization interconnects include redistribution interconnects. In some implementations, the plurality of under bump metallization interconnects 109 may be coupled to the plurality of pads 107 via metallization interconnects (e.g., redistribution interconnects).

[0038] The plurality of solder pillar interconnects 104 may be coupled to the die portion 102. The plurality of solder pillar interconnects 104 may be coupled to the plurality of under bump metallization interconnects 109. The plurality of solder pillar interconnects 104 may be coupled to the die portion 102 through the plurality of under bump metallization interconnects 109. The plurality of solder pillar interconnects 104 may be a means for solder pillar interconnection. The plurality of under bump metallization interconnects 109 may be a means for under bump metallization interconnection.

[0039] The plurality of pads 107 include a first pad 107a and a second pad 107b. The plurality of under bump metallization interconnects 109 include a first under bump metallization interconnect 109a and a second under bump metallization interconnect 109b. The plurality of solder pillar interconnects 104 include a first solder pillar interconnect 104a and a second solder pillar interconnect 104b. The plurality of solder interconnects 106 include a first solder interconnect 106a and a second solder interconnect 106b.

[0040] The first under bump metallization interconnect 109a is coupled to the first pad 107a. The first solder pillar interconnect 104a is coupled to the first under bump metallization interconnect 109a. The first solder interconnect 106a is coupled to the first solder pillar interconnect 104a. The width of the widest portion of the first solder pillar interconnect 104a may be equal to or less than the width of the first under bump metallization interconnect 109a. Note that in some implementations, the first solder pillar interconnect 104a is coupled to the first under bump metallization interconnect 109a through at least one metallization interconnect. That is, at least one metallization interconnect (e.g., a redistribution interconnect) may be located between the first solder pillar interconnect 104a and the first under bump metallization interconnect 109a.

[0041] The second under bump metallization interconnect 109b is coupled to the second pad 107b. The second solder pillar interconnect 104b is coupled to the second under bump metallization interconnect 109b. The second solder interconnect 106b is coupled to the second solder pillar interconnect 104b. The width of the widest portion of the second solder pillar interconnect 104b may be equal to or less than the width of the second under bump metallization interconnect 109b. Note that in some implementations, the second solder pillar interconnect 104b is coupled to the second under bump metallization interconnect 109b through at least one metallization interconnect. That is, at least one metallization interconnect (e.g., a redistribution interconnect) may be located between the second solder pillar interconnect 104b and the second under bump metallization interconnect 109b.

[0042] Figure 2 An exemplary view of solder pillar interconnect 104 is illustrated. Figure 2 The solder pillar interconnect 104 may represent Figure 1 Any one of the plurality of solder pillar interconnects 104 in the embodiment. For example, the solder pillar interconnect 104 may represent a first solder pillar interconnect 104a and / or a second solder pillar interconnect 104b. Figure 2As shown in , the solder pillar interconnect 104 includes a first solder pillar interconnect portion 201 and a second solder pillar interconnect portion 203. The first solder pillar interconnect portion 201 and the second solder pillar interconnect portion 203 may be continuous portions and / or adjacent portions of the solder pillar interconnect 104. The first solder pillar interconnect portion 201 may represent the base of the solder pillar interconnect 104. The first solder pillar interconnect portion 201 may represent and / or include a bottom portion of the solder pillar interconnect 104. The first solder pillar interconnect portion 201 may be coupled to an under bump metallization interconnect (e.g., 109a, 109b). The second solder pillar interconnect portion 203 may be configured to couple to a solder interconnect (e.g., 106a, 106b). The second solder pillar interconnect portion 203 may represent and / or include a top portion of the solder pillar interconnect 104. The solder pillar interconnect 104 may include a diagonal surface. For example, the second solder pillar interconnect portion 203 of the solder pillar interconnect 104 may include a diagonal surface. The diagonal surface may be diagonal relative to the top surface of the solder pillar interconnect 104. The diagonal surface may be diagonal relative to a surface of the passivation layer 108 .

[0043] Figure 3 1 illustrates a cross-sectional view of a solder pillar interconnect 104. As mentioned above, the solder pillar interconnect 104 includes a first solder pillar interconnect portion 201 and a second solder pillar interconnect portion 203. The first solder pillar interconnect portion 201 may include a bottom width (W B The second solder pillar interconnection portion 203 may include a top width (W T ) and the widest width (W W ). Maximum width (W W ) may be the width corresponding to the widest portion of the first solder pillar interconnect 104. The top width (W T ) may be the width corresponding to the portion of the solder pillar interconnect 104 that is the farthest vertically from the under bump metallization interconnect. T ) is smaller than the widest width (W W ). The bottom portion and the widest portion of the solder pillar interconnect 104 may be coupled to (eg, directly contact) the under bump metallization interconnect.

[0044] like Figure 3 As shown in , the first solder pillar interconnection portion 201 may have a cross-sectional cross section including a first trapezoidal shape. The second solder pillar interconnection portion 203 may have a cross-sectional cross section including a second trapezoidal shape. Thus, the solder pillar interconnection 104 may include a cross-sectional cross section including a first trapezoidal shape and a second trapezoidal shape. The second trapezoidal shape may be an inverted trapezoidal shape relative to the first trapezoidal shape. Similarly, the first trapezoidal shape may be an inverted trapezoidal shape relative to the second trapezoidal shape.

[0045] The second trapezoidal shape of the second solder pillar interconnect portion 203 includes a top portion and a bottom portion, wherein the top portion of the second trapezoidal shape is farther from the under bump metallization interconnect than the bottom portion of the second trapezoidal shape is from the under bump metallization interconnect. The bottom portion of the trapezoidal shape has a first width (e.g., a widest width (W W )). The top portion of the trapezoidal shape has a second width (eg, top width (W T )).

[0046] Note that the first solder pillar interconnect portion 201 and the second solder pillar interconnect portion 203 may be considered as one portion or two or more separate portions. An interface may or may not exist between the first solder pillar interconnect portion 201 and the second solder pillar interconnect portion 203. The second solder pillar interconnect portion 203 may include the widest portion of the solder pillar interconnect 104 and the portion with the greatest vertical distance from the under bump metallization interconnect to which the solder pillar interconnect 104 is coupled.

[0047] Figure 4 An exemplary view of another solder pillar interconnect 404 is illustrated. Figure 4 The solder pillar interconnect 404 can be used as a Figure 1 The plurality of solder pillar interconnects 104 may be used as a supplement or replacement for the solder pillar interconnects. Figure 4 As shown in , the solder pillar interconnect 404 includes a first solder pillar interconnect portion 401 and a second solder pillar interconnect portion 403. The first solder pillar interconnect portion 401 and the second solder pillar interconnect portion 403 may be continuous portions and / or adjacent portions of the solder pillar interconnect 404. The first solder pillar interconnect portion 401 may represent the base of the solder pillar interconnect 404. The first solder pillar interconnect portion 401 may represent and / or include a bottom portion of the solder pillar interconnect 404. The first solder pillar interconnect portion 401 may be coupled to an under bump metallization interconnect (e.g., 109a, 109b). The second solder pillar interconnect portion 403 may be configured to couple to a solder interconnect (e.g., 106a, 106b). The second solder pillar interconnect portion 403 may represent and / or include a top portion of the solder pillar interconnect 404. The solder pillar interconnect 404 may include a diagonal surface. For example, the second solder pillar interconnect portion 403 of the solder pillar interconnect 404 may include a diagonal surface. The diagonal surface may be diagonal to the top surface of the solder pillar interconnect 404.

[0048] Figure 5 4 illustrates a cross-sectional view of a solder pillar interconnect 404. The solder pillar interconnect 404 includes a first solder pillar interconnect portion 401 and a second solder pillar interconnect portion 403. The first solder pillar interconnect portion 401 may include a bottom width (W B The second solder pillar interconnection portion 403 may include a top width (W T ) and the widest width (W W ). Maximum width (W W) may be the width corresponding to the widest portion of the first solder pillar interconnect 404. The top width (W T ) may be the width corresponding to the portion of the solder pillar interconnect 404 that is the farthest vertically from the under bump metallization interconnect. T ) is smaller than the widest width (W W ). The bottom portion and the widest portion of the solder pillar interconnect 404 may be coupled to (eg, directly contact) the under bump metallization interconnect.

[0049] like Figure 5 As shown in , a portion of the solder pillar interconnect 404 includes a stepped pyramid shape. For example, the second solder pillar interconnect portion 403 has a side profile cross-section of a stepped pyramid. The stepped pyramid shape can simulate and / or replicate the shape of the diagonal surface of the solder pillar interconnect. The stepped pyramid can have the same benefits as described for the solder pillar interconnect 104. Different implementations can have different numbers of steps in the stepped pyramid shape.

[0050] Note that the first solder pillar interconnect portion 401 and the second solder pillar interconnect portion 403 may be considered as one portion or two or more separate portions. An interface may or may not exist between the first solder pillar interconnect portion 401 and the second solder pillar interconnect portion 403. The second solder pillar interconnect portion 403 may include the widest portion of the solder pillar interconnect 404 and the portion with the longest vertical distance from the under bump metallization interconnect to which the solder pillar interconnect 404 is coupled.

[0051] Figure 6 An exemplary view of another solder pillar interconnect 604 is illustrated. Figure 6 The solder pillar interconnect 604 can be used as a Figure 1 The plurality of solder pillar interconnects 104 may be used as a supplement or replacement for the solder pillar interconnects. Figure 6As shown in , the solder pillar interconnect 604 includes a first solder pillar interconnect portion 601 and a second solder pillar interconnect portion 603. The first solder pillar interconnect portion 601 and the second solder pillar interconnect portion 603 may be continuous portions and / or adjacent portions of the solder pillar interconnect 604. The first solder pillar interconnect portion 601 may represent the base of the solder pillar interconnect 604. The first solder pillar interconnect portion 601 may represent and / or include the bottom portion of the solder pillar interconnect 604. The first solder pillar interconnect portion 601 may be coupled to an under bump metallization interconnect (e.g., 109a, 109b). The second solder pillar interconnect portion 603 may be configured to couple to a solder interconnect (e.g., 106a, 106b). The second solder pillar interconnect portion 603 may represent and / or include the top portion of the solder pillar interconnect 604. The solder pillar interconnect 604 may include several diagonal surfaces. For example, the second solder pillar interconnect portion 603 of the solder pillar interconnect 604 may include a first diagonal surface having a first angle, a second diagonal surface having a second angle, and a third diagonal surface having a third angle. The diagonal surface may be diagonal with respect to a top surface of the pillar interconnect 604. The diagonal surface may be diagonal with respect to a surface of the passivation layer 108.

[0052] Figure 7 604. The solder pillar interconnect 604 includes a first solder pillar interconnect portion 601 and a second solder pillar interconnect portion 603. The first solder pillar interconnect portion 601 may include a bottom width (W B The second solder pillar interconnection portion 603 may include a top width (W T ) and the widest width (W W ). Maximum width (W W ) may be the width corresponding to the widest portion of the first solder pillar interconnect 604. The top width (W T ) may be the width corresponding to the portion of the solder pillar interconnect 604 that is the farthest vertically from the under bump metallization interconnect. T ) is smaller than the widest width (W W ). The bottom portion and the widest portion of the solder pillar interconnect 604 may be coupled to (eg, directly contact) the under bump metallization interconnect.

[0053] Figure 7 The portion of the solder pillar interconnect 604 is illustrated to include a stepped pyramid shape. For example, the second solder pillar interconnect portion 603 has a side profile cross-section of a stepped pyramid. The stepped pyramid shape can simulate and / or replicate the shape of the diagonal surface of the solder pillar interconnect. Each step of the solder pillar interconnect 604 can have a diagonal surface. The angle of the diagonal surface of each step can be different and / or can be the same. Different implementations can have different numbers of steps in the stepped pyramid shape.

[0054] like Figure 7As shown in, the first solder pillar interconnection portion 601 may have a cross-sectional cross section including a first trapezoidal shape. The second solder pillar interconnection portion 603 may include a second solder pillar interconnection portion 603a, a second solder pillar interconnection portion 603b, and a second solder pillar interconnection portion 603c. The second solder pillar interconnection portion 603a may have a cross-sectional cross section including a second trapezoidal shape. The second solder pillar interconnection portion 603b may have a cross-sectional cross section including a third trapezoidal shape. The second solder pillar interconnection portion 603c may have a cross-sectional cross section including a fourth trapezoidal shape. The solder pillar interconnection 104 may include a cross-sectional cross section including a first trapezoidal shape, a second trapezoidal shape, a third trapezoidal shape, and / or a fourth trapezoidal shape. The second trapezoidal shape, the third trapezoidal shape, and / or the fourth trapezoidal shape may be an inverted trapezoidal shape relative to the first trapezoidal shape. Similarly, the first trapezoidal shape may be an inverted trapezoidal shape relative to the second trapezoidal shape, the third trapezoidal shape, and / or the fourth trapezoidal shape.

[0055] Note that the first solder pillar interconnect portion 601 and the second solder pillar interconnect portion 603 can be considered as one portion or two or more separate portions. There may or may not be an interface between the first solder pillar interconnect portion 601 and the second solder pillar interconnect portion 603. The second solder pillar interconnect portion 603 may include the widest portion of the solder pillar interconnect 604 and the portion that is the farthest vertically from the under bump metallization interconnect to which the solder pillar interconnect 604 is coupled. Note that the widths described in the present disclosure may be used to describe the diameter of the solder pillar interconnect and / or the diameter of the solder pillar interconnect portion. Thus, for example, the widest width may correspond to the widest diameter, the top width may correspond to the top diameter, and / or the bottom width may correspond to the bottom diameter.

[0056] The integrated device 100 may be implemented in a package. Figure 8A package 800 including a substrate 802, an integrated device 100, and an encapsulation layer 808 is illustrated. The substrate 802 includes at least one dielectric layer 820, a plurality of interconnects 822, and a solder resist layer 826. A plurality of solder interconnects 830 may be coupled to the plurality of interconnects 822 of the substrate 802. The integrated device 100 is coupled to a first surface (e.g., a top surface) of the substrate 802 through a plurality of solder pillar interconnects 104 and a plurality of solder interconnects 106. The encapsulation layer 808 may be located above and / or around the integrated device 100 and / or the substrate 802. The encapsulation layer 808 is coupled to the integrated device 100 and / or the substrate 802. The encapsulation layer 808 may at least partially encapsulate the integrated device 100. The encapsulation layer 808 may include a molding, a resin, and / or an epoxy. The encapsulation layer 808 may be an encapsulation device. Encapsulation layer 808 may be provided using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that integrated device 100 may be coupled to substrate 802 via plurality of solder pillar interconnects 404 and / or plurality of solder pillar interconnects 604 in addition to or in lieu of plurality of solder pillar interconnects 104.

[0057] Fig. 9 A close-up view illustrating how an integrated device may be coupled to a substrate. Fig. 9 A portion of a package 800 is illustrated that includes an integrated device 100 and a substrate 802. The integrated device 100 is coupled to the substrate 802 via a plurality of solder pillar interconnects 104 and a plurality of solder interconnects 106. However, as mentioned above, the integrated device 100 may be coupled to the substrate 802 via a plurality of solder pillar interconnects 404 and / or a plurality of solder pillar interconnects 604 in addition to or in lieu of the plurality of solder pillar interconnects 104.

[0058] like Fig. 9 As shown in FIG. 1 , the first solder pillar interconnect 104a is coupled to the first solder interconnect 106a. The first solder interconnect 106a is coupled to the first interconnect 822a of the substrate 802. The first solder interconnect 106a may include an intermetallic compound (IMC) (not shown). The intermetallic compound may be formed when metal from the first interconnect 822a and / or the first solder pillar interconnect 104a diffuses in the solder interconnect 106a.

[0059] The second solder pillar interconnect 104b is coupled to the second solder interconnect 106b. The second solder interconnect 106b is coupled to the second interconnect 822b of the substrate 802. The second solder interconnect 106b may include an intermetallic compound (IMC). The intermetallic compound may be formed when metal from the second interconnect 822b and / or the second solder pillar interconnect 104b diffuses in the solder interconnect 106b. As mentioned above, using a variable width of the solder pillar interconnect helps reduce stress (e.g., reduces stress in the dielectric layer), which helps reduce the risk of delamination (e.g., helps reduce the risk of dielectric layer delamination). Specifically, the side of the solder pillar interconnect that is closest to the substrate 802 in vertical distance and / or farthest from the interconnect portion 122, the passivation layer 105, the plurality of pads 107, the passivation layer 108, and the plurality of under-bump metallization interconnects 109 is more likely to deform and / or bend because that particular side of the solder pillar interconnect is smaller in size than the side coupled to the under-bump metallization interconnect 109, resulting in less energy being applied to the die side of the solder pillar interconnect, which helps to reduce the risk of delamination of the dielectric layer of the integrated device 100.

[0060] An integrated device (e.g., 100) may include a die (e.g., a bare semiconductor die). An integrated device may include a power management integrated circuit (PMIC). An integrated device may include an application processor. An integrated device may include a modem. An integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, an integrated device based on gallium arsenide (GaAs), a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, an integrated device based on silicon (Si), an integrated device based on silicon carbide (SiC), a memory, a power management processor, and / or a combination thereof. An integrated device (e.g., 100) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a core particle. A core particle may be manufactured using one or more processes that provide better yields than other processes for manufacturing other types of integrated devices, which may reduce the overall cost of manufacturing the core particles. Different core particles may have different sizes and / or shapes. Different corelets may be configured to provide different functions. Different corelets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several corelets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Using several corelets that perform several functions may reduce the overall cost of a package relative to using a single chip to perform all functions of the package.

[0061] Having described an integrated device with solder pillar interconnects, a method for fabricating the integrated device will now be described below.

[0062] Exemplary process for fabricating an integrated device including solder pillar interconnects

[0063] In some implementations, fabricating an integrated device includes several processes. Figures 10A-10C Exemplary processes for providing or manufacturing an integrated device including solder pillar interconnects having variable widths are described. In some implementations, Figures 10A-10C The process can be used to provide or manufacture Figure 1 The integrated device 100. However, Figures 10A-10C The process can be used to manufacture any integrated device described in this disclosure.

[0064] It should be noted that Figures 10A-10C The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing an integrated device. In some implementations, the order of each process can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure.

[0065] like Fig. 10A As shown in , stage 1 illustrates a state after providing a die portion 102. The die portion 102 may include a die substrate 120, an interconnect portion 122, a passivation layer 105, a plurality of pads 107, a passivation layer 108, and a plurality of under bump metallization interconnects 109. The die portion 102 may include a bare die (e.g., a semiconductor bare die). Providing the die portion 102 may include manufacturing the die portion. The die portion 102 may be manufactured using FEOL and BEOL manufacturing processes.

[0066] Stage 2 illustrates a state after the first photoresist layer 1000 is formed on the tube core portion 102 and patterned to include a plurality of openings 1001 in the first photoresist layer 1000. The first photoresist layer 1000 may include a positive photoresist layer. However, in some implementations, the first photoresist layer 1000 may include a negative photoresist layer. A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the first photoresist layer 1000. The plurality of openings 1001 may include a cross-sectional shape including a trapezoidal shape. For example, the plurality of openings 1001 may have a top width at the top of the first photoresist layer 1000 that is less than (e.g., less than) a bottom width at the bottom of the first photoresist layer 1000. The plurality of openings 1001 may have diagonal sidewalls. The diagonal sidewalls of the plurality of openings 1001 may be achieved by irradiating light (e.g., using a laser) at one or more angles (e.g., an angle that is not perpendicular to the surface of the first photoresist layer 1000). This approach helps create an opening having a top width at the top of the first photoresist layer 1000 that is less than (eg, smaller than) a bottom width at the bottom of the first photoresist layer 1000 .

[0067] Stage 3 illustrates a state after a plurality of solder pillar interconnects 104 are formed through a plurality of openings 1001 of the first photoresist layer 1000. A plurality of solder pillar interconnects 104 may be formed on a plurality of under bump metallization interconnects 109 (or under bump metallization layers). A plating process may be used to form a plurality of solder pillar interconnects 104. A plurality of solder pillar interconnects 104 may include a side profile cross section including a trapezoidal shape. For example, a top portion of a solder pillar interconnect may have a smaller width (e.g., diameter) than a bottom portion of the solder pillar interconnect. A plurality of solder pillar interconnects 104 may have a diagonal surface.

[0068] like Fig. 10B As shown in FIG. 4 , stage 4 illustrates a state after the first photoresist layer 1000 is removed from the die portion 102. The first photoresist layer 1000 may be removed by a developing process. The first photoresist layer 1000 may be removed by a rinsing process.

[0069] Stage 5 illustrates a state after a second photoresist layer 1020 is formed on the die portion 102 and patterned. The second photoresist layer 1020 may be formed around the plurality of solder pillar interconnects 104. A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the second photoresist layer 1020. The second photoresist layer 1020 may have a plurality of openings 1003 therein. The plurality of openings 1003 may be located above the plurality of solder pillar interconnects 104.

[0070] like Fig. 10C As shown in FIG. 1 , stage 6 illustrates a state after forming a plurality of solder interconnects 106 over a plurality of solder pillar interconnects through a plurality of openings 1003 of a third photoresist layer 1020. In some implementations, a paste process may be used to form the plurality of solder interconnects 106. However, the plurality of solder interconnects 106 may be formed differently.

[0071] Stage 7 illustrates a state after the second photoresist layer 1020 is removed from the die portion 102. The second photoresist layer 1020 can be removed by a developing process. The second photoresist layer 1020 can be removed by a rinsing process. Portions of the under bump metallization interconnect 109 can also be removed. Stage 7 can illustrate an example of an integrated device including a solder pillar interconnect including a side profile cross section including a trapezoidal shape.

[0072] Exemplary flow chart of a method for fabricating an integrated device including solder pillar interconnects

[0073] In some implementations, fabricating an integrated device includes several processes. Fig.11 An exemplary flow chart of a method 1100 for providing or manufacturing an integrated device including solder pillar interconnects is illustrated. In some implementations, Fig.11 The method 1100 may be used to provide or manufacture the Figure 1However, the method 1100 may be used to provide or manufacture any integrated device described in the present disclosure.

[0074] It should be noted that Fig.11 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified.

[0075] The method provides (at 1105) a die portion (e.g., 102). The die portion 102 may include a die substrate 120, an interconnect portion 122, a passivation layer 105, a plurality of pads 107, a passivation layer 108, and a plurality of under bump metallization interconnects 109. The die portion 102 may include a bare die (e.g., a semiconductor bare die). Providing the die portion 102 may include manufacturing the die portion. The die portion 102 may be manufactured using FEOL and BEOL manufacturing processes. Fig. 10A Stage 1 of the present invention illustrates and describes an example of providing a die portion.

[0076] The method forms (at 1110) a first photoresist layer (e.g., 1000) over the die portion (e.g., 102). The method may also pattern (at 1110) the first photoresist layer (e.g., 1000). A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the first photoresist layer 1000.

[0077] Patterning the first photoresist layer may include forming openings (e.g., 1001) in the first photoresist layer 1000. The plurality of openings 1001 may include a cross-sectional shape including a trapezoid. For example, the plurality of openings 1001 may have a top width at the top of the first photoresist layer 1000 that is less than (e.g., less than) a bottom width at the bottom of the first photoresist layer 1000. The plurality of openings 1001 may have diagonal sidewalls. The diagonal sidewalls of the plurality of openings 1001 may be achieved by irradiating light (e.g., using a laser) at one or more angles (e.g., angles that are not perpendicular to the surface of the first photoresist layer 1000). This approach helps create openings having a top width at the top of the first photoresist layer 1000 that is less than (e.g., less than) a bottom width at the bottom of the first photoresist layer 1000. The first photoresist layer 1000 may include a positive photoresist layer. However, in some implementations, the first photoresist layer 1000 may include a negative photoresist layer. Fig. 10A Stage 2 of the present invention illustrates and describes an example of forming and patterning a first photoresist layer.

[0078] The method forms (at 1115) solder pillar interconnects (e.g., 104). The solder pillar interconnects 104 may be formed on a plurality of under bump metallization interconnects 109 (or under bump metallization layers). A plating process may be used to form the solder pillar interconnects 104. The solder pillar interconnects 104 may be formed through a plurality of openings 1001 of the first photoresist layer 1000. Fig. 10A Stage 3 of the present invention illustrates and describes an example of forming solder pillar interconnects.

[0079] The method removes (at 1120) the first photoresist layer (eg, 1000). The first photoresist layer 1000 can be removed by a developing process. The first photoresist layer 1000 can be removed by a rinsing process. Fig. 10B Stage 4 of the present invention illustrates and describes an example of removing the first photoresist layer.

[0080] The method forms (at 1125) a second photoresist layer (e.g., 1020) over the die portion (e.g., 102). The method may also pattern (at 1125) the second photoresist layer (e.g., 1020). A coating process, a masking process, and an exposure process as part of a photolithography process may be used to form and define the pattern of the first photoresist layer 1000. The second photoresist layer 1020 may be formed around the plurality of solder pillar interconnects 104. A coating process, a masking process, and an exposure process as part of a photolithography process may be used to form and define the pattern of the second photoresist layer 1020. The second photoresist layer 1020 may have a plurality of openings 1003 therein. The plurality of openings 1003 may be located over the plurality of solder pillar interconnects 104. Fig. 10B Stage 5 of the present invention illustrates and describes an example of forming and patterning a second photoresist layer.

[0081] The method forms (at 1130) a plurality of solder interconnects (e.g., 106). The plurality of solder interconnects 106 may be formed on the plurality of solder pillar interconnects through the plurality of openings 1003 of the third photoresist layer 1020. In some implementations, a paste process may be used to form the plurality of solder interconnects 106. However, the plurality of solder interconnects 106 may be formed differently. Fig. 10C Stage 6 of the present invention illustrates and describes an example of multiple solder interconnections formed.

[0082] The method removes (at 1135) a portion of the second photoresist layer (e.g., 1020) and the under bump metallization interconnect (e.g., 109). The second photoresist layer 1020 can be removed by a developing process. The second photoresist layer 1020 can be removed by a rinsing process. A portion of the under bump metallization interconnect 109 can also be removed by an etching process. Fig. 10C Stage 7 of FIG. 1 illustrates and describes an example of a state after the second photoresist layer is removed and a portion of the under bump metallization interconnect is removed.

[0083] Exemplary process for fabricating an integrated device including solder pillar interconnects

[0084] In some implementations, fabricating an integrated device includes several processes. Figures 12A-12D Exemplary processes for providing or manufacturing an integrated device including solder pillar interconnects having variable widths are described. In some implementations, Figures 12A-12D The process can be used to provide or manufacture Figure 1 The integrated device 100 includes the solder pillar interconnect 604. However, Figures 12A-12D The process can be used to manufacture any integrated device described in this disclosure.

[0085] It should be noted that Figures 12A-12D The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing an integrated device. In some implementations, the order of each process can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure.

[0086] like Fig. 12A As shown in , stage 1 illustrates a state after providing a die portion 102. The die portion 102 may include a die substrate 120, an interconnect portion 122, a passivation layer 105, a plurality of pads 107, a passivation layer 108, and a plurality of under bump metallization interconnects 109. The die portion 102 may include a bare die (e.g., a semiconductor bare die). Providing the die portion 102 may include manufacturing the die portion. The die portion 102 may be manufactured using FEOL and BEOL manufacturing processes.

[0087] Stage 2 illustrates a state after the first photoresist layer 1200 is formed on the die portion 102 and patterned to include a plurality of openings 1201 in the first photoresist layer 1200. The first photoresist layer 1200 may include a positive photoresist layer. However, in some implementations, the first photoresist layer 1200 may include a negative photoresist layer. A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the first photoresist layer 1200.

[0088] In some implementations, the plurality of openings 1201 may include a cross-sectional shape including a rectangle. For example, the plurality of openings 1201 may have a top width at the top of the first photoresist layer 1200 that is substantially the same as a bottom width at the bottom of the first photoresist layer 1200. The plurality of openings 1201 may have vertical sidewalls.

[0089] In some implementations, the plurality of openings 1201 may include a cross-sectional shape including a trapezoid. For example, the plurality of openings 1201 may have a top width at the top of the first photoresist layer 1200 that is less than (e.g., less than) a bottom width at the bottom of the first photoresist layer 1200. The plurality of openings 1201 may have diagonal sidewalls. The diagonal sidewalls of the plurality of openings 1201 may be achieved by irradiating light (e.g., using a laser) at one or more angles (e.g., angles that are not perpendicular to the surface of the first photoresist layer 1200). This approach helps create openings that have a top width at the top of the first photoresist layer 1200 that is less than (e.g., less than) a bottom width at the bottom of the first photoresist layer 1200.

[0090] Stage 3 illustrates a state after a plurality of solder pillar interconnects 1202 are formed through a plurality of openings 1201 of the first photoresist layer 1200. A plurality of solder pillar interconnects 1202 may be formed on a plurality of under bump metallization interconnects 109 (or under bump metallization layers). A plating process may be used to form a plurality of solder pillar interconnects 1202. A plurality of solder pillar interconnects 1202 may include a side profile cross section including a trapezoidal shape. For example, a top portion of a solder pillar interconnect may have a width (e.g., diameter) that is less (e.g., smaller) than a bottom portion of the solder pillar interconnect. In some implementations, a plurality of solder pillar interconnects 1202 may have diagonal sidewalls. In some implementations, a plurality of solder pillar interconnects 1202 may have vertical sidewalls.

[0091] like Fig. 12B As shown in FIG. 4 , stage 4 illustrates a state after a second photoresist layer 1210 is formed on the first photoresist layer 1200 and patterned to include a plurality of openings 1211 in the second photoresist layer 1200. The plurality of openings 1211 may be located above the plurality of openings 1201. The second photoresist layer 1210 may be similar to the first photoresist layer 1200. A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the second photoresist layer 1210.

[0092] Stage 5 illustrates a state after a plurality of solder pillar interconnects 1204 are formed through a plurality of openings 1211 of the second photoresist layer 1210. A plurality of solder pillar interconnects 1204 may be formed on a plurality of solder pillar interconnects 1202. A plating process may be used to form the plurality of solder pillar interconnects 1204. The plurality of solder pillar interconnects 1204 may include a side profile cross section including a trapezoidal shape. For example, a top portion of a solder pillar interconnect may have a width (e.g., a diameter) that is less (e.g., smaller) than a bottom portion of the solder pillar interconnect. In some implementations, the plurality of solder pillar interconnects 1204 may have diagonal sidewalls. In some implementations, the plurality of solder pillar interconnects 1204 may have vertical sidewalls.

[0093] like Fig. 12C As shown in FIG. 6 , stage 6 illustrates a state after the third photoresist layer 1220 is formed on the second photoresist layer 1210 and patterned to include a plurality of openings 1221 in the third photoresist layer 1220. The plurality of openings 1221 may be located above the plurality of openings 1211. The third photoresist layer 1220 may be similar to the first photoresist layer 1200 and / or the second photoresist layer 1210. A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the third photoresist layer 1220.

[0094] Stage 7 illustrates a state after a plurality of solder pillar interconnects 1206 are formed through a plurality of openings 1221 of the third photoresist layer 1220. A plurality of solder pillar interconnects 1206 may be formed on a plurality of solder pillar interconnects 1204. A plating process may be used to form the plurality of solder pillar interconnects 1206. The plurality of solder pillar interconnects 1206 may include a side profile cross section including a trapezoidal shape. For example, the top portion of the solder pillar interconnect may have a width less (e.g., smaller) than the bottom portion of the solder pillar interconnect. In some implementations, the plurality of solder pillar interconnects 1206 may have diagonal sidewalls. In some implementations, the plurality of solder pillar interconnects 1206 may have vertical sidewalls. Note that the plurality of solder pillar interconnects 1202, the plurality of solder pillar interconnects 1204, and / or the plurality of solder pillar interconnects 1206 may define a plurality of interconnects (e.g., 604) including a side profile cross section including a trapezoidal shape.

[0095] like Fig.12D As shown in FIG. 1 , stage 8 illustrates a state after forming a plurality of solder interconnects 106 over the plurality of solder pillar interconnects 604 through the plurality of openings 1221 of the third photoresist layer 1220. In some implementations, a paste process may be used to form the plurality of solder interconnects 106. However, the plurality of solder interconnects 106 may be formed differently.

[0096] Stage 9 illustrates a state after the first photoresist layer 1200, the second photoresist layer 1210, and the third photoresist layer 1220 are removed from the die portion 102. The first photoresist layer 1000, the second photoresist layer 1210, and / or the third photoresist layer 1220 may be removed by a developing process. The first photoresist layer 1000, the second photoresist layer 1210, and / or the third photoresist layer 1220 may be removed by a rinsing process.

[0097] Exemplary flow chart of a method for fabricating an integrated device including solder pillar interconnects

[0098] In some implementations, fabricating an integrated device includes several processes. Fig.13 An exemplary flow chart of a method 1300 for providing or manufacturing an integrated device including solder pillar interconnects is illustrated. In some implementations, Fig.13The method 1300 may be used to provide or manufacture the Figure 1 The integrated device 100 includes the solder pillar interconnect 404 and / or the solder pillar interconnect 604. However, the method 1300 may be used to provide or manufacture any integrated device described in the present disclosure.

[0099] It should be noted that Fig.13 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified.

[0100] The method provides (at 1305) a die portion (e.g., 102). The die portion 102 may include a die substrate 120, an interconnect portion 122, a passivation layer 105, a plurality of pads 107, a passivation layer 108, and a plurality of under bump metallization interconnects 109. The die portion 102 may include a bare die (e.g., a semiconductor bare die). Providing the die portion 102 may include manufacturing the die portion. The die portion 102 may be manufactured using FEOL and BEOL manufacturing processes. Fig. 12A Stage 1 of the present invention illustrates and describes an example of providing a die portion.

[0101] The method forms (at 1310) a first photoresist layer (e.g., 1200) over the die portion (e.g., 102). The method may also pattern (at 1210) the first photoresist layer (e.g., 1200). A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the first photoresist layer 1200.

[0102] Patterning the first photoresist layer may include forming openings (e.g., 1001) in the first photoresist layer 1200. The plurality of openings 1201 may include a cross-sectional shape including a trapezoid. For example, the plurality of openings 1201 may have a top width at the top of the first photoresist layer 1200 that is less than (e.g., less than) a bottom width at the bottom of the first photoresist layer 1200. The plurality of openings 1201 may have diagonal sidewalls. The diagonal sidewalls of the plurality of openings 1201 may be achieved by irradiating light (e.g., using a laser) at one or more angles (e.g., angles that are not perpendicular to the surface of the first photoresist layer 1200). This approach helps create openings having a top width at the top of the first photoresist layer 1200 that is less than (e.g., less than) a bottom width at the bottom of the first photoresist layer 1200. The first photoresist layer 1200 may include a positive photoresist layer. However, in some implementations, the first photoresist layer 1200 may include a negative photoresist layer. Fig. 12A Stage 2 of the present invention illustrates and describes an example of forming and patterning a first photoresist layer.

[0103] The method forms (at 1315) solder pillar interconnects (e.g., 1202). The solder pillar interconnects 1202 may be formed on the plurality of under bump metallization interconnects 109 (or under bump metallization layers). A plating process may be used to form the solder pillar interconnects 1202. The solder pillar interconnects 1202 may be formed through the plurality of openings 1201 of the first photoresist layer 1200. Fig. 12A Stage 3 of the present invention illustrates and describes an example of forming a solder pillar interconnect portion.

[0104] The method forms (at 1320) a second photoresist layer (e.g., 1210) on the first photoresist layer (e.g., 1210). The method may also pattern (at 1220) the second photoresist layer (e.g., 1210). A coating process, a mask process, and an exposure process as part of a photolithography process may be used to form and define a pattern of the second photoresist layer 1210. Fig. 12B Stage 4 of the present invention illustrates and describes an example of forming and patterning a second photoresist layer.

[0105] The method forms (at 1325) solder pillar interconnects (eg, 1204). The solder pillar interconnects 1204 may be formed on the plurality of solder pillar interconnects 1202. A plating process may be used to form the solder pillar interconnects 1204. The solder pillar interconnects 1204 may be formed through the plurality of openings 1311 of the second photoresist layer 1210. Fig. 12B Stage 5 of the present invention illustrates and describes an example of forming a solder pillar interconnect portion.

[0106] In some implementations, method 1300 can iteratively form and pattern additional photoresist layers and subsequently form additional solder pillar interconnect portions in a manner similar to that described at 1320 and 1325 . Fig. 12C Stage 6 illustrates and describes an example of forming and patterning an additional photoresist layer. Fig. 12C An example of forming additional solder pillar interconnects is illustrated and described in stage 7 of FIG. 1202 , multiple solder pillar interconnects 1204 , and / or multiple solder pillar interconnects 1206 may define multiple solder pillar interconnects 604 .

[0107] The method forms (at 1330) a plurality of solder interconnects (e.g., 106). The plurality of solder interconnects 106 may be formed on the plurality of solder pillar interconnects (e.g., 604) through the plurality of openings 1223 of the third photoresist layer 1220. For example, the plurality of solder interconnects 106 may be formed on the plurality of solder pillar interconnects 1206 through the plurality of openings 1223 of the third photoresist layer 1220. In some implementations, a paste process may be used to form the plurality of solder interconnects 106. However, the plurality of solder interconnects 106 may be formed differently. Fig.12D Stage 8 of the present invention illustrates and describes an example of multiple solder interconnections formed.

[0108] The method removes (at 1335) portions of the photoresist layer(s) (e.g., 1200, 1210, 1220) and the under bump metallization interconnect (e.g., 109). The photoresist layer(s) (e.g., 1200, 1210, 1220) may be removed by a developing process. The photoresist layer(s) (e.g., 1200, 1210, 1220) may be removed by a rinsing process.

[0109] The method removes (at 1340 ) portions of the under bump metallization interconnect 109 via an etching process. Fig.12D Stage 9 of FIG. 1 illustrates and describes an example of a state after the second photoresist layer is removed and a portion of the under bump metallization interconnect is removed.

[0110] Exemplary flow chart of a method for fabricating an integrated device including solder pillar interconnects

[0111] In some implementations, fabricating an integrated device includes several processes. Fig.14 An exemplary flow chart of a method 1400 for providing or manufacturing an integrated device including solder pillar interconnects is illustrated. In some implementations, Fig.14 The method 1400 may be used to provide or manufacture the Figure 1 The integrated device 100 includes the pillar interconnect 104, the pillar interconnect 404, and / or the pillar interconnect 604. However, the method 1400 may be used to provide or manufacture any integrated device described in the present disclosure.

[0112] It should be noted that Fig.14 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing an integrated device. In some implementations, the order of the processes may be changed or modified. Fig.14 The method 1400 may represent Fig.11 and / or a simplified version of the method of 13.

[0113] The method provides (at 1405) a die portion (e.g., 102). The die portion 102 may include a die substrate 120, an interconnect portion 122, a passivation layer 105, a plurality of pads 107, a passivation layer 108, and a plurality of under bump metallization interconnects 109. The die portion 102 may include a bare die (e.g., a semiconductor bare die). The plurality of under bump metallization interconnects 109 are coupled to the plurality of pads 107. Fig. 10A Stage 1 of the present invention illustrates and describes an example of providing a die portion. Fig. 12A Stage 1 of the present invention illustrates and describes an example of providing a die portion.

[0114] The method forms (at 1410) a plurality of solder pillar interconnects on a plurality of under bump metallization interconnects. Forming a plurality of solder pillar interconnects includes forming a plurality of solder pillar interconnect portions. Forming a plurality of solder pillar interconnects includes forming a first solder pillar interconnect. Forming a first solder pillar interconnect so that the first solder pillar interconnect includes a first width corresponding to the widest portion of the first solder pillar interconnect and a second width corresponding to the portion of the first solder pillar interconnect that is the farthest vertically from the first under bump metallization interconnect. Forming a first solder pillar interconnect includes forming a first solder pillar interconnect portion including a first width, and forming a second solder pillar interconnect portion including a second width less than the first width. A coating process, a mask process, and an exposure process as part of a photolithography process can be used to form and define a pattern of (all) photoresist layers. A plating process and a developing process and / or a rinsing process can be used to form solder pillar interconnects and remove (all) photoresist layers. Figures 10A-10B Stages 2-4 of FIG. 1 illustrate and describe an example of forming multiple solder pillar interconnects. Figures 12A-12C Stages 2-7 of FIG. 1 illustrate and describe an example of forming multiple solder pillar interconnects.

[0115] The method forms (at 1415) a plurality of solder interconnects (e.g., 106) over the plurality of solder pillar interconnects (e.g., 104, 404, 604). The plurality of solder interconnects 106 may be formed over the plurality of solder pillar interconnects (e.g., 604) through the plurality of openings of the photoresist layer. In some implementations, a paste process may be used to form the plurality of solder interconnects 106. However, the plurality of solder interconnects 106 may be formed differently. Fig. 10C Stage 6 of the present invention illustrates and describes an example of multiple solder interconnections formed. Fig.12D The example of the multiple solder interconnections formed is illustrated and described in stage 8. Once the multiple interconnections are formed, the photoresist layer(s) and / or portions of the multiple under bump metallization interconnections may be removed. The photoresist layer(s) and / or portions of the multiple under bump metallization interconnections may be removed using a developing process and / or a rinsing process. Fig. 10C Stage 7 of the present invention illustrates and describes an example of removing portions of the photoresist layer and the under bump metallization interconnect. Fig.12D Stage 9 of the present invention illustrates and describes an example of removing portions of the photoresist layer and the under bump metallization interconnect.

[0116] Exemplary process for making a package including an integrated device including solder pillar interconnects

[0117] In some implementations, manufacturing the package includes several processes. Fig.15 Exemplary processes for providing or manufacturing a package including an integrated device including solder pillar interconnects are described. In some implementations, Fig.15 The process can be used to provide or manufacture Figure 8 of package 800. However, Fig.15 The process may be used to manufacture any of the packages described in this disclosure.

[0118] It should be noted that Fig.15 The process of one or more stages can be combined to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure.

[0119] like Fig.15 , stage 1 illustrates a state after providing a substrate 802. The substrate 802 includes at least one dielectric layer 820, a plurality of interconnects 822, and a solder resist layer 826. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded trace substrate (ETS).

[0120] Stage 2 illustrates a state after the integrated device 100 is coupled to the substrate 802 through the plurality of solder pillar interconnects 104 and the plurality of solder interconnects 106. The integrated device 100 may be coupled to the substrate 802 using a solder reflow process. Fig. 9 An example of how integrated device 100 may be coupled to substrate 802 is illustrated. Different implementations may couple different components and / or devices to substrate 802.

[0121] Stage 3 illustrates a state after providing (e.g., forming) an encapsulation layer 808 on the substrate 802. The encapsulation layer 808 can encapsulate the integrated device 100. The encapsulation layer 808 can include a molding, a resin, and / or an epoxy resin. The encapsulation layer 808 can be formed using a compression molding process, a transfer molding process, or a liquid molding process. The encapsulation layer 808 can be photoetchable. The encapsulation layer 808 can be an encapsulation device.

[0122] Stage 4 illustrates a state after the plurality of solder interconnects 830 are coupled to the substrate 802. The plurality of solder interconnects 830 may be coupled to the substrate 802 using a solder reflow process.

[0123] Exemplary flow chart of a method for manufacturing a package including an integrated device including solder pillar interconnects

[0124] In some implementations, manufacturing the package includes several processes. Fig.16 An exemplary flow chart of a method 1600 for providing or manufacturing a package including an integrated device including solder pillar interconnects is illustrated. In some implementations, Fig.16 The method 1600 may be used to provide or manufacture the Figure 8 However, method 1600 may be used to provide or manufacture any package (eg, 800) described in the present disclosure.

[0125] It should be noted that Fig.16The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0126] The method provides (at 1605) a substrate (e.g., 802). The substrate 802 may be provided by a supplier or manufactured. Different implementations may use different processes to manufacture the substrate 802. Examples of processes that may be used to manufacture the substrate 802 include a semi-additive process (SAP) and a modified semi-additive process (mSAP). The substrate 802 includes at least one dielectric layer 820, a plurality of interconnects 822, and a solder mask layer 826. The substrate 802 may include an embedded trace substrate (ETS). In some implementations, at least one dielectric layer 820 may include a prepreg layer. Fig.15 Stage 1 of the present invention illustrates and describes an example of providing a substrate.

[0127] The method (at 1610) couples an integrated device (e.g., 100, 300, 800) to a first surface of a substrate 802. For example, the integrated device 100 is coupled to a first surface (e.g., a top surface) of the substrate 802. The integrated device 100 is coupled to the substrate 802 via a plurality of solder pillar interconnects 104 and a plurality of solder interconnects 106. A solder reflow process may be used to couple the integrated device 100 to the substrate 802. In some implementations, the integrated device may be coupled to the substrate 802 via a plurality of solder pillar interconnects 104, a plurality of solder pillar interconnects 304, and / or a plurality of solder interconnects 106. Figure 6-8 An example of how an integrated device may be coupled to substrate 802 is illustrated. Fig.15 Stage 2 of the present invention illustrates and describes an example of coupling an integrated device to a substrate.

[0128] The method forms (at 1615) an encapsulation layer (e.g., 808) over the substrate (e.g., 802). Encapsulation layer 808 may be provided and formed over and / or around substrate 802 and integrated device 100. Encapsulation layer 808 may include a molding, a resin, and / or an epoxy. Encapsulation layer 808 may be formed using a compression molding process, a transfer molding process, or a liquid molding process. Encapsulation layer 808 may be photoetchable. Encapsulation layer 808 may be an encapsulation device. Fig.15 Stage 3 of the present invention illustrates and describes an example of forming an encapsulation layer.

[0129] The method couples (at 1620) a plurality of solder interconnects (eg, 830) to the substrate 802. The plurality of solder interconnects 830 may be coupled to the substrate 802 using a solder reflow process. Fig.15 Stage 4 of the present invention illustrates and describes an example of coupling a solder interconnect to a substrate.

[0130] The packages (eg, 800 ) described in this disclosure may be fabricated one at a time, or may be fabricated together (as part of one or more wafers) and subsequently singulated into individual packages.

[0131] Exemplary Electronic Devices

[0132] Fig.17 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 1702, a laptop computer device 1704, a fixed location terminal device 1706, a wearable device 1708, or a motor vehicle 1710 may include a device 1700 as described herein. The device 1700 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig.17 The devices 1702, 1704, 1706, and 1708, and the vehicle 1710 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 1700, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0133] Figure 1-9 , Figures 10A-10C , Fig.11 , Fig. 12A – 12D and / or Figure 13-17 One or more of the components, processes, features, and / or functions described herein may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-9 , Figures 10A-10C , Fig.11 , Fig. 12A – 12D and / or Figure 13-17 and its corresponding description in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-9, Figures 10A-10C , Fig.11 , Fig. 12A – 12D and / or Figure 13-17 The invention and its corresponding description may be used to manufacture, create, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0134] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0135] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have an electric current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate", "encapsulate" and / or any derivatives thereof refer to an object that may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. Further note that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. A value of about X-XX may mean a value between X and XX (inclusive). The value(s) between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0136] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces, through-holes, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnections. In some implementations, interconnection may include a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), grounding, and / or power. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0137] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0138] Further examples are described below to facilitate understanding of the present disclosure.

[0139] Aspect 1: An integrated device includes a tube core portion and a plurality of solder pillar interconnects. The tube core portion includes a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, wherein the plurality of under bump metallization interconnects include a first under bump metallization interconnect. The plurality of solder pillar interconnects are coupled to the plurality of under bump metallization interconnects. The plurality of solder pillar interconnects include a first solder pillar interconnect, the first solder pillar interconnect including a first width corresponding to the widest portion of the first solder pillar interconnect; and a second width corresponding to a portion of the first solder pillar interconnect that is the farthest vertically from the first under bump metallization interconnect, wherein the second width is less than the first width.

[0140] Aspect 2: The integrated device of aspect 1, wherein the first solder pillar interconnect comprises a diagonal surface.

[0141] Aspect 3: The integrated device of any one of aspects 1 to 2, wherein the first solder pillar interconnect comprises a surface including a stepped surface.

[0142] Aspect 4: The integrated device of aspects 1 to 3, wherein the first solder pillar interconnect comprises a cross-sectional profile including a trapezoidal shape.

[0143] Aspect 5: An integrated device as in Aspect 4, wherein the trapezoidal shape includes a top portion and a bottom portion, wherein the top portion of the trapezoidal shape is farther from the first under-bump metallization interconnect than the bottom portion of the trapezoidal shape is from the first under-bump metallization interconnect, wherein the bottom portion of the trapezoidal shape has the first width, and wherein the top portion of the trapezoidal shape has the second width.

[0144] Aspect 6: The integrated device of aspects 1 to 5, wherein the first solder pillar interconnect comprises a cross-sectional profile including a first trapezoidal shape and a second trapezoidal shape.

[0145] Aspect 7: The integrated device of Aspect 6, wherein the second trapezoidal shape is an inverted trapezoidal shape relative to the first trapezoidal shape.

[0146] Aspect 8: The integrated device of any one of aspects 1 to 7, wherein the first solder pillar interconnect comprises a first diagonal surface having a first angle and a second diagonal surface having a second angle.

[0147] Aspect 9: The integrated device of aspects 1 to 8, wherein the die portion comprises: a die substrate; a plurality of transistors formed in and / or on the die substrate; and an interconnection portion located on the die substrate.

[0148] Aspect 10: A package includes a substrate and an integrated device. The integrated device includes a plurality of under-bump metallization interconnects including a first under-bump metallization interconnect, and a plurality of solder pillar interconnects including a first solder pillar interconnect. The first solder pillar interconnect is coupled to the first under-bump metallization interconnect. The first solder pillar interconnect includes a first width corresponding to the widest portion of the first solder pillar interconnect and a second width corresponding to a portion of the first solder pillar interconnect that is the farthest vertically from the first under-bump metallization interconnect, wherein the second width is less than the first width. The integrated device is coupled to the substrate via the plurality of solder pillar interconnects and the plurality of solder interconnects.

[0149] Aspect 11: The package of aspect 10, wherein the first solder pillar interconnect comprises a diagonal surface.

[0150] Aspect 12: The package of aspects 10 to 11, wherein the first solder pillar interconnect comprises a surface including a stepped surface.

[0151] Aspect 13: The package of aspects 10 to 12, wherein the first solder pillar interconnect comprises a cross-sectional profile comprising a trapezoidal shape.

[0152] Aspect 14: A package as in Aspect 13, wherein the trapezoidal shape includes a top portion and a bottom portion, wherein the top portion of the trapezoidal shape is farther away from the first under-bump metallization interconnect than the bottom portion of the trapezoidal shape is from the first under-bump metallization interconnect, wherein the bottom portion of the trapezoidal shape has the first width, and wherein the top portion of the trapezoidal shape has the second width.

[0153] Aspect 15: The package of aspects 10 to 14, wherein the first solder pillar interconnect comprises a cross-sectional profile comprising a first trapezoidal shape and a second trapezoidal shape.

[0154] Aspect 16: The package of aspect 15, wherein the second trapezoidal shape is an inverted trapezoidal shape relative to the first trapezoidal shape.

[0155] Aspect 17: The package of aspects 10 to 16, wherein the first solder pillar interconnect comprises a first diagonal surface having a first angle and a second diagonal surface having a second angle.

[0156] Aspect 18: A package as in Aspects 10 to 17, wherein the package is part of a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0157] Aspect 19: A method for manufacturing an integrated device. The method provides: a tube core portion including a plurality of pads; and a plurality of under bump metallization interconnects coupled to the plurality of pads. The method forms a plurality of solder pillar interconnects on the plurality of under bump metallization interconnects, wherein forming the plurality of solder pillar interconnects includes forming a first solder pillar interconnect so that the first solder pillar interconnect includes: a first width corresponding to a widest portion of the first solder pillar interconnect and a second width corresponding to a portion of the first solder pillar interconnect that is the farthest vertically from the first under bump metallization interconnect, wherein the second width is less than the first width.

[0158] Aspect 20: The method of aspect 19, wherein forming the first solder pillar interconnect comprises: forming the first solder pillar interconnect such that the first solder pillar interconnect includes a diagonal surface.

[0159] Aspect 21: The method of aspects 19 to 20, wherein forming the first solder pillar interconnect comprises forming the first solder pillar interconnect such that a cross-sectional profile of the first solder pillar interconnect comprises a trapezoidal shape.

[0160] Aspect 22: A method as in Aspect 21, wherein the trapezoidal shape includes a top portion and a bottom portion, wherein the top portion of the trapezoidal shape is farther from the first under-bump metallization interconnect than the bottom portion of the trapezoidal shape is from the first under-bump metallization interconnect, wherein the bottom portion of the trapezoidal shape has the first width, and wherein the top portion of the trapezoidal shape has the second width. The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative and not to limit the scope of the appended claims. Thus, the teachings of the present disclosure can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An integrated device, comprising: The die part includes: a plurality of pads; and a plurality of under bump metallization interconnects coupled to the plurality of pads, wherein the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect; and a plurality of solder pillar interconnects coupled to the plurality of under bump metallization interconnects, wherein the plurality of solder pillar interconnects comprises a first solder pillar interconnect, the first solder pillar interconnect comprising: a first width corresponding to a widest portion of the first solder pillar interconnect; and A second width corresponding to a portion of the first pillar interconnect that is vertically farthest from the first under bump metallization interconnect, wherein the second width is smaller than the first width.

2. The integrated device of claim 1, wherein the first solder pillar interconnect comprises a diagonal surface.

3. The integrated device of claim 1, wherein the first solder pillar interconnect comprises a surface including a stepped surface.

4. The integrated device of claim 1, wherein the first solder pillar interconnect comprises a profile cross-section comprising a trapezoidal shape.

5. The integrated device according to claim 4, wherein the trapezoidal shape comprises a top portion and a bottom portion, wherein the top portion of the trapezoidal shape is further away from the first under bump metallization interconnect than the bottom portion of the trapezoidal shape is from the first under bump metallization interconnect, wherein the bottom portion of the trapezoidal shape has the first width, and Wherein the top portion of the trapezoidal shape has the second width.

6. The integrated device of claim 1, wherein the first solder pillar interconnect comprises a cross-sectional profile including a first trapezoidal shape and a second trapezoidal shape. 7 . The integrated device of claim 6 , wherein the second trapezoidal shape is an inverted trapezoidal shape relative to the first trapezoidal shape.

8. The integrated device of claim 1, wherein the first solder pillar interconnect comprises a first diagonal surface having a first angle and a second diagonal surface having a second angle.

9. The integrated device of claim 1, wherein the die portion comprises: die substrate; a plurality of transistors formed in and / or on the die substrate; as well as An interconnect portion is located on the die substrate.

10. A package comprising: substrate; as well as An integrated device, comprising: a plurality of under bump metallization interconnects, the plurality of under bump metallization interconnects including a first under bump metallization interconnect; and a plurality of solder pillar interconnects, the plurality of solder pillar interconnects comprising a first solder pillar interconnect, wherein the first solder pillar interconnect is coupled to the first under bump metallization interconnect, and The first solder column interconnection comprises: a first width corresponding to a widest portion of the first solder pillar interconnect; and a second width corresponding to a portion of the first solder pillar interconnect that is vertically farthest from the first under bump metallization interconnect, wherein the second width is less than the first width, and The integrated device is coupled to the substrate through the plurality of solder pillar interconnects and the plurality of solder interconnects. The package of claim 10 , wherein the first solder pillar interconnect comprises a diagonal surface.

12. The package of claim 10, wherein the first solder pillar interconnect comprises a surface including a stepped surface.

13. The package of claim 10, wherein the first solder pillar interconnect comprises a profile cross-section comprising a trapezoidal shape.

14. The package according to claim 13, wherein the trapezoidal shape comprises a top portion and a bottom portion, wherein the top portion of the trapezoidal shape is further away from the first under bump metallization interconnect than the bottom portion of the trapezoidal shape is from the first under bump metallization interconnect, wherein the bottom portion of the trapezoidal shape has the first width, and Wherein the top portion of the trapezoidal shape has the second width.

15. The package of claim 10, wherein the first solder pillar interconnect comprises a cross-sectional profile including a first trapezoidal shape and a second trapezoidal shape.

16. The package of claim 15, wherein the second trapezoidal shape is an inverted trapezoidal shape relative to the first trapezoidal shape.

17. The package of claim 10, wherein the first solder pillar interconnect comprises a first diagonal surface having a first angle and a second diagonal surface having a second angle.

18. A package as described in claim 10, wherein the package is part of a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

19. A method for manufacturing an integrated device, comprising: A tube core portion is provided, the tube core portion comprising: a plurality of pads; and a plurality of under bump metallization interconnects coupled to the plurality of pads; and forming a plurality of solder pillar interconnects on the plurality of under bump metallization interconnects, Wherein forming the plurality of solder pillar interconnections comprises: forming a first solder pillar interconnection so that the first solder pillar interconnection comprises: a first width corresponding to a widest portion of the first solder pillar interconnect; and A second width corresponding to a portion of the first pillar interconnect that is vertically farthest from the first under bump metallization interconnect, wherein the second width is smaller than the first width.

20. The method of claim 19, wherein forming the first solder pillar interconnect comprises: The first solder pillar interconnect is formed such that the first solder pillar interconnect includes a diagonal surface.

21. The method of claim 19, wherein forming the first solder pillar interconnect comprises: The first solder pillar interconnect is formed such that a cross-sectional profile of the first solder pillar interconnect includes a trapezoidal shape.

22. The method of claim 21, wherein the trapezoidal shape comprises a top portion and a bottom portion, wherein the top portion of the trapezoidal shape is further away from the first under bump metallization interconnect than the bottom portion of the trapezoidal shape is from the first under bump metallization interconnect, wherein the bottom portion of the trapezoidal shape has the first width, and Wherein the top portion of the trapezoidal shape has the second width.

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