Imaging element and imaging device

Abstract

This imaging element (1) is provided with a pixel array (40) in which a plurality of pixels (30) are arranged in a matrix, and is provided, for each column, with: a plurality of impedance conversion circuits (61) to which a pixel signal output from at least one pixel (30) is input; and an AD converter (64) for AD-converting a plurality of signals output from the plurality of impedance conversion circuits (61), the pixel array (40) being provided with N pixel groups (100) for each column, each of the N pixel groups (100) comprising K or more pixels (30) arranged consecutively in the column direction, and each of the N pixel groups (100) being provided with a vertical signal line (50) connected to L or more pixels (30) among the K or more pixels (30). In each column, each of N vertical signal lines (50) provided in N pixel groups (100) is connected to an input of any one of a plurality of impedance conversion circuits (61), and an output of each of the plurality of impedance conversion circuits (61) is connected to an AD converter (64).

Description

Technical Field

[0001] The present disclosure relates to an imaging element and an imaging device for capturing an image. Background Art

[0002] There are conventional imaging elements that capture images (for example, see Patent Document 1).

[0003] (Prior art literature)

[0004] (Patent Document)

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-53648 Summary of the invention

[0006] Problems to be solved by the invention

[0007] It is desirable for an image sensor to increase the speed of reading out pixel signals from pixels, but even when the speed of reading out is increased, it is undesirable that the quality of the captured image deteriorates.

[0008] Therefore, an object of the present disclosure is to provide an image pickup element or the like that can suppress degradation in the quality of a captured image and increase the speed at which pixel signals are read out from pixels.

[0009] Means for solving problems

[0010] An imaging element according to one embodiment of the present disclosure includes a pixel array in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels includes a photoelectric conversion unit for converting received light into electric charge, a charge storage unit for storing the electric charge converted by the photoelectric conversion unit, and an amplifier transistor for outputting a pixel signal corresponding to the amount of electric charge stored in the charge storage unit, and the imaging element includes, for each column of the pixel array: a plurality of first impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of first impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; and a first AD converter for converting each of the plurality of first impedance conversion signals output from the plurality of first impedance conversion circuits into an analog-to-digital converter. A method for performing AD conversion, wherein the pixel array comprises N pixel groups in each column, each of the N pixel groups is composed of K or more pixels among the plurality of pixels, and the K or more pixels are arranged continuously in a column direction, N is an integer greater than 2, K is an integer greater than 2, each of the N pixel groups comprises a first vertical signal line, the first vertical signal line is connected to L or more first pixels among the K or more pixels, L is an integer greater than 2 and less than K, and in each column of the pixel array, each of the N first vertical signal lines of the N pixel groups is connected to the input of any one of the plurality of first impedance conversion circuits, and the output of each of the plurality of first impedance conversion circuits is connected to the first AD converter.

[0011] An imaging device according to one aspect of the present disclosure includes the above-mentioned imaging element.

[0012] An imaging element according to one embodiment of the present invention comprises: a pixel array in which pixels are arranged in a matrix, and the pixels have a photoelectric conversion unit that converts received light into electric charge; a pixel group composed of a plurality of pixels in the pixel array; a vertical signal line connected to at least one of the plurality of pixels in the pixel group; an impedance conversion circuit connected to the vertical signal line, the output impedance of the impedance conversion circuit being lower than the input impedance; and an AD converter connected to the impedance conversion circuit.

[0013] Effects of the Invention

[0014] According to the imaging element and the like according to one embodiment of the present disclosure, it is possible to increase the speed of reading pixel signals from pixels while suppressing degradation in the quality of captured images. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a perspective view showing the appearance of the image pickup element according to the first embodiment.

[0016] Figure 2This is a plan view of the first semiconductor chip according to the first embodiment.

[0017] Figure 3 This is a plan view of the pixel array involved in Embodiment 1.

[0018] Figure 4 This is a circuit diagram showing the structure of a pixel according to Embodiment 1.

[0019] Figure 5 This is a plan view of the second semiconductor chip involved in the first embodiment.

[0020] Figure 6 This is a plan view of the readout circuit involved in Embodiment 1.

[0021] Figure 7 : is a circuit diagram showing an example of the configuration of the first impedance conversion circuit according to the first embodiment.

[0022] Figure 8 This is a timing chart showing how the control unit according to Embodiment 1 operates the current source and the like to flow a current into the first vertical signal line.

[0023] Fig. 9 This is a timing chart showing how the control unit according to Embodiment 1 operates the current source and the like to flow a current into the first vertical signal line.

[0024] Fig.10 This is a timing chart showing how the control unit according to Embodiment 1 operates the current source and the like to flow a current into the first vertical signal line.

[0025] Fig.11 This is a timing chart showing how the control unit according to Embodiment 1 operates the current source and the like to flow a current into the first vertical signal line.

[0026] Fig.12 1 is a plan view of a readout circuit according to Modification 1.

[0027] Fig.13 It is a plan view of a readout circuit involved in Modification Example 2.

[0028] Fig.14 This is a plan view of a pixel array according to variation 3.

[0029] Fig.15 This is a circuit diagram showing the structure of a pixel according to Modification Example 3.

[0030] Fig.16 1 is a plan view showing a readout circuit according to Modification 3.

[0031] Fig.17It is a plan view of a readout circuit involved in Modification Example 4.

[0032] Fig.18 This is a plan view of a pixel array according to the second embodiment.

[0033] Fig.19 This is a plan view of a readout circuit according to the second embodiment.

[0034] Fig. 20 This is a configuration diagram showing an example of the configuration of a readout circuit according to the second embodiment.

[0035] Fig.21 This is a plan view of a pixel array according to variation 5.

[0036] Fig. 22 This is a plan view of a readout circuit according to Modification Example 5.

[0037] Fig.23 This is a schematic diagram showing the structure of an imaging device according to the third embodiment.

[0038] Fig.24 It is a plan view of a pixel array involved in a supplementary variation.

[0039] Fig.25 It is a plan view of a readout circuit involved in a supplementary variation.

[0040] Fig.26 : is a circuit diagram showing an example of the configuration of a first impedance conversion circuit according to a supplementary modification. DETAILED DESCRIPTION

[0041] (The process of obtaining one method of the present disclosure)

[0042] In the past, as a technology for achieving a faster read speed of pixel signals from pixels, there is a known technology, namely: dividing the vertical signal line configured according to each column of the pixel array into multiple, and connecting multiple AD (Analog to Digital) converters to each of the divided multiple vertical signal lines (hereinafter also referred to as "divided vertical signal lines"), so as to use the multiple divided vertical signal lines and multiple AD converters to read pixel signals from the pixels of each column.

[0043] Through this technology, compared with the technology of using one vertical signal line and one AD converter to read pixel signals from pixels of each column, since the wiring capacity of multiple divided vertical signal lines is reduced compared with one vertical signal line, and the number of pixels connected to the multiple divided vertical signal lines as loads is also less than the number of pixels connected to one vertical signal line as load, the read speed of pixel signals from the pixels can be increased.

[0044] The inventors of the present invention conducted experiments using the above-mentioned technology and studied the experiments, and found that the image captured by the imaging element would be degraded due to the use of the technology.

[0045] That is, when this technology is used, since the pixels connected to different split vertical signal lines are read out by different AD converters, the characteristics of the AD converter connected to the split vertical line are reflected in the pixel signals read out for each of the multiple split vertical lines. Therefore, due to manufacturing non-uniformity, when a characteristic difference occurs in multiple AD converters, the characteristic difference of the multiple AD converters is reflected between the pixel signals read out from the pixels connected to different split vertical signal lines. As a result, the image quality of the image captured by the imaging element is degraded.

[0046] Therefore, based on the above-mentioned findings, the inventors of the present invention believed that the degradation of the image quality of images captured by the imaging element should be suppressed, and further conducted studies and repeated experiments, thereby conceiving of the imaging element and the like according to the present disclosure described below.

[0047] An imaging element according to one embodiment of the present disclosure includes a pixel array in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels includes a photoelectric conversion unit for converting received light into electric charge, a charge storage unit for storing the electric charge converted by the photoelectric conversion unit, and an amplifier transistor for outputting a pixel signal corresponding to the amount of electric charge stored in the charge storage unit, and the imaging element includes, for each column of the pixel array: a plurality of first impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of first impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; and a first AD converter for converting each of the plurality of first impedance conversion signals output from the plurality of first impedance conversion circuits into an analog-to-digital converter. A method for performing AD conversion, wherein the pixel array comprises N pixel groups in each column, each of the N pixel groups is composed of K or more pixels among the plurality of pixels, and the K or more pixels are arranged continuously in a column direction, N is an integer greater than 2, K is an integer greater than 2, each of the N pixel groups comprises a first vertical signal line, the first vertical signal line is connected to L or more first pixels among the K or more pixels, L is an integer greater than 2 and less than K, and in each column of the pixel array, each of the N first vertical signal lines of the N pixel groups is connected to the input of any one of the plurality of first impedance conversion circuits, and the output of each of the plurality of first impedance conversion circuits is connected to the first AD converter.

[0048] With the imaging element having the above configuration, in each column, a plurality of first pixels are connected to any one of the N first vertical signal lines divided into N. Accordingly, with the imaging element having the above configuration, compared with a configuration in which a plurality of first pixels are connected to one vertical signal line in each column, the wiring capacity of each first vertical signal line is reduced compared with the wiring capacity of one vertical signal line, and the number of first pixels connected to each first vertical signal line as a load is also reduced compared with the number of first pixels connected to one vertical signal line as a load, thereby making it possible to increase the speed of reading pixel signals from the first pixels.

[0049] Furthermore, with the imaging element of the above configuration, each of the N first vertical signal lines is connected to one AD converter via any one of the plurality of first impedance conversion circuits in each column. Accordingly, with the imaging element of the above configuration, compared with a configuration in which each of the N first vertical signal lines is connected to each of the plurality of AD converters in each column, the characteristic difference that would occur in the plurality of AD converters is not reflected between the pixel signals read out from the first pixels connected to the first vertical signal lines that are different from each other. Therefore, with the imaging element of the above configuration, the image quality degradation of the image captured by the imaging element due to the characteristic difference generated in the plurality of AD converters in each column is suppressed.

[0050] As described above, the imaging element having the above-described structure can increase the speed of reading pixel signals from pixels while suppressing degradation in the quality of captured images.

[0051] Furthermore, L may be equal to K, and the K or more pixels may be the L or more first pixels.

[0052] Accordingly, in each of the N pixel groups, all pixels included in the pixel group can be regarded as first pixels.

[0053] It may also be that K is an integer greater than 4, L is an integer greater than 2 and less than K / 2, and the imaging element further comprises, for each column of the pixel array: a plurality of second impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of second impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; and a second AD converter that performs AD conversion on the plurality of second impedance conversion signals output from the plurality of second impedance conversion circuits, and each of the N pixel groups further comprises a second vertical signal line, the second vertical signal line being connected to L or more second pixels among the K or more pixels, the L or more second pixels being different from the L or more first pixels, and in each column of the pixel array, each of the N second vertical signal lines possessed by the N pixel groups is connected to the input of any one of the plurality of second impedance conversion circuits, and the output of each of the plurality of second impedance conversion circuits is connected to the second AD converter.

[0054] Accordingly, in each column, pixel signals can be read out in parallel from the first pixel and the second pixel that are included in the same pixel group, i.e., are relatively close. Accordingly, when pixel signals are read out from pixels that are sequentially read out and scanned in each row, when photographing a moving subject, the distortion of the subject in the photographed image (rolling shutter distortion phenomenon) that is likely to occur when pixel signals are read out in parallel from two pixels that are relatively far apart in each column can be reduced, and thus the distortion can be made less noticeable.

[0055] It may also be that, in each column of the pixel array, at least one output of the multiple first impedance conversion circuits is connected to the first AD converter via a first common signal line, and at least one other output of the multiple first impedance conversion circuits is connected to the first AD converter via a second common signal line different from the first common signal line.

[0056] According to this, compared with a configuration in which the outputs of the plurality of first impedance conversion circuits in each column are all connected to the first AD converter via a common signal line, the load capacity when at least one output of the plurality of first impedance conversion circuits is driven and the load capacity when at least one other output of the plurality of first impedance conversion circuits is driven can be reduced. Therefore, the readout speed of the pixel signal from the pixel can be further increased.

[0057] Furthermore, in each column of the pixel array, at least one input of the plurality of first impedance conversion circuits may be selectively connected to two of the first vertical signal lines of two pixel groups adjacent to each other in the column direction among the N pixel groups.

[0058] According to this, in each column, two first vertical signal lines included in two pixel groups adjacent to each other in the column direction can share one first impedance conversion circuit.

[0059] Furthermore, each of the plurality of first impedance conversion circuits may include an output transistor for outputting each of the plurality of first impedance conversion signals, and each of the output transistors may have a higher driving capability than the amplifying transistor.

[0060] According to this, in each column, the speed of reading pixel signals from the first pixels via the first impedance conversion circuit can be further increased.

[0061] It may also be that the imaging element further has a plurality of current sources for each column of the pixel array, and the plurality of current sources flow current into each of the N first vertical signal lines, and the imaging element further has a reference current source, and the reference current source uniformly regulates the current flowing in at least two current sources among all the plurality of current sources possessed by the imaging element.

[0062] This makes it possible to uniformly regulate the currents flowing through all the current sources included in the pixel array.

[0063] Furthermore, N may be an integer greater than 4, the imaging element is formed by stacking a first semiconductor chip and a second semiconductor chip, the pixel array is formed on the first semiconductor chip, the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed on the second semiconductor chip, in a plan view of the pixel array, in each column of the pixel array, the N first vertical signal lines provided by the N pixel groups extend in the column direction of the pixel array and are arranged in the column direction of the pixel array, one of the plurality of first impedance conversion circuits is located between a third vertical signal line and a fourth vertical signal line that are adjacent to each other in the column direction of the pixel array among the N first vertical signal lines, another one of the plurality of first impedance conversion circuits is located between a fifth vertical signal line and a sixth vertical signal line that are adjacent to each other in the column direction of the pixel array among the N first vertical signal lines, and the fifth vertical signal line and the sixth vertical signal line are different from the third vertical signal line and the fourth vertical signal line.

[0064] Accordingly, in each column, the distance from the third vertical signal line and the fourth vertical signal line to one of the multiple first impedance conversion circuits, and the distance from the fifth vertical signal line and the sixth vertical signal line to another first impedance conversion circuit among the multiple first impedance conversion circuits can be made relatively short.

[0065] It may also be that the imaging element is formed by stacking a first semiconductor chip and a second semiconductor chip on each other, the pixel array is formed on the first semiconductor chip, and the multiple first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed on the second semiconductor chip. In a plan view of the pixel array, in each column of the pixel array, the N first vertical signal lines provided by the N pixel groups extend in the column direction of the pixel array and are arranged in the column direction of the pixel array, and the range of one or more wirings for connecting the outputs of the multiple first impedance conversion circuits with the first AD converter in the column direction of the pixel array is included in the range of the N first vertical signal lines in the column direction of the pixel array.

[0066] According to this, in each column, it is possible to suppress unnecessary growth of one or more wirings that connect the outputs of the plurality of first impedance conversion circuits and the first AD converter.

[0067] It may also be that the imaging element is formed by stacking a first semiconductor chip and a second semiconductor chip on each other, the pixel array is formed on the first semiconductor chip, and the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed on the second semiconductor chip, and in a plan view of the pixel array, in each column of the pixel array, the N first vertical signal lines provided by the N pixel groups extend in the column direction of the pixel array and are arranged in the column direction of the pixel array, and the total wiring length of one or more wirings for connecting the outputs of the plurality of first impedance conversion circuits to the first AD converter is smaller than the total wiring length of the N first vertical signal lines.

[0068] According to this, in each column, it is possible to suppress unnecessary growth of one or more wirings that connect the outputs of the plurality of first impedance conversion circuits and the first AD converter.

[0069] It may also be that the pixel array further has a plurality of current sources for each column, and the plurality of current sources flow current into each of the N first vertical signal lines. The imaging element further has a control unit, and the control unit controls all of the plurality of current sources of the pixel array. The control unit activates, for each column of the pixel array, a current source among the plurality of current sources that flows current into the first vertical signal line of a pixel group that performs readout, and deactivates other current sources. The pixel group that performs readout is a pixel group composed of the K or more pixels that output pixel signals.

[0070] In this way, in each column, current sources other than the current source that flows current into the first vertical signal line of the pixel group performing readout can be inactivated, thereby reducing power consumption of the imaging element compared to the case where current flows into all first vertical signal lines.

[0071] It may also be that the pixel array further has a plurality of current sources for each column, and the plurality of current sources flow current into each of the N first vertical signal lines, and the imaging element further has a control unit, and the control unit controls all of the plurality of current sources of the pixel array, and the control unit sets, for each column of the pixel array, a current source among the plurality of current sources that flows current into the first vertical signal line of a pixel group performing readout to a first activation state, and sets other current sources to a second activation state, the pixel group performing readout is a pixel group composed of the K or more pixels that output pixel signals, and the amount of current flowing in the second activation state is less than the amount of current flowing in the first activation state.

[0072] According to this, in each column, a current source other than the current source that flows a current into the first vertical signal line of the pixel group that performs readout can be set to the second activation state, and the second activation state is a state in which the amount of current flowing is less than that in the first activation state. Therefore, compared with the case in which the current of the amount corresponding to the first activation state flows into all the first vertical signal lines, the power consumption of the imaging element can be suppressed.

[0073] Furthermore, the pixel array may further include a plurality of current sources for each column, the plurality of current sources flowing current into each of the N first vertical signal lines, and the imaging element may further include a control unit, the control unit controlling all of the plurality of current sources included in the pixel array, the control unit activating or deactivating current sources (1) to (3) among the plurality of current sources for each column of the pixel array, (1) activating a current source flowing current into the first vertical signal line included in a readout pixel group, the readout pixel group being a pixel group consisting of the K or more pixels that output pixel signals , (2) a current source that flows current into the first vertical signal line of the pixel group before the readout is in the activated state before the K or more pixels of the pixel group before the readout start to output pixel signals, the pixel group before the readout is a pixel group consisting of the K or more pixels that output pixel signals after the K or more pixels of the pixel group for readout, and (3) current sources other than the current source that flows current into the first vertical signal line of the pixel group for readout and the current source that flows current into the first vertical signal line of the pixel group before the readout are in the inactivated state.

[0074] Generally speaking, when a pixel signal is read from a pixel using a vertical signal line into which a current flows from a current source immediately after a current source is changed from an inactive state to an active state, the pixel signal may not be read with high accuracy.

[0075] In this regard, with the imaging element having the above configuration, in each column, the current source that flows current into the first vertical signal line of the pixel group before the readout is changed from an inactive state to an active state before the pixels included in the pixel group before the readout start outputting pixel signals. Therefore, with the imaging element having the above configuration, when reading pixel signals from pixels, it is possible to suppress the pixel signals from not being read out with high accuracy.

[0076] Furthermore, the pixel array may further include a plurality of current sources for each column, and the plurality of current sources flow current into a power wiring connected to the K or more pixels included in the pixel group for each of the N pixel groups, and the imaging element may further include a control unit for controlling the plurality of current sources included in the pixel array, and the control unit may activate, for each column of the pixel array, a current source among the plurality of current sources that flows current into the power wiring connected to the K or more pixels included in the pre-readout pixel group before the K or more pixels in the pre-readout pixel group start outputting pixel signals, and may inactivate current sources other than the current source that flows current into the power wiring connected to the K or more pixels included in the pre-readout pixel group, the pre-readout pixel group being a pixel group consisting of the K or more pixels that output pixel signals after the K or more pixels included in the readout pixel group, and the readout pixel group being a pixel group consisting of the K or more pixels that output pixel signals.

[0077] Generally speaking, a voltage difference occurs between the voltage of the power supply supplied to the pixel when no current flows in the power supply wiring connected to the pixel and the voltage of the power supply supplied to the pixel when current flows in the power supply wiring connected to the pixel. Furthermore, when a pixel signal is read from a pixel in a state where no voltage drop occurs and when a pixel signal is read from a pixel in a state where a voltage drop occurs, a difference occurs in the read pixel signal.

[0078] In this regard, the imaging element of the above configuration starts to flow current into the power supply wiring connected to the pixels included in the pixel group before the readout is performed in each column before the pixels included in the pixel group before the readout is performed start to output the pixel signal. Therefore, the imaging element of the above configuration generates a voltage drop in advance at the moment when the pixels included in the pixel group before the readout is performed start to output the pixel signal in each column. Therefore, the imaging element of the above configuration can suppress the inability to read the pixel signal with high accuracy due to the presence or absence of the above voltage drop when the pixel signal is read out from the pixel.

[0079] Furthermore, the pixel array may further include a plurality of current sources for each column, the plurality of current sources flowing current into each of the N first vertical signal lines, and the imaging element may further include a control unit, the control unit controlling all of the plurality of current sources included in the pixel array, the control unit activating or deactivating current sources (1) to (3) among the plurality of current sources for each column of the pixel array, (1) activating a current source flowing current into the first vertical signal line included in a pixel group for performing readout, the pixel group for performing readout being a pixel group consisting of the K or more pixels that output pixel signals group, (2) making the current source that flows current into the first vertical signal line of the pixel group after the readout is performed, in the activated state for a certain period of time that continues after the K or more pixels included in the pixel group after the readout is performed finish outputting pixel signals, the pixel group after the readout is a pixel group composed of the K or more pixels that output pixel signals immediately before the K or more pixels in the pixel group performing the readout, and (3) making current sources other than the current source that flows current into the first vertical signal line of the pixel group performing the readout and the current source that flows current into the first vertical signal line of the pixel group after the readout is performed in the inactivated state.

[0080] Generally speaking, when a current source that flows a current into a vertical signal line of a certain column is changed from an active state to an inactive state, a negative influence is exerted on a current flowing into a vertical signal line of another column adjacent to the column. As a result, due to this negative influence, a pixel signal cannot be read accurately from a pixel connected to the vertical signal line of the other column.

[0081] In this regard, with the imaging element having the above configuration, even if there are pixels in other columns adjacent to the column that continue to read out pixel signals for a certain period after the completion of the readout of pixel signals from pixels included in the readout pixel group of a certain column, the current source that flows current into the first vertical signal line of the readout pixel group during the certain period can continue to maintain an activated state. Therefore, with the imaging element having the above configuration, even if there are pixels in other columns adjacent to the column that continue to read out pixel signals for a certain period after the completion of the readout of pixel signals from pixels included in the readout pixel group of a certain column, it is possible to suppress the inability to read out pixel signals from these pixels with high accuracy.

[0082] Furthermore, the pixel array may further include a plurality of current sources for each column, and the plurality of current sources flow current into a power wiring connected to the K or more pixels included in the pixel group for each of the N pixel groups, and the imaging element may further include a control unit for controlling the plurality of current sources included in the pixel array, and the control unit may activate, for each column of the pixel array, a current source among the plurality of current sources that flows current into the power wiring connected to the K or more pixels included in the post-readout pixel group for a certain period of time after the K or more pixels included in the post-readout pixel group finish outputting pixel signals, and may inactivate current sources other than the current source that flows current into the power wiring connected to the K or more pixels included in the post-readout pixel group, the post-readout pixel group being a pixel group consisting of the K or more pixels that output pixel signals immediately before the K or more pixels included in the readout pixel group, and the readout pixel group being a pixel group consisting of the K or more pixels that output pixel signals.

[0083] Generally speaking, a voltage difference occurs between the voltage of the power supply supplied to the pixel when no current flows in the power supply wiring connected to the pixel and the voltage of the power supply supplied to the pixel when current flows in the power supply wiring connected to the pixel. Furthermore, when a pixel signal is read from a pixel in a state where no voltage drop occurs and when a pixel signal is read from a pixel in a state where a voltage drop occurs, a difference occurs in the read pixel signal.

[0084] Furthermore, when a state where a current flows into a pixel in a certain column changes to a state where no current flows into the pixel, the voltage of the power supply wiring connected to the pixels in other columns adjacent to the column may change. As a result, due to this voltage change, the pixel signals of the pixels in other columns may not be read out with high accuracy.

[0085] In this regard, with the imaging element having the above configuration, even if there are pixels in other columns adjacent to a certain column that continue to read out pixel signals during a certain period after the completion of the readout of pixel signals from pixels included in the readout pixel group of a certain column, the power supply wiring connected to the pixels included in the readout pixel group of the certain column continues to flow current during the certain period. Therefore, with the imaging element having the above configuration, even if there are pixels in other columns adjacent to the column that continue to read out pixel signals during a certain period after the completion of the readout of pixel signals from pixels included in the readout pixel group of a certain column, it is possible to suppress the inability to read out pixel signals from these pixels with high accuracy.

[0086] It may also be that N is an even number greater than 4, and in each column of the pixel array, the N pixel groups include at least a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group, and the imaging element has a first switch and a second switch for each column of the pixel array, the first switch switches the first vertical signal line of the first pixel group and the first vertical signal line of the second pixel group to one of a conductive state and a non-conductive state, and the second switch switches the first vertical signal line of the third pixel group and the first vertical signal line of the fourth pixel group to one of a conductive state and a non-conductive state.

[0087] Accordingly, in each column, pixel signals can be mixed and read out from the first pixel included in the first pixel group and the first pixel included in the second pixel group, and pixel signals can be mixed and read out from the first pixel included in the third pixel group and the first pixel included in the fourth pixel group.

[0088] Furthermore, K may be an integer greater than 8, L may be an integer greater than 2 and less than K / 4, and each of the N pixel groups further comprises: a third vertical signal line connected to L or more third pixels among the K or more pixels, the L or more third pixels being different from the L or more first pixels and the L or more second pixels; and a fourth vertical signal line connected to L or more fourth pixels among the K or more pixels, the L or more fourth pixels being different from the L or more first pixels, the L or more second pixels, and the L or more third pixels, and the imaging element further comprises a plurality of pixel groups. Each column of the array is provided with: a plurality of third impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of third impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; a plurality of fourth impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of fourth impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; a third AD converter for performing AD conversion on the plurality of third impedance conversion signals output from the plurality of third impedance conversion circuits; and a fourth AD converter for performing AD conversion on the plurality of fourth impedance conversion signals output from the plurality of fourth impedance conversion circuits. The imaging element includes a first switch and a second switch for each column of the pixel array and each of the N pixel groups, the first switch switches the first vertical signal line and the third vertical signal line to one of a conducting state and a non-conducting state, and the second switch switches the second vertical signal line and the fourth vertical signal line to one of a conducting state and a non-conducting state, and in each column of the pixel array, each of the N third vertical signal lines included in the N pixel groups is connected to an input of any one of the plurality of third impedance conversion circuits, and an output of each of the plurality of third impedance conversion circuits is connected to the third An AD converter is connected, each of the N fourth vertical signal lines of the N pixel groups is connected to the input of any one of the plurality of fourth impedance conversion circuits, the output of each of the plurality of fourth impedance conversion circuits is connected to the fourth AD converter, the photoelectric conversion units of the L or more first pixels and the photoelectric conversion units of the L or more third pixels receive light of the first color transmitted through the first color filter, and the photoelectric conversion units of the L or more second pixels and the photoelectric conversion units of the L or more fourth pixels receive light of a second color different from the first color transmitted through the second color filter.

[0089] Thus, in each column and each pixel group, pixel signals from the first pixel and the third pixel receiving the first color light can be mixed and read out, and pixel signals from the second pixel and the fourth pixel receiving the second color light can be mixed and read out.

[0090] An imaging device according to one aspect of the present disclosure includes the above-mentioned imaging element.

[0091] As described above, the imaging element included in the imaging device having the above configuration can increase the speed of reading pixel signals from pixels while suppressing degradation in the quality of captured images.

[0092] Therefore, the imaging device having the above configuration can suppress degradation of the quality of the captured image and increase the speed of reading pixel signals from pixels.

[0093] An imaging element according to one embodiment of the present invention comprises: a pixel array in which pixels are arranged in a matrix, and the pixels have a photoelectric conversion unit that converts received light into electric charge; a pixel group composed of a plurality of pixels in the pixel array; a vertical signal line connected to at least one of the plurality of pixels in the pixel group; an impedance conversion circuit connected to the vertical signal line, the output impedance of the impedance conversion circuit being lower than the input impedance; and an AD converter connected to the impedance conversion circuit.

[0094] The image pickup element having the above-described structure can suppress degradation in the quality of captured images and increase the speed at which pixel signals are read from pixels.

[0095] The following describes a specific example of an imaging element and the like involved in one embodiment of the present invention with reference to the accompanying drawings. The embodiments shown here are all specific examples of the present invention. Therefore, the numerical values, shapes, components, configurations of components, connection methods, steps (processes), and the order of steps shown in the following embodiments are all examples, and the main purpose is not to limit the present invention. In addition, each figure is a schematic diagram, not a rigorous illustration. In each figure, substantially the same structure is given the same mark, and repeated descriptions are omitted or simplified.

[0096] (Implementation Method 1)

[0097] Next, an imaging element for capturing images will be described.

[0098] [constitute]

[0099] Figure 1 This is a perspective view showing the appearance of the image sensor 1 according to the first embodiment.

[0100] like Figure 1 As shown, the image pickup element 1 is formed by stacking a first semiconductor chip 11 and a second semiconductor chip 12 on each other.

[0101] Figure 2 is a plan view of the first semiconductor chip 11 .

[0102] exist Figure 2 In FIG. 1 , the components formed on the first semiconductor chip 11 are indicated by solid lines, and further, a part of the components formed on the second semiconductor chip 12 is indicated by dotted lines. That is, the first semiconductor chip 11 is only composed of Figure 2 It is formed by the components shown by solid lines.

[0103] Here, about Figure 2 The recorded positions of the components formed on the second semiconductor chip 12 represented by the dotted lines are positions where these components are projected onto the first semiconductor chip 11 in a direction perpendicular to the back side of the imaging element 1 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on each other.

[0104] like Figure 2 As shown, a pixel array 40 is formed on the first semiconductor chip 11 , in which a plurality of pixels 30 are arranged in a matrix.

[0105] Figure 3 is a plan view of the pixel array 40 .

[0106] like Figure 3 As shown, the pixel array 40 includes N (N is an integer greater than or equal to 3) pixel groups 100 (with Figure 3 The first pixel group 100A, the second pixel group 100B, the third pixel group 100C, and the fourth pixel group 100D correspond to each other), and each of the N pixel groups is composed of K (K is an integer greater than 2) or more pixels 30 arranged continuously in the column direction. Figure 3 As shown, the case where N is 4 is used for explanation, that is, the case where the N pixel groups 100 are the first pixel group 100A, the second pixel group 100B, the third pixel group 100C, and the fourth pixel group 100D is used for explanation. However, as long as N is an integer greater than 3, it is not necessarily limited to 4. Moreover, each of the pixel groups 100 is used for explanation herein to be composed of K pixels 30. However, it is not necessarily limited to the case where all the pixel groups 100 are composed of K pixels 30. For example, the first pixel group 100A may be composed of K pixels 30, the second pixel group 100B may be composed of K+1 pixels 30, the third pixel group 100C may be composed of K pixels 30, and the fourth pixel group 100D may be composed of K+2 pixels 30.

[0107] like Figure 3 As shown, each of the N pixel groups 100 includes a first vertical signal line 50 (connected to K pixels 30) connected to the first vertical signal line 50. Figure 3Corresponding to the first vertical signal line 50A, the first vertical signal line 50B, the first vertical signal line 50C, and the first vertical signal line 50D).

[0108] In each column of the pixel array 40 , the N first vertical signal lines 50 extend along the column direction of the pixel array 40 in a plan view of the image sensor 1 , and are arranged in the column direction of the pixel array 40 .

[0109] In each column of the pixel array 40, the first vertical signal line 50A has a node 2AA connected to a node (here, a node 2AB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the first vertical signal line 50A has the node 2AA located at the end of the first vertical signal line 50B side.

[0110] In each column of the pixel array 40, the first vertical signal line 50B has a node 2BA connected to a node (here, a node 2BB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the first vertical signal line 50B has the node 2BA located at the end of the first vertical signal line 50A side.

[0111] In each column of the pixel array 40, the first vertical signal line 50C has a node 2CA connected to a node (here, a node 2CB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the first vertical signal line 50C has the node 2CA located at the end on the first vertical signal line 50D side.

[0112] In each column of the pixel array 40, the first vertical signal line 50D has a node 2DA connected to a node (here, a node 2DB described later) on the second semiconductor chip 12 side. As a non-limiting example, the first vertical signal line 50D has the node 2DA located at the end on the first vertical signal line 50C side.

[0113] Figure 4 is a circuit diagram showing the configuration of the pixel 30 .

[0114] like Figure 4 As shown, the pixel 30 includes a photoelectric conversion unit 31 , a charge storage unit 32 , a transfer transistor 33 , a reset transistor 34 , an amplifier transistor 35 , a selection transistor 36 , and a power supply wiring 37 .

[0115] The pixel 30 is, for example, a back-illuminated pixel.

[0116] The photoelectric conversion unit 31 converts received light into electric charges. The photoelectric conversion unit 31 is realized by, for example, a photodiode.

[0117] The charge storage section 32 stores the charge converted by the photoelectric conversion section 31 .

[0118] The transfer transistor 33 transfers the charge converted by the photoelectric conversion section 31 to the charge storage section 32. The transfer transistor 33 is realized by, for example, a MOS transistor.

[0119] The reset transistor 34 resets the charge accumulated in the charge accumulation unit 32. The reset transistor 34 is realized by, for example, a MOS transistor.

[0120] The amplifier transistor 35 outputs a pixel signal according to the charge amount of the charges accumulated in the charge accumulation unit 32. The amplifier transistor 35 is realized by, for example, a MOS transistor.

[0121] The selection transistor 36 selects the pixel 30 that outputs the pixel signal to the first vertical signal line 50. The selection transistor 36 is realized by, for example, a MOS transistor.

[0122] The power supply wiring 37 is connected to the drain of the reset transistor 34 and the drain of the amplifier transistor 35 .

[0123] The power supply wiring 37 only needs to be connected to the drain of the amplifier transistor 35 and does not need to be connected to the drain of the reset transistor 34 . In this case, the drain of the reset transistor 34 is connected to another power supply wiring.

[0124] Figure 5 is a plan view of the second semiconductor chip 12 .

[0125] exist Figure 5 In FIG. 1 , the components formed on the second semiconductor chip 12 are indicated by solid lines, and further, the formation area of ​​the pixel array 40 in the first semiconductor chip 11 is indicated by dotted lines. That is, only the components formed in the second semiconductor chip 12 are indicated by solid lines. Figure 5 Components represented by solid lines.

[0126] Here, about Figure 5 The recorded position of the formation area of ​​the pixel array 40 represented by the dotted line in the figure is a position where the pixel array 40 is projected onto the second semiconductor chip 12 in a direction perpendicular to the front surface of the imaging element 1 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on each other.

[0127] like Figure 5 As shown, a readout circuit 60 , a control unit 70 , a vertical scanning circuit 80 , a reference current source 90 , and a signal processing circuit 200 are formed on the second semiconductor chip 12 .

[0128] like Figure 5 As shown, in a state where the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on each other, the pixel array 40 and the readout circuit 60 overlap each other in a plan view of the image pickup element 1 .

[0129] In addition, although the example in which the pixel array 40 and the readout circuit 60 overlap each other in a plan view of the imaging element 1 in a state where the first semiconductor chip 11 and the second semiconductor chip 12 are stacked is described here, the invention is not limited to the overlapping configuration.

[0130] Figure 6 is a plan view of the readout circuit 60 .

[0131] like Figure 6 As shown, the readout circuit 60 includes N first impedance conversion circuits 61 (connected to the first impedance conversion circuit 61) for each column of the pixel array 40. Figure 6 The first impedance conversion circuit 61A, the first impedance conversion circuit 61B, the first impedance conversion circuit 61C, and the first impedance conversion circuit 61D in the embodiment of the present invention correspond to each other), N current sources 62 (corresponding to the ... Figure 6 Corresponding to the current source 62A, the current source 62B, the current source 62C, and the current source 62D), the common signal line 63, and the first AD converter 64.

[0132] Furthermore, the readout circuit 60 has a node 2AB, a node 2BB, a node 2CB, and a node 2DB for each column of the pixel array 40 .

[0133] The first impedance conversion circuit 61 is an impedance conversion circuit having an output impedance lower than an input impedance, and receives as input a pixel signal output from at least one of the plurality of pixels 30 included in a corresponding column of the pixel array 40 .

[0134] As a non-limiting example, the first impedance conversion circuit 61 is described as a buffer.

[0135] Figure 7 2 is a circuit diagram showing an example of the configuration of the first impedance conversion circuit 61 .

[0136] like Figure 7 As shown, the first impedance conversion circuit 61 has an output transistor 641 and a switch 642 .

[0137] In addition, the first impedance conversion circuit 61 may be formed of a circuit having an amplification function.

[0138] The output transistor 641 is a MOS transistor having a gate connected to an input and a drain connected to an output via a switch 642. The output transistor 641 has a higher driving capability than the amplifier transistor 35.

[0139] The first impedance conversion circuit 61 has a function of setting the output to high impedance. That is, the first impedance conversion circuit 61 can set the output to high impedance by making the switch 642 non-conductive.

[0140] Here, setting the output to high impedance means that, in a state where the output of the first impedance conversion circuit 61 on one side is short-circuited with the output of the first impedance conversion circuit 61 on the other side, the impedance of the output of the first impedance conversion circuit 61 on one side is made higher than the output of the first impedance conversion circuit 61 on the other side which does not perform the function of setting the output to high impedance.

[0141] In addition, when the first impedance conversion circuit 61 has the above-mentioned structure, a current source for driving the first impedance conversion circuit 61 is connected to the common signal line 63 .

[0142] Return to Figure 6 The description of the readout circuit 60 continues.

[0143] like Figure 6 as well as Figure 3 As shown, the input of the first impedance conversion circuit 61A is connected to the first vertical signal line 50A in the corresponding column of the pixel array 40 via nodes 2AB and 2AA, the input of the first impedance conversion circuit 61B is connected to the first vertical signal line 50B in the corresponding column of the pixel array 40 via nodes 2BB and 2BA, the input of the first impedance conversion circuit 61C is connected to the first vertical signal line 50C in the corresponding column of the pixel array 40 via nodes 2CB and 2CA, and the input of the first impedance conversion circuit 61D is connected to the first vertical signal line 50D in the corresponding column of the pixel array 40 via nodes 2DB and 2DA.

[0144] The outputs of the N first impedance conversion circuits 61 are connected to a first AD converter 64 via a common signal line 63 .

[0145] Here, in each column of the pixel array 40, regarding the positions of the first impedance conversion circuit 61A and the first impedance conversion circuit 61B in the plan view of the imaging element 1, when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on each other, in the plan view of the pixel array 40, they are located between the first vertical signal line 50A and the first vertical signal line 50B in the column direction of the pixel array 40.

[0146] Accordingly, in each column of the pixel array 40 , the distance from the first vertical signal line 50A to the first impedance conversion circuit 61A and the distance from the first vertical signal line 50B to the first impedance conversion circuit 61B become relatively short.

[0147] In addition, although the positions of the first impedance conversion circuit 61A and the first impedance conversion circuit 61B in the plan view of the imaging element 1 are described as being between the first vertical signal line 50A and the first vertical signal line 50B in the column direction of the pixel array 40 in the plan view of the pixel array 40 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on each other, the position is not limited to the configuration of being between the first vertical signal line 50A and the first vertical signal line 50B in the column direction of the pixel array 40.

[0148] Furthermore, in each column of the pixel array 40, with respect to the positions of the first impedance conversion circuit 61C and the first impedance conversion circuit 61D in the plan view of the imaging element 1, when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on each other, in the plan view of the pixel array 40, they are located between the first vertical signal line 50C and the first vertical signal line 50D in the column direction of the pixel array 40.

[0149] Accordingly, in each column of the pixel array 40 , the distance from the first vertical signal line 50C to the first impedance conversion circuit 61C and the distance from the first vertical signal line 50D to the first impedance conversion circuit 61D are relatively short.

[0150] In addition, although the positions of the first impedance conversion circuit 61C and the first impedance conversion circuit 61D in the plan view of the imaging element 1 are described as being between the first vertical signal line 50C and the first vertical signal line 50D in the column direction of the pixel array 40 in the plan view of the pixel array 40 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on each other, the position is not limited to the configuration of being between the first vertical signal line 50C and the first vertical signal line 50D in the column direction of the pixel array 40.

[0151] Furthermore, in each column of the pixel array 40, the common signal line 63 extends in the column direction of the pixel array 40 in the plan view of the imaging element 1. Therefore, in the plan view of the imaging element 1, the existence range of the common signal line 63 in the column direction of the pixel array 40 is included in the existence range of the N first vertical signal lines 50 in the column direction of the pixel array 40, and the wiring length of the common signal line 63 is smaller than the total wiring length of the N first vertical signal lines 50.

[0152] This can suppress unnecessary growth of the common signal lines 63 in each column of the pixel array 40 .

[0153] The first AD converter 64 performs AD conversion on each of the first impedance conversion signals output from the N first impedance conversion circuits 61 .

[0154] Here, in each column of the pixel array 40 , the first AD converter 64 is located between the first impedance conversion circuit 61A and the first impedance conversion circuit 61B and the first impedance conversion circuit 61C and the first impedance conversion circuit 61D in a plan view of the pixel array 40 .

[0155] Accordingly, in each column of the pixel array 40 , the distance from the first impedance conversion circuit 61A and the first impedance conversion circuit 61B to the first AD converter 64 and the distance from the first impedance conversion circuit 61C and the first impedance conversion circuit 61D to the first AD converter 64 become relatively short.

[0156] In addition, although the first AD converter 64 is described here as being located between the first impedance conversion circuit 61A and the first impedance conversion circuit 61B and the first impedance conversion circuit 61C and the first impedance conversion circuit 61D in the plan view of the pixel array 40, it is not limited to the structure of being located between the first impedance conversion circuit 61A and the first impedance conversion circuit 61B and the first impedance conversion circuit 61C and the first impedance conversion circuit 61D.

[0157] The current source 62 forms a reference current source 90 and a current mirror circuit to be described later, and causes a current defined by a current flowing into the reference current source 90 to flow.

[0158] like Figure 6 As shown, the current source 62A is connected to the first vertical signal line 50A (see FIG. 1 ) in the corresponding column of the pixel array 40 via the node 2AA and the node 2AB. Figure 3 ) is connected, the current source 62B is connected to the first vertical signal line 50B in the corresponding column of the pixel array 40 via the node 2BA and the node 2BB (refer to Figure 3 ) is connected, the current source 62C is connected to the first vertical signal line 50C in the corresponding column of the pixel array 40 via the node 2CA and the node 2CB (refer to Figure 3 ) is connected, the current source 62D is connected to the first vertical signal line 50D (refer to Figure 3 )connect.

[0159] Return to Figure 5 , the second semiconductor chip 12 is further described.

[0160] The vertical scanning circuit 80 outputs a vertical scanning signal for controlling the pixels 30 located in each row of the pixel array 40 .

[0161] The reference current source 90 is a current source that forms each of the plurality of current sources 62 included in the readout circuit 60 and the current mirror circuit, and uniformly regulates the currents flowing into all the current sources 62 included in the readout circuit 60 .

[0162] In addition, although the reference current source 90 is described here as a current source constituting each of the plurality of current sources 62 and the current mirror circuit included in the readout circuit 60, it is not limited to being a current source constituting each of the plurality of current sources 62 and the current mirror circuit included in the readout circuit 60 as long as it is a current source constituting each of at least two current sources 62 and the current mirror circuit included in the readout circuit 60. In this case, the reference current source 90 uniformly regulates the currents flowing into at least the two current sources 62.

[0163] The signal processing circuit 200 generates an image based on a plurality of AD conversion signals output from a plurality of first AD converters 64 included in the readout circuit 60 .

[0164] The control unit 70 controls the readout circuit 60 , the vertical scanning circuit 80 , the reference current source 90 , and the signal processing circuit 200 .

[0165] Figure 8 This is a timing chart showing how the control unit 70 controls the corresponding current source 62 and the like in each column of the pixel array 40 to flow current into the first vertical signal line 50 in order to read pixel signals from each pixel 30 of the pixel array 40 .

[0166] exist Figure 8 In the top timing diagram, the vertical axis is the current flowing into the first vertical signal line 50A, and the horizontal axis is time. The vertical axis of the second timing diagram from the top is the current flowing into the first vertical signal line 50B, and the horizontal axis is time. The vertical axis of the third timing diagram from the top is the current flowing into the first vertical signal line 50C, and the horizontal axis is time. The vertical axis of the fourth timing diagram from the top is the current flowing into the first vertical signal line 50D, and the horizontal axis is time.

[0167] like Figure 8 As shown, the control unit 70 activates the current source 62 that flows current into the first vertical signal line 50 of the pixel group 100 composed of pixels 30 that output pixel signals, i.e., the pixel group that performs readout, for each column of the pixel array 40. That is, by making the current flow, the current of the first current amount flows into the first vertical signal line 50 of the pixel group that performs readout, and makes the other current sources 62 inactive, that is, by making the current not flow, the current does not flow into the first vertical signal line 50 of the pixel group 100 other than the pixel group that performs readout.

[0168] The control unit 70 controls the current source 62 as described above, and thus the power consumption of the image sensor 1 is suppressed compared to the case where the current of the first current amount flows into all the first vertical signal lines 50 .

[0169] <Inspection>

[0170] According to the imaging element 1 of the above configuration, in each column of the pixel array 40, the plurality of pixels 30 in the column are connected to any one of the N first vertical signal lines 50 divided into N. Accordingly, according to the imaging element 1 of the above configuration, compared with a configuration in which the plurality of pixels 30 in the column are connected to one vertical signal line in each column of the pixel array 40, the wiring capacity of each first vertical signal line 50 is reduced compared with the wiring capacity of one vertical signal line, and the number of pixels 30 connected to each first vertical signal line 50 as a load is reduced compared with the number of pixels connected to one vertical signal line as a load, thereby making it possible to increase the speed of reading pixel signals from the pixels 30.

[0171] Furthermore, with the imaging element 1 having the above configuration, each of the N first vertical signal lines 50 is connected to one first AD converter 64 via any one of the plurality of first impedance conversion circuits 61 in each column of the pixel array 40. Accordingly, with the imaging element 1 having the above configuration, the characteristic difference that may occur due to the plurality of AD converters is not reflected between the pixel signals read out from the pixels 30 connected to the first vertical signal lines 50 that are different from each other, as compared with a configuration in which each of the N first vertical signal lines 50 is connected to each of the plurality of AD converters in each column of the pixel array 40. Therefore, with the imaging element 1 having the above configuration, the image quality of the image captured by the imaging element is suppressed from being deteriorated due to the characteristic difference that occurs in the plurality of AD converters in each column of the pixel array 40.

[0172] As described above, the image sensor 1 having the above-described structure can increase the speed of reading pixel signals from the pixels 30 while suppressing degradation in the quality of captured images.

[0173] In addition, in the first embodiment, although Figure 8 As shown in FIG. 1 , the control unit 70 controls the current source 62 and the like. However, the control unit 70 may also be configured as described later. Fig. 9 The current source 62 and the like may be controlled as shown, or as described later. Fig.10 The current source 62 and the like can also be controlled as described later. Fig.11 The current source 62 and the like are controlled as shown.

[0174] Fig. 9This is a timing chart showing how the control unit 70 controls the corresponding current source 62 and the like for each column of the pixel array 40 to flow current into the first vertical signal line 50 in order to read pixel signals from each pixel 30 of the pixel array 40 .

[0175] exist Fig. 9 In the top timing diagram, the vertical axis is the current flowing into the first vertical signal line 50A, and the horizontal axis is time. The vertical axis of the second timing diagram from the top is the current flowing into the first vertical signal line 50B, and the horizontal axis is time. The vertical axis of the third timing diagram from the top is the current flowing into the first vertical signal line 50C, and the horizontal axis is time. The vertical axis of the fourth timing diagram from the top is the current flowing into the first vertical signal line 50D, and the horizontal axis is time.

[0176] like Fig. 9 As shown, the control unit 70 puts, for each column of the pixel array 40, a current source 62 that flows current into a pixel group 100 composed of pixels 30 that output pixel signals, i.e., a first vertical signal line 50 of a pixel group that performs readout, into a first activation state, that is, into a state in which a current of a first current amount flows, thereby causing a current of the first current amount to flow into the first vertical signal line 50 of the pixel group that performs readout, and puts other current sources 62 into a second activation state, that is, into a state in which a current of a second current amount that is less than the first current amount flows, thereby causing a second current to flow into the first vertical signal line of a pixel group 100 other than the pixel group that performs readout.

[0177] By controlling the current source 62 as described above, the control unit 70 reduces the power consumption of the image sensor 1 compared to the case where the current of the first current amount flows into all the first vertical signal lines 50 .

[0178] Fig.10 This is a timing chart showing how the control unit 70 controls the corresponding current source 62 and the like for each column of the pixel array 40 to flow current into the first vertical signal line 50 in order to read pixel signals from each pixel 30 of the pixel array 40 .

[0179] exist Fig.10 In the top timing diagram, the vertical axis is the current flowing into the first vertical signal line 50A, and the horizontal axis is time. The vertical axis of the second timing diagram from the top is the current flowing into the first vertical signal line 50B, and the horizontal axis is time. The vertical axis of the third timing diagram from the top is the current flowing into the first vertical signal line 50C, and the horizontal axis is time. The vertical axis of the fourth timing diagram from the top is the current flowing into the first vertical signal line 50D, and the horizontal axis is time.

[0180] like Fig.10As shown, the control unit 70, for each column of the pixel array 40, (1) activates the current source 62 that flows current into the first vertical signal line 50 of the pixel group 100 composed of the pixels 30 that output pixel signals, i.e., the pixel group that performs readout, i.e., makes the current flow so that the current of the first current amount flows into the first vertical signal line 50 of the pixel group that performs readout, and (2) causes the current source 62 that flows current into the first vertical signal line 50 of the pixel group 100 composed of the pixels 30 that output pixel signals after the pixels 30 included in the pixel group that performs readout, i.e., the pixel group before readout begins to perform readout. The first vertical signal line 50 of the pixel group before the readout is executed is activated before the output of the row pixel signal, thereby causing the current of the first current to flow into the first vertical signal line 50 of the pixel group before the readout is executed before the pixel 30 included in the pixel group before the readout is executed starts to output the pixel signal, (3) except for the current source 62 that causes the current to flow into the first vertical signal line 50 of the pixel group for executing the readout and the current source 62 that causes the current to flow into the first vertical signal line 50 of the pixel group before the readout is executed, the current sources 62 are in an inactive state, that is, by becoming a state in which the current is not allowed to flow, no current flows into the first vertical signal line 50 of the pixel group 100 other than the pixel group for executing the readout and the pixel group before the readout is executed.

[0181] By controlling the current source 62 as described above, the control unit 70 reduces the power consumption of the image sensor 1 compared to the case where the current of the first current amount flows into all the first vertical signal lines 50 .

[0182] Furthermore, generally speaking, immediately after the current source 62 is changed from the inactive state to the active state, when a pixel signal is read from the pixel 30 using the first vertical signal line 50 into which a current flows from the current source 62 , the pixel signal may not be read with high accuracy.

[0183] In response to this, the control unit 70 controls the current source 62 as described above, so that in each column of the pixel array 40, the current source 62 that flows current into the first vertical signal line 50 of the pixel group before the read-out is performed is changed from an inactive state to an active state before the pixels 30 included in the pixel group before the read-out starts to output pixel signals.

[0184] Therefore, when the control unit 70 controls the current source 62 as described above to read the pixel signal from the pixel 30 , it is possible to suppress the situation where the pixel signal cannot be read with high accuracy.

[0185] Fig.11This is a timing chart showing how the control unit 70 controls the corresponding current source 62 and the like for each column of the pixel array 40 to flow current into the first vertical signal line 50 in order to read pixel signals from each pixel 30 of the pixel array 40 .

[0186] exist Fig.11 In the top timing diagram, the vertical axis is the current flowing into the first vertical signal line 50A, and the horizontal axis is time. The vertical axis of the second timing diagram from the top is the current flowing into the first vertical signal line 50B, and the horizontal axis is time. The vertical axis of the third timing diagram from the top is the current flowing into the first vertical signal line 50C, and the horizontal axis is time. The vertical axis of the fourth timing diagram from the top is the current flowing into the first vertical signal line 50D, and the horizontal axis is time.

[0187] like Fig.11 As shown, the control unit 70, for each column of the pixel array 40, (1) activates the current source 62 that flows current into the first vertical signal line 50 of the pixel group 100 composed of the pixels 30 that output pixel signals, i.e., the pixel group that performs readout, i.e., makes the current of the first current amount flow into the first vertical signal line 50 of the pixel group that performs readout by making the current flow, and (2) causes the current source 62 to flow current into the first vertical signal line 50 of the pixel group 100 composed of the pixels 30 that output pixel signals immediately before the pixels 30 included in the pixel group that performs readout, i.e., the pixel group after the readout ends the output of the pixel signals. (3) the current sources 62 other than the current source 62 that flows the current into the first vertical signal line 50 of the pixel group after the readout is performed and the current source 62 that flows the current into the first vertical signal line 50 of the pixel group after the readout is performed are in an inactive state, that is, by becoming a state in which the current is not allowed to flow, no current flows into the first vertical signal line 50 of the pixel group 100 other than the pixel group 100 that executes the readout and the pixel group after the readout is performed.

[0188] By controlling the current source 62 as described above by the control unit 70 , the power consumption of the image sensor 1 is suppressed compared to the case where the current of the first current amount flows into all the first vertical signal lines 50 .

[0189] Furthermore, generally, when the current source 62 that flows current into the first vertical signal line 50 of a certain column of the pixel array 40 is changed from an active state to an inactive state, it will have an adverse effect on the current flowing into the first vertical signal line 50 of other columns adjacent to the column. Therefore, due to this adverse effect, it may be impossible to read pixel signals from the pixels 30 connected to the first vertical signal lines 50 of other columns with high accuracy.

[0190] In this regard, the control unit 70 controls the current source 62 as described above. Even if the reading of the pixel signal of the pixel 30 included in the read-out pixel group from a certain column of the pixel array 40 is completed, when there are pixels 30 in other columns adjacent to the column that continue to read the pixel signal, the current source 62 that flows the current into the first vertical signal line 50 of the read-out pixel group will remain activated during the certain period.

[0191] Therefore, by controlling the current source 62 as described above by the control unit 70, even if there are pixels 30 in other columns adjacent to the column that continue to read out pixel signals during a certain period after the reading out of the pixel signals of the pixels 30 included in the pixel group that performs the read-out operation in a certain column of the pixel array 40 is completed, it is possible to suppress the inability to read out the pixel signals from these pixels 30 with high accuracy.

[0192] (Variant 1)

[0193] An imaging device according to Modification 1 will be described below. The configuration of Modification 1 is obtained by partially changing the configuration of the imaging device 1 according to Embodiment 1.

[0194] Since the same components as those of the image sensor 1 according to the first embodiment have already been described, the same reference numerals are given and detailed description thereof is omitted. Hereinafter, the modification 1 will be described mainly focusing on the differences from the image sensor 1 .

[0195] The configuration of the image sensor according to Modification 1 is different from that of the image sensor 1 according to Embodiment 1 in that the readout circuit 60 is changed to the readout circuit according to Modification 1.

[0196] Fig.12 2 is a plan view of a readout circuit 60A according to Modification 1.

[0197] like Fig.12 As shown, the readout circuit 60A is different from the readout circuit 60 according to the first embodiment in that the first impedance conversion circuit 61B and the first impedance conversion circuit 61D are deleted and switches 65A and 65B are added for each column of the pixel array 40 .

[0198] The switch 65A selectively switches the input of the first impedance conversion circuit 61A to connect either the node 2AB or the node 2BB.

[0199] The switch 65B selectively switches the input of the first impedance conversion circuit 61C to connect either the node 2CB or the node 2DB.

[0200] <Inspection>

[0201] With the imaging element according to the first variation configured as described above, in each column of the pixel array 40, the first vertical signal lines 50A and the first vertical signal lines 50B included in the first pixel group 100A and the second pixel group 100B adjacent to each other in the column direction can share a first impedance conversion circuit 61A.

[0202] Furthermore, with the imaging element according to the first variant of the above-described structure, in each column of the pixel array 40, the first vertical signal line 50C and the first vertical signal line 50D of the third pixel group 100C and the fourth pixel group 100D adjacent to each other in the column direction can share a first impedance conversion circuit 61B.

[0203] (Variant 2)

[0204] An imaging device according to Modification 2 will be described below. The imaging device according to Modification 2 is a device in which a part of the configuration is changed from that of the imaging device according to Modification 1.

[0205] The components identical to those of the imaging element according to variant example 1 have already been described and are therefore given the same reference numerals and detailed descriptions thereof are omitted. The imaging element according to variant example 2 will be described below, focusing on the differences from the imaging element according to variant example 1.

[0206] The configuration of the imaging element according to Modification 2 is different from that of the imaging element according to Modification 1 in that the readout circuit 60A is changed to the readout circuit according to Modification 2.

[0207] Fig.13 2 is a plan view of a readout circuit 60B according to Modification 2.

[0208] like Fig.13 As shown, the readout circuit 60B is different from the readout circuit 60A according to the first modification in that the common signal line 63 is deleted and a first common signal line 631 , a second common signal line 632 , and a switch 66 are added for each column of the pixel array 40 .

[0209] The output of the first impedance conversion circuit 61A is connected to one input of the switch 66 via the first common signal line 631 , and the output of the first impedance conversion circuit 61C is connected to the other input of the switch 66 via the second common signal line 632 .

[0210] The switch 66 selectively switches the input of the first AD converter 64 to one of the first common signal line 631 and the second common signal line 632 for connection.

[0211] <Inspection>

[0212] According to the imaging element of Modification 2 having the above configuration, the load capacity driven by the output of the first impedance conversion circuit 61A and the load capacity driven by the output of the first impedance conversion circuit 61C can be reduced in each column of the pixel array 40, compared with the imaging element of Modification 1. Therefore, according to the imaging element of Modification 2, the speed of reading pixel signals from the pixels 30 can be further increased.

[0213] (Variant 3)

[0214] An imaging device according to Modification 3 will be described below. The imaging device according to Modification 3 is one in which a part of the configuration is changed from that of the imaging device 1 according to Embodiment 1.

[0215] Since the same components as those of the imaging device 1 according to the first embodiment have already been described, the same reference numerals are given and detailed description thereof is omitted. The imaging device according to the third modification will be described below, focusing on the differences from the imaging device 1 .

[0216] The difference between the imaging element involved in variant example 3 and the imaging element 1 involved in embodiment 1 is that the pixel 30 is changed to the pixel involved in variant example 3, the pixel array 40 is changed to the pixel array involved in variant example 3, the readout circuit 60 is changed to the readout circuit involved in variant example 3, and the control unit 70 is changed to the control unit involved in variant example 3.

[0217] Fig.14 4 is a plan view of a pixel array 40C according to Modification 3.

[0218] like Fig.14 As shown, the pixel array 40C is different from the pixel array 40 according to the first embodiment in that each of the N pixel groups 100 is changed into N pixel groups 101 (with Fig.14 The first pixel group 101A, the second pixel group 101B, the third pixel group 101C, and the fourth pixel group 101D correspond to each other).

[0219] Each of the N pixel groups 101 is different from each of the N pixel groups 100 in that the pixel 30 is changed to a pixel 30C and a power supply wiring 51 (which is the same as the power supply wiring 51) is added. Fig.14 The power supply wiring 51A, the power supply wiring 51B, the power supply wiring 51C, and the power supply wiring 51D correspond to each other).

[0220] Fig.15 : is a circuit diagram showing the configuration of a pixel 30C according to Modification 3.

[0221] like Fig.15 As shown, in the configuration of the pixel 30C, the power supply wiring 37 according to the first embodiment is changed to a power supply wiring 37D.

[0222] The power supply wiring 37D is connected to the power supply wiring 51 included in the pixel group 100 including the pixel 30C.

[0223] Return to Fig.14 , the description of pixel array 40C is continued.

[0224] In each column of the pixel array 40C, the power supply wiring 51A is connected to the power supply wiring 37D of the pixel 30C included in the first pixel group 100A and has a node 2AC connected to a node on the second semiconductor chip 12 side (here, a node 2AD described later).

[0225] In each column of the pixel array 40C, the power supply wiring 51B is connected to the power supply wiring 37D of the pixel 30C included in the second pixel group 100B and has a node 2BC connected to a node on the second semiconductor chip 12 side (here, a node 2BD described later).

[0226] In each column of the pixel array 40C, the power supply wiring 51C is connected to the power supply wiring 37D of the pixel 30C included in the third pixel group 100C and has a node 2CC connected to a node on the second semiconductor chip 12 side (here, a node 2CD described later).

[0227] In each column of the pixel array 40C, the power supply wiring 51D is connected to the power supply wiring 37D of the pixel 30C included in the fourth pixel group 100D and has a node 2DC connected to a node (here, a node 2DD described later) on the second semiconductor chip 12 side.

[0228] Fig.16 2 is a plan view of a readout circuit 60C according to Modification 3.

[0229] like Fig.16As shown, the readout circuit 60C is different from the readout circuit 60 involved in embodiment 1 in that switches 67A, 67B, 67C, 67D, nodes 2AD, 2BD, 2CD, and 2DD are added for each column of the pixel array 40.

[0230] The switch 67A selectively switches the input of the first impedance conversion circuit 61A and the current source 62A to either the node 2AB or the node 2AD for connection.

[0231] The switch 67B selectively switches the input of the first impedance conversion circuit 61B and the current source 62B to either the node 2BB or the node 2BD for connection.

[0232] The switch 67C selectively switches the input of the first impedance conversion circuit 61C and the current source 62C to either the node 2CB or the node 2CD for connection.

[0233] The switch 67D selectively switches the input of the first impedance conversion circuit 61D and the current source 62D to either the node 2DB or the node 2DD for connection.

[0234] The control unit involved in variant example 3 makes the current source 62 that flows current into the power wiring 51 connected to the pixel 30C included in the pixel group before read execution be activated before the pixel 30C included in the pixel group before read execution starts to output the pixel signal for each column of the pixel array 40, thereby flowing current into the power wiring 37 of the pixel 30C included in the pixel group before read execution before the pixel 30C included in the pixel group before read execution starts to output the pixel signal. The pixel group before read execution is a pixel group 100 composed of pixels 30C that output pixel signals after the pixel 30C included in the pixel group for read execution, and the pixel group for read execution is a pixel group 100 composed of pixels 30C that output pixel signals. By making other current sources 62 in an inactive state, no current other than the current that flows when the pixel 30C is working will flow into the power wiring 37 of the pixel 30C included in the pixel group 100 other than the pixel group before read execution.

[0235] Here, activating the current source 62 that flows a current into the power supply wiring 51 means controlling the switch 67 connected to the current source 62 to connect the corresponding power supply wiring 51 to the current source 62 .

[0236] Here, to deactivate the current source 62 that flows current into the power supply wiring 51 means to control the switch 67 connected to the current source 62 so that the corresponding power supply wiring 51 is not connected to the current source 62 .

[0237] <Inspection>

[0238] Generally speaking, a voltage difference occurs between the voltage of the power supply supplied to the pixel 30C in a state where no current flows into the power supply wiring 51 connected to the pixel 30C and the voltage of the power supply supplied to the pixel 30C in a state where current flows into the power supply wiring 51 connected to the pixel 30C, and the voltage difference is a voltage generated by a voltage drop generated according to the amount of current flowing in. Furthermore, when a pixel signal is read out from the pixel 30C in a state where no voltage drop occurs and when a pixel signal is read out from the pixel 30C in a state where a voltage drop occurs, a difference occurs in the read pixel signal.

[0239] In this regard, in the imaging element according to the above-mentioned modification example 3, in each column, in the power supply wiring 51 connected to the pixel 30C included in the pixel group before the readout is performed, current begins to flow before the pixel 30C included in the pixel group before the readout is performed starts to output the pixel signal. Therefore, in the imaging element according to the above-mentioned modification example 3, in each column, the pixel 30C included in the pixel group before the readout is performed has a voltage drop in advance when it starts to output the pixel signal. Therefore, in the case of reading the pixel signal from the pixel 30C, the inability to read the pixel signal with high accuracy due to the presence or absence of the above-mentioned voltage drop can be suppressed.

[0240] In addition, in Modification 3, the control unit according to Modification 3 may perform the following operation instead of the above-mentioned operation.

[0241] That is, the control unit involved in variant example 3 makes the current source 62 that flows current into the power wiring 51 connected to the pixel 30C included in the pixel group after the read-out execution, for each column of the pixel array 40, be in an activated state for a certain period of time after the pixel 30C included in the pixel group after the read-out execution finishes outputting the pixel signal, thereby making current flow into the power wiring 37 of the pixel 30C included in the pixel group after the read-out execution for a certain period of time after the pixel 30C included in the pixel group after the read-out execution finishes outputting the pixel signal, the pixel group after the read-out execution is a pixel group 100 composed of pixels 30C that output pixel signals immediately before the pixel 30C included in the pixel group for executing the read-out, and the pixel group for executing the read-out is a pixel group 100 composed of pixels 30C that output pixel signals, and by making other current sources 62 in an inactive state, no current other than the current that flows when the pixel 30C is working will flow into the power wiring 37 of the pixel 30C included in the pixel group 100 other than the pixel group after the read-out execution.

[0242] Generally speaking, when a state in which a current flows into a pixel 30C in a certain column changes to a state in which a current does not flow into the pixel 30C, the voltage of the power supply wiring 51 connected to the pixel 30C in another column adjacent to the column changes. As a result, due to the change in voltage, pixel signals may not be read accurately from the pixel 30C included in the other column.

[0243] In this regard, with the imaging element according to the third modification having the above configuration, even if there are pixels 30C in other columns adjacent to the column that continue to read out pixel signals during a certain period after the completion of the readout of pixel signals from the pixels 30C included in the readout pixel group of a certain column, the power supply wiring connected to the pixels 30C included in the readout pixel group of the certain column can maintain a state in which current continues to flow during the certain period. Therefore, with the imaging element according to the third modification having the above configuration, even if there are pixels 30C in other columns adjacent to the column that continue to read out pixel signals during a certain period after the completion of the readout of pixel signals from the pixels 30C included in the readout pixel group of a certain column, it is possible to suppress the inability to read out pixel signals from these pixels 30C with high accuracy.

[0244] (Variant 4)

[0245] An imaging device according to Modification 4 will be described below. The imaging device according to Modification 4 has a partially modified configuration compared to the imaging device according to Modification 2.

[0246] Regarding the components of the imaging element involved in variant example 4 that are the same as those of the imaging element involved in variant example 2, since they have already been described, they are given the same marks and detailed descriptions are omitted, and the description focuses on the differences from the imaging element involved in variant example 2.

[0247] The imaging element according to Modification 4 is different in configuration from the imaging element according to Modification 2 in that the readout circuit 60B is changed to the readout circuit according to Modification 4.

[0248] Fig.17 2 is a plan view of a readout circuit 60D according to Modification 4.

[0249] like Fig.17 As shown, the readout circuit 60D is configured in such a way that a switch 68A and a switch 68B are added for each column of the pixel array 40 , compared to the readout circuit 60B according to the second modification.

[0250] The switch 68A switches the node 2AB and the node 2BB to either a conducting state or a non-conducting state. That is, the switch 68A switches the first vertical signal line 50A of the first pixel group 100A and the first vertical signal line 50B of the second pixel group 100B to either a conducting state or a non-conducting state.

[0251] The switch 68B switches the node 2CB and the node 2DB to either a conducting state or a non-conducting state. That is, the switch 68B switches the first vertical signal line 50C of the third pixel group 100C and the first vertical signal line 50D of the fourth pixel group 100D to either a conducting state or a non-conducting state.

[0252] <Inspection>

[0253] Through the imaging element involved in the variant example 4 constructed as described above, in each column of the pixel array 40, pixel signals from the pixels 30 included in the first pixel group 100A and the pixels 30 included in the second pixel group 100B can be mixed and read out, and pixel signals from the pixels 30 included in the third pixel group 100C and the pixels 30 included in the fourth pixel group 100D can be mixed and read out.

[0254] (Implementation Method 2)

[0255] An imaging device according to a second embodiment will be described below. The imaging device according to the second embodiment is different from the imaging device 1 according to the first embodiment in that a part of the configuration is changed.

[0256] Since the same components of the imaging device according to the second embodiment as those of the imaging device 1 according to the first embodiment have already been described, the same reference numerals are given and detailed description is omitted. The following description will focus on the differences from the imaging device 1.

[0257] The imaging element according to the second embodiment differs from the imaging element 1 according to the first embodiment in that the pixel array 40 is changed to the pixel array according to the second embodiment and the readout circuit 60 is changed to the readout circuit according to the second embodiment.

[0258] Fig.18 It is a plan view of a pixel array 40E according to the second embodiment.

[0259] like Fig.18 As shown, the pixel array 40E is formed by arranging a plurality of pixels 30 in a matrix.

[0260] like Fig.18 As shown, the pixel array 40E includes N (N is an integer greater than or equal to 3) pixel groups 110 (with Fig.18 Each of the N pixel groups 110 is composed of K (K is an integer greater than 4) or more pixels 30 arranged continuously in the column direction. Fig.18 As shown, the case where N is 4 is used for explanation, that is, the N pixel groups 110 are the first pixel group 110A, the second pixel group 110B, the third pixel group 110C, and the fourth pixel group 110D. However, as long as N is an integer greater than 3, it does not need to be limited to 4. Moreover, each group of pixel groups 110 is illustrated as being composed of K pixels 30. However, not all pixel groups 110 are composed of K pixels 30, and there is no need to limit their composition. For example, the first pixel group 110A may be composed of K pixels 30, the second pixel group 110B may be composed of K+1 pixels 30, the third pixel group 110C may be composed of K pixels 30, and the fourth pixel group 110D may be composed of K+2 pixels 30.

[0261] like Fig.18 As shown, each of the N pixel groups 110 includes M (M is an integer greater than 2 and less than K / 2) vertical signal lines, and the M vertical signal lines include the first vertical signal lines 55A (connected to L or more pixels 30 (L is an integer greater than 2 and less than K / 2) among the K pixels 30). Fig.18 ), and a second vertical signal line 55B (corresponding to the first vertical signal line 55AA, the first vertical signal line 55AB, the first vertical signal line 55AC, and the first vertical signal line 55AD connected to the other L or more pixels 30 among the K pixels 30. Fig.18 Corresponding to the second vertical signal line 55BA, the second vertical signal line 55BB, the second vertical signal line 55BC, and the second vertical signal line 55BD).

[0262] Here, although the N pixel groups 110 are described as each having M vertical signal lines including a first vertical signal line 55A, a second vertical signal line 55B, a third vertical signal line 55C, and an Mth vertical signal line 55M, the M vertical signal lines of each of the N pixel groups 110 only need to include at least two vertical signal lines, the first vertical signal line 55A and the second vertical signal line 55B.

[0263] Here, the example in which each of the first vertical signal line 55A, the second vertical signal line 55B, the third vertical signal line 55C, and the M-th vertical signal line 55M is connected to L pixels 30 is used for explanation. However, as long as each of the first vertical signal line 55A, the second vertical signal line 55B, the third vertical signal line 55C, and the M-th vertical signal line 55M is connected to L or more pixels 30, it is not necessary to have the first vertical signal line 55A, the second vertical signal line 55B, the third vertical signal line 55C, and the M-th vertical signal line 55M all connected to L pixels 30, and the configuration is not limited. For example, the first vertical signal line 55A may be connected to L pixels 30, the second vertical signal line 55B may be connected to L+1 pixels 30, the third vertical signal line 55C may be connected to L pixels 30, and the M-th vertical signal line 55M may be connected to L+2 pixels 30.

[0264] In each column of the pixel array 40E, the first vertical signal line 55AA has a node 2AAA connected to a node (here, a node 2AAB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the first vertical signal line 55AA has the node 2AAA located at the end of the first vertical signal line 55AB side.

[0265] In each column of the pixel array 40E, the first vertical signal line 55AB has a node 2ABA connected to a node (here, a node 2ABB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the first vertical signal line 55AB has the node 2ABA located at the end portion on the first vertical signal line 55AA side.

[0266] In each column of the pixel array 40E, the first vertical signal line 55AC has a node 2ACA connected to a node (here, a node 2ACB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the first vertical signal line 55AC has the node 2ACA located at the end portion on the first vertical signal line 55AD side.

[0267] In each column of the pixel array 40E, the first vertical signal line 55AD has a node 2ADA connected to a node (here, a node 2ADB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the first vertical signal line 55AD has a node 2ADA located at an end portion on the first vertical signal line 55AC side.

[0268] In each column of the pixel array 40E, the second vertical signal line 55BA has a node 2BAA connected to a node (here, a node 2BAB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the second vertical signal line 55BA has a node 2BAA located at an end portion on the second vertical signal line 55BB side.

[0269] In each column of the pixel array 40E, the second vertical signal line 55BB has a node 2BBA connected to a node (here, a node 2BBB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the second vertical signal line 55BB has a node 2BBA located at an end portion on the second vertical signal line 55BA side.

[0270] In each column of the pixel array 40E, the second vertical signal line 55BC has a node 2BCA connected to a node (here, a node 2BCB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the second vertical signal line 55BC has a node 2BCA located at an end portion on the second vertical signal line 55BD side.

[0271] In each column of the pixel array 40E, the second vertical signal line 55BD has a node 2BDA connected to a node (here, a node 2BDB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the second vertical signal line 55BD has the node 2BDA located at the end portion on the second vertical signal line 55BC side.

[0272] In each column of the pixel array 40E, the third vertical signal line 55CA has a node 2CAA connected to a node (here, a node 2CAB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the third vertical signal line 55CA has the node 2CAA located at the end portion on the third vertical signal line 55CB side.

[0273] In each column of the pixel array 40E, the third vertical signal line 55CB has a node 2CBA connected to a node (here, a node 2CBB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the third vertical signal line 55CB has a node 2CBA located at an end portion on the third vertical signal line 55CA side.

[0274] In each column of the pixel array 40E, the third vertical signal line 55CC has a node 2CCA connected to a node (here, a node 2CCB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the third vertical signal line 55CC has a node 2CCA located at an end portion on the third vertical signal line 55CD side.

[0275] In each column of the pixel array 40E, the third vertical signal line 55CD has a node 2CDA connected to a node (here, a node 2CDB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the third vertical signal line 55CD has a node 2CDA located at an end portion on the third vertical signal line 55CC side.

[0276] In each column of the pixel array 40E, the M-th vertical signal line 55MA has a node 2MAA connected to a node (here, a node 2MAB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the M-th vertical signal line 55MA has a node 2MAA located at an end portion on the side of the M-th vertical signal line 55MB.

[0277] In each column of the pixel array 40E, the M-th vertical signal line 55MB has a node 2MBA connected to a node (here, a node 2MBB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the M-th vertical signal line 55MB has a node 2MBA located at an end portion on the side of the M-th vertical signal line 55MA.

[0278] In each column of the pixel array 40E, the Mth vertical signal line 55MC has a node 2MCA connected to a node (here, a node 2MCB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the Mth vertical signal line 55MC has a node 2MCA located at an end portion on the side of the Mth vertical signal line 55MD.

[0279] In each column of the pixel array 40E, the M-th vertical signal line 55MD has a node 2MDA connected to a node (here, a node 2MDB described later) on the second semiconductor chip 12 side. Here, as a non-limiting example, the M-th vertical signal line 55MD has a node 2MDA located at an end portion on the M-th vertical signal line 55MC side.

[0280] Fig.19 It is a plan view of a readout circuit 60E according to the second embodiment.

[0281] like Fig.19 As shown, the readout circuit 60E includes N / 2 (here, 2) first impedance conversion circuits 611 (connected to Fig.19 The first impedance conversion circuit 611A and the first impedance conversion circuit 611C correspond to each other), N / 2 second impedance conversion circuits 612 (corresponding to Fig.19 The second impedance conversion circuit 612A and the second impedance conversion circuit 612C correspond to each other), N / 2 third impedance conversion circuits 613 (corresponding to Fig.19The third impedance conversion circuit 613A and the third impedance conversion circuit 613C correspond to each other), N / 2 Mth impedance conversion circuits 61M (corresponding to Fig.19 The Mth impedance conversion circuit 61MA and the Mth impedance conversion circuit 61MC correspond to each other), M×N current sources 62 (corresponding to Fig.19 The current sources 62AA, 62AB, 62AC, 62AD, 62BA, 62BB, 62BC, 62BD, 62CA, 62CB, 62CC, 62CD, 62MA, 62MB, 62MC, and 62MD in the circuit are M×N / 2 switches 65 (corresponding to the ... Fig.19 corresponding to switches 65AA, 65AB, 65BA, 65BB, 65CA, 65CB, 65MA, and 65MB), M (in Fig.19 M) common signal lines 63 (with Fig.19 Corresponding to the common signal line 63A, the common signal line 63B, the common signal line 63C, and the common signal line 63M), the first AD converter 64A, the second AD converter 64B, the third AD converter 64C, and the third AD converter 64M.

[0282] Although the readout circuit 60E is described here as an example in which each column of the pixel array 40E includes multiple (here two) first impedance conversion circuits 611, multiple (here two) second impedance conversion circuits 612, multiple (here two) third impedance conversion circuits 613, and multiple (here two) Mth impedance conversion circuits 61M, the readout circuit 60E only needs to include at least multiple first impedance conversion circuits 611 and multiple second impedance conversion circuits 612 for each column of the pixel array 40E.

[0283] Furthermore, although the readout circuit 60E is described here as having M AD converters for each column of the pixel array 40E, and the M AD converters include a first AD converter 64A, a second AD converter 64B, a third AD converter 64C, and a third AD converter 64M, the readout circuit 60E only needs to have at least a first AD converter 64A and a second AD converter 64B for each column of the pixel array 40E.

[0284] Furthermore, the readout circuit 60E has nodes 2AAB, 2ABB, 2ACB, 2ADB, 2BAB, 2BBB, 2BCB, 2BDB, 2CAB, 2CBB, 2CCB, 2CDB, 2MAB, 2MBB, 2MCB, and 2MDB for each column of the pixel array 40E.

[0285] The switch 65AA selectively switches the input of the first impedance conversion circuit 611A to either the node 2AAB or the node 2ABB for connection.

[0286] The switch 65AB selectively switches the input of the first impedance conversion circuit 611C to connect either the node 2ACB or the node 2ADB.

[0287] The switch 65BA selectively switches the input of the second impedance conversion circuit 612A to either the node 2BAB or the node 2BBB for connection.

[0288] The switch 65BB selectively switches the input of the second impedance conversion circuit 612C to either the node 2BCB or the node 2BDB for connection.

[0289] The switch 65CA selectively switches the input of the third impedance conversion circuit 613A to either the node 2CAB or the node 2CBB for connection.

[0290] The switch 65CB selectively switches the input of the third impedance conversion circuit 613C to either the node 2CCB or the node 2CDB for connection.

[0291] The switch 65MA selectively switches the input of the Mth impedance conversion circuit 61MA to either the node 2MAB or the node 2MBB for connection.

[0292] The switch 65MB selectively switches the input of the Mth impedance conversion circuit 61MC to either the node 2MCB or the node 2MDB for connection.

[0293] The first impedance conversion circuit 611, the second impedance conversion circuit 612, the third impedance conversion circuit 613, and the Mth impedance conversion circuit 61M are the same circuits as the first impedance conversion circuit 61 according to the first embodiment.

[0294] like Fig.19 as well as Fig.18As shown, the input of the first impedance conversion circuit 611A is connected to the first vertical signal line 55AA or the first vertical signal line 55AB in the corresponding column of the pixel array 40E via the switch 65AA and the node 2AAB and the node 2AAA, or the node 2ABB and the node 2ABA, and the input of the first impedance conversion circuit 611C is connected to the first vertical signal line 55AC or the first vertical signal line 55AD in the corresponding column of the pixel array 40E via the switch 65AB and the node 2ACB and the node 2ACA, or the node 2ADB and the node 2ADA. The input of the second impedance conversion circuit 612A is connected to the second vertical signal line 55BA or the second vertical signal line 55BB in the corresponding column of the pixel array 40E via the switch 65BA and the node 2BAB and the node 2BAA, or the node 2BBB and the node 2BBA, and the input of the second impedance conversion circuit 612C is connected to the second vertical signal line 55BC or the second vertical signal line 55BD in the corresponding column of the pixel array 40E via the switch 65BB and the node 2BCB and the node 2BCA, or the node 2BDB and the node 2BDA. The input of the third impedance conversion circuit 613A is connected to the third vertical signal line 55CA or the third vertical signal line 55CB in the corresponding column of the pixel array 40E via the switch 65CA and the node 2CAB and the node 2CAA, or the node 2CBB and the node 2CBA, and the input of the third impedance conversion circuit 613C is connected to the third vertical signal line 55CC or the third vertical signal line 55CD in the corresponding column of the pixel array 40E via the switch 65CB and the node 2CCB and the node 2CCA, or the node 2CDB and the node 2CDA. The input of the M-th impedance conversion circuit 61MA is connected to the M-th vertical signal line 55MA or the M-th vertical signal line 55MB in the corresponding column of the pixel array 40E via the switch 65MA and via the node 2MAB and the node 2MAA, or the node 2MBB and the node 2MBA, and the input of the M-th impedance conversion circuit 61MC is connected to the M-th vertical signal line 55MC or the M-th vertical signal line 55MD in the corresponding column of the pixel array 40E via the switch 65MB and via the node 2MCB and the node 2MCA, or the node 2MDB and the node 2MDA.

[0295] The outputs of the N / 2 first impedance conversion circuits 611 are connected to the first AD converter 64A via a common signal line 63A, the outputs of the N / 2 second impedance conversion circuits 612 are connected to the second AD converter 64B via a common signal line 63B, the outputs of the N / 2 third impedance conversion circuits 613 are connected to the third AD converter 64C via a common signal line 63C, and the outputs of the N / 2 Mth impedance conversion circuits 61M are connected to the Mth AD converter 64M via a common signal line 63M.

[0296] The first AD converter 64A performs AD conversion on each of the first impedance conversion signals output from the N / 2 first impedance conversion circuits 611 .

[0297] The second AD converter 64B AD-converts each of the second impedance conversion signals output from the N / 2 second impedance conversion circuits 612 .

[0298] The third AD converter 64C AD-converts each of the third impedance conversion signals output from the N / 2 third impedance conversion circuits 613 .

[0299] The th MAD converter 64M performs AD conversion on each of the Mth impedance conversion signals output from the N / 2 Mth impedance conversion circuits 61M.

[0300] The current source 62AA is connected to the first vertical signal line 55AA in the corresponding column of the pixel array 40E via the node 2AAB and the node 2AAA, the current source 62AB is connected to the first vertical signal line 55AB in the corresponding column of the pixel array 40E via the node 2ABB and the node 2ABA, the current source 62AC is connected to the first vertical signal line 55AC in the corresponding column of the pixel array 40E via the node 2ACB and the node 2ACA, and the current source 62AD is connected to the first vertical signal line 55AD in the corresponding column of the pixel array 40E via the node 2ADB and the node 2ADA. The current source 62BA is connected to the second vertical signal line 55BA in the corresponding column of the pixel array 40E via the node 2BAB and the node 2BAA, the current source 62BB is connected to the second vertical signal line 55BB in the corresponding column of the pixel array 40E via the node 2BBB and the node 2BBA, the current source 62BC is connected to the second vertical signal line 55BC in the corresponding column of the pixel array 40E via the node 2BCB and the node 2BCA, and the current source 62BD is connected to the second vertical signal line 55BD in the corresponding column of the pixel array 40E via the node 2BDB and the node 2BDA. The current source 62CA is connected to the third vertical signal line 55CA in the corresponding column of the pixel array 40E via the node 2CAB and the node 2CAA, the current source 62CB is connected to the third vertical signal line 55CB in the corresponding column of the pixel array 40E via the node 2CBB and the node 2CBA, the current source 62CC is connected to the third vertical signal line 55CC in the corresponding column of the pixel array 40E via the node 2CCB and the node 2CCA, and the current source 62CD is connected to the third vertical signal line 55CD in the corresponding column of the pixel array 40E via the node 2CDB and the node 2CDA. The current source 62MA is connected to the Mth vertical signal line 55MA in the corresponding column of the pixel array 40E via the node 2MAB and the node 2MAA, the current source 62MB is connected to the Mth vertical signal line 55MB in the corresponding column of the pixel array 40E via the node 2MBB and the node 2MBA, the current source 62MC is connected to the Mth vertical signal line 55MC in the corresponding column of the pixel array 40E via the node 2MCB and the node 2MCA, and the current source 62MD is connected to the Mth vertical signal line 55MD in the corresponding column of the pixel array 40E via the node 2MDB and the node 2MDA.

[0301] <Inspection>

[0302] With the imaging device according to the second embodiment configured as described above, pixel signals can be read out in parallel from the pixels 30 included in the same pixel group in each column of the pixel array 40E, that is, pixel signals can be read out in parallel from the pixels 30 connected to the first vertical signal line 55A and the pixels 30 connected to the second vertical signal line 55B which are relatively close. Accordingly, when pixel signals are read out from the pixels 30 by sequentially reading out and scanning each row of the pixel array 40E, when photographing a moving subject, distortion (rolling shutter distortion phenomenon) of the subject in the photographed image that would otherwise occur when pixel signals are read out in parallel from two pixels which are relatively far apart in each column of the pixel array 40E can be reduced, and thus such distortion can be made less noticeable.

[0303] In the second embodiment, in one pixel group 110 (eg, the first pixel group 110A) among the N pixel groups 110 , at least one of the pixels 30 connected to each of the M vertical signal lines may be an OB (Optical Black) pixel 30E.

[0304] Here, the OB pixel 30E refers to a pixel 30 that does not receive light from the photoelectric conversion section 31 .

[0305] Fig. 20 1 is a schematic diagram showing an example of the configuration of the readout circuit 60E when N is 4, M is 4, K is 8, and L is 2.

[0306] like Fig. 20 As shown, in this configuration example, four of the pixels 30 included in the first pixel group 110A are OB pixels 30E. Therefore, in the first pixel group 110A, each of the four vertical signal lines is connected to each of the four OB pixels 30E.

[0307] According to this configuration example, four AD converters (with Fig. 20 ADC1, ADC2, ADC3, ADC4 correspond to each other, and Fig.19 Each of the first AD converter 64A, the second AD converter 64B, the third AD converter 64C, and the third AD converter 64M (corresponding to each other) performs AD conversion on the pixel signal of the OB pixel 30E.

[0308] Therefore, according to this configuration example, the offset errors of the four AD converters can be corrected using the pixel signals of the four OB pixels 30E.

[0309] (Variant 5)

[0310] An imaging device according to a fifth modification will be described below. The imaging device according to the fifth modification is different from the imaging device according to the second embodiment in that a part of its structure is changed.

[0311] Regarding the components of the imaging element involved in variant example 5 that are the same as those of the imaging element involved in embodiment 2, since they have already been described, they are given the same marks and detailed descriptions are omitted. The following description will focus on the differences from the imaging element involved in embodiment 2.

[0312] The configuration of the imaging element according to Modification 5 is different from that of the imaging element according to Embodiment 2 in that the pixel array 40E is changed to the pixel array according to Modification 5 and the readout circuit 60E is changed to the readout circuit according to Modification 5.

[0313] Fig.21 It is a plan view of a pixel array 40F according to Modification Example 5.

[0314] like Fig.21 As shown, the pixel array 40F is different from the pixel array 40E according to the second embodiment in that, in each column, the N pixel groups 110 are changed into N pixel groups 111 (with Fig.18 The first pixel group 111A, the second pixel group 111B, the third pixel group 111C, and the fourth pixel group 111D correspond to each other).

[0315] The structure of each of the N pixel groups 111 is that, relative to each of the N pixel groups 110, the pixel 30 connected to the first vertical signal line 55A and the pixel 30 connected to the third vertical signal line 55C are changed to pixel 30A, and the pixel 30 connected to the second vertical signal line 55B and the pixel 30 connected to the Mth vertical signal line 55M are changed to pixel 30B.

[0316] Here, in Modification 5, L is an integer greater than or equal to 2, M is an integer greater than or equal to 4, and K is an integer greater than or equal to 8.

[0317] And, in Fig.21 Although not shown in the figure, more than L pixels 30A are connected to the first vertical signal line 55A, more than L pixels 30B are connected to the second vertical signal line 55B, more than L pixels 30A are connected to the third vertical signal line 55C, and more than L pixels 30B are connected to the Mth vertical signal line 55M.

[0318] The structure of pixel 30A is different from that of pixel 30 involved in embodiment 1, in that the structure of the photoelectric conversion unit 31 is changed to receive light of the first color transmitted through the first color filter. The structure of pixel 30B is different from that of pixel 30 involved in embodiment 1, in that the structure of the photoelectric conversion unit 31 is changed to receive light of a second color different from the first color transmitted through the second color filter.

[0319] Fig. 22 2 is a plan view of a readout circuit 60F according to Modification 5.

[0320] like Fig. 22 As shown, the structure of the readout circuit 60F is different from that of the readout circuit 60E according to the second embodiment, except that M×N / 2 switches 69 (with Fig. 22 The switches 69AA, 69AB, 69AC, 69AD, 69BA, 69BB, 69BC and 69BD correspond to each other).

[0321] The switch 69AA switches the node 2AAB and the node 2CAB to either a conducting state or a non-conducting state. That is, the switch 69AA switches the first vertical signal line 55AA included in the first pixel group 111A, i.e., the first vertical signal line 55AA connected to the pixel 30A, and the third vertical signal line 55CA included in the first pixel group 111A, i.e., the third vertical signal line 55CA connected to the pixel 30A, to either a conducting state or a non-conducting state.

[0322] The switch 69AB switches the node 2ABB and the node 2CBB to either a conducting state or a non-conducting state. That is, the switch 69AB switches the first vertical signal line 55AB of the second pixel group 111B, i.e., the first vertical signal line 55AB connected to the pixel 30A, and the third vertical signal line 55CB of the second pixel group 111B, i.e., the third vertical signal line 55CB connected to the pixel 30A, to either a conducting state or a non-conducting state.

[0323] The switch 69AC switches the node 2ACB and the node 2CCB to either a conducting state or a non-conducting state. That is, the switch 69AC switches the first vertical signal line 55AC of the third pixel group 111C, i.e., the first vertical signal line 55AC connected to the pixel 30A, and the third vertical signal line 55CC of the third pixel group 111C, i.e., the third vertical signal line 55CC connected to the pixel 30A, to either a conducting state or a non-conducting state.

[0324] The switch 69AD switches the node 2ADB and the node 2CDB to either a conducting state or a non-conducting state. That is, the switch 69AD switches the first vertical signal line 55AD of the fourth pixel group 111D, i.e., the first vertical signal line 55AD connected to the pixel 30A, and the third vertical signal line 55CD of the fourth pixel group 111D, i.e., the third vertical signal line 55CD connected to the pixel 30A, to either a conducting state or a non-conducting state.

[0325] The switch 69BA switches the node 2BAB and the node 2MAB to either a conducting state or a non-conducting state. That is, the switch 69BA switches the second vertical signal line 55BA included in the first pixel group 111A, i.e., the second vertical signal line 55BA connected to the pixel 30B, and the Mth vertical signal line 55MA included in the first pixel group 111A, i.e., the Mth vertical signal line 55MA connected to the pixel 30B, to either a conducting state or a non-conducting state.

[0326] The switch 69BB switches the node 2BBB and the node 2MBB to either a conducting state or a non-conducting state. That is, the switch 69BB switches the second vertical signal line 55BB of the second pixel group 111B, i.e., the second vertical signal line 55BB connected to the pixel 30B, and the Mth vertical signal line 55MB of the second pixel group 111B, i.e., the Mth vertical signal line 55MB connected to the pixel 30B, to either a conducting state or a non-conducting state.

[0327] The switch 69BC switches the node 2BCB and the node 2MCB to either a conducting state or a non-conducting state. That is, the switch 69BC switches the second vertical signal line 55BC of the third pixel group 111C, i.e., the second vertical signal line 55BC connected to the pixel 30B, and the Mth vertical signal line 55MC of the third pixel group 111C, i.e., the Mth vertical signal line 55MC connected to the pixel 30B, to either a conducting state or a non-conducting state.

[0328] The switch 69BD switches the node 2BDB and the node 2MDB to either a conducting state or a non-conducting state. That is, the switch 69BD switches the third vertical signal line 55CD of the fourth pixel group 111D, i.e., the third vertical signal line 55CD connected to the pixel 30B, and the Mth vertical signal line 55MD of the fourth pixel group 111D, i.e., the Mth vertical signal line 55MD connected to the pixel 30B, to either a conducting state or a non-conducting state.

[0329] <Inspection>

[0330] With the imaging device involved in the variant example 5 constructed as described above, in each column and each pixel group 111 of the pixel array 40F, pixel signals from the pixel 30A receiving light of the first color connected to the first vertical signal line 55A and the pixel 30A receiving light of the first color connected to the third vertical signal line 55C can be mixed and read out, and pixel signals from the pixel 30B receiving light of the second color connected to the second vertical signal line 55B and the pixel 30B receiving light of the second color connected to the Mth vertical signal line 55M can be mixed and read out.

[0331] (Implementation method 3)

[0332] Hereinafter, an imaging device according to Embodiment 3 including an imaging element according to any one of Embodiment 1 to Embodiment 2 and Modifications 1 to 5 will be described.

[0333] In the following, although the imaging device involved in Embodiment 3 is described as an example in which the imaging element 1 involved in Embodiment 1 is included, the imaging device involved in Embodiment 3 does not necessarily need to include the imaging element 1 involved in Embodiment 1 as long as it includes the imaging element involved in any one of Embodiments 1 to 2 and Modifications 1 to 5.

[0334] Fig.23 This is a schematic diagram showing the structure of an imaging device 300 according to the third embodiment.

[0335] The imaging device 300 is, for example, a digital still camera, a handheld video camera, or the like.

[0336] like Fig.23 As shown, the imaging device 300 includes an imaging element 1 , a signal processing device 310 , and a lens 320 .

[0337] The lens 320 focuses light from a subject to be captured by the imaging device 300 onto a region of the imaging element 1 where the pixel array 40 is formed, and forms an image of the subject on the region of the imaging element 1 where the pixel array 40 is formed.

[0338] The signal processing device 310 performs various signal processing on the signal (for example, image) output from the imaging element 1 .

[0339] <Inspection>

[0340] As described above, in the first embodiment, the image sensor 1 can increase the speed of reading pixel signals from the pixels 30 while suppressing degradation in the quality of the captured image.

[0341] Therefore, according to the imaging device 300 having the above configuration, it is possible to increase the speed of reading pixel signals from the pixels 30 while suppressing degradation in the quality of the captured image.

[0342] (Replenish)

[0343] Although the imaging element and the imaging device involved in one embodiment of the present disclosure are described above based on Embodiments 1 to 3 and Variations 1 to 5, the present disclosure is not limited to these embodiments and variations. Without departing from the gist of the present disclosure, various modifications conceived by those skilled in the art are performed on the embodiments and variations, and the forms formed by combining the constituent elements in different embodiments and variations can be included in one or more embodiments of the present disclosure.

[0344] (1) In Embodiments 1 to 3 and Modifications 1 to 5, N is described as an integer greater than or equal to 3. However, N may be 2. In other words, N may be an integer greater than or equal to 2.

[0345] An example of a plan view of the pixel array 40 when N is 2 is shown by Fig.24 An example of a plan view of the readout circuit 60A when N is 2 is shown by Fig.25 Shown.

[0346] (2) In the first embodiment, as an example of the circuit configuration of the first impedance conversion circuit 61 having the function of setting the output to high impedance, Figure 7 The circuit configuration shown.

[0347] However, the configuration of the first impedance conversion circuit 61 does not need to be the same as Figure 7 The circuit configuration shown is exactly the same.

[0348] As another circuit configuration of the first impedance conversion circuit 61 having the function of setting the output to high impedance, for example, Fig.26 The circuit configuration shown.

[0349] Industrial Applicability

[0350] The present disclosure can be widely applied to image pickup elements, image pickup devices, and the like.

[0351] Description of Reference Numerals

[0352] 1 Camera element

[0353] 2AA, 2BA, 2CA, 2DA, 2AC, 2BC, 2CC, 2DC, 2AB, 2BB, 2CB, 2DB, 2AD, 2BD, 2CD, 2DD, 2AAA, 2ABA, 2ACA, 2ADA, 2BAA, 2BBA, 2BCA, 2BDA, 2CAA, 2CB Node

[0354] 11First Semiconductor Chip

[0355] 12 second semiconductor chip

[0356] 30, 30A, 30B, 30C pixels

[0357] 30E OB pixels

[0358] 31 Photoelectric conversion unit

[0359] 32 Charge storage unit

[0360] 33 pass transistor

[0361] 34 Reset transistor

[0362] 35 Amplifier transistor

[0363] 36 Select transistor

[0364] 37, 37D, 51, 51A, 51B, 51C, 51D power supply wiring

[0365] 40, 40C, 40E, 40F pixel arrays

[0366] 50, 50A, 50B, 50C, 50D, 55A, 55AA, 55AB, 55AC, 55AD first vertical signal line

[0367] 55B, 55BA, 55BB, 55BC, 55BD second vertical signal line

[0368] 55C, 55CA, 55CB, 55CC, 55CD third vertical signal line

[0369] 55M, 55MA, 55MB, 55MC, 55MD Mth vertical signal line

[0370] 60, 60A, 60B, 60C, 60D, 60E, 60F readout circuit

[0371] 61, 61A, 61B, 61C, 61D, 611, 611A, 611C first impedance conversion circuit 62, 62A, 62B, 62C, 62D, 62AA, 62AB, 62AC, 62AD, 62BA, 62BB, 62BC, 62BD, 62CA, 62CB, 62CC, 62CD, 62MA, 62MB, 62MC, 62MD current source

[0372] 63, 63A, 63B, 63C, 63M share signal line

[0373] 64, 64A first AD converter

[0374] 64B Second AD Converter

[0375] 64C third AD converter

[0376] 64M MAD Converter

[0377] 65, 65A, 65B, 65AA, 65AB, 65BA, 65BB, 65CA, 65CB, 65MA, 65MB, 66, 67, 67A, 67B, 67C, 67D, 68A, 68B, 69, 69AA, 69AB, 69AC, 69AD, 69BA, 69BB, 69BC, 69BD, 642 switch

[0378] 70 Control Unit

[0379] 80 vertical scanning circuit

[0380] 90 Reference current source

[0381] 100, 101, 110, 111 pixel groups

[0382] 100A, 101A, 110A, 111A first pixel group

[0383] 100B, 101B, 110B, 111B second pixel group

[0384] 100C, 101C, 110C, 111C third pixel group

[0385] 100D, 101D, 110D, 111D fourth pixel group

[0386] 200 signal processing circuit

[0387] 300 Camera Devices

[0388] 310 signal processing device

[0389] 320 lens

[0390] 612, 612A, 612C second impedance conversion circuit

[0391] 613, 613A, 613C third impedance conversion circuit

[0392] 61M, 61MA, 61MC Mth impedance conversion circuit

[0393] 631 first common signal line

[0394] 632 second common signal line

[0395] 641 Output Transistor

Claims

1. An imaging element, The imaging element includes a pixel array in which a plurality of pixels are arranged in a matrix, each of the plurality of pixels includes a photoelectric conversion unit that converts received light into electric charge, a charge storage unit that stores the electric charge converted by the photoelectric conversion unit, and an amplifier transistor that outputs a pixel signal corresponding to the amount of electric charge stored in the charge storage unit. Furthermore, the imaging element includes, for each column of the pixel array: a plurality of first impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of first impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; and a first AD converter that performs AD conversion on each of the plurality of first impedance conversion signals output from the plurality of first impedance conversion circuits; The pixel array includes N pixel groups per column, each of the N pixel groups is composed of K or more pixels among the plurality of pixels, and the K or more pixels are arranged continuously in a column direction, N is an integer greater than 2, K is an integer greater than 2, Each of the N pixel groups includes a first vertical signal line, wherein the first vertical signal line is connected to L or more first pixels among the K or more pixels, where L is an integer not less than 2 and not more than K. In each column of the pixel array, each of the N first vertical signal lines included in the N pixel groups is connected to an input of any one of the plurality of first impedance conversion circuits, and an output of each of the plurality of first impedance conversion circuits is connected to the first AD converter.

2. The imaging element according to claim 1, L is equal to K, The K or more pixels are the L or more first pixels.

3. The imaging element according to claim 1, K is an integer greater than 4, L is an integer greater than 2 and less than K / 2, The imaging element further includes, for each column of the pixel array: a plurality of second impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of second impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; and The second AD converter performs AD conversion on the plurality of second impedance conversion signals output from the plurality of second impedance conversion circuits, Each of the N pixel groups further includes a second vertical signal line, the second vertical signal line is connected to L or more second pixels among the K or more pixels, the L or more second pixels are different from the L or more first pixels, In each column of the pixel array, each of the N second vertical signal lines included in the N pixel groups is connected to an input of any one of the plurality of second impedance conversion circuits, and an output of each of the plurality of second impedance conversion circuits is connected to the second AD converter.

4. The imaging element according to any one of claims 1 to 3, In each column of the pixel array, at least one output of the multiple first impedance conversion circuits is connected to the first AD converter via a first common signal line, and at least one other output of the multiple first impedance conversion circuits is connected to the first AD converter via a second common signal line different from the first common signal line.

5. The imaging element according to any one of claims 1 to 3, In each column of the pixel array, at least one input of the plurality of first impedance conversion circuits is selectively connected to two of the first vertical signal lines provided by two pixel groups adjacent to each other in the column direction among the N pixel groups.

6. The imaging element according to any one of claims 1 to 3, Each of the plurality of first impedance conversion circuits has an output transistor for outputting each of the plurality of first impedance conversion signals. Each of the output transistors has a higher driving capability than the amplifying transistor.

7. The imaging element according to any one of claims 1 to 3, The imaging element further includes a plurality of current sources for each column of the pixel array, and the plurality of current sources flows a current into each of the N first vertical signal lines. The imaging element further includes a reference current source that uniformly regulates currents flowing through at least two current sources among all the plurality of current sources included in the imaging element.

8. The imaging element according to any one of claims 1 to 3, N is an integer greater than 4, The imaging element is formed by stacking a first semiconductor chip and a second semiconductor chip, the pixel array is formed on the first semiconductor chip, and the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed on the second semiconductor chip. In a plan view of the pixel array, in each column of the pixel array, The N first vertical signal lines included in the N pixel groups extend in the column direction of the pixel array and are arranged in the column direction of the pixel array. One of the plurality of first impedance conversion circuits is located between a third vertical signal line and a fourth vertical signal line that are adjacent to each other in a column direction of the pixel array among the N first vertical signal lines. Another first impedance conversion circuit among the multiple first impedance conversion circuits is located between the fifth vertical signal line and the sixth vertical signal line among the N first vertical signal lines, which are adjacent to each other in the column direction of the pixel array, and the fifth vertical signal line and the sixth vertical signal line are different from the third vertical signal line and the fourth vertical signal line.

9. The imaging element according to any one of claims 1 to 3, The imaging element is formed by stacking a first semiconductor chip and a second semiconductor chip, the pixel array is formed on the first semiconductor chip, and the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed on the second semiconductor chip. In a plan view of the pixel array, in each column of the pixel array, The N first vertical signal lines included in the N pixel groups extend in the column direction of the pixel array and are arranged in the column direction of the pixel array. The existence range of one or more wirings for connecting the outputs of the plurality of first impedance conversion circuits to the first AD converter in the column direction of the pixel array is included in the existence range of the N first vertical signal lines in the column direction of the pixel array.

10. The imaging element according to any one of claims 1 to 3, The imaging element is formed by stacking a first semiconductor chip and a second semiconductor chip, the pixel array is formed on the first semiconductor chip, and the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed on the second semiconductor chip. In a plan view of the pixel array, in each column of the pixel array, The N first vertical signal lines included in the N pixel groups extend in the column direction of the pixel array and are arranged in the column direction of the pixel array. The total wiring length of one or more wirings for connecting the outputs of the plurality of first impedance conversion circuits and the first AD converter is smaller than the total wiring length of the N first vertical signal lines.

11. The imaging element according to any one of claims 1 to 3, The pixel array further includes a plurality of current sources for each column, and the plurality of current sources flows a current into each of the N first vertical signal lines. The imaging element further includes a control unit that controls all of the plurality of current sources included in the pixel array. For each column of the pixel array, the control unit activates the current source among the multiple current sources that flows current into the first vertical signal line of the pixel group that performs readout, and deactivates the other current sources. The pixel group that performs readout is a pixel group composed of more than K pixels that output pixel signals.

12. The imaging element according to any one of claims 1 to 3, The pixel array further includes a plurality of current sources for each column, and the plurality of current sources flows a current into each of the N first vertical signal lines. The imaging element further includes a control unit that controls all of the plurality of current sources included in the pixel array. The control unit causes, for each column of the pixel array, a current source among the multiple current sources that flows current into the first vertical signal line of a pixel group that performs readout to be in a first activation state, and causes other current sources to be in a second activation state. The pixel group that performs readout is a pixel group composed of more than K pixels that output pixel signals, and the amount of current flowing in the second activation state is less than the amount of current flowing in the first activation state.

13. The imaging element according to any one of claims 1 to 3, The pixel array further includes a plurality of current sources for each column, and the plurality of current sources flows a current into each of the N first vertical signal lines. The imaging element further includes a control unit that controls all of the plurality of current sources included in the pixel array. The control unit activates or deactivates one of the current sources (1) to (3) among the plurality of current sources for each column of the pixel array, (1) activating a current source that flows current into the first vertical signal line of a pixel group that performs readout, wherein the pixel group that performs readout is a pixel group composed of the K or more pixels that output pixel signals, (2) activating a current source that flows current into the first vertical signal line of a pixel group before readout is performed before the K or more pixels of the pixel group before readout start outputting pixel signals, wherein the pixel group before readout is a pixel group composed of the K or more pixels that output pixel signals after the K or more pixels of the pixel group that performs readout, and (3) deactivating current sources other than the current source that flows current into the first vertical signal line of the pixel group that performs readout and the current source that flows current into the first vertical signal line of the pixel group before readout.

14. The imaging element according to any one of claims 1 to 3, The pixel array further includes a plurality of current sources for each column, and the plurality of current sources flow current into power supply wirings connected to the K or more pixels included in each of the N pixel groups, The imaging element further includes a control unit that controls the plurality of current sources included in the pixel array. The control unit causes, for each column of the pixel array, a current source among the multiple current sources that flows current into the power wiring connected to the K or more pixels included in the pixel group before readout is activated before the K or more pixels in the pixel group before readout start outputting pixel signals, and causes current sources other than the current source that flows current into the power wiring connected to the K or more pixels included in the pixel group before readout to be inactivated. The pixel group before readout is a pixel group consisting of the K or more pixels that output pixel signals after the K or more pixels included in the pixel group that performs readout, and the pixel group that performs readout is a pixel group consisting of the K or more pixels that output pixel signals.

15. The imaging element according to any one of claims 1 to 3, The pixel array further includes a plurality of current sources for each column, and the plurality of current sources flows a current into each of the N first vertical signal lines. The imaging element further includes a control unit that controls all of the plurality of current sources included in the pixel array. The control unit activates or deactivates one of the current sources (1) to (3) among the plurality of current sources for each column of the pixel array, (1) activating the current source that flows current into the first vertical signal line of the readout pixel group, the readout pixel group being a pixel group consisting of the K or more pixels that output pixel signals, (2) activating the current source that flows current into the first vertical signal line of the post-readout pixel group for a certain period of time after the K or more pixels included in the post-readout pixel group have finished outputting pixel signals, the post-readout pixel group being a pixel group consisting of the K or more pixels that have output pixel signals immediately before the K or more pixels in the readout pixel group, and (3) deactivating current sources other than the current source that flows current into the first vertical signal line of the readout pixel group and the current source that flows current into the first vertical signal line of the post-readout pixel group.

16. The imaging element according to any one of claims 1 to 3, The pixel array further includes a plurality of current sources for each column, and the plurality of current sources flow current into power supply wirings connected to the K or more pixels included in each of the N pixel groups, The imaging element further includes a control unit that controls the plurality of current sources included in the pixel array. The control unit causes, for each column of the pixel array, a current source among the multiple current sources that flows current into the power wiring connected to the K or more pixels included in the pixel group after the readout is executed to be in an activated state for a certain period of time after the K or more pixels included in the pixel group after the readout has finished outputting pixel signals, and causes current sources other than the current source that flows current into the power wiring connected to the K or more pixels included in the pixel group after the readout is in an inactivated state, the pixel group after the readout is a pixel group consisting of the K or more pixels that output pixel signals immediately before the K or more pixels included in the pixel group for executing the readout, and the pixel group for executing the readout is a pixel group consisting of the K or more pixels that output pixel signals.

17. The imaging element according to any one of claims 1 to 3, N is an even number greater than 4, In each column of the pixel array, the N pixel groups include at least a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group. The imaging element includes a first switch and a second switch for each column of the pixel array, the first switch switching the first vertical signal line of the first pixel group and the first vertical signal line of the second pixel group to one of a conductive state and a non-conductive state, and the second switch switching the first vertical signal line of the third pixel group and the first vertical signal line of the fourth pixel group to one of a conductive state and a non-conductive state.

18. The imaging element according to claim 3, K is an integer greater than 8, L is an integer greater than 2 and less than K / 4, Each of the N pixel groups further comprises: a third vertical signal line connected to L or more third pixels among the K or more pixels, the L or more third pixels being different from the L or more first pixels and the L or more second pixels; as well as a fourth vertical signal line connected to L or more fourth pixels among the K or more pixels, the L or more fourth pixels being different from the L or more first pixels, the L or more second pixels, and the L or more third pixels, The imaging element further includes, for each column of the pixel array: a plurality of third impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of third impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; a plurality of fourth impedance conversion circuits having an output impedance lower than an input impedance, each of the plurality of fourth impedance conversion circuits being input with a pixel signal output from at least one of the plurality of pixels; a third AD converter, performing AD conversion on a plurality of third impedance conversion signals output from the plurality of third impedance conversion circuits; as well as a fourth AD converter, performing AD conversion on a plurality of fourth impedance conversion signals output from the plurality of fourth impedance conversion circuits, The imaging element includes a first switch and a second switch for each column of the pixel array and for each of the N pixel groups. The first switch switches the first vertical signal line and the third vertical signal line to one of a conducting state and a non-conducting state. The second switch switches the second vertical signal line and the fourth vertical signal line to one of a conducting state and a non-conducting state. In each column of the pixel array, Each of the N third vertical signal lines included in the N pixel groups is connected to an input of any one of the plurality of third impedance conversion circuits, and an output of each of the plurality of third impedance conversion circuits is connected to the third AD converter. Each of the N fourth vertical signal lines included in the N pixel groups is connected to an input of any one of the plurality of fourth impedance conversion circuits, and an output of each of the plurality of fourth impedance conversion circuits is connected to the fourth AD converter. The photoelectric conversion units of the L or more first pixels and the photoelectric conversion units of the L or more third pixels receive light of the first color that has passed through the first color filter, and the photoelectric conversion units of the L or more second pixels and the photoelectric conversion units of the L or more fourth pixels receive light of a second color that is different from the first color that has passed through the second color filter.

19. An imaging device comprising the imaging element according to any one of claims 1 to 3.

20. An imaging device comprising: A pixel array in which pixels are arranged in a matrix, the pixels having a photoelectric conversion unit that converts received light into electric charge; a pixel group, consisting of a plurality of the pixels in the pixel array; a vertical signal line connected to at least one of the plurality of pixels in the pixel group; an impedance conversion circuit connected to the vertical signal line, wherein the output impedance of the impedance conversion circuit is lower than the input impedance; and The AD converter is connected to the impedance conversion circuit.

21. The imaging element according to claim 20, The impedance conversion circuit is multiple, The pixel array includes N pixel groups per column, each of the N pixel groups is composed of the plurality of pixels connected to any one of the M vertical signal lines, N is an integer greater than 2, and M is an integer greater than 1. Each of the N×M vertical signal lines included in the N pixel groups is connected to an input of any one of the plurality of impedance conversion circuits.

22. The imaging element according to claim 21, The imaging element further includes a plurality of switches capable of selectively selecting one of the M vertical signal lines provided in each of two or more different pixel groups among the N pixel groups. Inputs of the plurality of impedance conversion circuits are respectively connected to any one of the plurality of switches.

23. The imaging element according to claim 21 or claim 22, There are multiple AD converters. The M vertical signal lines included in each of P pixel groups among the N pixel groups are connected to any one of the multiple AD converters via any one of the multiple impedance conversion circuits, where P is an integer greater than or equal to 2 and less than or equal to N.

24. The imaging element according to claim 21 or claim 22, One of the M vertical signal lines included in each of the P pixel groups in the N pixel groups is connected to the common AD converter via one of the impedance conversion circuits, where P is an integer greater than 2 and less than N. The plurality of impedance conversion circuits have a function of setting output to high impedance.

25. The imaging element according to claim 22, There are multiple AD converters. At least one of the output lines connecting any one of the plurality of impedance conversion circuits and any one of the plurality of AD converters overlaps at least one of the plurality of AD converters that is not connected to the impedance conversion circuit in a plan view.

26. The imaging element according to claim 22, The AD converter is connected to one or more vertical signal lines overlapping with the AD converter in a plan view and one or more vertical signal lines not overlapping with the AD converter in the plan view, among the M vertical signal lines.

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