Array substrate and display device

Abstract

The array substrate comprises a plurality of signal lines. Each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are in two different layers. The plurality of first signal line portions and the plurality of third signal line portions are in two different layers. The two separate first signal line portions, the separate second signal line portion, and the separate third signal line portion form a ring substantially surrounding an area of a transistor and a capacitor of a pixel driving circuit having sub-pixels. The two independent first signal line parts are connected through the independent second signal line part and are connected through the independent third signal line part.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate signal line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising a plurality of signal lines; wherein each of the plurality of signal lines comprises a plurality of first signal line portions, a plurality of second signal line portions and a plurality of third signal line portions; the plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions; each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions; two separate first signal line portions of the plurality of first signal line portions, a separate second signal line portion of the plurality of second signal line portions, and a separate third signal line portion of the plurality of third signal line portions form a ring, which substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels; and the two separate first signal line portions are connected via the separate second signal line portions and via the separate third signal line portions.

[0004] Optionally, the array substrate includes a plurality of rings arranged in rows in sequence; wherein the plurality of rings respectively substantially surround an area of ​​a pixel driving circuit of a sub-pixel of the same color; and each of the plurality of rings substantially surrounds an area of ​​a pixel driving circuit of a sub-pixel of the same color.

[0005] Optionally, the array substrate includes a plurality of rings arranged in rows in sequence; wherein the plurality of rings respectively substantially surround an area of ​​an anode of a sub-pixel having the same color; and each of the plurality of rings substantially surrounds an area of ​​an anode of a sub-pixel having the same color.

[0006] Optionally, the sub-pixels are arranged in multiple rows and columns; in the mth row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; in the (m+1)th row of sub-pixels, the array substrate includes a row of third sub-pixels of a third color; in the (m+2)th row of sub-pixels, the array substrate includes a row of second sub-pixels of a second color; in the nth column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; in the (n-1)th column of sub-pixels, the array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color that are alternately arranged; in the (n+1)th column of sub-pixels, the array substrate includes a row of second sub-pixels of a second color. The array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color arranged alternately; the first signal line portion among the multiple first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column and the (m+1)th row of sub-pixels, is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column and the mth row of sub-pixels, and is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column and the (m+2)th row of sub-pixels.

[0007] Optionally, a second signal line portion among the multiple second signal line portions connects the first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

[0008] Optionally, a third signal line portion among the multiple third signal line portions connects the first signal line portion to a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel and the mth row sub-pixel.

[0009] Optionally, the array substrate further comprises a plurality of light-transmitting regions; wherein, in the n-th column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

[0010] Optionally, the plurality of signal lines include a plurality of initialization signal lines; the plurality of first signal line portions include a plurality of first initialization signal line portions; the plurality of second signal line portions include a plurality of second initialization signal line portions; and the plurality of third signal line portions include a plurality of third initialization signal line portions.

[0011] Optionally, the plurality of signal lines include a plurality of gate signal lines; the plurality of first signal line portions include a plurality of first gate signal line portions; the plurality of second signal line portions include a plurality of second gate signal line portions; and the plurality of third signal line portions include a plurality of third gate signal line portions.

[0012] Optionally, the multiple signal lines include multiple reset control signal lines; the multiple first signal line portions include multiple first reset control signal line portions; the multiple second signal line portions include multiple second reset control signal line portions; and the multiple third signal line portions include multiple third reset control signal line portions.

[0013] Optionally, the multiple signal lines include multiple light-emitting control signal lines; the multiple first signal line portions include multiple first light-emitting control signal line portions; the multiple second signal line portions include multiple second light-emitting control signal line portions; and the multiple third signal line portions include multiple third light-emitting control signal line portions.

[0014] Optionally, the array substrate further includes multiple light-transmitting areas; wherein the array substrate includes a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer and an anode layer; the signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer and the anode layer do not exist in the multiple light-transmitting areas.

[0015] Optionally, the array substrate further comprises a second signal line layer; wherein the signal lines in the second signal line layer comprise a substantially transparent conductive material; and the signal lines of the second signal line layer exist in the plurality of light-transmitting regions.

[0016] Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and the plurality of first signal line portions are located in the first conductive layer or the second conductive layer.

[0017] Optionally, the array substrate also includes a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; the plurality of voltage connection bridges are arranged in an array of multiple rows and columns; two adjacent voltage connection bridges among the plurality of voltage connection bridges in the same pixel row are connected to the same voltage supply line among the plurality of voltage supply lines; and a voltage connection bridge among the plurality of voltage connection bridges in the same pixel column is connected to the same adjacent voltage supply line among the plurality of voltage supply lines.

[0018] Optionally, the plurality of voltage supply lines include a first adjacent voltage supply line, a second adjacent voltage supply line and a third adjacent voltage supply line; the first adjacent voltage supply line is configured to provide a voltage supply signal to a first pixel driving circuit in a corresponding first sub-pixel, the second adjacent voltage supply line is configured to provide a voltage supply signal to a second pixel driving circuit in a corresponding second sub-pixel, and the third adjacent voltage supply line is configured to provide a voltage supply signal to a third pixel driving circuit in a corresponding third sub-pixel; and each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line and the third adjacent voltage supply line.

[0019] Optionally, each of the first adjacent voltage supply line, the second adjacent voltage supply line and the third adjacent voltage supply line includes a plurality of first voltage supply line portions and a plurality of second voltage supply line portions arranged alternately; each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

[0020] Optionally, the plurality of voltage supply lines include a first adjacent voltage supply line and a second adjacent voltage supply line; each of the plurality of voltage supply lines is connected to voltage connection bridges of two adjacent columns of the plurality of voltage connection bridges; and each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

[0021] Optionally, each of the plurality of voltage connection bridges comprises a second capacitor electrode of a plurality of pixel driving circuits.

[0022] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, and one or more integrated circuits connected to the array substrate.

[0023] On the other hand, the present disclosure provides an array substrate, comprising a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; wherein the plurality of voltage connection bridges are arranged in an array of multiple rows and columns; two adjacent voltage connection bridges among the plurality of voltage connection bridges in the same pixel row are connected to the same voltage supply line among the plurality of voltage supply lines; and a voltage connection bridge among the plurality of voltage connection bridges in the same pixel column is connected to the same adjacent voltage supply line among the plurality of voltage supply lines.

[0024] Optionally, the plurality of voltage supply lines include a first adjacent voltage supply line, a second adjacent voltage supply line and a third adjacent voltage supply line; the first adjacent voltage supply line is configured to provide a voltage supply signal to a first pixel driving circuit in a corresponding first sub-pixel, the second adjacent voltage supply line is configured to provide a voltage supply signal to a second pixel driving circuit in a corresponding second sub-pixel, and the third adjacent voltage supply line is configured to provide a voltage supply signal to a third pixel driving circuit in a corresponding third sub-pixel; and each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line and the third adjacent voltage supply line.

[0025] Optionally, each of the first adjacent voltage supply line, the second adjacent voltage supply line and the third adjacent voltage supply line includes a plurality of first voltage supply line portions and a plurality of second voltage supply line portions arranged alternately; each of the plurality of voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

[0026] Optionally, the plurality of voltage supply lines include a first adjacent voltage supply line and a second adjacent voltage supply line; each of the plurality of voltage supply lines is connected to voltage connection bridges of two adjacent columns of the plurality of voltage connection bridges; and each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

[0027] Optionally, each of the plurality of voltage connection bridges comprises a second capacitor electrode of a plurality of pixel driving circuits.

[0028] Optionally, the array substrate also includes a plurality of signal lines; wherein each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions and a plurality of third signal line portions; the plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions; each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions; two separate first signal line portions of the plurality of first signal line portions, a separate second signal line portion of the plurality of second signal line portions, and a separate third signal line portion of the plurality of third signal line portions form a ring, which basically surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels; and the two separate first signal line portions are connected through the separate second signal line portion and through the separate third signal line portion.

[0029] Optionally, the array substrate includes a plurality of rings arranged in rows in sequence; wherein the plurality of rings respectively substantially surround an area of ​​a pixel driving circuit of a sub-pixel of the same color; and each of the plurality of rings substantially surrounds an area of ​​a pixel driving circuit of a sub-pixel of the same color.

[0030] Optionally, the array substrate includes a plurality of rings arranged in rows in sequence; wherein the plurality of rings respectively substantially surround an area of ​​an anode of a sub-pixel having the same color; and each of the plurality of rings substantially surrounds an area of ​​an anode of a sub-pixel having the same color.

[0031] Optionally, the sub-pixels are arranged in multiple rows and columns; in the mth row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; in the (m+1)th row of sub-pixels, the array substrate includes a row of third sub-pixels of a third color; in the (m+2)th row of sub-pixels, the array substrate includes a row of second sub-pixels of a second color; in the nth column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; in the (n-1)th column of sub-pixels, the array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color that are alternately arranged; in the (n+1)th column of sub-pixels, the array substrate includes a row of second sub-pixels of the second color that are alternately arranged. The array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color arranged alternately; the first signal line portion among the multiple first signal line portions is connected to one or more transistors in the pixel driving circuit of the third sub-pixel in the nth column and the (m+1)th row of sub-pixels, is connected to one or more transistors in the pixel driving circuit of the first sub-pixel in the (n-1)th column and the mth row of sub-pixels, and is connected to one or more transistors in the pixel driving circuit of the second sub-pixel in the (n+1)th column and the (m+2)th row of sub-pixels.

[0032] Optionally, a second signal line portion among the multiple second signal line portions connects the first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

[0033] Optionally, a third signal line portion among the multiple third signal line portions connects the first signal line portion to a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel and the mth row sub-pixel.

[0034] Optionally, the array substrate further comprises a plurality of light-transmitting regions; wherein, in the n-th column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

[0035] Optionally, the plurality of signal lines include a plurality of initialization signal lines; the plurality of first signal line portions include a plurality of first initialization signal line portions; the plurality of second signal line portions include a plurality of second initialization signal line portions; and the plurality of third signal line portions include a plurality of third initialization signal line portions.

[0036] Optionally, the plurality of signal lines include a plurality of gate signal lines; the plurality of first signal line portions include a plurality of first gate signal line portions; the plurality of second signal line portions include a plurality of second gate signal line portions; and the plurality of third signal line portions include a plurality of third gate signal line portions.

[0037] Optionally, the multiple signal lines include multiple reset control signal lines; the multiple first signal line portions include multiple first reset control signal line portions; the multiple second signal line portions include multiple second reset control signal line portions; and the multiple third signal line portions include multiple third reset control signal line portions.

[0038] Optionally, the multiple signal lines include multiple light-emitting control signal lines; the multiple first signal line portions include multiple first light-emitting control signal line portions; the multiple second signal line portions include multiple second light-emitting control signal line portions; and the multiple third signal line portions include multiple third light-emitting control signal line portions.

[0039] Optionally, the array substrate also includes multiple light-transmitting areas; wherein the array substrate includes a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer and an anode layer; the signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer and the anode layer are not present in the multiple light-transmitting areas.

[0040] Optionally, the array substrate further comprises a second signal line layer; wherein the signal lines in the second signal line layer comprise a substantially transparent conductive material; and the signal lines of the second signal line layer exist in the plurality of light-transmitting regions.

[0041] Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and the plurality of first signal line portions are located in the first conductive layer or the second conductive layer.

[0042] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0044] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0045] Figure 2Ais a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0046] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0047] Figure 2C is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0048] Figure 3A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0049] Figure 3B It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0050] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0051] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0052] Figure 3E It is shown Figure 3A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG.

[0053] Figure 3F It is shown Figure 3A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0054] Figure 3G It is shown Figure 3A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG.

[0055] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG.

[0056] Fig. 3I It is shown Figure 3A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG.

[0057] Figure 3J It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG.

[0058] Figure 3K It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG.

[0059] Figure 3L It is shown Figure 3A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG.

[0060] Figure 3M It is shown Figure 3A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0061] Figure 4 is along Figure 3A Cross-sectional view along line A-A'.

[0062] Figure 5A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0063] Figure 5B It is shown Figure 5A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0064] Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0065] Figure 5D It is shown Figure 5A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0066] Figure 5E It is shown Figure 5A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG.

[0067] Fig. 5F It is shown Figure 5A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0068] Figure 5G It is shown Figure 5A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG.

[0069] Figure 5H It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG.

[0070] Fig.5I It is shown Figure 5ASchematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG.

[0071] Figure 5J It is shown Figure 5A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG.

[0072] Figure 5K It is shown Figure 5A Schematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG.

[0073] Figure 5L It is shown Figure 5A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG.

[0074] Figure 5M It is shown Figure 5A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0075] Figure 6 is a schematic diagram showing a voltage supply network in a portion of an array substrate in some embodiments of the present disclosure.

[0076] Figure 7 is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0077] Figure 8 is a schematic diagram showing a reset signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0078] Fig. 9 is a schematic diagram showing a reset signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0079] Fig.10 is a schematic diagram showing a gate scan signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0080] Fig.11 is a schematic diagram showing a gate scan signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0081] Fig.12 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0082] Fig.13 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0083] Fig.14 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0084] Fig.15 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0085] Fig.16A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0086] Fig. 16B It is shown Fig.16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0087] Fig. 16C It is shown Fig.16A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0088] Fig.16D It is shown Fig.16A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0089] Fig.16E It is shown Fig.16A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG.

[0090] Fig.16F It is shown Fig.16A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0091] Figure 16G It is shown Fig.16A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG.

[0092] Fig.16H It is shown Fig.16A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG.

[0093] Fig.16I It is shown Fig.16A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG.

[0094] Fig.16J It is shown Fig.16A Schematic diagram of the structure of the third signal line layer in a portion of the array substrate described in .

[0095] Figure 16K It is shown Fig.16ASchematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG.

[0096] Figure 16L It is shown Fig.16A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG.

[0097] Figure 16M It is shown Fig.16A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0098] Fig.17A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0099] Fig. 17B It is shown Fig.17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0100] Fig. 17C It is shown Fig.17A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0101] Fig.17D It is shown Fig.17A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0102] Fig.17E It is shown Fig.17A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG.

[0103] Fig.17F It is shown Fig.17A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0104] Figure 17G It is shown Fig.17A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG.

[0105] Fig.17H It is shown Fig.17A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG.

[0106] Fig.17I It is shown Fig.17A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG.

[0107] Fig.17J It is shown Fig.17AA schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG.

[0108] Figure 17K It is shown Fig.17A Schematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG.

[0109] Figure 17L It is shown Fig.17A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG.

[0110] Fig.17M It is shown Fig.17A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0111] Fig.18 is a schematic diagram showing a voltage supply network in a portion of an array substrate in some embodiments of the present disclosure.

[0112] Fig.19 is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0113] Fig. 20 is a schematic diagram showing a reset signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0114] Fig.21 is a schematic diagram showing a reset signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0115] Fig. 22 is a schematic diagram showing a gate scan signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0116] Fig.23 is a schematic diagram showing a gate scan signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0117] Fig.24 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0118] Fig.25 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0119] Fig.26 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0120] Fig. 27is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0121] Fig.28A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0122] Fig.28B It is shown Fig.28A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0123] Fig.28C It is shown Fig.28A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0124] Fig.28D It is shown Fig.28A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0125] Fig.28E It is shown Fig.28A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG.

[0126] Fig.28F It is shown Fig.28A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0127] Figure 28G It is shown Fig.28A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG.

[0128] Fig.28H It is shown Fig.28A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG.

[0129] Fig.28I It is shown Fig.28A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG.

[0130] Fig.28J It is shown Fig.28A Schematic diagram of the structure of the second planarization layer in a portion of the array substrate described in.

[0131] Figure 28K It is shown Fig.28A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG.

[0132] Figure 28L It is shown Fig.28AA schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0133] Fig.29 is along Fig.28A Cross-sectional view along line BB'.

[0134] Fig. 30A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0135] Fig. 30B It is shown Fig. 30A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG.

[0136] Fig. 30C It is shown Fig. 30A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG.

[0137] Fig.30D It is shown Fig. 30A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG.

[0138] Fig.30E It is shown Fig. 30A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG.

[0139] Fig.30F It is shown Fig. 30A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG.

[0140] Figure 30G It is shown Fig. 30A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG.

[0141] Fig. 30H It is shown Fig. 30A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG.

[0142] Fig. 30I It is shown Fig. 30A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG.

[0143] Fig. 30J It is shown Fig. 30A Schematic diagram of the structure of the second planarization layer in a portion of the array substrate described in.

[0144] Figure 30K It is shown Fig. 30A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG.

[0145] Figure 30L It is shown Fig. 30A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0146] Fig.31 is a schematic diagram showing a voltage supply network in a portion of an array substrate in some embodiments of the present disclosure.

[0147] Fig.32 is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0148] Fig.33 is a schematic diagram showing a reset signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0149] Fig.34 is a schematic diagram showing a reset signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0150] Fig.35 is a schematic diagram showing a gate scan signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0151] Fig.36 is a schematic diagram showing a gate scan signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0152] Fig.37 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0153] Fig.38 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0154] Fig.39 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure.

[0155] Fig.40 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0156] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0157] The present disclosure provides an array substrate and a display device, which substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of signal lines. Optionally, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. Optionally, the plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. Optionally, the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, each of the plurality of second signal line portions is connected to two adjacent first signal line portions in the plurality of first signal line portions, respectively. Optionally, each of the plurality of third signal line portions is connected to two adjacent first signal line portions in the plurality of first signal line portions, respectively. Optionally, two separate first signal line portions in the plurality of first signal line portions, a separate second signal line portion in the plurality of second signal line portions, and a separate third signal line portion in the plurality of third signal line portions form a ring that substantially surrounds the region of the transistor and capacitor of the pixel driving circuit having the sub-pixel. Optionally, two separate first signal line portions are connected via a separate second signal line portion and via a separate third signal line portion.

[0158] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0159] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate signal lines GL, a plurality of data lines DL, and a plurality of voltage supply lines Vdd (for example, a plurality of first voltage supply lines and / or a plurality of second voltage supply lines). Each sub-pixel Sp is driven by a corresponding pixel driving circuit PDC to emit light. In one example, a high voltage signal (for example, a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of a light-emitting element through each of a plurality of voltage supply lines Vdd; a low voltage signal (for example, a VSS signal) is input to a cathode of a light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (for example, a VDD signal) and the low voltage signal (for example, a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0160] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line among a plurality of reset control signal lines rst, a first electrode connected to a corresponding initialization signal line among a plurality of initialization signal lines Vint, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate signal line among a plurality of gate signal lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate signal line, a first capacitor electrode Ce1 connected to the storage capacitor Cst, and a gate of the driving transistor Td; a first electrode connected to the first electrode of the first transistor Td and a second electrode connected to the second electrode of the driving transistor Td; a fourth transistor T4 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 having a gate connected to a corresponding light emitting control signal line, a first electrode connected to the second electrode of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light emitting element LE; and a sixth transistor T6 having a gate connected to a corresponding gate signal line among a plurality of gate signal lines GL, a first electrode connected to a corresponding initialization signal line among a plurality of initialization signal lines Vint, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the fourth transistor T4.

[0161] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0162] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate signal line among the plurality of first gate signal lines GL1 twice (alternatively, the corresponding gate signal line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is Figure 3C The first transistor T1 is a "double-gate" transistor. The gate of the third transistor T3 is Figure 3C Marked as “G3”, wherein the third transistor T3 is a “dual-gate” transistor.

[0163] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6 and the anode of the light emitting element LE.

[0164] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, and the first terminal and the second terminal are connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0165] Figure 2C is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. FIG. 2A to FIG. 2CDuring one frame of image, the operation of the pixel driving circuit includes a reset sub-phase t1, a data writing sub-phase t2, and a light emitting sub-phase t3. In the initial sub-phase t0, a cut-off reset control signal is provided to the gate of the first transistor T1 through a corresponding reset control signal line among a plurality of reset control signal lines rst, so that the first transistor T1 is cut off. In the initial sub-phase t0, a corresponding gate signal line among a plurality of gate signal lines GL is provided with a cut-off signal, so that the second transistor T2 and the third transistor T3 are cut off.

[0166] In the reset sub-phase t1, the on-reset control signal is provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst to turn on the first transistor T1; to allow the initialization voltage signal from the corresponding initialization signal line in the plurality of initialization signal lines Vint to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding second voltage supply line in the plurality of second voltage supply lines Vdd2. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the reset sub-phase t1. In the reset sub-phase t1, the corresponding gate signal line in the plurality of gate signal lines GL is provided with a cut-off signal, so the second transistor T2 and the third transistor T3 are cut off. The corresponding light emitting control signal line in the plurality of light emitting control signal lines em is provided with a high voltage signal to cut off the fourth transistor T4 and the fifth transistor T5.

[0167] In the data writing sub-phase t2, the gate of the first transistor T1 is again provided with a cut-off reset control signal through the corresponding reset control signal line in the plurality of reset control signal lines rst to cut off the first transistor T1. The corresponding gate signal line in the plurality of gate signal lines GL is provided with a turn-on signal, so that the second transistor T2 and the third transistor T3 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on in the data writing sub-phase t2, the gate of the driving transistor Td is connected to the second electrode and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The second transistor T2 is turned on in the data writing sub-phase t2. The data voltage signal transmitted through the corresponding data line in the plurality of data lines DL is received by the first electrode of the second transistor T2, and then transmitted to the first electrode of the driving transistor Td, and the first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the data writing sub-phase t2, the voltage level at the node N1 gradually rises to (Vdata+Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. The corresponding light emitting control signal line among the plurality of light emitting control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0168] In the data writing sub-phase t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 through a corresponding gate signal line among the plurality of gate signal lines GL to turn on the sixth transistor T6; to allow an initialization voltage signal from a corresponding initialization signal line among the plurality of initialization signal lines Vint to be transferred from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and further to the node N4. The anode of the light emitting element LE is initialized.

[0169] In the light-emitting sub-stage t3, a cut-off reset control signal is again provided to the gate of the first transistor T1 through the corresponding reset control signal line among the plurality of reset control signal lines rst to cut off the first transistor T1. The corresponding gate signal line among the plurality of gate signal lines GL is provided with a cut-off signal, and the second transistor T2 and the third transistor T3 are cut off. The corresponding light-emitting control signal line among the plurality of light-emitting control signal lines em is provided with a low voltage signal to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting sub-stage t3, the voltage level at the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and operates in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0170] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, and respective third sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0171] In another example, the array of multiple sub-pixels includes a repeating array of the S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0172] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0173] In an alternative embodiment, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0174] Figure 3A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Figure 3B It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Figure 3C It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Figure 3D It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Figure 3E It is shown Figure 3A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG. Figure 3F It is shown Figure 3A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG. Figure 3G It is shown Figure 3A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG. Fig. 3I It is shown Figure 3A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG. Figure 3J It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG. Figure 3K It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG. Figure 3L It is shown Figure 3A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG. Figure 3M It is shown Figure 3A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG. Figure 4 is along Figure 3A Cross-sectional view along line A-A'.

[0175] Reference FIG. 3A to FIG. 3M and Figure 4In some embodiments, the array substrate includes: a base substrate BS; a semiconductor material layer SML, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1, which is located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN, which is located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2, which is located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD, which is located on a side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL1, which is located on a side of the interlayer dielectric layer ILD away from the second conductive layer CT2; a passivation layer PVX, It is located on the side of the first signal line SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2 is located on the side of the passivation layer PVX away from the first signal line layer SL1; the first planarization layer PLN1 is located on the side of the second signal line layer SL2 away from the passivation layer PVX; the third signal line layer SL3 is located on the side of the first planarization layer PLN1 away from the second signal line layer SL2; the second planarization layer PLN2 is located on the side of the third signal line layer SL3 away from the first planarization layer PLN1; the anode layer ADL is located on the side of the second planarization layer PLN2 away from the third signal line layer SL3; and the pixel defining layer PDL is located on the side of the anode layer ADL away from the second planarization layer PLN2.

[0176] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3B, the corresponding pixel driving circuit is marked with reference numerals, which represent the regions corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td) in the corresponding pixel driving circuit. The corresponding pixel driving circuit is also marked with reference numerals representing the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuits are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuits, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located in the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are located in the same layer.

[0177] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of which on the substrate substrate overlaps with the orthographic projection of the gate on the substrate substrate. A first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion located between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the first gate on the substrate substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the second gate on the substrate substrate. In the context of a dual-gate transistor, a first electrode refers to a component of a transistor connected to a side of the first portion away from the third portion, and a second electrode refers to a component of a transistor connected to a side of the second portion away from the third portion.

[0178] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C In some embodiments, the first conductive layer includes a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of a storage capacitor Cst are located in the same layer.

[0179] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of gate signal lines GL and the first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the plurality of gate signal lines GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the step of forming the plurality of gate signal lines GL and the step of forming the first capacitor electrode Ce1, the plurality of gate signal lines GL and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0180] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3D In some embodiments, the second conductive layer includes a plurality of initialization signal lines Vint and a second capacitor electrode Ce2 of a storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on a substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of initialization signal lines Vint and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0181] Figure 3E A via extending through the interlayer dielectric layer ILD is depicted in FIG.

[0182] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3F In some embodiments, the first signal line layer includes a node connection line Cln, a voltage connection pad VCP, a data signal connection pad DCP, an electrode connection line Cle, and a reset signal connection line Cli. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sublayers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection line Cln, the voltage connection pad VCP, the data signal connection pad DCP, the electrode connection line Cle, and the reset signal connection line Cli are located in the same layer.

[0183] The node connection line Cln is connected to the first capacitor electrode Ce1 and is connected to the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1 in the corresponding pixel driving circuit. The data signal connection pad DCP connects the corresponding data line among the plurality of data lines to the first electrode of the second transistor T2. The reset signal connection line Cli connects the corresponding initialization signal line among the plurality of initialization signal lines to the first electrode of the first transistor T1 and the sixth transistor T6. The voltage connection pad VCP connects the corresponding voltage supply line among the plurality of voltage supply lines to the first electrode of the fourth transistor T4, and connects the corresponding voltage supply line among the plurality of voltage supply lines to the second capacitor electrode of the storage capacitor. The electrode connection line Cle is respectively connected to the second electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6.

[0184] Figure 3G A via extending through the passivation layer PVX is depicted in FIG.

[0185] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3H In some embodiments, the second signal line layer includes a plurality of voltage supply lines Vdd and a plurality of data lines DL. Each of the plurality of voltage supply lines Vdd includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 that are alternately arranged. Each of the plurality of first voltage supply line portions Vdd-1 and the corresponding second voltage supply line portions Vdd-2 are connected via a voltage connection bridge located in the third signal line layer. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 via a data signal connection pad located in the first signal line layer.

[0186] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, substantially transparent conductive materials, such as metal oxide conductive materials. In one example, the second signal line layer includes indium tin oxide. Optionally, multiple voltage supply lines Vdd and multiple data lines DL are located in the same layer. As used herein, the term "substantially transparent" means that at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, and at least 95%) of incident light in the visible light wavelength range is transmitted therethrough.

[0187] Fig. 3I A via extending through the first planarization layer PLN1 is depicted in FIG.

[0188] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3J In some embodiments, the third signal line layer includes a voltage connection bridge VCB and an anode connection pad ACP. The voltage connection bridge VCB connects the first voltage supply line portion located in the second signal line layer and the second voltage supply line portion located in the second signal line layer. The anode connection pad ACP is respectively connected to the fourth node N4 and the corresponding anode in the corresponding sub-pixel. The anode connection pad ACP is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in the corresponding sub-pixel is connected to the anode connection pad ACP.

[0189] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the third signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the third signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes a plurality of sublayers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the voltage connection bridge VCB is located in the same layer as the anode connection pad ACP.

[0190] Figure 3K A via extending through the second planarization layer PLN2 is depicted in FIG.

[0191] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3L In some embodiments, the anode layer includes anodes of corresponding light emitting elements. The anodes are connected to anode connection pads located in the third signal line layer, and the anode connection pads are connected to second electrodes of the fifth transistor T5 and the sixth transistor T6.

[0192] Figure 3M A via extending through the pixel definition layer PDL is depicted in FIG. Figure 3M , the array substrate includes a sub-pixel opening SA configured to accommodate the light emitting material.

[0193] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M and Figure 4In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. In some embodiments, the array substrate further includes a first via v1 and a second via v2. The first via v1 extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor and / or the second electrode D1 of the first transistor, as shown in FIG. Figure 4 Depicted.

[0194] In some embodiments, the array substrate further includes a third via v3 and a fourth via v4. The voltage connection bridge VCB is connected to a corresponding first voltage supply line portion in the plurality of first voltage supply line portions Vdd-1 through the third via v3, and is connected to a corresponding second voltage supply line portion in the plurality of second voltage supply line portions Vdd-2 through the fourth via v4. In one example, the third via v3 extends through the first planarization layer PLN1. In another example, the fourth via v4 extends through the first planarization layer PLN1.

[0195] In some embodiments, the array substrate further includes a fifth via v5. A corresponding voltage supply line (e.g., a corresponding second voltage supply line portion in a plurality of second voltage supply line portions Vdd-2 of the corresponding voltage supply line) is connected to the voltage connection pad VCP through the fifth via v5. In one example, the fifth via v5 extends through the passivation layer PVX.

[0196] In some embodiments, the array substrate further includes a sixth via v6. The voltage connection pad VCP is connected to the first electrode S4 of the fourth transistor T4 through the sixth via v6, thereby providing a voltage supply signal to the first electrode S4 of the fourth transistor T4. In one example, the sixth via v6 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0197] Figure 5A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Figure 5B It is shown Figure 5A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Figure 5D It is shown Figure 5A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Figure 5E It is shown Figure 5A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG. Fig. 5F It is shown Figure 3A Schematic diagram of the structure of the first signal line layer in a part of the array substrate. Figure 5G It is shown Figure 5A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG. Figure 5H It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG. Fig.5I It is shown Figure 5A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG. Figure 5J It is shown Figure 5A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG. Figure 5K It is shown Figure 5A Schematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG. Figure 5L It is shown Figure 5A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG. Figure 5M It is shown Figure 5A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0198] In some embodiments, reference Figure 5A , a minimum repeating unit of a plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3. Figure 3A A portion of the array substrate depicted in Figure 5A A portion of the corresponding third sub-pixel sp3 is depicted in FIG.

[0199] In some embodiments, each of the corresponding first subpixel sp1, the corresponding second subpixel sp2 and the corresponding third subpixel sp3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td and a storage capacitor Cst.

[0200] In some embodiments, the corresponding first sub-pixel sp1 is a sub-pixel of a first color (e.g., red), the corresponding second sub-pixel sp2 is a sub-pixel of a second color (e.g., green), and the corresponding third sub-pixel sp3 is a sub-pixel of a third color (e.g., blue). In some embodiments, the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 are three sub-pixels of a pixel in the array substrate.

[0201] Reference Figure 5A , Figure 5H and Figure 5J In some embodiments, each of the plurality of voltage supply lines Vdd includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 alternately arranged in the second signal line layer. Each of the plurality of first voltage supply line portions Vdd-1 and the corresponding second voltage supply line portion of the plurality of second voltage supply line portions Vdd-2 are connected via a voltage connection bridge VCB in the third signal line layer.

[0202] Figure 6 is a schematic diagram showing a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. Figure 5A , Figure 5H , Figure 5J and Figure 6 In some embodiments, the array substrate includes a plurality of voltage connection bridges VCBS. Optionally, the plurality of voltage connection bridges VCBS are arranged in an array of multiple rows and columns. The plurality of voltage supply lines Vdd include a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3. Optionally, the first adjacent voltage supply line AVdd1 is configured to provide a voltage supply signal to a first pixel drive circuit PDC1 in a corresponding first sub-pixel Sp1, the second adjacent voltage supply line AVdd2 is configured to provide a voltage supply signal to a second pixel drive circuit PDC2 in a corresponding second sub-pixel Sp2, and the third adjacent voltage supply line AVdd3 is configured to provide a voltage supply signal to a third pixel drive circuit PDC3 in a corresponding third sub-pixel Sp3.

[0203] In some embodiments, each of the plurality of voltage connection bridges VCBS is connected to a first adjacent voltage supply line AVdd1 , a second adjacent voltage supply line AVdd2 , and a third adjacent voltage supply line AVdd3 , respectively.

[0204] In some embodiments, each of the first adjacent voltage supply line AVdd1, the second adjacent voltage supply line AVdd2, and the third adjacent voltage supply line AVdd3 includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 alternately arranged in the second signal line layer. In some embodiments, each of the plurality of voltage connection bridges VCBS is respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the first adjacent voltage supply line AVdd1, respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the second adjacent voltage supply line AVdd2, and respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the third adjacent voltage supply line AVdd3.

[0205] In some embodiments, a plurality of voltage supply lines (including a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3) are located at the second signal line layer, and a plurality of voltage connection bridges VCBS are located at the third signal line layer.

[0206] In some embodiments, the signal lines in the second signal line layer are made of a substantially transparent conductive material, thereby allowing a plurality of light-transmitting regions to exist in the array substrate. Figure 7 Schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Figure 7 In some embodiments, the array substrate includes a plurality of light-transmitting regions TR that allow light to pass through. In the plurality of light-transmitting regions TR, signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, and a plurality of second voltage supply line portions) exist, while signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer do not exist. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0207] In some embodiments, two adjacent voltage connection bridges among the plurality of voltage connection bridges VCBS in the same pixel row are connected to the same voltage supply line among the plurality of voltage supply lines, such as Figure 6 Depicted. Fig. 9 In some embodiments, the pixel row includes an m-th row of sub-pixels Rm, an (m+1)-th row of sub-pixels R(m+1), and an (m+2)-th row of sub-pixels R(m+2).

[0208] In some embodiments, the voltage connection bridges in the plurality of voltage connection bridges VCBS in the same pixel column are connected to the same three adjacent voltage supply lines in the plurality of voltage supply lines. Fig. 9 In some embodiments, the pixel column includes an nth column sub-pixel Cn, an (n-1)th column sub-pixel C(n-1), and an (n+1)th column sub-pixel C(n+1).

[0209] In some embodiments, the array substrate is a full display with camera (FDC) array substrate, wherein the array substrate further includes photosensors located in the plurality of light-transmitting regions TR and configured to detect light.

[0210] Figure 8 is a schematic diagram showing a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Figure 5A , Figure 5D , Figure 5H and Figure 8 , each of the multiple initialization signal lines includes multiple first initialization signal line portions Vint-1 and multiple second initialization signal line portions Vint-2. The multiple first initialization signal line portions Vint-1 and the multiple second initialization signal line portions Vint-2 are located in two different layers. In one example, the multiple first initialization signal line portions Vint-1 are located in the second conductive layer, and the multiple second initialization signal line portions Vint-2 are located in the second signal line layer. Each of the multiple second initialization signal line portions Vint-2 is respectively connected to two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1 are connected through a separate second initialization signal line portion in the multiple second initialization signal line portions Vint-2.

[0211] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1 and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. In one example, the plurality of first initialization signal line portions Vint-1 are located in the second conductive layer, and the plurality of third initialization signal line portions Vint-3 are located in the second signal line layer. Each of the plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 in the same row. Two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 are connected via a separate third initialization signal line portion in the plurality of third initialization signal line portions Vint-3.

[0212] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of second initialization signal line portions Vint-2 are located in two different layers; and the plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. Optionally, the plurality of second initialization signal line portions Vint-2 and the plurality of third initialization signal line portions Vint-3 are located in the same layer. In one example, the plurality of first initialization signal line portions Vint-1 are located in the second conductive layer, the plurality of second initialization signal line portions Vint-2 are located in the second signal line layer, and the plurality of third initialization signal line portions Vint-3 are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0213] In some embodiments, each second initialization signal line portion in a plurality of second initialization signal line portions Vint-2 is respectively connected to two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1. Each third initialization signal line portion in a plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1 are connected by a separate second initialization signal line portion in a plurality of second initialization signal line portions Vint-2, and are connected by a separate third initialization signal line portion in a plurality of third initialization signal line portions Vint-3. Two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1, a separate second initialization signal line portion in a plurality of second initialization signal line portions Vint-2, and a separate third initialization signal line portion in a plurality of third initialization signal line portions Vint-3 form a first ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having a sub-pixel. In one example, the first ring substantially surrounds an area of ​​transistors and capacitors having a corresponding first sub-pixel. In another example, the first ring substantially surrounds the area of ​​transistors and capacitors having sub-pixels of the first color. In another example, the first ring substantially surrounds the area of ​​transistors and capacitors having red sub-pixels. As used herein, the term "substantially surrounds" means at least 50% surrounding, such as at least 55% surrounding, at least 60% surrounding, at least 65% surrounding, at least 70% surrounding, at least 75% surrounding, at least 80% surrounding, at least 85% surrounding, at least 90% surrounding, at least 95% surrounding, at least 99% surrounding, or 100% surrounding.

[0214] In some embodiments, the array substrate includes a plurality of first rings LPS1 arranged in a row. Optionally, the plurality of first rings LPS1 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0215] In some embodiments, the plurality of first rings LPS1 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of first rings LPS1 substantially surrounds the region of the anode of the red sub-pixel.

[0216] Fig. 9is a schematic diagram showing a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig. 9 , the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig. 9 A corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2 and a corresponding third sub-pixel sp3 are represented in FIG.

[0217] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0218] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 5A to FIG. 5M and Fig. 9 In some embodiments, a first initialization signal line portion among multiple first initialization signal line portions Vint-1 is connected to a first electrode of one or more reset transistors in a pixel driving circuit in a third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to a first electrode of one or more reset transistors in a pixel driving circuit in a first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to a first electrode of one or more reset transistors in a pixel driving circuit in a second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0219] In some embodiments, a second initialization signal line portion among multiple second initialization signal line portions Vint-2 connects the first initialization signal line portion with a first adjacent first initialization signal line portion, and the first adjacent first initialization signal line portion is connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0220] In some embodiments, a third initialization signal line portion among multiple third initialization signal line portions Vint-3 connects the first initialization signal line portion with a second adjacent first initialization signal line portion, and the second adjacent first initialization signal line portion is connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0221] Fig.10 is a schematic diagram showing a gate scanning signal network in a portion of an array substrate according to some embodiments of the present disclosure. Figure 5A , Figure 5C , Figure 5H and Fig.10 , each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line parts GL-1 and a plurality of second gate signal line parts GL-2. A plurality of first gate signal line parts GL-1 and a plurality of second gate signal line parts GL-2 are located in two different layers. In one example, a plurality of first gate signal line parts GL-1 are located in the first conductive layer, and a plurality of second gate signal line parts GL-2 are located in the second signal line layer. Each second gate signal line part in a plurality of second gate signal line parts GL-2 is connected to two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1, respectively. Two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 are connected by a separate second gate signal line part in a plurality of second gate signal line parts GL-2.

[0222] In certain embodiments, each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line parts GL-1 and a plurality of third gate signal line parts GL-3. A plurality of first gate signal line parts GL-1 and a plurality of third gate signal line parts GL-3 are located in two different layers. In one example, a plurality of first gate signal line parts GL-1 are located in the first conductive layer, and a plurality of third gate signal line parts GL-3 are located in the second signal line layer. Each third gate signal line part in a plurality of third gate signal line parts GL-3 is respectively connected to two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 in the same row. Two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 are connected by a separate third gate signal line part in a plurality of third gate signal line parts GL-3.

[0223] In some embodiments, each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line portions GL-1, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3. A plurality of first gate signal line portions GL-1 and a plurality of second gate signal line portions GL-2 are located in two different layers; and a plurality of first gate signal line portions GL-1 and a plurality of third gate signal line portions GL-3 are located in two different layers. Optionally, a plurality of second gate signal line portions GL-2 and a plurality of third gate signal line portions GL-3 are located in the same layer. In one example, a plurality of first gate signal line portions GL-1 are located in a first conductive layer, a plurality of second gate signal line portions GL-2 are located in a second signal line layer, and a plurality of third gate signal line portions GL-3 are located in a second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0224] In some embodiments, each second gate signal line portion in a plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1. Each third gate signal line portion in a plurality of third gate signal line portions GL-3 is connected to two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1. Two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1 are connected by a separate second gate signal line portion in a plurality of second gate signal line portions GL-2, and are connected by a separate third gate signal line portion in a plurality of third gate signal line portions GL-3. Two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1, a separate second gate signal line portion in a plurality of second gate signal line portions GL-2, and a separate third gate signal line portion in a plurality of third gate signal line portions GL-3 form a second ring, which substantially surrounds the region of transistors and capacitors of the pixel driving circuit having sub-pixels. In one example, the second ring substantially surrounds the region of transistors and capacitors having corresponding first sub-pixels. In another example, the second ring substantially surrounds the region of transistors and capacitors of sub-pixels having a first color. In another example, the second ring substantially surrounds the area having the transistor and capacitor of the red sub-pixel.

[0225] In some embodiments, the array substrate includes a plurality of second rings LPS2 arranged in a row. Optionally, the plurality of second rings LPS2 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0226] In some embodiments, the plurality of second rings LPS2 respectively substantially surround the region of the anodes of the sub-pixels having the same color. Each second ring in the plurality of second rings LPS2 substantially surrounds the region of the anodes of the sub-pixels having the same color. In one example, the plurality of second rings LPS2 substantially surrounds the region of the anodes of the red sub-pixels.

[0227] Fig.11 is a schematic diagram showing a gate scanning signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.11, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.11 , a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3 are represented.

[0228] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0229] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 5A to FIG. 5M and Fig.11 In some embodiments, a first gate signal line portion among the plurality of first gate signal line portions GL-1 is connected to gates of one or more data write transistors in a pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), is connected to gates of one or more data write transistors in a pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and is connected to gates of one or more data write transistors in a pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0230] In some embodiments, a second gate signal line portion GL-2 among a plurality of second gate signal line portions GL-2 connects a first gate signal line portion with a first adjacent first gate signal line portion, and the first adjacent first gate signal line portion is connected to the gate of one or more data write transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0231] In some embodiments, a third gate signal line portion GL-3 among a plurality of third gate signal line portions GL-3 connects the first gate signal line portion with a second adjacent first gate signal line portion, and the second adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0232] Fig.12 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure. Figure 5A , Figure 5C , Figure 5H and Fig.12 , each of the multiple reset control signal lines includes multiple first reset control signal line sections rst-1 and multiple second reset control signal line sections rst-2. Multiple first reset control signal line sections rst-1 and multiple second reset control signal line sections rst-2 are located in two different layers. In one example, multiple first reset control signal line sections rst-1 are located in the first conductive layer, and multiple second reset control signal line sections rst-2 are located in the second signal line layer. Each of the multiple second reset control signal line sections rst-2 is respectively connected to two adjacent first reset control signal line sections in the multiple first reset control signal line sections rst-1. Two adjacent first reset control signal line sections in the multiple first reset control signal line sections rst-1 are connected through a separate second reset control signal line section in the multiple second reset control signal line sections rst-2.

[0233] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in the first conductive layer, and the plurality of third reset control signal line portions rst-3 are located in the second signal line layer. Each of the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 in the same row. Two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 are connected by a separate third reset control signal line portion in the plurality of third reset control signal line portions rst-3.

[0234] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers; and the plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. Optionally, the plurality of second reset control signal line portions rst-2 and the plurality of third reset control signal line portions rst-3 are located in the same layer. In one example, the plurality of first reset control signal line portions rst-1 are located in the first conductive layer, the plurality of second reset control signal line portions rst-2 are located in the second signal line layer, and the plurality of third reset control signal line portions rst-3 are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0235] In some embodiments, each second reset control signal line portion of the plurality of second reset control signal line portions rst-2 is respectively connected to two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1. Each third reset control signal line portion of the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1. Two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1 are connected through a separate second reset control signal line portion of the plurality of second reset control signal line portions rst-2, and are connected through a separate third reset control signal line portion of the plurality of third reset control signal line portions rst-3. Two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1, a separate second reset control signal line portion of the plurality of second reset control signal line portions rst-2, and a separate third reset control signal line portion of the plurality of third reset control signal line portions rst-3 form a third ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels. In one example, the third ring substantially surrounds the region with transistors and capacitors for the corresponding first sub-pixel. In another example, the third ring substantially surrounds the region with transistors and capacitors for sub-pixels of the first color. In another example, the third ring substantially surrounds the region with transistors and capacitors for sub-pixels of the red color.

[0236] In some embodiments, the array substrate includes a plurality of third rings LPS3 arranged in a row. Optionally, the plurality of third rings LPS3 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of third rings LPS3 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of third rings LPS3 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0237] In some embodiments, the plurality of third rings LPS3 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each third ring in the plurality of third rings LPS3 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of third rings LPS3 substantially surrounds the region of the anode of the red sub-pixel.

[0238] Fig.13 is a schematic diagram showing a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.13, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.13 , a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3 are represented.

[0239] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0240] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 5A to FIG. 5M and Fig.13 In some embodiments, a first reset control signal line portion among multiple first reset control signal line portions rst-1 is connected to the gates of one or more reset control transistors in the pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gates of one or more reset control transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gates of one or more reset control transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0241] In some embodiments, a second reset control signal line portion among a plurality of second reset control signal line portions rst-2 connects the first reset control signal line portion with a first adjacent first reset control signal line portion, and the first adjacent first reset control signal line portion is connected to the gates of one or more reset control transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0242] In some embodiments, a third reset control signal line portion among multiple third reset control signal line portions rst-3 connects the first reset control signal line portion with a second adjacent first reset control signal line portion, and the second adjacent first reset control signal line portion is connected to the gates of one or more reset control transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0243] Fig.14 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure. Figure 5A , Figure 5C , Figure 5H and Fig.14 , each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of second light-emitting control signal line portions em-2. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, and the plurality of second light-emitting control signal line portions em-2 are located in the second signal line layer. Each of the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2.

[0244] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, and the plurality of third light-emitting control signal line portions em-3 are located in the second signal line layer. Each of the plurality of third light-emitting control signal line portions em-3 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 in the same row. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected by a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3.

[0245] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1, a plurality of second light-emitting control signal line portions em-2, and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers; and the plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. Optionally, the plurality of second light-emitting control signal line portions em-2 and the plurality of third light-emitting control signal line portions em-3 are located in the same layer. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, the plurality of second light-emitting control signal line portions em-2 are located in the second signal line layer, and the plurality of third light-emitting control signal line portions em-3 are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second light-emission control signal line portions em-2, and a plurality of third light-emission control signal line portions em-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0246] In some embodiments, each second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Each third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2, and are connected through a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1, a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2, and a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3 form a fourth ring, which substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having a sub-pixel. In one example, the fourth ring substantially surrounds an area of ​​transistors and capacitors having a corresponding first sub-pixel. In another example, the fourth ring substantially surrounds the region of transistors and capacitors having sub-pixels of the first color. In another example, the fourth ring substantially surrounds the region of transistors and capacitors having sub-pixels of the red color.

[0247] In some embodiments, the array substrate includes a plurality of fourth rings LPS4 arranged in a row. Optionally, the plurality of fourth rings LPS4 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0248] In some embodiments, the plurality of fourth rings LPS4 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of fourth rings LPS4 substantially surrounds the region of the anode of the red sub-pixel.

[0249] Fig.15 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure. Fig.15, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.15 A corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3 are represented in FIG.

[0250] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0251] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 5A to FIG. 5M and Fig.15 In some embodiments, a first light-emitting control signal line portion among multiple first light-emitting control signal line portions em-1 is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel.

[0252] In some embodiments, a second light-emitting control signal line portion among a plurality of second light-emitting control signal line portions em-2 connects the first light-emitting control signal line portion with a first adjacent first light-emitting control signal line portion, and the first adjacent first light-emitting control signal line portion is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0253] In some embodiments, a third light emitting control signal line portion among a plurality of third light emitting control signal line portions em-3 connects the first light emitting control signal line portion with a second adjacent first light emitting control signal line portion, and the second adjacent first light emitting control signal line portion is connected to the gates of one or more light emitting control transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0254] Reference Figure 5A , Figure 5C , Figure 5H as well as Figures 8 to 15 In some embodiments, the array substrate includes a plurality of signal lines, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of second signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of second signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of second signal line portions are located in a second signal line layer. Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions are connected through a separate second signal line portion of the plurality of second signal line portions.

[0255] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of third signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of third signal line portions are located in a second signal line layer. Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions in the same row. Two adjacent first signal line portions of the plurality of first signal line portions are connected by a separate third signal line portion of the plurality of third signal line portions.

[0256] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; and the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the same layer. In one example, the plurality of first signal line portions are located in the first conductive layer, the plurality of second signal line portions are located in the second signal line layer, and the plurality of third signal line portions are located in the second signal line layer. In one example, the plurality of first signal line portions are located in the second conductive layer, the plurality of second signal line portions are located in the second signal line layer, and the plurality of third signal line portions are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In a plurality of light-transmitting regions TR, there are signal lines of the second signal line layer, but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light may pass through the plurality of light-transmitting regions TR.

[0257] In some embodiments, each second signal line portion in a plurality of second signal line portions is respectively connected to two adjacent first signal line portions in a plurality of first signal line portions. Each third signal line portion in a plurality of third signal line portions is respectively connected to two adjacent first signal line portions in a plurality of first signal line portions. Two adjacent first signal line portions in a plurality of first signal line portions are connected by a separate second signal line portion in a plurality of second signal line portions, and are connected by a separate third signal line portion in a plurality of third signal line portions. Two adjacent first signal line portions in a plurality of first signal line portions, a separate second signal line portion in a plurality of second signal line portions, and a separate third signal line portion in a plurality of third signal line portions form a ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels. In one example, the ring substantially surrounds an area of ​​transistors and capacitors having corresponding first sub-pixels. In another example, the ring substantially surrounds an area of ​​transistors and capacitors having sub-pixels of a first color. In another example, the ring substantially surrounds an area of ​​transistors and capacitors having red sub-pixels.

[0258] In some embodiments, the array substrate includes a plurality of rings arranged in a row. Optionally, the plurality of rings substantially surround the region of the pixel drive circuit of the sub-pixel of the same color. Each of the plurality of rings substantially surrounds the region of the pixel drive circuit of the sub-pixel of the same color. In one example, the plurality of rings substantially surrounds the region of the pixel drive circuit of the red sub-pixel.

[0259] In some embodiments, the plurality of rings respectively substantially surround the region of the anode of the sub-pixels having the same color. Each of the plurality of rings substantially surrounds the region of the anode of the sub-pixels having the same color. In one example, the plurality of rings substantially surrounds the region of the anode of the red sub-pixel.

[0260] In some embodiments, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. The first color, the second color, and the third color are three different colors. In one example, the first color is red, the second color is green, and the third color is blue.

[0261] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0262] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 5A to FIG. 5M as well as Figures 8 to 15 In some embodiments, a first signal line portion among multiple first signal line portions is connected to one or more transistors in a pixel driving circuit in a third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to one or more transistors in a pixel driving circuit in a first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0263] In some embodiments, a second signal line portion among a plurality of second signal line portions connects the first signal line portion with a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0264] In some embodiments, a third signal line portion among a plurality of third signal line portions connects the first signal line portion and a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0265] Fig.16A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig. 16B It is shown Fig.16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig. 16C It is shown Fig.16A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.16D It is shown Fig.16A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Fig.16E It is shown Fig.16A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG. Fig.16F It is shown Fig.16A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG. Figure 16G It is shown Fig.16A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG. Fig.16H It is shown Fig.16A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG. Fig.16I It is shown Fig.16A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG. Fig.16J It is shown Fig.16A Schematic diagram of the structure of the third signal line layer in a portion of the array substrate described in . Figure 16K It is shown Fig.16A Schematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG. Figure 16L It is shown Fig.16A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG. Figure 16M It is shown Fig.16ASchematic diagram of the structure of a pixel defining layer in a portion of an array substrate.

[0266] Fig.17A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig. 17B It is shown Fig.17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig. 17C It is shown Fig.17A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.17D It is shown Fig.17A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Fig.17E It is shown Fig.17A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG. Fig.17F It is shown Fig.17A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG. Figure 17G It is shown Fig.17A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG. Fig.17H It is shown Fig.17A A schematic diagram of the structure of the second signal line layer in a portion of an array substrate depicted in FIG. Fig.17I It is shown Fig.17A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG. Fig.17J It is shown Fig.17A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG. Figure 17K It is shown Fig.17A Schematic diagram of the structure of the second planarization layer in a portion of an array substrate depicted in FIG. Figure 17L It is shown Fig.17A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG. Fig.17M It is shown Fig.17A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0267] FIG. 16A to FIG. 16M and FIG. 17A to FIG. 17M The array substrate depicted in FIG. 3A to FIG. 3M and FIG. 5A to FIG. 5M The difference between the array substrate depicted in FIG. 1 and FIG. 2 is that FIG. 16A to FIG. 16M and FIG. 17A to FIG. 17M The extending directions of the multiple initialization signal lines, the multiple reset control signal lines, the multiple gate signal lines and the multiple light emission control signal lines in the array substrate depicted in FIG. FIG. 3A to FIG. 3M and FIG. 5A to FIG. 5MThe multiple initialization signal lines, multiple reset control signal lines, multiple gate signal lines, and multiple light emission control signal lines in the array substrate depicted in the drawing have different extending directions.

[0268] Reference Figure 2A , Figure 2B , Fig.16A and Fig. 16B , the corresponding pixel driving circuit is marked with reference numerals, which represent the regions corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td) in the corresponding pixel driving circuit. The corresponding pixel driving circuit is also marked with reference numerals representing the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd.

[0269] Reference Figure 2A , Figure 2B , Fig.16A and Fig. 16C In some embodiments, the first conductive layer includes a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of the storage capacitor Cst.

[0270] Reference Figure 2A , Figure 2B , Fig.16A and Fig.16D In some embodiments, the second conductive layer includes a plurality of initialization signal lines Vint and a second capacitor electrode Ce2 of the storage capacitor Cst.

[0271] Fig.16E A via extending through the interlayer dielectric layer ILD is depicted in FIG.

[0272] Reference Figure 2A , Figure 2B , Fig.16A and Fig.16F In some embodiments, the first signal line layer includes a node connection line Cln, a voltage connection pad VCP, a data signal connection pad DCP, an electrode connection line Cle, and a reset signal connection line Cli.

[0273] The node connection line Cln connects the first capacitor electrode Ce1 to the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1 in the corresponding pixel driving circuit, respectively. The data signal connection pad DCP connects the corresponding data line among the plurality of data lines to the first electrode of the second transistor T2. The reset signal connection line Cli connects the corresponding initialization signal line among the plurality of initialization signal lines to the first electrode of the first transistor T1 and the sixth transistor T6. The voltage connection pad VCP connects the corresponding voltage supply line among the plurality of voltage supply lines to the first electrode of the fourth transistor T4, and connects the corresponding voltage supply line among the plurality of voltage supply lines to the second capacitor electrode of the storage capacitor. The electrode connection line Cle is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6, respectively.

[0274] Figure 16G A via extending through the passivation layer PVX is depicted in FIG.

[0275] Reference Figure 2A , Figure 2B , Fig.16A and Fig.16H In some embodiments, the second signal line layer includes a plurality of voltage supply lines Vdd and a plurality of data lines DL. Each of the plurality of voltage supply lines Vdd includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 that are alternately arranged. Each of the plurality of first voltage supply line portions Vdd-1 and the corresponding second voltage supply line portions Vdd-2 are connected via a voltage connection bridge located in the third signal line layer. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 via a data signal connection pad located in the first signal line layer.

[0276] Fig.16I A via extending through the first planarization layer PLN1 is depicted in FIG.

[0277] Reference Figure 2A , Figure 2B , Fig.16A and Fig.16J In some embodiments, the third signal line layer includes a voltage connection bridge VCB and an anode connection pad ACP. The voltage connection bridge VCB connects the first voltage supply line portion located in the second signal line layer and the second voltage supply line portion located in the second signal line layer. The anode connection pad ACP is respectively connected to the fourth node N4 and the corresponding anode in the corresponding sub-pixel. The anode connection pad ACP is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in the corresponding sub-pixel is connected to the anode connection pad ACP.

[0278] Figure 16K A via extending through the second planarization layer PLN2 is depicted in FIG.

[0279] Reference Figure 2A , Figure 2B , Fig.16A and Figure 16L In some embodiments, the anode layer includes anodes of corresponding light emitting elements. The anodes are connected to anode connection pads in the third signal line layer, and the anode connection pads are connected to second electrodes of the fifth transistor T5 and the sixth transistor T6.

[0280] Figure 16M A via extending through the pixel definition layer PDL is depicted in FIG. Figure 16M , the array substrate includes a sub-pixel opening SA configured to accommodate the light emitting material.

[0281] In some embodiments, reference Fig.17A , a minimum repeating unit of a plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3. Fig.16A A portion of the array substrate depicted in Fig.17A A portion of the corresponding third sub-pixel sp3 depicted in FIG.

[0282] In some embodiments, each of the corresponding first subpixel sp1, the corresponding second subpixel sp2 and the corresponding third subpixel sp3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td and a storage capacitor Cst.

[0283] In some embodiments, the corresponding first sub-pixel sp1 is a sub-pixel of a first color (e.g., red), the corresponding second sub-pixel sp2 is a sub-pixel of a second color (e.g., green), and the corresponding third sub-pixel sp3 is a sub-pixel of a third color (e.g., blue). In some embodiments, the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 are three sub-pixels of a pixel in the array substrate.

[0284] Reference Fig.17A , Fig.17H and Fig.17J In some embodiments, each of the plurality of voltage supply lines Vdd includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 alternately arranged in the second signal line layer. Each of the plurality of first voltage supply line portions Vdd-1 and the corresponding second voltage supply line portion of the plurality of second voltage supply line portions Vdd-2 are connected via a voltage connection bridge VCB in the third signal line layer.

[0285] Fig.18 is a schematic diagram showing a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.17A , Fig.17H , Fig.17J and Fig.18 In some embodiments, the array substrate includes a plurality of voltage connection bridges VCBS. Optionally, the plurality of voltage connection bridges VCBS are arranged in an array of multiple rows and columns. The plurality of voltage supply lines Vdd include a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3. Optionally, the first adjacent voltage supply line AVdd1 is configured to provide a voltage supply signal to a first pixel drive circuit in a corresponding first sub-pixel Sp1, the second adjacent voltage supply line AVdd2 is configured to provide a voltage supply signal to a second pixel drive circuit in a corresponding second sub-pixel Sp2, and the third adjacent voltage supply line AVdd3 is configured to provide a voltage supply signal to a third pixel drive circuit in a corresponding third sub-pixel Sp3.

[0286] In some embodiments, each of the plurality of voltage connection bridges VCBS is connected to a first adjacent voltage supply line AVdd1 , a second adjacent voltage supply line AVdd2 , and a third adjacent voltage supply line AVdd3 , respectively.

[0287] In some embodiments, each of the first adjacent voltage supply line AVdd1, the second adjacent voltage supply line AVdd2, and the third adjacent voltage supply line AVdd3 includes a plurality of first voltage supply line portions Vdd-1 and a plurality of second voltage supply line portions Vdd-2 alternately arranged in the second signal line layer. In some embodiments, each of the plurality of voltage connection bridges VCBS is respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the first adjacent voltage supply line AVdd1, respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the second adjacent voltage supply line AVdd2, and respectively connected to the first adjacent voltage supply line portion AVdd-1 and the second adjacent voltage supply line portion AVdd-2 of the third adjacent voltage supply line AVdd3.

[0288] In some embodiments, a plurality of voltage supply lines (including a first adjacent voltage supply line AVdd1, a second adjacent voltage supply line AVdd2, and a third adjacent voltage supply line AVdd3) are located in the second signal line layer, and a plurality of voltage connection bridges VCBS are located in the third signal line layer.

[0289] In some embodiments, the signal lines in the second signal line layer are made of a substantially transparent conductive material, thereby allowing a plurality of light-transmitting regions to exist in the array substrate. Fig.19 Schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig.19 In some embodiments, the array substrate includes a plurality of light-transmitting regions TR that allow light to pass through. In the plurality of light-transmitting regions TR, signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, and a plurality of second voltage supply line portions) exist, while signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer do not exist. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0290] In some embodiments, two adjacent voltage connection bridges among the plurality of voltage connection bridges VCBS in the same pixel row are connected to the same voltage supply line among the plurality of voltage supply lines, such as Fig.18 Depicted. Fig. 9 In some embodiments, the pixel row includes an m-th row of sub-pixels Rm, an (m+1)-th row of sub-pixels R(m+1), and an (m+2)-th row of sub-pixels R(m+2).

[0291] In some embodiments, the voltage connection bridges in the plurality of voltage connection bridges VCBS in the same pixel column are connected to the same three adjacent voltage supply lines in the plurality of voltage supply lines. Fig. 9 In some embodiments, the pixel column includes an nth column sub-pixel Cn, an (n-1)th column sub-pixel C(n-1), and an (n+1)th column sub-pixel C(n+1).

[0292] In some embodiments, the array substrate is a full display with camera (FDC) array substrate, wherein the array substrate further includes photosensors located in the plurality of light-transmitting regions TR and configured to detect light.

[0293] Fig. 20 is a schematic diagram showing a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.17A , Fig.17D , Fig.17H and Fig. 20, each of the multiple initialization signal lines includes multiple first initialization signal line portions Vint-1 and multiple second initialization signal line portions Vint-2. The multiple first initialization signal line portions Vint-1 and the multiple second initialization signal line portions Vint-2 are located in two different layers. In one example, the multiple first initialization signal line portions Vint-1 are located in the second conductive layer, and the multiple second initialization signal line portions Vint-2 are located in the second signal line layer. Each of the multiple second initialization signal line portions Vint-2 is respectively connected to two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1 are connected through a separate second initialization signal line portion in the multiple second initialization signal line portions Vint-2.

[0294] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1 and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. In one example, the plurality of first initialization signal line portions Vint-1 are located in the second conductive layer, and the plurality of third initialization signal line portions Vint-3 are located in the second signal line layer. Each of the plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 in the same row. Two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 are connected via a separate third initialization signal line portion in the plurality of third initialization signal line portions Vint-3.

[0295] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of second initialization signal line portions Vint-2 are located in two different layers; and the plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. Optionally, the plurality of second initialization signal line portions Vint-2 and the plurality of third initialization signal line portions Vint-3 are located in the same layer. In one example, the plurality of first initialization signal line portions Vint-1 are located in the second conductive layer, the plurality of second initialization signal line portions Vint-2 are located in the second signal line layer, and the plurality of third initialization signal line portions Vint-3 are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0296] In some embodiments, each second initialization signal line portion in a plurality of second initialization signal line portions Vint-2 is respectively connected to two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1. Each third initialization signal line portion in a plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1 are connected by a separate second initialization signal line portion in a plurality of second initialization signal line portions Vint-2, and are connected by a separate third initialization signal line portion in a plurality of third initialization signal line portions Vint-3. Two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1, a separate second initialization signal line portion in a plurality of second initialization signal line portions Vint-2, and a separate third initialization signal line portion in a plurality of third initialization signal line portions Vint-3 form a first ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having a sub-pixel. In one example, the first ring substantially surrounds an area of ​​transistors and capacitors having a corresponding first sub-pixel. In another example, the first ring substantially surrounds the region of transistors and capacitors having sub-pixels of a first color. In another example, the first ring substantially surrounds the region of transistors and capacitors having sub-pixels of a red color.

[0297] In some embodiments, the array substrate includes a plurality of first rings LPS1 arranged in a row. Optionally, the plurality of first rings LPS1 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0298] In some embodiments, the plurality of first rings LPS1 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of first rings LPS1 substantially surrounds the region of the anode of the red sub-pixel.

[0299] Fig.21 is a schematic diagram showing a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.21, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.21 , a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3 are represented.

[0300] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0301] Reference Figure 2A , Figure 2B , FIG. 16A to FIG. 16M , FIG. 17A to FIG. 17M and Fig.21 In some embodiments, a first initialization signal line portion among multiple first initialization signal line portions Vint-1 is connected to a first electrode of one or more reset transistors in a pixel driving circuit in a third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to a first electrode of one or more reset transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to a first electrode of one or more reset transistors in a pixel driving circuit in a first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0302] In some embodiments, a second initialization signal line portion among multiple second initialization signal line portions Vint-2 connects the first initialization signal line portion with a first adjacent first initialization signal line portion, and the first adjacent first initialization signal line portion is connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm.

[0303] In some embodiments, a third initialization signal line portion among multiple third initialization signal line portions Vint-3 connects the first initialization signal line portion with a second adjacent first initialization signal line portion, and the second adjacent first initialization signal line portion is connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0304] Fig. 22 is a schematic diagram showing a gate scanning signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.17A , Fig. 17C , Fig.17H and Fig. 22 , each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line parts GL-1 and a plurality of second gate signal line parts GL-2. A plurality of first gate signal line parts GL-1 and a plurality of second gate signal line parts GL-2 are located in two different layers. In one example, a plurality of first gate signal line parts GL-1 are located in the first conductive layer, and a plurality of second gate signal line parts GL-2 are located in the second signal line layer. Each second gate signal line part in a plurality of second gate signal line parts GL-2 is connected to two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1, respectively. Two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 are connected by a separate second gate signal line part in a plurality of second gate signal line parts GL-2.

[0305] In certain embodiments, each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line parts GL-1 and a plurality of third gate signal line parts GL-3. A plurality of first gate signal line parts GL-1 and a plurality of third gate signal line parts GL-3 are located in two different layers. In one example, a plurality of first gate signal line parts GL-1 are located in the first conductive layer, and a plurality of third gate signal line parts GL-3 are located in the second signal line layer. Each third gate signal line part in a plurality of third gate signal line parts GL-3 is respectively connected to two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 in the same row. Two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 are connected by a separate third gate signal line part in a plurality of third gate signal line parts GL-3.

[0306] In some embodiments, each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line portions GL-1, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3. A plurality of first gate signal line portions GL-1 and a plurality of second gate signal line portions GL-2 are located in two different layers; and a plurality of first gate signal line portions GL-1 and a plurality of third gate signal line portions GL-3 are located in two different layers. Optionally, a plurality of second gate signal line portions GL-2 and a plurality of third gate signal line portions GL-3 are located in the same layer. In one example, a plurality of first gate signal line portions GL-1 are located in a first conductive layer, a plurality of second gate signal line portions GL-2 are located in a second signal line layer, and a plurality of third gate signal line portions GL-3 are located in a second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0307] In some embodiments, each second gate signal line portion in a plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1. Each third gate signal line portion in a plurality of third gate signal line portions GL-3 is connected to two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1. Two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1 are connected by a separate second gate signal line portion in a plurality of second gate signal line portions GL-2, and are connected by a separate third gate signal line portion in a plurality of third gate signal line portions GL-3. Two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1, a separate second gate signal line portion in a plurality of second gate signal line portions GL-2, and a separate third gate signal line portion in a plurality of third gate signal line portions GL-3 form a second ring, which substantially surrounds the region of transistors and capacitors of the pixel driving circuit having sub-pixels. In one example, the second ring substantially surrounds the region of transistors and capacitors having corresponding first sub-pixels. In another example, the second ring substantially surrounds the region of transistors and capacitors of sub-pixels having a first color. In another example, the second ring substantially surrounds the area having the transistor and capacitor of the red sub-pixel.

[0308] In some embodiments, the array substrate includes a plurality of second rings LPS2 arranged in a row. Optionally, the plurality of second rings LPS2 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0309] In some embodiments, the plurality of second rings LPS2 respectively substantially surround the region of the anodes of the sub-pixels having the same color. Each second ring in the plurality of second rings LPS2 substantially surrounds the region of the anodes of the sub-pixels having the same color. In one example, the plurality of second rings LPS2 substantially surrounds the region of the anodes of the red sub-pixels.

[0310] Fig.23 is a schematic diagram showing a gate scanning signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.23 , the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.23 , a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3 are represented.

[0311] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0312] Reference Figure 2A , Figure 2B , FIG. 16A to FIG. 16M , FIG. 17A to FIG. 17M and Fig.23In some embodiments, a first gate signal line portion among the plurality of first gate signal line portions GL-1 is connected to gates of one or more data write transistors in a pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), is connected to gates of one or more data write transistors in a pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and is connected to gates of one or more data write transistors in a pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0313] In some embodiments, a second gate signal line portion GL-2 among a plurality of second gate signal line portions GL-2 connects a first gate signal line portion with a first adjacent first gate signal line portion, and the first adjacent first gate signal line portion is connected to the gate of one or more data writing transistors in a pixel driving circuit in a first sub-pixel in the (n-1)th column sub-pixel C(n-1) and an mth row sub-pixel Rm.

[0314] In some embodiments, a third gate signal line portion GL-3 among a plurality of third gate signal line portions GL-3 connects the first gate signal line portion and a second adjacent first gate signal line portion, and the second adjacent first gate signal line portion is connected to the gate of one or more data write transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0315] Fig.24 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure. Fig.17A , Fig. 17C , Fig.17H and Fig.24, each of the multiple reset control signal lines includes multiple first reset control signal line sections rst-1 and multiple second reset control signal line sections rst-2. Multiple first reset control signal line sections rst-1 and multiple second reset control signal line sections rst-2 are located in two different layers. In one example, multiple first reset control signal line sections rst-1 are located in the first conductive layer, and multiple second reset control signal line sections rst-2 are located in the second signal line layer. Each of the multiple second reset control signal line sections rst-2 is respectively connected to two adjacent first reset control signal line sections in the multiple first reset control signal line sections rst-1. Two adjacent first reset control signal line sections in the multiple first reset control signal line sections rst-1 are connected through a separate second reset control signal line section in the multiple second reset control signal line sections rst-2.

[0316] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in the first conductive layer, and the plurality of third reset control signal line portions rst-3 are located in the second signal line layer. Each of the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 in the same row. Two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 are connected by a separate third reset control signal line portion in the plurality of third reset control signal line portions rst-3.

[0317] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers; and the plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. Optionally, the plurality of second reset control signal line portions rst-2 and the plurality of third reset control signal line portions rst-3 are located in the same layer. In one example, the plurality of first reset control signal line portions rst-1 are located in the first conductive layer, the plurality of second reset control signal line portions rst-2 are located in the second signal line layer, and the plurality of third reset control signal line portions rst-3 are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0318] In some embodiments, each second reset control signal line portion of the plurality of second reset control signal line portions rst-2 is respectively connected to two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1. Each third reset control signal line portion of the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1. Two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1 are connected through a separate second reset control signal line portion of the plurality of second reset control signal line portions rst-2, and are connected through a separate third reset control signal line portion of the plurality of third reset control signal line portions rst-3. Two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1, a separate second reset control signal line portion of the plurality of second reset control signal line portions rst-2, and a separate third reset control signal line portion of the plurality of third reset control signal line portions rst-3 form a third ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels. In one example, the third ring substantially surrounds the region with transistors and capacitors for the corresponding first sub-pixel. In another example, the third ring substantially surrounds the region with transistors and capacitors for sub-pixels of the first color. In another example, the third ring substantially surrounds the region with transistors and capacitors for sub-pixels of the red color.

[0319] In some embodiments, the array substrate includes a plurality of third rings LPS3 arranged in a row. Optionally, the plurality of third rings LPS3 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of third rings LPS3 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of third rings LPS3 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0320] In some embodiments, the plurality of third rings LPS3 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each third ring in the plurality of third rings LPS3 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of third rings LPS3 substantially surrounds the region of the anode of the red sub-pixel.

[0321] Fig.25 is a schematic diagram showing a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.25, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.25 , a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3 are represented.

[0322] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0323] Reference Figure 2A , Figure 2B , FIG. 16A to FIG. 16M , FIG. 17A to FIG. 17M and Fig.25 In some embodiments, a first reset control signal line portion among multiple first reset control signal line portions rst-1 is connected to the gates of one or more reset control transistors in the pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gates of one or more reset control transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to the gates of one or more reset control transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0324] In some embodiments, a second reset control signal line portion among multiple second reset control signal line portions rst-2 connects the first reset control signal line portion with a first adjacent first reset control signal line portion, and the first adjacent first reset control signal line portion is connected to the gates of one or more reset control transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm.

[0325] In some embodiments, a third reset control signal line portion among multiple third reset control signal line portions rst-3 connects the first reset control signal line portion with a second adjacent first reset control signal line portion, and the second adjacent first reset control signal line portion is connected to the gates of one or more reset control transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0326] Fig.26 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure. Fig.17A , Fig. 17C , Fig.17H and Fig.26 , each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of second light-emitting control signal line portions em-2. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, and the plurality of second light-emitting control signal line portions em-2 are located in the second signal line layer. Each of the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2.

[0327] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, and the plurality of third light-emitting control signal line portions em-3 are located in the second signal line layer. Each of the plurality of third light-emitting control signal line portions em-3 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 in the same row. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected by a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3.

[0328] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1, a plurality of second light-emitting control signal line portions em-2, and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers; and the plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. Optionally, the plurality of second light-emitting control signal line portions em-2 and the plurality of third light-emitting control signal line portions em-3 are located in the same layer. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, the plurality of second light-emitting control signal line portions em-2 are located in the second signal line layer, and the plurality of third light-emitting control signal line portions em-3 are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In the plurality of light-transmitting regions TR, there are signal lines of the second signal line layer (e.g., a plurality of data lines, a plurality of first voltage supply line portions, a plurality of second voltage supply line portions, a plurality of second light-emission control signal line portions em-2, and a plurality of third light-emission control signal line portions em-3), but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light can pass through the plurality of light-transmitting regions TR.

[0329] In some embodiments, each second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Each third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2, and are connected through a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1, a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2, and a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3 form a fourth ring, which substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having a sub-pixel. In one example, the fourth ring substantially surrounds an area of ​​transistors and capacitors having a corresponding first sub-pixel. In another example, the fourth ring substantially surrounds the region of transistors and capacitors having sub-pixels of the first color. In another example, the fourth ring substantially surrounds the region of transistors and capacitors having sub-pixels of the red color.

[0330] In some embodiments, the array substrate includes a plurality of fourth rings LPS4 arranged in a row. Optionally, the plurality of fourth rings LPS4 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0331] In some embodiments, the plurality of fourth rings LPS4 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of fourth rings LPS4 substantially surrounds the region of the anode of the red sub-pixel.

[0332] Fig. 27 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure. Fig. 27, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig. 27 A corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2 and a corresponding third sub-pixel sp3 are represented in FIG.

[0333] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0334] Reference Figure 2A , Figure 2B , FIG. 16A to FIG. 16M , FIG. 17A to FIG. 17M and Fig. 27 In some embodiments, a first light-emitting control signal line portion among multiple first light-emitting control signal line portions em-1 is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0335] In some embodiments, a second light-emitting control signal line portion among a plurality of second light-emitting control signal line portions em-2 connects a first light-emitting control signal line portion with a first adjacent first light-emitting control signal line portion, and the first adjacent first light-emitting control signal line portion is connected to the gates of one or more light-emitting control transistors in a pixel driving circuit in a first sub-pixel in the (n-1)th column sub-pixel C(n-1) and an mth row sub-pixel Rm.

[0336] In some embodiments, a third light emitting control signal line portion among a plurality of third light emitting control signal line portions em-3 connects the first light emitting control signal line portion with a second adjacent first light emitting control signal line portion, and the second adjacent first light emitting control signal line portion is connected to the gates of one or more light emitting control transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0337] Reference Fig.17A , Fig. 17C , Fig.17H and Figures 20 to 27 In some embodiments, the array substrate includes a plurality of signal lines, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of second signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of second signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of second signal line portions are located in a second signal line layer. Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions are connected through a separate second signal line portion of the plurality of second signal line portions.

[0338] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of third signal line portions are located in a second signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of third signal line portions are located in a second signal line layer. Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions in the same row. Two adjacent first signal line portions of the plurality of first signal line portions are connected by a separate third signal line portion of the plurality of third signal line portions.

[0339] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; and the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the same layer. In one example, the plurality of first signal line portions are located in the first conductive layer, the plurality of second signal line portions are located in the second signal line layer, and the plurality of third signal line portions are located in the second signal line layer. In one example, the plurality of first signal line portions are located in the second conductive layer, the plurality of second signal line portions are located in the second signal line layer, and the plurality of third signal line portions are located in the second signal line layer. In some embodiments, the signal line located in the second signal line layer is made of a substantially transparent conductive material. In a plurality of light-transmitting regions TR, there are signal lines of the second signal line layer, but there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer. Since the signal lines of the second signal line layer are made of a substantially transparent conductive material, light may pass through the plurality of light-transmitting regions TR.

[0340] In some embodiments, each second signal line portion of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions. Each third signal line portion of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions are connected by a separate second signal line portion of the plurality of second signal line portions and by a separate third signal line portion of the plurality of third signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions, a separate second signal line portion of the plurality of second signal line portions, and a separate third signal line portion of the plurality of third signal line portions form a ring substantially surrounding an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels. In one example, the ring substantially surrounds an area of ​​transistors and capacitors having corresponding first sub-pixels. In another example, the ring substantially surrounds an area of ​​transistors and capacitors having sub-pixels of a first color. In another example, the ring substantially surrounds an area of ​​transistors and capacitors having red sub-pixels.

[0341] In some embodiments, the array substrate includes a plurality of rings arranged in a row. Optionally, the plurality of rings substantially surround the region of the pixel drive circuit of the sub-pixel of the same color. Each of the plurality of rings substantially surrounds the region of the pixel drive circuit of the sub-pixel of the same color. In one example, the plurality of rings substantially surrounds the region of the pixel drive circuit of the red sub-pixel.

[0342] In some embodiments, the plurality of rings respectively substantially surround the region of the anode of the sub-pixels having the same color. Each of the plurality of rings substantially surrounds the region of the anode of the sub-pixels having the same color. In one example, the plurality of rings substantially surrounds the region of the anode of the red sub-pixel.

[0343] In some embodiments, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. The first color, the second color, and the third color are three different colors. In one example, the first color is red, the second color is green, and the third color is blue.

[0344] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0345] Reference Figure 2A , Figure 2B , FIG. 16A to FIG. 16M , FIG. 17A to FIG. 17M as well as Figures 20 to 27 In some embodiments, a first signal line portion among the plurality of first signal line portions is connected to one or more transistors in a pixel driving circuit in a third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2), and connected to one or more transistors in a pixel driving circuit in a first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0346] In some embodiments, a second signal line portion among a plurality of second signal line portions connects the first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in a first sub-pixel in the (n-1)th column sub-pixel C(n-1) and an mth row sub-pixel Rm.

[0347] In some embodiments, a third signal line portion among a plurality of third signal line portions connects the first signal line portion and a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0348] Fig.28A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig.28B It is shown Fig.28A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig.28C It is shown Fig.28A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.28D It is shown Fig.28A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Fig.28E It is shown Fig.28A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG. Fig.28F It is shown Fig.28A A schematic diagram of the structure of a first signal line layer in a portion of an array substrate depicted in FIG. Figure 28G It is shown Fig.28A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG. Fig.28H It is shown Fig.28A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG. Fig.28I It is shown Fig.28A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG. Fig.28J It is shown Fig.28A Schematic diagram of the structure of the second planarization layer in a portion of the array substrate described in. Figure 28K It is shown Fig.28A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG. Figure 28L It is shown Fig.28A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG. Fig.29 is along Fig.28A Cross-sectional view along line BB'.

[0349] Fig.28A To Figure 28M and Fig.29 The array substrate depicted in FIG. 3A to FIG. 3M and Figure 4 The difference between the array substrate depicted in FIG. 1 and FIG. 2 is that Fig.28A To Figure 28M and Fig.29 The array substrate depicted in does not include a second signal line layer.

[0350] Reference Fig.28A To Figure 28M and Fig.29 In some embodiments, the array substrate includes: a base substrate BS; a semiconductor material layer SML, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1, which is located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN, which is located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2, which is located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD, which is located on a side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL1, which is located on a side of the interlayer dielectric layer ILD away from the first conductive layer CT1; on one side of the second conductive layer CT2; the passivation layer PVX, which is located on the side of the first signal line SL1 away from the interlayer dielectric layer ILD; the first planarization layer PLN1, which is located on the side of the passivation layer PVX away from the first signal line layer SL1; the third signal line layer SL3, which is located on the side of the first planarization layer PLN1 away from the passivation layer PVX; the second planarization layer PLN2, which is located on the side of the third signal line layer SL3 away from the first planarization layer PLN1; the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the third signal line layer SL3; and the pixel defining layer PDL, which is located on the side of the anode layer ADL away from the second planarization layer PLN2.

[0351] Reference Figure 2A , Figure 2B , Fig.28A and Fig.28B, the corresponding pixel driving circuit is marked with reference numerals, which represent the regions corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td) in the corresponding pixel driving circuit. The corresponding pixel driving circuit is also marked with reference numerals representing the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuits are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in the corresponding pixel driving circuits, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located in the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are located in the same layer.

[0352] Reference Figure 2A , Figure 2B , Fig.28A and Fig.28CIn some embodiments, the first conductive layer includes a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, a plurality of gate signal lines GL, and a first capacitor electrode Ce1 of a storage capacitor Cst are located in the same layer.

[0353] Reference Figure 2A , Figure 2B , Fig.28A and Fig.28D In some embodiments, the second conductive layer includes a plurality of initialization signal lines Vint and a second capacitor electrode Ce2 of a storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on a substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of initialization signal lines Vint and the second capacitor electrode Ce2 of the storage capacitor Cst are in the same layer.

[0354] In some embodiments, the second capacitor electrodes of a row of pixel driving circuits are interconnected to form a line for transmitting a voltage supply signal.

[0355] Fig.28E A via extending through the interlayer dielectric layer ILD is depicted in FIG.

[0356] Reference Figure 2A , Figure 2B , Fig.28A and Fig.28FIn some embodiments, the first signal line layer includes a node connection line Cln, a voltage connection pad VCP, a data signal connection pad DCP, an electrode connection line Cle, and a reset signal connection line Cli. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sublayers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection line Cln, the voltage connection pad VCP, the data signal connection pad DCP, the electrode connection line Cle, and the reset signal connection line Cli are located in the same layer.

[0357] The node connection line Cln is connected to the first capacitor electrode Ce1 and is connected to the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1. The data signal connection pad DCP connects the corresponding data line of the plurality of data lines to the first electrode of the second transistor T2. The reset signal connection line Cli connects the corresponding initialization signal line of the plurality of initialization signal lines to the first electrode of the first transistor T1 and the sixth transistor T6. The voltage connection pad VCP connects the corresponding voltage supply line of the plurality of voltage supply lines to the first electrode of the fourth transistor T4, and connects the corresponding voltage supply line of the plurality of voltage supply lines to the second capacitor electrode of the storage capacitor. The electrode connection line Cle is respectively connected to the second electrode of the fifth transistor T5 and the sixth transistor T6.

[0358] Figure 28G A via extending through the passivation layer PVX is depicted in FIG.

[0359] Fig.28H A via extending through the first planarization layer PLN1 is depicted in FIG.

[0360] Reference Figure 2A , Figure 2B , Fig.28A and Fig.28I In some embodiments, the third signal line layer includes a plurality of data lines DL and an anode connection pad ACP. The anode connection pad ACP is respectively connected to the fourth node N4 and the corresponding anode in the corresponding sub-pixel. The anode connection pad ACP is connected to the second electrode of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in the corresponding sub-pixel is connected to the anode connection pad ACP.

[0361] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the third signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the third signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes a plurality of sublayers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, a plurality of data lines DL, a voltage connection bridge VCB, and an anode connection pad ACP are located in the same layer.

[0362] Fig.28J A via extending through the second planarization layer PLN2 is depicted in FIG.

[0363] Reference Figure 2A , Figure 2B , Fig.28A and Figure 28K In some embodiments, the anode layer includes anodes of corresponding light emitting elements. The anodes are connected to anode connection pads in the third signal line layer, and the anode connection pads are connected to second electrodes of the fifth transistor T5 and the sixth transistor T6.

[0364] Figure 28L A via extending through the pixel definition layer PDL is depicted in FIG. Figure 28L , the array substrate includes a sub-pixel opening SA configured to accommodate the light emitting material.

[0365] Reference Figure 2A , Figure 2B , FIG. 28A to FIG. 28L and Fig.29 In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. In some embodiments, the array substrate further includes a first via v1 and a second via v2. The first via v1 extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor and / or the second electrode D1 of the first transistor, as shown in FIG. Fig.29 Depicted.

[0366] In some embodiments, the array substrate further includes a sixth via v6. The voltage connection pad VCP is connected to the first electrode S4 of the fourth transistor T4 through the sixth via v6, thereby providing a voltage supply signal to the first electrode S4 of the fourth transistor T4. In one example, the sixth via v6 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0367] In some embodiments, the array substrate further includes a seventh via hole v7. The voltage connection bridge VCB is connected to the voltage connection pad VCP through the seventh via hole v7. In one example, the seventh via hole v7 extends through the first planarization layer PLN1 and the passivation layer PVX.

[0368] Fig. 30A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig. 30B It is shown Fig. 30A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate is depicted in FIG. Fig. 30C It is shown Fig. 30A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is depicted in FIG. Fig.30D It is shown Fig. 30A A schematic diagram of the structure of the second conductive layer in a portion of an array substrate depicted in FIG. Fig.30E It is shown Fig. 30A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is depicted in FIG. Fig.30F It is shown Fig. 30A Schematic diagram of the structure of the first signal line layer in a part of the array substrate. Figure 30G It is shown Fig. 30A A schematic diagram of the structure of a passivation layer in a portion of an array substrate is depicted in FIG. Fig. 30H It is shown Fig. 30A Schematic diagram of the structure of a first planarization layer in a portion of an array substrate depicted in FIG. Fig. 30I It is shown Fig. 30A A schematic diagram of the structure of the third signal line layer in a portion of an array substrate depicted in FIG. Fig. 30J It is shown Fig. 30A Schematic diagram of the structure of the second planarization layer in a portion of the array substrate described in. Figure 30K It is shown Fig. 30A A schematic diagram of the structure of an anode layer in a portion of an array substrate is depicted in FIG. Figure 30L It is shown Fig. 30A A schematic diagram of the structure of a pixel defining layer in a portion of an array substrate is depicted in FIG.

[0369] In some embodiments, reference Fig. 30A, a minimum repeating unit of a plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3. Fig.28A A portion of the array substrate depicted in Fig. 30A A portion of the corresponding third sub-pixel sp3 depicted in FIG.

[0370] In some embodiments, each of the corresponding first subpixel sp1, the corresponding second subpixel sp2 and the corresponding third subpixel sp3 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td and a storage capacitor Cst.

[0371] In some embodiments, the corresponding first sub-pixel sp1 is a sub-pixel of a first color (e.g., red), the corresponding second sub-pixel sp2 is a sub-pixel of a second color (e.g., green), and the corresponding third sub-pixel sp3 is a sub-pixel of a third color (e.g., blue). In some embodiments, the corresponding first sub-pixel sp1, the corresponding second sub-pixel sp2, and the corresponding third sub-pixel sp3 are three sub-pixels of a pixel in the array substrate.

[0372] Fig.31 is a schematic diagram showing a voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. Fig. 30A , Fig. 30H , Fig. 30J and Fig.31 In some embodiments, the array substrate includes a plurality of voltage connection bridges VCBS. Optionally, the plurality of voltage connection bridges VCBS are arranged in an array of multiple rows and columns.

[0373] In some embodiments, each of the plurality of voltage connection bridges VCBS includes a second capacitor electrode of a plurality of pixel drive circuits. Optionally, each of the plurality of voltage connection bridges VCBS includes a second capacitor electrode of a pixel drive circuit of a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3. Optionally, a corresponding voltage connection bridge of the plurality of voltage connection bridges VCBS is configured to provide a voltage supply signal to a first electrode of a fourth transistor of a pixel drive circuit of a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3.

[0374] In some embodiments, a corresponding voltage supply line in a plurality of voltage supply lines Vdd is connected to a voltage connection bridge of two adjacent columns in a plurality of voltage connection bridges VCBS. In some embodiments, a corresponding voltage connection bridge in a plurality of voltage connection bridges VCBS is respectively connected to two adjacent voltage supply lines in a plurality of voltage supply lines Vdd. In some embodiments, a plurality of voltage supply lines Vdd include a first adjacent voltage supply line AVdd1 and a second adjacent voltage supply line AVdd2. Each voltage connection bridge in a plurality of voltage connection bridges VCBS is connected to a first adjacent voltage supply line AVdd1 and to a second adjacent voltage supply line AVdd2.

[0375] In some embodiments, a plurality of voltage supply lines (including a first adjacent voltage supply line AVdd1 and a second adjacent voltage supply line AVdd2 ) are located in the second conductive layer, and a plurality of voltage connection bridges VCBS are located in the second conductive layer CT2 .

[0376] In some embodiments, two adjacent voltage connection bridges among the plurality of voltage connection bridges VCBS in the same pixel row are connected to the same voltage supply line among the plurality of voltage supply lines, such as Fig.31 Depicted. Fig. 9 In some embodiments, the pixel row includes an m-th row of sub-pixels Rm, an (m+1)-th row of sub-pixels R(m+1), and an (m+2)-th row of sub-pixels R(m+2).

[0377] In some embodiments, the voltage connection bridges in the plurality of voltage connection bridges VCBS in the same pixel column are connected to the same two adjacent voltage supply lines in the plurality of voltage supply lines. Fig. 9 In some embodiments, the pixel column includes an nth column sub-pixel Cn, an (n-1)th column sub-pixel C(n-1), and an (n+1)th column sub-pixel C(n+1).

[0378] Fig.32 Schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Fig.32 In some embodiments, the array substrate includes a plurality of light-transmitting regions TR that allow light to pass through. In the plurality of light-transmitting regions TR, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0379] In some embodiments, the array substrate is a full display with camera (FDC) array substrate, wherein the array substrate further includes photosensors located in the plurality of light-transmitting regions TR and configured to detect light.

[0380] Fig.33 is a schematic diagram showing a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig. 30A , Fig.30D , Fig. 30H and Fig.33 , each of the multiple initialization signal lines includes multiple first initialization signal line portions Vint-1 and multiple second initialization signal line portions Vint-2. The multiple first initialization signal line portions Vint-1 and the multiple second initialization signal line portions Vint-2 are located in two different layers. In one example, the multiple first initialization signal line portions Vint-1 are located in the second conductive layer, and the multiple second initialization signal line portions Vint-2 are located in the first signal line layer. Each of the multiple second initialization signal line portions Vint-2 is respectively connected to two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in the multiple first initialization signal line portions Vint-1 are connected through a separate second initialization signal line portion in the multiple second initialization signal line portions Vint-2.

[0381] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1 and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. In one example, the plurality of first initialization signal line portions Vint-1 are located in the second conductive layer, and the plurality of third initialization signal line portions Vint-3 are located in the first signal line layer. Each of the plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 in the same row. Two adjacent first initialization signal line portions in the plurality of first initialization signal line portions Vint-1 are connected by a separate third initialization signal line portion in the plurality of third initialization signal line portions Vint-3.

[0382] In some embodiments, each of the plurality of initialization signal lines includes a plurality of first initialization signal line portions Vint-1, a plurality of second initialization signal line portions Vint-2, and a plurality of third initialization signal line portions Vint-3. The plurality of first initialization signal line portions Vint-1 and the plurality of second initialization signal line portions Vint-2 are located in two different layers; and the plurality of first initialization signal line portions Vint-1 and the plurality of third initialization signal line portions Vint-3 are located in two different layers. Optionally, the plurality of second initialization signal line portions Vint-2 and the plurality of third initialization signal line portions Vint-3 are located in the same layer. In one example, the plurality of first initialization signal line portions Vint-1 are located in the second conductive layer, the plurality of second initialization signal line portions Vint-2 are located in the first signal line layer, and the plurality of third initialization signal line portions Vint-3 are located in the first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0383] In some embodiments, each second initialization signal line portion in a plurality of second initialization signal line portions Vint-2 is respectively connected to two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1. Each third initialization signal line portion in a plurality of third initialization signal line portions Vint-3 is respectively connected to two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1. Two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1 are connected by a separate second initialization signal line portion in a plurality of second initialization signal line portions Vint-2, and are connected by a separate third initialization signal line portion in a plurality of third initialization signal line portions Vint-3. Two adjacent first initialization signal line portions in a plurality of first initialization signal line portions Vint-1, a separate second initialization signal line portion in a plurality of second initialization signal line portions Vint-2, and a separate third initialization signal line portion in a plurality of third initialization signal line portions Vint-3 form a first ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having a sub-pixel. In one example, the first ring substantially surrounds an area of ​​transistors and capacitors having a corresponding first sub-pixel. In another example, the first ring substantially surrounds the region of transistors and capacitors having sub-pixels of a first color. In another example, the first ring substantially surrounds the region of transistors and capacitors having sub-pixels of a red color.

[0384] In some embodiments, the array substrate includes a plurality of first rings LPS1 arranged in a row. Optionally, the plurality of first rings LPS1 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of first rings LPS1 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0385] In some embodiments, the plurality of first rings LPS1 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of first rings LPS1 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of first rings LPS1 substantially surrounds the region of the anode of the red sub-pixel.

[0386] Fig.34 is a schematic diagram showing a reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.34 , the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.34 , a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, and a corresponding third sub-pixel sp3 are represented.

[0387] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0388] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 30A to FIG. 30L and Fig.34In some embodiments, the first initialization signal line portion among the multiple first initialization signal line portions Vint-1 is connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0389] In some embodiments, a second initialization signal line portion among multiple second initialization signal line portions Vint-2 connects the first initialization signal line portion with a first adjacent first initialization signal line portion, and the first adjacent first initialization signal line portion is connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0390] In some embodiments, a third initialization signal line portion among multiple third initialization signal line portions Vint-3 connects the first initialization signal line portion with a second adjacent first initialization signal line portion, and the second adjacent first initialization signal line portion is connected to the first electrodes of one or more reset transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0391] Fig.35 is a schematic diagram showing a gate scanning signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig. 30A , Fig. 30C , Fig. 30H and Fig.35 , each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line parts GL-1 and a plurality of second gate signal line parts GL-2. A plurality of first gate signal line parts GL-1 and a plurality of second gate signal line parts GL-2 are located in two different layers. In one example, a plurality of first gate signal line parts GL-1 are located in the first conductive layer, and a plurality of second gate signal line parts GL-2 are located in the first signal line layer. Each second gate signal line part in a plurality of second gate signal line parts GL-2 is connected to two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1, respectively. Two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 are connected by a separate second gate signal line part in a plurality of second gate signal line parts GL-2.

[0392] In certain embodiments, each gate signal line in a plurality of gate signal lines includes a plurality of first gate signal line parts GL-1 and a plurality of third gate signal line parts GL-3. A plurality of first gate signal line parts GL-1 and a plurality of third gate signal line parts GL-3 are located in two different layers. In one example, a plurality of first gate signal line parts GL-1 are located in the first conductive layer, and a plurality of third gate signal line parts GL-3 are located in the first signal line layer. Each third gate signal line part in a plurality of third gate signal line parts GL-3 is connected to two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 in the same row respectively. Two adjacent first gate signal line parts in a plurality of first gate signal line parts GL-1 are connected by a separate third gate signal line part in a plurality of third gate signal line parts GL-3.

[0393] In some embodiments, each of the plurality of gate signal lines includes a plurality of first gate signal line portions GL-1, a plurality of second gate signal line portions GL-2, and a plurality of third gate signal line portions GL-3. A plurality of first gate signal line portions GL-1 and a plurality of second gate signal line portions GL-2 are located in two different layers; and a plurality of first gate signal line portions GL-1 and a plurality of third gate signal line portions GL-3 are located in two different layers. Optionally, a plurality of second gate signal line portions GL-2 and a plurality of third gate signal line portions GL-3 are located in the same layer. In one example, a plurality of first gate signal line portions GL-1 are located in the first conductive layer, a plurality of second gate signal line portions GL-2 are located in the first signal line layer, and a plurality of third gate signal line portions GL-3 are located in the first signal line layer. In a plurality of light-transmitting regions TR, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0394] In some embodiments, each second gate signal line portion in a plurality of second gate signal line portions GL-2 is connected to two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1. Each third gate signal line portion in a plurality of third gate signal line portions GL-3 is connected to two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1. Two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1 are connected by a separate second gate signal line portion in a plurality of second gate signal line portions GL-2, and are connected by a separate third gate signal line portion in a plurality of third gate signal line portions GL-3. Two adjacent first gate signal line portions in a plurality of first gate signal line portions GL-1, a separate second gate signal line portion in a plurality of second gate signal line portions GL-2, and a separate third gate signal line portion in a plurality of third gate signal line portions GL-3 form a second ring, which substantially surrounds the region of transistors and capacitors of the pixel driving circuit having sub-pixels. In one example, the second ring substantially surrounds the region of transistors and capacitors having corresponding first sub-pixels. In another example, the second ring substantially surrounds the region of transistors and capacitors of sub-pixels having a first color. In another example, the second ring substantially surrounds the area having the transistor and capacitor of the red sub-pixel.

[0395] In some embodiments, the array substrate includes a plurality of second rings LPS2 arranged in a row. Optionally, the plurality of second rings LPS2 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of second rings LPS2 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0396] In some embodiments, the plurality of second rings LPS2 respectively substantially surround the region of the anodes of the sub-pixels having the same color. Each second ring in the plurality of second rings LPS2 substantially surrounds the region of the anodes of the sub-pixels having the same color. In one example, the plurality of second rings LPS2 substantially surrounds the region of the anodes of the red sub-pixels.

[0397] Fig.36 is a schematic diagram showing a gate scanning signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.36, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.36 A corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2 and a corresponding third sub-pixel sp3 are represented in FIG.

[0398] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0399] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 30A to FIG. 30L and Fig.36 In some embodiments, a first gate signal line portion among the plurality of first gate signal line portions GL-1 is connected to gates of one or more data write transistors in a pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), is connected to gates of one or more data write transistors in a pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and is connected to gates of one or more data write transistors in a pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0400] In some embodiments, a second gate signal line portion among the plurality of second gate signal line portions GL-2 connects the first gate signal line portion with a first adjacent first gate signal line portion, and the first adjacent first gate signal line portion is connected to the gate of one or more data write transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0401] In some embodiments, a third gate signal line portion among a plurality of third gate signal line portions GL-3 connects the first gate signal line portion with a second adjacent first gate signal line portion, and the second adjacent first gate signal line portion is connected to the gate of one or more data write transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0402] Fig.37 is a schematic diagram showing a reset control signal network in a portion of an array substrate in some embodiments of the present disclosure. Fig. 30A , Fig. 30C , Fig. 30H and Fig.37 , each of the multiple reset control signal lines includes multiple first reset control signal line sections rst-1 and multiple second reset control signal line sections rst-2. Multiple first reset control signal line sections rst-1 and multiple second reset control signal line sections rst-2 are located in two different layers. In one example, multiple first reset control signal line sections rst-1 are located in the first conductive layer, and multiple second reset control signal line sections rst-2 are located in the first signal line layer. Each of the multiple second reset control signal line sections rst-2 is respectively connected to two adjacent first reset control signal line sections in the multiple first reset control signal line sections rst-1. Two adjacent first reset control signal line sections in the multiple first reset control signal line sections rst-1 are connected through a separate second reset control signal line section in the multiple second reset control signal line sections rst-2.

[0403] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1 and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. In one example, the plurality of first reset control signal line portions rst-1 are located in the first conductive layer, and the plurality of third reset control signal line portions rst-3 are located in the first signal line layer. Each of the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 in the same row. Two adjacent first reset control signal line portions in the plurality of first reset control signal line portions rst-1 are connected by a separate third reset control signal line portion in the plurality of third reset control signal line portions rst-3.

[0404] In some embodiments, each of the plurality of reset control signal lines includes a plurality of first reset control signal line portions rst-1, a plurality of second reset control signal line portions rst-2, and a plurality of third reset control signal line portions rst-3. The plurality of first reset control signal line portions rst-1 and the plurality of second reset control signal line portions rst-2 are located in two different layers; and the plurality of first reset control signal line portions rst-1 and the plurality of third reset control signal line portions rst-3 are located in two different layers. Optionally, the plurality of second reset control signal line portions rst-2 and the plurality of third reset control signal line portions rst-3 are located in the same layer. In one example, the plurality of first reset control signal line portions rst-1 are located in the first conductive layer, the plurality of second reset control signal line portions rst-2 are located in the first signal line layer, and the plurality of third reset control signal line portions rst-3 are located in the first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0405] In some embodiments, each second reset control signal line portion of the plurality of second reset control signal line portions rst-2 is respectively connected to two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1. Each third reset control signal line portion of the plurality of third reset control signal line portions rst-3 is respectively connected to two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1. Two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1 are connected through a separate second reset control signal line portion of the plurality of second reset control signal line portions rst-2, and are connected through a separate third reset control signal line portion of the plurality of third reset control signal line portions rst-3. Two adjacent first reset control signal line portions of the plurality of first reset control signal line portions rst-1, a separate second reset control signal line portion of the plurality of second reset control signal line portions rst-2, and a separate third reset control signal line portion of the plurality of third reset control signal line portions rst-3 form a third ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels. In one example, the third ring substantially surrounds the region with transistors and capacitors for the corresponding first sub-pixel. In another example, the third ring substantially surrounds the region with transistors and capacitors for sub-pixels of the first color. In another example, the third ring substantially surrounds the region with transistors and capacitors for sub-pixels of the red color.

[0406] In some embodiments, the array substrate includes a plurality of third rings LPS3 arranged in a row. Optionally, the plurality of third rings LPS3 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of third rings LPS3 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of third rings LPS3 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0407] In some embodiments, the plurality of third rings LPS3 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each third ring in the plurality of third rings LPS3 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of third rings LPS3 substantially surrounds the region of the anode of the red sub-pixel.

[0408] Fig.38 is a schematic diagram showing a reset control signal network in a portion of an array substrate according to some embodiments of the present disclosure. Fig.38 , the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.38 A corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2 and a corresponding third sub-pixel sp3 are represented in FIG.

[0409] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0410] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 30A to FIG. 30L and Fig.38In some embodiments, a first reset control signal line portion among multiple first reset control signal line portions rst-1 is connected to the gates of one or more reset control transistors in the pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to the gates of one or more reset control transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to the gates of one or more reset control transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0411] In some embodiments, a second reset control signal line portion among a plurality of second reset control signal line portions rst-2 connects the first reset control signal line portion with a first adjacent first reset control signal line portion, and the first adjacent first reset control signal line portion is connected to the gates of one or more reset control transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0412] In some embodiments, a third reset control signal line portion among multiple third reset control signal line portions rst-3 connects the first reset control signal line portion with a second adjacent first reset control signal line portion, and the second adjacent first reset control signal line portion is connected to the gates of one or more reset control transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0413] Fig.39 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure. Fig. 30A , Fig. 30C , Fig. 30H and Fig.39, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of second light-emitting control signal line portions em-2. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, and the plurality of second light-emitting control signal line portions em-2 are located in the first signal line layer. Each of the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2.

[0414] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1 and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, and the plurality of third light-emitting control signal line portions em-3 are located in the first signal line layer. Each of the plurality of third light-emitting control signal line portions em-3 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 in the same row. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected by a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3.

[0415] In some embodiments, each of the plurality of light-emitting control signal lines includes a plurality of first light-emitting control signal line portions em-1, a plurality of second light-emitting control signal line portions em-2, and a plurality of third light-emitting control signal line portions em-3. The plurality of first light-emitting control signal line portions em-1 and the plurality of second light-emitting control signal line portions em-2 are located in two different layers; and the plurality of first light-emitting control signal line portions em-1 and the plurality of third light-emitting control signal line portions em-3 are located in two different layers. Optionally, the plurality of second light-emitting control signal line portions em-2 and the plurality of third light-emitting control signal line portions em-3 are located in the same layer. In one example, the plurality of first light-emitting control signal line portions em-1 are located in the first conductive layer, the plurality of second light-emitting control signal line portions em-2 are located in the first signal line layer, and the plurality of third light-emitting control signal line portions em-3 are located in the first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0416] In some embodiments, each second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Each third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3 is respectively connected to two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1 are connected through a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2, and are connected through a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3. Two adjacent first light-emitting control signal line portions in the plurality of first light-emitting control signal line portions em-1, a separate second light-emitting control signal line portion in the plurality of second light-emitting control signal line portions em-2, and a separate third light-emitting control signal line portion in the plurality of third light-emitting control signal line portions em-3 form a fourth ring, which substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having a sub-pixel. In one example, the fourth ring substantially surrounds an area of ​​transistors and capacitors having a corresponding first sub-pixel. In another example, the fourth ring substantially surrounds the region of transistors and capacitors having sub-pixels of the first color. In another example, the fourth ring substantially surrounds the region of transistors and capacitors having sub-pixels of the red color.

[0417] In some embodiments, the array substrate includes a plurality of fourth rings LPS4 arranged in a row. Optionally, the plurality of fourth rings LPS4 substantially surround the region of the pixel driving circuit of the sub-pixel of the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of the sub-pixel of the same color. In one example, the plurality of fourth rings LPS4 substantially surrounds the region of the pixel driving circuit of the red sub-pixel.

[0418] In some embodiments, the plurality of fourth rings LPS4 respectively substantially surround the region of the anode of the sub-pixel having the same color. Each of the plurality of fourth rings LPS4 substantially surrounds the region of the anode of the sub-pixel having the same color. In one example, the plurality of fourth rings LPS4 substantially surrounds the region of the anode of the red sub-pixel.

[0419] Fig.40 is a schematic diagram showing a light emitting control signal network in a portion of an array substrate in some embodiments of the present disclosure. Fig.40 , the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. Fig.40 A corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2 and a corresponding third sub-pixel sp3 are represented in FIG.

[0420] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0421] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 30A to FIG. 30L and Fig.40In some embodiments, a first light-emitting control signal line portion among multiple first light-emitting control signal line portions em-1 is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0422] In some embodiments, a second light-emitting control signal line portion among a plurality of second light-emitting control signal line portions em-2 connects the first light-emitting control signal line portion with a first adjacent first light-emitting control signal line portion, and the first adjacent first light-emitting control signal line portion is connected to the gates of one or more light-emitting control transistors in the pixel driving circuit in the second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0423] In some embodiments, a third light emitting control signal line portion among a plurality of third light emitting control signal line portions em-3 connects the first light emitting control signal line portion with a second adjacent first light emitting control signal line portion, and the second adjacent first light emitting control signal line portion is connected to the gates of one or more light emitting control transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0424] Reference Fig. 30A , Fig. 30C , Fig. 30H and Figures 33 to 40 In some embodiments, the array substrate includes a plurality of signal lines, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of second signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in a first conductive layer, and the plurality of second signal line portions are located in a first signal line layer. In another example, the plurality of first signal line portions are located in a second conductive layer, and the plurality of second signal line portions are located in a first signal line layer. Each of the plurality of second signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions. Two adjacent first signal line portions of the plurality of first signal line portions are connected through a separate second signal line portion of the plurality of second signal line portions.

[0425] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. In one example, the plurality of first signal line portions are located in the first conductive layer, and the plurality of third signal line portions are located in the first signal line layer. In another example, the plurality of first signal line portions are located in the second conductive layer, and the plurality of third signal line portions are located in the first signal line layer. Each of the plurality of third signal line portions is respectively connected to two adjacent first signal line portions of the plurality of first signal line portions in the same row. Two adjacent first signal line portions of the plurality of first signal line portions are connected by a separate third signal line portion of the plurality of third signal line portions.

[0426] In some embodiments, each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions. The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; and the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, the plurality of second signal line portions and the plurality of third signal line portions are located in the same layer. In one example, the plurality of first signal line portions are located in the first conductive layer, the plurality of second signal line portions are located in the first signal line layer, and the plurality of third signal line portions are located in the first signal line layer. In one example, the plurality of first signal line portions are located in the second conductive layer, the plurality of second signal line portions are located in the first signal line layer, and the plurality of third signal line portions are located in the first signal line layer. In the plurality of light-transmitting regions TR, there are no signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer.

[0427] In some embodiments, each second signal line portion in a plurality of second signal line portions is respectively connected to two adjacent first signal line portions in a plurality of first signal line portions. Each third signal line portion in a plurality of third signal line portions is respectively connected to two adjacent first signal line portions in a plurality of first signal line portions. Two adjacent first signal line portions in a plurality of first signal line portions are connected by a separate second signal line portion in a plurality of second signal line portions, and are connected by a separate third signal line portion in a plurality of third signal line portions. Two adjacent first signal line portions in a plurality of first signal line portions, a separate second signal line portion in a plurality of second signal line portions, and a separate third signal line portion in a plurality of third signal line portions form a ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels. In one example, the ring substantially surrounds an area of ​​transistors and capacitors having corresponding first sub-pixels. In another example, the ring substantially surrounds an area of ​​transistors and capacitors having sub-pixels of a first color. In another example, the ring substantially surrounds an area of ​​transistors and capacitors having red sub-pixels.

[0428] In some embodiments, the array substrate includes a plurality of rings arranged in a row. Optionally, the plurality of rings substantially surround the region of the pixel drive circuit of the sub-pixel of the same color. Each of the plurality of rings substantially surrounds the region of the pixel drive circuit of the sub-pixel of the same color. In one example, the plurality of rings substantially surrounds the region of the pixel drive circuit of the red sub-pixel.

[0429] In some embodiments, the plurality of rings respectively substantially surround the region of the anode of the sub-pixels having the same color. Each of the plurality of rings substantially surrounds the region of the anode of the sub-pixels having the same color. In one example, the plurality of rings substantially surrounds the region of the anode of the red sub-pixel.

[0430] In some embodiments, the sub-pixels in the array substrate are arranged in multiple rows and columns. In the mth row of sub-pixels Rm, the array substrate includes a row of first sub-pixels. In the (m+1)th row of sub-pixels R(m+1), the array substrate includes a row of third sub-pixels. In the (m+2)th row of sub-pixels R(m+2), the array substrate includes a row of second sub-pixels. Optionally, a row of first sub-pixels is a row of sub-pixels of a first color, a row of second sub-pixels is a row of sub-pixels of a second color, and a row of third sub-pixels is a row of sub-pixels of a third color. The first color, the second color, and the third color are three different colors. In one example, the first color is red, the second color is green, and the third color is blue.

[0431] In some embodiments, in the nth column of sub-pixels Cn, the array substrate includes a column of third sub-pixels. In the (n-1)th column of sub-pixels C(n-1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. In the (n+1)th column of sub-pixels C(n+1), the array substrate includes a column of first sub-pixels and second sub-pixels arranged alternately. Optionally, the column of third sub-pixels is a column of sub-pixels of a third color, and the column of first sub-pixels and second sub-pixels arranged alternately is a column of sub-pixels of a first color and sub-pixels of a second color arranged alternately. Optionally, in the nth column of sub-pixels Cn, each of the plurality of light-transmitting regions TR separates two adjacent third sub-pixels.

[0432] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3M , FIG. 30A to FIG. 30L as well as Figures 33 to 40 In some embodiments, a first signal line portion among multiple first signal line portions is connected to one or more transistors in a pixel driving circuit in a third sub-pixel in the nth column sub-pixel Cn and the (m+1)th row sub-pixel R(m+1), connected to one or more transistors in a pixel driving circuit in a first sub-pixel in the (n-1)th column sub-pixel C(n-1) and the mth row sub-pixel Rm, and connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n+1)th column sub-pixel C(n+1) and the (m+2)th row sub-pixel R(m+2).

[0433] In some embodiments, a second signal line portion among a plurality of second signal line portions connects the first signal line portion with a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel C(n-1) and the (m+2)th row sub-pixel R(m+2).

[0434] In some embodiments, a third signal line portion among a plurality of third signal line portions connects the first signal line portion and a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel C(n+1) and the mth row sub-pixel Rm.

[0435] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0436] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of signal lines. Optionally, forming each of the plurality of signal lines includes: forming a plurality of first signal line portions, forming a plurality of second signal line portions, and forming a plurality of third signal line portions. Optionally, the plurality of first signal line portions and the plurality of second signal line portions are formed in two different layers. Optionally, the plurality of first signal line portions and the plurality of third signal line portions are located in two different layers. Optionally, each of the plurality of second signal line portions is connected to two adjacent first signal line portions in the plurality of first signal line portions, respectively. Optionally, each of the plurality of third signal line portions is connected to two adjacent first signal line portions in the plurality of first signal line portions, respectively. Optionally, two separate first signal line portions in the plurality of first signal line portions, a separate second signal line portion in the plurality of second signal line portions, and a separate third signal line portion in the plurality of third signal line portions form a ring that substantially surrounds an area of ​​transistors and capacitors of a pixel driving circuit having sub-pixels. . Optionally, two separate first signal line portions are connected via a separate second signal line portion and via a separate third signal line portion.

[0437] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate comprising a plurality of signal lines; in, Each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions; The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; Each of the plurality of second signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions, respectively; Each of the plurality of third signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions, respectively; two individual first signal line portions of the plurality of first signal line portions, an individual second signal line portion of the plurality of second signal line portions, and an individual third signal line portion of the plurality of third signal line portions form a ring substantially surrounding a region having a transistor and a capacitor of a pixel driving circuit of a sub-pixel; as well as The two separate first signal line portions are connected via the separate second signal line portion and are connected via the separate third signal line portion.

2. The array substrate according to claim 1, comprising a plurality of rings arranged in a row; in, The plurality of rings respectively substantially surround regions of pixel driving circuits of sub-pixels of the same color; and Each of the plurality of rings substantially surrounds an area of ​​a pixel driving circuit of a sub-pixel of the same color.

3. The array substrate according to claim 1, comprising a plurality of rings arranged in a row; in, The plurality of rings respectively substantially surround regions of anodes of sub-pixels having the same color; and Each of the plurality of rings substantially surrounds an area of ​​the anode of the sub-pixel having the same color.

4. The array substrate according to any one of claims 1 to 3, wherein: The sub-pixels are arranged in multiple rows and columns; In the mth row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; In the (m+1)th row of sub-pixels, the array substrate includes a row of third sub-pixels of a third color; In the (m+2)th row of sub-pixels, the array substrate includes a row of second sub-pixels of a second color; In the nth column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; In the (n-1)th column of sub-pixels, the array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color that are alternately arranged; In the (n+1)th column of sub-pixels, the array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color that are alternately arranged; The first signal line portion among the multiple first signal line portions is connected to one or more transistors in the pixel driving circuit in the third sub-pixel in the nth column and the (m+1)th row of sub-pixels, is connected to one or more transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column and the mth row of sub-pixels, and is connected to one or more transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column and the (m+2)th row of sub-pixels.

5. The array substrate according to claim 4, wherein: A second signal line portion among the multiple second signal line portions connects the first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

6. The array substrate according to claim 4, wherein: A third signal line portion among the multiple third signal line portions connects the first signal line portion to a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel and the mth row sub-pixel.

7. The array substrate according to claim 4, further comprising a plurality of light-transmitting areas; in, In the n-th column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

8. The array substrate according to any one of claims 1 to 7, wherein: The plurality of signal lines include a plurality of initialization signal lines; The plurality of first signal line portions include a plurality of first initialization signal line portions; The plurality of second signal line portions include a plurality of second initialization signal line portions; and The plurality of third signal line portions include a plurality of third initialization signal line portions.

9. The array substrate according to any one of claims 1 to 8, wherein: The plurality of signal lines include a plurality of gate signal lines; The plurality of first signal line portions include a plurality of first gate signal line portions; The plurality of second signal line portions include a plurality of second gate signal line portions; and The plurality of third signal line portions include a plurality of third gate signal line portions.

10. The array substrate according to any one of claims 1 to 9, wherein: The plurality of signal lines include a plurality of reset control signal lines; The plurality of first signal line portions include a plurality of first reset control signal line portions; The plurality of second signal line portions include a plurality of second reset control signal line portions; and The plurality of third signal line portions include a plurality of third reset control signal line portions.

11. The array substrate according to any one of claims 1 to 10, wherein: The plurality of signal lines include a plurality of light emission control signal lines; The plurality of first signal line portions include a plurality of first light emission control signal line portions; The plurality of second signal line portions include a plurality of second light emission control signal line portions; and The plurality of third signal line portions include a plurality of third light emission control signal line portions.

12. The array substrate according to any one of claims 1 to 6 and 8 to 11, further comprising a plurality of light-transmitting areas; in, The array substrate comprises a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer and an anode layer; The signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer do not exist in the plurality of light-transmitting regions.

13. The array substrate according to claim 12, further comprising a second signal line layer; in, The signal line in the second signal line layer includes a substantially transparent conductive material; as well as The signal lines of the second signal line layer exist in the plurality of light-transmitting regions.

14. The array substrate according to claim 13, wherein: The plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and The plurality of first signal line portions are located in the first conductive layer or the second conductive layer.

15. The array substrate according to any one of claims 1 to 11, further comprising a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; The plurality of voltage connection bridges are arranged in an array of multiple rows and columns; two adjacent voltage connection bridges among the plurality of voltage connection bridges in the same pixel row are connected to the same voltage supply line among the plurality of voltage supply lines; and The voltage connection bridges among the plurality of voltage connection bridges in the same pixel column are connected to the same adjacent voltage supply line among the plurality of voltage supply lines.

16. The array substrate according to claim 15, wherein: the plurality of voltage supply lines comprising a first adjacent voltage supply line, a second adjacent voltage supply line, and a third adjacent voltage supply line; the first adjacent voltage supply line being configured to provide a voltage supply signal to a first pixel drive circuit in a corresponding first sub-pixel, the second adjacent voltage supply line being configured to provide a voltage supply signal to a second pixel drive circuit in a corresponding second sub-pixel, and the third adjacent voltage supply line being configured to provide a voltage supply signal to a third pixel drive circuit in a corresponding third sub-pixel; as well as Respective voltage connection bridges of the plurality of voltage connection bridges are respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line.

17. The array substrate according to claim 16, wherein: each of the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line includes a plurality of first voltage supply line portions and a plurality of second voltage supply line portions that are alternately arranged; Each of the multiple voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

18. The array substrate according to claim 15, wherein: the plurality of voltage supply lines comprising a first adjacent voltage supply line and a second adjacent voltage supply line; Each of the plurality of voltage supply lines is connected to voltage connection bridges of two adjacent columns of the plurality of voltage connection bridges; and Each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

19. The array substrate according to claim 15, wherein: Each of the plurality of voltage connection bridges includes a second capacitor electrode of a plurality of pixel driving circuits.

20. A display device comprising the array substrate according to any one of claims 1 to 19, and one or more integrated circuits connected to the array substrate.

21. An array substrate comprising a plurality of voltage supply lines and a plurality of voltage connection bridges located in two different layers; in, The plurality of voltage connection bridges are arranged in an array of multiple rows and columns; Two adjacent voltage connection bridges among the plurality of voltage connection bridges in the same pixel row are connected to the same voltage supply line among the plurality of voltage supply lines; as well as The voltage connection bridges among the plurality of voltage connection bridges in the same pixel column are connected to the same adjacent voltage supply line among the plurality of voltage supply lines.

22. The array substrate according to claim 21, wherein: the plurality of voltage supply lines comprising a first adjacent voltage supply line, a second adjacent voltage supply line, and a third adjacent voltage supply line; the first adjacent voltage supply line being configured to provide a voltage supply signal to a first pixel drive circuit in a corresponding first sub-pixel, the second adjacent voltage supply line being configured to provide a voltage supply signal to a second pixel drive circuit in a corresponding second sub-pixel, and the third adjacent voltage supply line being configured to provide a voltage supply signal to a third pixel drive circuit in a corresponding third sub-pixel; as well as Respective voltage connection bridges of the plurality of voltage connection bridges are respectively connected to the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line.

23. The array substrate according to claim 22, wherein: each of the first adjacent voltage supply line, the second adjacent voltage supply line, and the third adjacent voltage supply line includes a plurality of first voltage supply line portions and a plurality of second voltage supply line portions that are alternately arranged; Each of the multiple voltage connection bridges is respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the first adjacent voltage supply line, respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the second adjacent voltage supply line, and respectively connected to the first adjacent voltage supply line portion and the second adjacent voltage supply line portion of the third adjacent voltage supply line.

24. The array substrate according to claim 21, wherein: the plurality of voltage supply lines comprising a first adjacent voltage supply line and a second adjacent voltage supply line; Each of the plurality of voltage supply lines is connected to voltage connection bridges of two adjacent columns of the plurality of voltage connection bridges; and Each of the plurality of voltage connection bridges is connected to the first adjacent voltage supply line and to the second adjacent voltage supply line.

25. The array substrate according to claim 21, wherein: Each of the plurality of voltage connection bridges includes a second capacitor electrode of a plurality of pixel driving circuits.

26. The array substrate according to any one of claims 21 to 25, further comprising a plurality of signal lines; in, Each of the plurality of signal lines includes a plurality of first signal line portions, a plurality of second signal line portions, and a plurality of third signal line portions; The plurality of first signal line portions and the plurality of second signal line portions are located in two different layers; The plurality of first signal line portions and the plurality of third signal line portions are located in two different layers; Each of the plurality of second signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions, respectively; Each of the plurality of third signal line portions is connected to two adjacent first signal line portions of the plurality of first signal line portions, respectively; two individual first signal line portions of the plurality of first signal line portions, an individual second signal line portion of the plurality of second signal line portions, and an individual third signal line portion of the plurality of third signal line portions form a ring substantially surrounding a region having a transistor and a capacitor of a pixel driving circuit of a sub-pixel; as well as The two separate first signal line portions are connected via the separate second signal line portion and are connected via the separate third signal line portion.

27. The array substrate according to claim 26, comprising a plurality of rings arranged in rows in sequence; in, The plurality of rings respectively substantially surround regions of pixel driving circuits of sub-pixels of the same color; and Each of the plurality of rings substantially surrounds an area of ​​a pixel driving circuit of a sub-pixel of the same color.

28. The array substrate according to claim 26, comprising a plurality of rings arranged in rows in sequence; in, The plurality of rings respectively substantially surround regions of anodes of sub-pixels having the same color; and Each of the plurality of rings substantially surrounds an area of ​​the anode of the sub-pixel having the same color.

29. The array substrate according to any one of claims 26 to 28, wherein: The sub-pixels are arranged in multiple rows and columns; In the mth row of sub-pixels, the array substrate includes a row of first sub-pixels of a first color; In the (m+1)th row of sub-pixels, the array substrate includes a row of third sub-pixels of a third color; In the (m+2)th row of sub-pixels, the array substrate includes a row of second sub-pixels of a second color; In the nth column of sub-pixels, the array substrate includes a column of third sub-pixels of the third color; In the (n-1)th column of sub-pixels, the array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color that are alternately arranged; In the (n+1)th column of sub-pixels, the array substrate includes a column of first sub-pixels of the first color and second sub-pixels of the second color that are alternately arranged; The first signal line portion among the multiple first signal line portions is connected to one or more transistors in the pixel driving circuit in the third sub-pixel in the nth column and the (m+1)th row of sub-pixels, is connected to one or more transistors in the pixel driving circuit in the first sub-pixel in the (n-1)th column and the mth row of sub-pixels, and is connected to one or more transistors in the pixel driving circuit in the second sub-pixel in the (n+1)th column and the (m+2)th row of sub-pixels.

30. The array substrate according to claim 29, wherein: A second signal line portion among the multiple second signal line portions connects the first signal line portion to a first adjacent first signal line portion, and the first adjacent first signal line portion is connected to one or more transistors in a pixel driving circuit in a second sub-pixel in the (n-1)th column sub-pixel and the (m+2)th row sub-pixel.

31. The array substrate according to claim 29, wherein: A third signal line portion among the multiple third signal line portions connects the first signal line portion to a second adjacent first signal line portion, and the second adjacent first signal line portion is connected to one or more transistors in the pixel driving circuit in the first sub-pixel in the (n+1)th column sub-pixel and the mth row sub-pixel.

32. The array substrate according to claim 29, further comprising a plurality of light-transmitting areas; in, In the n-th column of sub-pixels, each of the plurality of light-transmitting regions separates two adjacent third sub-pixels.

33. The array substrate according to any one of claims 26 to 32, wherein: The plurality of signal lines include a plurality of initialization signal lines; The plurality of first signal line portions include a plurality of first initialization signal line portions; The plurality of second signal line portions include a plurality of second initialization signal line portions; and The plurality of third signal line portions include a plurality of third initialization signal line portions.

34. The array substrate according to any one of claims 26 to 33, wherein: The plurality of signal lines include a plurality of gate signal lines; The plurality of first signal line portions include a plurality of first gate signal line portions; The plurality of second signal line portions include a plurality of second gate signal line portions; and The plurality of third signal line portions include a plurality of third gate signal line portions.

35. The array substrate according to any one of claims 26 to 34, wherein: The plurality of signal lines include a plurality of reset control signal lines; The plurality of first signal line portions include a plurality of first reset control signal line portions; The plurality of second signal line portions include a plurality of second reset control signal line portions; and The plurality of third signal line portions include a plurality of third reset control signal line portions.

36. The array substrate according to any one of claims 26 to 35, wherein: The plurality of signal lines include a plurality of light emission control signal lines; The plurality of first signal line portions include a plurality of first light emission control signal line portions; The plurality of second signal line portions include a plurality of second light emission control signal line portions; and The plurality of third signal line portions include a plurality of third light emission control signal line portions.

37. The array substrate according to any one of claims 26 to 31 and 33 to 36, further comprising a plurality of light-transmitting areas; in, The array substrate comprises a first conductive layer, a second conductive layer, a first signal line layer, a third signal line layer and an anode layer; The signal lines and electrodes of the first conductive layer, the second conductive layer, the first signal line layer, the third signal line layer, and the anode layer do not exist in the plurality of light-transmitting regions.

38. The array substrate according to claim 37, further comprising a second signal line layer; in, The signal line in the second signal line layer includes a substantially transparent conductive material; as well as The signal lines of the second signal line layer exist in the plurality of light-transmitting regions.

39. The array substrate according to claim 38, wherein: The plurality of second signal line portions and the plurality of third signal line portions are located in the second signal line layer; and The plurality of first signal line portions are located in the first conductive layer or the second conductive layer.

40. A display device comprising the array substrate according to any one of claims 21 to 39, and one or more integrated circuits connected to the array substrate.

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