A chip testing method, device and electronic device

Abstract

The present application provides a chip testing method, apparatus and electronic device, relating to the technical field of chip testing, including: obtaining application requirement information of a target test chip; determining a test period and a parallel distributed test layout structure through parallel testing, and determining a first coverage set; determining a test depth and a cross distributed test layout structure through cross testing, and determining a second coverage set; simulating a test environment based on the test period and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, and iteratively testing the target test chip according to the first coverage set and the second coverage set. By means of the present application, the technical problem in the prior art that due to the increased complexity of chips and the improved requirement for test coverage, the efficiency of chip testing is poor can be solved. By establishing two coverage sets and combining parallel and cross test layouts, the coverage rate and efficiency of chip testing are improved.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and particularly to a chip testing method, device, and electronic device. Background Art

[0002] With the continuous development of technology, chip technology plays an increasingly important role in various fields. As the core of modern electronic devices, it undertakes extremely complex computing and control tasks. With the improvement of integration, the structure of chips has become more and more complex, adopting advanced technologies such as multi-core, 3D packaging, and heterogeneous computing. With the continuous progress of the manufacturing process technology, the size of chips has gradually shrunk and entered the nanometer process, enabling a single chip to accommodate more functions and higher performance. Existing chip testing methods usually adopt functional testing, scan chain testing, parameter testing, automated testing, etc. Although they can effectively detect some common functional failures and parameter anomalies, with the increase in chip complexity, existing testing methods face many challenges. After the complexity of the chip increases, the interaction between functional modules becomes more complex. Existing testing methods are difficult to comprehensively cover all functions and interaction modes, and it is easy to overlook some boundary conditions or low-probability failure modes. In addition, with the increase in the complexity of chip functions and structures, the number of test cases has increased sharply, and each possible failure mode needs to be verified, resulting in too long test time and low efficiency.

[0003] In summary, there is a technical problem in the prior art that due to the increase in chip complexity and the improvement of test coverage requirements, it is difficult for chip testing to comprehensively cover all functions and potential failure modes, and it is easy to overlook some boundary conditions or low-probability failures, resulting in poor efficiency of chip testing. Summary of the Invention

[0004] The purpose of this application is to provide a chip testing method, device, and electronic device to solve the technical problem in the prior art that due to the increase in chip complexity and the improvement of test coverage requirements, it is difficult for chip testing to comprehensively cover all functions and potential failure modes, and it is easy to overlook some boundary conditions or low-probability failures, resulting in poor efficiency of chip testing.

[0005] In view of the above problems, this application provides a chip testing method, device, and electronic device.

[0006] In a first aspect, the present application provides a chip testing method, which is implemented by a chip testing device. Among them, the chip testing method includes: obtaining application requirement information of a target test chip, setting a plurality of test cases, and the plurality of test cases include a plurality of test marking points; according to the test marking points, in a parallel testing manner, determining a test period and a parallel distributed testing layout structure; according to the test marking points, in a cross-testing manner, determining a test depth and a cross distributed testing layout structure; based on the plurality of test cases, through the test period and the parallel distributed testing layout structure, determining a first coverage set; based on the plurality of test cases, through the test depth and the cross distributed testing layout structure, determining a second coverage set; through the test period and the parallel distributed testing layout structure, the test depth and the cross distributed testing layout structure, simulating a test environment according to the first coverage set and the second coverage set, and performing iterative testing on the target test chip.

[0007] In a second aspect, the present application further provides a chip testing device for executing the chip testing method described in the first aspect. Among them, the chip testing device includes: a test case setting module, which is used to obtain application requirement information of a target test chip and set a plurality of test cases, and the plurality of test cases include a plurality of test marking points; a parallel testing module, which is used to determine a test period and a parallel distributed testing layout structure in a parallel testing manner according to the test marking points; a cross-testing module, which is used to determine a test depth and a cross distributed testing layout structure in a cross-testing manner according to the test marking points; a first coverage module, which is used to determine a first coverage set based on the plurality of test cases through the test period and the parallel distributed testing layout structure; a second coverage module, which is used to determine a second coverage set based on the plurality of test cases through the test depth and the cross distributed testing layout structure; a simulation testing module, which is used to simulate a test environment according to the first coverage set and the second coverage set through the test period and the parallel distributed testing layout structure, the test depth and the cross distributed testing layout structure, and perform iterative testing on the target test chip.

[0008] In a third aspect, the present application further provides an electronic device, including: at least one processor; a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the steps of the chip testing method described in any item of the first aspect above.

[0009] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0010] By obtaining the application requirement information of the target test chip, multiple test cases are set, and the multiple test cases include multiple test marking points; according to the test marking points, in a parallel test manner, the test cycle and the parallel distributed test layout structure are determined; according to the test marking points, in a cross-test manner, the test depth and the cross distributed test layout structure are determined; based on the multiple test cases, through the test cycle and the parallel distributed test layout structure, a first coverage set is determined; based on the multiple test cases, through the test depth and the cross distributed test layout structure, a second coverage set is determined; through the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, and based on the first coverage set and the second coverage set, a test environment is simulated to perform iterative testing on the target test chip. That is to say, through the application requirement information of the target test chip, multiple test cases are determined, a distributed layout design combining parallel testing and cross testing is introduced, and combined with the evaluation of the coverage set and the iterative testing of the simulation environment, the problems of low test efficiency and insufficient coverage rate caused by the increased complexity of the chip are solved, and the coverage rate and efficiency of chip testing are improved.

[0011] The above description is only an overview of the technical solutions of this application. In order to be able to understand the technical means of this application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of this application more obvious and understandable, the following specific embodiments of this application are specifically given. It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of this application, nor is it used to limit the scope of this application. Other features of this application will become easily understood through the following description. Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions in this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only exemplary, and for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0013] Figure 1 It is a schematic flow chart of a chip testing method of this application;

[0014] Figure 2 It is a schematic structural diagram of a chip testing device of this application;

[0015] Figure 3This is a schematic structural diagram of an exemplary electronic device of the present application.

[0016] Description of reference numerals: Test case setting module 11, parallel test module 12, cross test module 13, first coverage module 14, second coverage module 15, simulation test module 16, bus 300, receiver 301, processor 302, transmitter 303, memory 304, bus interface 305. Detailed implementation manners

[0017] By providing a chip testing method, device and electronic device, the present application solves the technical problem in the prior art that due to the increasing complexity of chips and the increasing requirements for test coverage, it is difficult to comprehensively cover all functions and potential failure modes in chip testing, and it is easy to overlook some boundary conditions or low-probability failures, resulting in poor efficiency of chip testing. By determining multiple test cases based on the application requirement information of the target test chip, introducing a distributed layout design combining parallel testing and cross testing, and combining the evaluation of the coverage set and the iterative testing of the simulation environment, the problems of low testing efficiency and insufficient coverage caused by the increasing complexity of chips are solved, and the coverage and efficiency of chip testing are improved.

[0018] Next, the technical solutions in the present application will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the present application is not limited by the exemplary embodiments described herein. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application. Additionally, it should be noted that for the sake of description, only the parts related to the present application are shown in the accompanying drawings rather than all of them.

[0019] Embodiment 1. Please refer to the attached Figure 1 The present application provides a chip testing method. Among them, the chip testing method is applied to a chip testing device, and the chip testing method specifically includes the following steps:

[0020] Step 1: Obtain the application requirement information of the target test chip and set multiple test cases, where the multiple test cases include multiple test marking points.

[0021] Specifically, by analyzing the product specification, user requirement document, and communicating with the chip design team, the application requirement information of the target test chip is obtained, that is, various performance and function requirement information related to the actual application scenario of the target chip, including the working environment of the chip in a specific device, required speed, power consumption, stability, etc. The target test chip refers to the chip that needs to be tested during the chip design, production, or function verification process, including microprocessors, sensors, communication modules, etc., and is usually the core component in product development. According to the application requirement information of the target chip, multiple test cases are designed, including functional tests, performance tests, environmental tests, etc., to ensure that the performance of all aspects of the chip can be verified in actual applications. In each test case, several test marker points are set to identify the parts or stages that need special attention, usually the key nodes in the chip function implementation, to ensure that various parameters of the chip can be monitored in real time during the test. By obtaining the application requirements, it is ensured that the test cases and test marker points can comprehensively cover the application requirements of the chip, providing a clear direction and measurement standard for the subsequent test work.

[0022] Step 2: According to the test marker points, in a parallel test manner, determine the test cycle and the parallel distributed test layout structure.

[0023] Specifically, in chip testing, due to the complexity and diversity of chips, the number and types of test marker points are usually relatively large. To improve the test efficiency and ensure the comprehensiveness of the test, a parallel test method can be used for testing. Parallel testing means that multiple test tasks are carried out simultaneously instead of serially, thus saving time and improving efficiency. The test marker point refers to the specific test location or test function that needs to be verified in the chip design or function. The parallel test method means that instead of testing each marker point sequentially in order, multiple test tasks are assigned to different test resources or test units, allowing multiple test tasks to be carried out simultaneously, significantly improving the test efficiency and shortening the test cycle. For example, suppose there are five test marker points A, B, C, D, and E. If the serial test method is used, each test marker point needs to be carried out sequentially in order. Assuming that each test takes 30 minutes, the total test time is 150 minutes. While using the parallel test method, different test tasks are assigned to different test resources, such as A and B are tested simultaneously using one device, and C, D, and E are tested simultaneously using another device, reducing the total test time.

[0024] The test cycle refers to the time required to complete a full round of testing. In parallel testing mode, the test cycle is determined by the slowest test task because all test tasks need to be completed within the same time window. If there are more test devices and more efficient test processes, the test cycle can be significantly shortened. Suppose test marker point A takes 10 minutes, B takes 20 minutes, and C takes 30 minutes. If these tasks are carried out simultaneously, the total time of the parallel test cycle is 30 minutes (i.e., the test task with the longest time). During the parallel test, it is necessary to reasonably allocate the test resources and time required for each test marker point to ensure that the test is completed in the shortest time. Predict the duration of each test task based on the complexity and required resources of each test marker point, and comprehensively consider the longest time required for parallel test tasks to determine the overall test cycle.

[0025] In parallel testing mode, to improve resource utilization and test efficiency, test tasks are assigned to multiple test devices or test units to form a distributed test structure, and each test unit can perform different test tasks in parallel. For example, suppose there are five test marker points A, B, C, D, E and three test devices: X, Y, Z. The test marker points are assigned as follows: Device X: A, B; Device Y: C, D; Device Z: E. Each device performs different test tasks in parallel. Eventually, the test tasks of devices X, Y, and Z will be completed within the same time period, saving the overall test time. The parallel distributed layout of test marker points needs to be optimized to ensure the full utilization of resources. Test resources include hardware devices (such as test instruments, simulators, etc.) and software tools (such as automated test frameworks). To achieve an efficient test process, different types and quantities of resources are allocated according to the requirements of different test marker points.

[0026] The parallel distributed test layout structure refers to how to allocate test tasks to different test resources, and factors such as the performance of test resources, the dependency relationships of test tasks, and communication delays need to be considered. In parallel testing, due to multiple test tasks being carried out simultaneously, resource contention may occur, resulting in a loss of test accuracy. Therefore, it is necessary to first evaluate the accuracy loss based on test marker points. To ensure the accuracy of test results, an acceptable accuracy loss threshold is set according to the application requirements and test objectives of the chip. In parallel testing, it is necessary to synchronize the progress of each test task to ensure the coordination and consistency of the test, which is usually achieved through test management software. It can monitor the execution of each test task and make adjustments when the task progress deviates. According to the accuracy loss threshold and test task progress, it may be necessary to reallocate parallel test tasks and update the parallel distributed test layout structure to ensure the efficient utilization of test resources and the balanced allocation of test tasks.

[0027] Analyze the functional requirements of each test marker point, determine its test time, required resources and difficulty, and evaluate the complexity of each test marker point. According to the complexity of each test marker point, assign different tasks to different parallel test devices. Based on the allocation structure of parallel testing, calculate the completion time of the slowest task, which is the test cycle. Optimize the resource allocation in real time according to the actual progress and task completion status. For example, if a certain task is progressing slowly, allocate more resources to this task to ensure that the entire test process proceeds as planned. By means of parallel testing, the time for the entire chip test can be significantly shortened. Especially when there are many test marker points, the parallel execution of multiple test tasks can be carried out simultaneously, thus reducing the overall test cycle.

[0028] Step 3: According to the test marker points, in a cross-testing manner, determine the test depth and the cross-distributed test layout structure.

[0029] Specifically, in the chip testing process, cross-testing is a complex test strategy. By cross-executing test tasks between different test marker points, it can more comprehensively evaluate the functions and performance of the chip. The purpose is to more deeply explore potential problems of the chip under different working conditions and loads to ensure higher test coverage and lower omission probability. During the testing process, some test marker points may involve multiple inputs or conditions. Cross-testing is to combine these conditions with the conditions of other marker points for combined testing to simulate more complex application scenarios. By crossing different test points, conditions or parameters, potential errors and failure modes can be discovered.

[0030] The test depth refers to the levels and combinations of test conditions and parameters involved in cross-testing. The greater the test depth, the more scenarios and combinations are covered by the test, and more potential failure modes can be discovered. For example, if the performance of the chip may vary under different environments (such as temperature, voltage, clock frequency, etc.), then the test depth of cross-testing is the combination of these environmental conditions. In cross-testing, the test depth is usually selected according to the functional complexity of the chip, test objectives, resources and time limitations, etc. Each combination needs to be tested separately, and the test depth of each combination will be determined according to the characteristics of the chip.

[0031] The cross-distributed test layout structure refers to, according to the requirements of cross-testing, distributing test tasks to multiple resource units or test devices to form a distributed test system. During the cross-testing process, different combinations of test marker points will be assigned to different devices for simultaneous testing. The cross-distributed test layout structure not only requires reasonable allocation of test tasks, but also ensures that each combination of test marker points can be completed within a reasonable time range. The rationality of the layout directly affects the test efficiency and coverage, and the layout can be optimized through resource allocation, load balancing, parallel execution, etc.

[0032] Analyze which combinations of marker points need to be cross-tested, which marker points are independent, and which combinations may lead to higher failure rates or errors, and evaluate the combination relationships of each test marker point. Based on the functional complexity of the chip, test objectives, and resource limitations, determine the test depth and the combinations of test marker points required, determine the test conditions for each combination of test marker points, that is, the depth of cross-testing. Allocate the test tasks to different test devices and ensure load balancing and optimal use of resources. Design a reasonable test layout to ensure the smooth progress of parallel and cross-testing. Through the designed cross-test layout structure, execute the tests and collect the test results of each combination of test marker points. According to the results of the cross-tests, analyze the performance of the chip under different combination conditions, and optimize the test strategy based on the test results. By cross-combining different test conditions, certain low-probability failure modes can be revealed. These failures may not be easily detected during individual tests. The test that combines multiple test marker points can efficiently evaluate the chip performance under different conditions, avoid repeated tests at the same time, and improve the utilization efficiency of resources.

[0033] Step 4: Based on the multiple test cases, determine the first coverage set through the test cycle and the parallel distributed test layout structure.

[0034] Specifically, the multiple test cases target different chip functions, working conditions, and potential failure modes to verify whether the specific functions of the chip or system work as expected. Through the set multiple test cases, test cycle, and parallel distributed test layout structure, determine the first coverage set, that is, the set of chip functions or failure modes actually covered during the test. The first coverage set reflects all the parallelly executed test cases and can ultimately cover various functions and potential failure modes of the chip.

[0035] According to the application requirements of the target chip, select multiple representative test cases, which cover multiple aspects of the chip functions, such as power consumption, stability, electromagnetic compatibility, etc. Through parallel testing, multiple test cases are executed simultaneously on multiple test resources, shortening the test time and improving the test efficiency. According to the test cycle requirements, adjust the execution order of each test case and the resource allocation of the test devices. If the test cycle is short, select to test the more critical functions first, and other secondary functions can be tested in subsequent stages. After all parallel test tasks are completed, summarize the functions or failure modes covered by each test case to form the first coverage set, which includes all the chip functions covered by the test cases.

[0036] The process of determining the first coverage set involves the analysis and prioritization of test cases. Usually, test cases for critical functions and high-risk areas are given priority. Then, based on the test cycle and the availability of test resources, the set of test cases that can be executed is determined. By determining the first coverage set, it is ensured that under the constraints of limited time and resources, the test coverage is maximized. Through the parallel distributed test layout structure, the test efficiency can be improved while ensuring the test coverage of critical functions.

[0037] Step Five: Based on the multiple test cases, determine the second coverage set through the test depth and the cross-distributed test layout structure.

[0038] Specifically, according to the test depth requirements, each test case is analyzed in depth to ensure that the test can cover all important functions and performance boundaries of the chip. Using the cross-distributed test layout structure, the test cases are tested in different orders and combinations to simulate various situations that may be encountered in actual use, realizing cross-testing. Different test cases, test conditions, or working states can be cross-executed on different devices to ensure the comprehensiveness and diversity of the test.

[0039] Determine multiple test cases that cover different functions of the chip, including the power consumption, stability, voltage, and temperature adaptability of the chip, etc. For each test case, set different test depths. According to the working environment that the chip may face, design a cross-testing scheme. At multiple cross-testing points, conduct in-depth tests to evaluate the performance of the chip under complex conditions. After all the depth tests and cross-tests are completed, summarize the chip functions and failure modes covered to form the second coverage set, which includes the performance of the chip under various extreme conditions, further ensuring the comprehensiveness of the test. The second coverage set refers to the set of chip functions, failure modes, or performance issues covered based on cross-testing and test depth, usually involving more fine-grained tests, especially the performance of the chip under extreme conditions or complex working modes. By setting multiple test depths and cross-tests, it is possible to comprehensively cover the performance of the chip under various extreme conditions, especially conduct in-depth analysis of the long-term stability of the chip and its performance under extreme conditions, cover potential failures of the chip under various environmental conditions, especially low-probability failure modes that may not be detected under a single condition, ensuring the comprehensiveness and efficiency of the test, thereby improving the quality and reliability of the chip.

[0040] Step Six: Through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, simulate the test environment based on the first coverage set and the second coverage set, and conduct iterative testing on the target test chip.

[0041] Specifically, in complex chip testing, multiple factors (such as test cycle, test layout, coverage, etc.) need to work in coordination to ensure comprehensive testing of the chip. That is to say, through a reasonable test cycle and layout structure, combined with the coverage set, an efficient simulation test environment is established and iterative testing is carried out to ensure that the performance and reliability of the chip can be verified under different conditions. The first coverage set obtained through the parallel distributed test layout structure is combined with the test cycle and the parallel distributed test layout structure. The second coverage set obtained through the cross distributed test layout structure is combined with the test depth and the cross distributed test layout structure to construct a simulation test environment, that is, a test environment similar to the actual operating environment is created through virtualization or simulation technology. This enables multiple rounds of testing to be carried out under controlled conditions to evaluate the performance, stability, and reliability of the chip. Iterative testing refers to the process of adjusting and continuously improving the test plan based on the results of the previous round of testing during the testing process. It is a cyclic process in which analysis and feedback are carried out after each round of testing, thereby improving the comprehensiveness and accuracy of the testing. Through iterative testing, potential problems that may exist in the chip can be gradually discovered, and the stability and reliability of the chip can be gradually improved. By reasonably arranging the test cycle, parallel distributed test layout, test depth, and cross distributed test layout structure, efficient and comprehensive chip testing can be achieved. Combining the first coverage set and the second coverage set, iterative testing is carried out in the simulation test environment to ensure the performance stability of the chip under complex conditions, significantly improving the test efficiency, comprehensiveness, and accuracy, thereby providing reliable quality assurance for the research and development and production of the chip.

[0042] Further, step one of this application includes:

[0043] Obtain a type of key requirement indicators in the application requirement information, where the type of key requirement indicators is related to the reliability of the target test chip. The type of key requirement indicators includes anti-vibration requirements and electromagnetic compatibility requirements; set a reliability verification link through the anti-vibration requirements and electromagnetic compatibility requirements in the type of key requirement indicators; under the constraint of the resource synchronization monitoring mechanism, seamlessly integrate the reliability verification link into the test operation stage for resource balanced scheduling.

[0044] Specifically, according to the actual application scenarios of the chip, specific requirements regarding the chip's functions, performance, environmental adaptability, etc. are obtained. Among numerous application requirements, key requirement indicators refer to the requirements that are crucial for the chip's performance and determine whether it can operate normally in actual applications, and are vital for aspects such as the chip's reliability, stability, and security. A category of key requirement indicators related to reliability is obtained from the application requirement information, including anti-vibration requirements and electromagnetic compatibility requirements. The anti-vibration requirement means that the chip needs to maintain normal operation without malfunction or performance degradation when subjected to mechanical forces such as vibration or shock. The electromagnetic compatibility requirement means that the chip must be able to operate normally in an electromagnetic environment, not be affected by electromagnetic interference (EMI), and not generate excessive electromagnetic radiation (EMC) to interfere with other devices. A category of key requirement indicators is associated with the reliability of the target test chip and directly affects the performance and stability of the chip in actual applications.

[0045] Based on the anti-vibration requirements and electromagnetic compatibility requirements in a category of key requirement indicators, a reliability verification session is set up, that is, a series of test sessions, to verify the performance and stability of the chip under these specific conditions. The reliability verification session refers to the test processes and steps designed to verify the chip's reliability, focusing on whether the chip can maintain normal operation in environments such as vibration and electromagnetic interference. Reliability verification not only tests the chip's performance in a normal operating environment but also includes the chip's performance under harsh conditions, such as its stability when operating in environments such as high temperature, high humidity, vibration, and electromagnetic interference. For example, combining vibration testing with electromagnetic compatibility testing to ensure that the chip can operate stably under complex environmental conditions.

[0046] The purpose of reliability verification is to ensure that the chip operates stably in the expected working environment, prevent potential failure modes, ensure the stability of the chip during long-term use, optimize product design, etc. By simulating the working state of the chip under different environmental conditions, including high-temperature testing, low-temperature testing, humidity testing, etc., the tolerance of the chip is tested; the performance of the chip in a vibration environment is simulated, and the drop impact it receives during transportation or use is checked to see if the physical structure and electronic functions of the chip are affected. The chip is quickly switched from an extremely high or low temperature environment to another environment in a short period of time to detect the chip's heat stress and thermal expansion capabilities. The working stability of the chip in an electromagnetic interference environment is tested, and at the same time, it is ensured that the electromagnetic radiation of the chip itself does not affect other devices. The power consumption of the chip is tested through high-load operation and long-term operation to ensure that the chip does not overheat or fail during high-power operation. The reaction of the chip when subjected to overvoltage or overcurrent is tested to ensure that it has sufficient overload resistance. By exposing the chip to extreme environmental conditions (such as high temperature, high humidity, strong electromagnetic interference, etc.), the long-term use of the chip is simulated so as to obtain the life prediction data of the chip in a relatively short period of time; the reliability of the chip during long-term use is evaluated, such as the number of insertions and removals of the connector, the number of switchings of the chip, etc., to determine the mechanical life.

[0047] Before conducting reliability verification, it is necessary to clarify the reliability standards required for the chip, which are usually determined by the chip's design requirements, industry standards (such as ISO9001, MIL-STD, etc.), and customer needs. According to the application scenario and key requirements of the chip, appropriate test methods are selected. For example, for communication chips, EMC testing and power consumption testing are relatively important. According to the application and test requirements of the chip, a detailed test plan is formulated, clarifying the test conditions, test time, and test objectives for each test link. Professional test equipment and environment are used to execute each test link according to the plan. During the test process, test data should be recorded in real time, and fault analysis should be carried out based on the test results. After the test is completed, the test data is analyzed to find possible failure modes or performance deviations, and the chip's design or manufacturing process is adjusted based on the test result analysis.

[0048] During the actual chip testing process, it may be necessary to conduct multiple test links simultaneously (such as vibration resistance testing, electromagnetic compatibility testing, functional testing, etc.). To avoid waste of resources or test conflicts, it is necessary to reasonably schedule the test tasks. Suppose there are multiple test devices that need to be used at the same time, such as a vibration table and an EMC tester. Through the scheduling system, according to the priority and time requirements of each test link, the execution order and required resources of each test task are reasonably arranged. The resource synchronization monitoring mechanism refers to monitoring and coordinating the use of all test resources (such as test equipment, test personnel, computing power, etc.) in real time during the chip testing process to ensure the efficient cooperation of each test link and the reasonable allocation of resources.

[0049] Under the constraint of the resource synchronization monitoring mechanism, the reliability verification link is integrated into the test operation stage, that is, the reliability verification link (such as vibration resistance test, electromagnetic compatibility test) is seamlessly integrated with other function tests, performance tests and other links. Through a unified resource scheduling platform, the operation and monitoring links of test equipment are coordinated to avoid resource conflicts and ensure that all test links can be executed smoothly. Resource balanced scheduling means that in the case of multiple test links running simultaneously, the test resources are reasonably allocated to avoid over-concentration or waste of resources, ensure that each test case can obtain appropriate resource support, and at the same time will not affect the normal operation of other test links. The test operation stage refers to all links from test design, execution to result analysis in the chip test process. The test operation stage involves multiple stages and different types of tests, such as function verification, performance verification, environmental adaptability test, reliability test, etc. Through reasonable scheduling and resource synchronization monitoring, the smooth progress of different test links is ensured, resource conflicts and test delays are reduced, and the overall test efficiency is improved.

[0050] Furthermore, the present application further includes the following steps:

[0051] Obtain the secondary key requirement indicators in the application requirement information, where the secondary key requirement indicators are associated with the stability of the target test chip, and the secondary key requirement indicators include signal reception sensitivity requirements, transmit power requirements and spectral efficiency requirements; set the stability verification link through the signal reception sensitivity requirements, transmit power requirements and spectral efficiency requirements in the secondary key requirement indicators; under the constraint of the resource synchronization monitoring mechanism, seamlessly integrate the stability verification link into the test operation stage and perform resource balanced scheduling.

[0052] Specifically, according to the application scenario and expected usage environment of the chip, obtain the secondary key requirement indicators related to stability, including signal reception sensitivity requirements, transmit power requirements and spectral efficiency requirements. The signal reception sensitivity requirement refers to the minimum signal strength that the chip can detect when receiving a signal, and is used to evaluate the reception ability of a wireless communication device or module under low signal strength. The transmit power requirement refers to the output power of the chip when transmitting a signal, which usually affects the coverage range and transmission distance of communication. Too low transmit power may result in insufficient communication distance, while too high transmit power may cause energy waste or electromagnetic interference. The spectral efficiency requirement refers to the ability of the chip or device to efficiently transmit data within a certain bandwidth. High spectral efficiency means that more information can be transmitted under limited spectral resources. Spectral efficiency is usually measured in bits per hertz (bps / Hz) and is an important indicator of the performance of a communication system.

[0053] Determine the corresponding stability verification links for each secondary key requirement indicator. The signal reception sensitivity verification verifies whether the chip can stably receive the expected minimum signal strength by simulating environments with different signal strengths; the transmit power verification ensures that the chip can maintain stable signal transmission under different environmental conditions by controlling the transmit power and testing the chip's performance at different power outputs; the spectral efficiency verification evaluates whether the spectral efficiency meets the design requirements by testing the maximum data transmission rate of the chip within a certain bandwidth.

[0054] Similarly, under the constraint of the resource synchronization monitoring mechanism, the stability verification links are also seamlessly integrated into the test operation stage for resource balanced scheduling. When conducting stability verification tests, multiple test devices (such as signal generators, spectrum analyzers, oscilloscopes, etc.) need to work in coordination. The resource synchronization monitoring mechanism ensures that the operating status of each test device is fed back to the system in real time and adjusted to avoid resource conflicts or excessive idle time of test devices. For example, when verifying signal reception sensitivity, a spectrum analyzer is needed to measure the received signal strength, while a signal generator provides signal sources with different strengths. Through the synchronization monitoring mechanism, these devices are scheduled in real time to ensure that the tests are carried out as planned. During the stability verification process of the chip, the test links and resource requirements may proceed in parallel. Through resource balanced scheduling, ensure that each test link obtains appropriate resource support and avoid overloading of devices or delays in test links. By verifying signal reception sensitivity, transmit power, and spectral efficiency, ensure that the chip can work stably under different environments, improving the overall stability of the chip.

[0055] Furthermore, the present application further includes the following steps:

[0056] Based on the reliability verification links and stability verification links, establish a resource configuration optimization function; denote the total number of the test marking points as K, and the resource configuration optimization function ( ) ; where, R opt is the optimal resource configuration, R k is the actual resource configuration corresponding to the kth test marking point, D k is the resource requirement corresponding to the kth test marking point, λ is the coefficient for weighing between resource configuration and comprehensive evaluation value, and the comprehensive evaluation value , where, is the test result of the ith reliability verification link, is the test result of the jth stability verification link, and are the weights corresponding to the reliability verification links and stability verification links.

[0057] Specifically, based on the requirements for reliability and stability in chip testing, an optimization function for resource allocation is established to optimize the allocation of test resources, ensuring that each verification link (reliability verification and stability verification) is completed as efficiently as possible under limited resources. Denote the total number of test marking points as K, representing different functional points or performance indicators to be verified in the test task. The resource allocation optimization function ( ); where R opt is the optimal resource allocation, that is, the resources allocated to each test marking point. R k is the actual resource allocation corresponding to the k-th test marking point, which can be test equipment, time, or other resource-related quantities. D k is the resource requirement corresponding to the k-th test marking point, and each test marking point requires different amounts of resources according to the complexity of the test and the verification link. represents the resource allocation error of the k-th test marking point. The two should be as close as possible to reduce resource waste and improve the accuracy of the test. λ is the coefficient between resource allocation and the comprehensive evaluation value, used to balance the weight between the accuracy of resource allocation and the comprehensive evaluation value. By adjusting λ, the optimal balance can be found between the resource allocation error and the comprehensive evaluation value. is a term reflecting the difference between the comprehensive evaluation value and the target value. The comprehensive evaluation value measures the overall effect or quality of the test process and is required to be close to 1, indicating the efficiency and quality of the test process.

[0058] Next, the expression of the comprehensive evaluation value is: , where is the comprehensive evaluation value, representing the overall performance or quality of the test process, which depends on the test effects of all reliability verification links and stability verification links. is the test result of the i-th reliability verification link, is the test result of the j-th stability verification link, and are the weights corresponding to the reliability verification link and the stability verification link. represents the weighted sum of all reliability verification links, reflecting the impact of reliability verification on the overall evaluation. is the weighted sum of all stability verification links, reflecting the impact of stability verification on the overall evaluation.

[0059] Resource allocation error means that for each test marking point, the resource allocation is made as close as possible to the required resources, effectively reducing resource waste and ensuring the comprehensiveness of the test. The comprehensive evaluation value reflects the overall performance of all test links (reliability and stability verification links). The test links not only require resource support but also high-quality verification results. The comprehensive evaluation value will weigh the test effects of these links. The reliability verification link may involve tests of electromagnetic compatibility and anti-vibration performance, while the stability verification link focuses on signal reception sensitivity, etc. Each link has its corresponding weight. By optimizing the comprehensive evaluation value, the effectiveness and test quality of these verification links are ensured. The λ coefficient controls the balance between the resource allocation error and the comprehensive evaluation value. If the value of λ is large, the optimization process will be more inclined to reduce the resource allocation error, that is, more focused on accurately allocating resources. If the value of λ is small, the optimization process will pay more attention to improving the comprehensive evaluation value, that is, ensuring the quality of the test results. By solving this resource allocation optimization function, an optimal resource allocation R will ultimately be obtained. opt , which means that under the given resource constraints and test requirements, the most effective resource allocation and the optimal test quality can be achieved. Through the resource allocation optimization function, each link of the test task (such as reliability verification and stability verification) can be executed with the optimal resource allocation, avoiding problems such as resource waste or unreasonable resource allocation.

[0060] Furthermore, step two of this application includes:

[0061] Based on the test marking points, evaluate the accuracy loss and set an accuracy loss threshold; in the way of parallel testing, synchronize the progress of the test task; through the accuracy loss threshold and the test task progress, reallocate the parallel test tasks and update the parallel distributed test layout structure.

[0062] Specifically, in chip testing, the performance indicators corresponding to the test marking points (such as power consumption, voltage, current, signal transmission speed, etc.) may deviate due to different test methods. The purpose of the accuracy loss evaluation is to detect the degree of this deviation and ensure that the test results do not exceed the set tolerance range. When the load of the test equipment is high, it may lead to a decrease in test accuracy. For example, if the computing power of the test equipment is insufficient to process multiple test marking points simultaneously, resulting in inaccurate results. The accuracy loss evaluation is to analyze this error and make adjustments within an acceptable range. To ensure that the accuracy of parallel testing meets the requirements, an accuracy loss threshold needs to be set, which is a predefined tolerance range. When the accuracy loss of the test exceeds this threshold, measures need to be taken to adjust the test strategy.

[0063] In parallel testing, each test task is carried out in parallel. However, since the test order of test markers may affect the progress of the entire test process, it is necessary to synchronize the progress of each test task to ensure the efficient operation of the entire test system. During parallel testing, some test markers may complete the test ahead of schedule, while other markers may progress slowly due to resource allocation issues or tasks with higher complexity. To ensure that all tasks can be completed within a reasonable time, the test system needs to monitor the progress of each task, adjust the test strategy in a timely manner, and ensure that all tasks can be completed within a reasonable time window, avoiding affecting the overall test progress due to the lag of a single test marker. Reallocate parallel test tasks according to the precision loss threshold and the progress of test tasks. That is to say, when the precision loss of some markers during the test exceeds the set threshold, or the progress of test tasks is uneven, it is necessary to readjust the resource allocation of test tasks to optimize the test efficiency.

[0064] If the precision loss of a certain test marker exceeds the set threshold (such as test interruption or device resource overload), ensure that the precision meets the requirements by reallocating other resources. For example, allocate more powerful computing resources to this marker or extend its test time to compensate for the precision loss. When some tasks progress slowly, ensure the balance of the test progress by increasing resources or adjusting the task order. For instance, when the test progress of a certain test marker lags behind due to device failure or insufficient resources, other idle devices can be dynamically scheduled for supplementation.

[0065] The layout structure of parallel testing refers to the distribution of test tasks on multiple test devices. During the test process, as the task progress changes and the precision loss is evaluated, it is necessary to continuously adjust and update the layout structure of test tasks. For example, if the task progress of a certain test marker lags behind, allocate this task to a device with relatively idle resources, or split it into smaller subtasks and distribute them to multiple devices; if the resources of some test devices are already fully loaded, migrate some test tasks to other devices to maintain load balance and test progress synchronization. Through precision loss evaluation and adjustment, ensure the precision and reliability of the test, avoid test result errors caused by insufficient resources or overloaded device loads, and maintain high-precision test results while ensuring test coverage.

[0066] Furthermore, step six of this application includes:

[0067] Obtain the basic power consumption parameters of the target test chip; based on the basic power consumption parameters, initialize and configure the test environment to establish an initial test environment with overvoltage protection mechanism and overcurrent protection mechanism; based on the initial test environment, set the test running stage through the test cycle and parallel distributed test layout structure, and the test depth and cross distributed test layout structure.

[0068] Specifically, the basic power consumption parameters of the target test chip are obtained through the data sheet, design document, or by measuring the power consumption of the chip, that is, the power consumed by the target test chip under different working states, including static power consumption, dynamic power consumption, peak power consumption, average power consumption, etc. For example, in laboratory tests, a power analyzer is used to monitor the power consumption of the chip under different workloads. According to the basic power consumption parameters, the test environment is initialized and configured to set an environment with necessary protection mechanisms, that is, the test environment is initialized to ensure that the chip is not damaged due to power consumption problems during the test. The initialized test environment has overvoltage protection and overcurrent protection mechanisms. The overvoltage protection mechanism is used to protect the chip from voltage inputs exceeding its maximum rated voltage. The overvoltage protection mechanism can detect that the voltage exceeds the threshold and cut off the power supply to protect the chip from damage; the overcurrent protection mechanism is used to protect the chip from excessive current. Excessive current may cause short circuits or overheating in the internal circuits of the chip, or even burn out the chip. The overcurrent protection mechanism immediately cuts off or limits the current when the current exceeds the rated value of the chip to protect the chip from damage.

[0069] Initializing the test environment requires combining the aforementioned power consumption parameters with the protection mechanisms to ensure that the voltage and current during the test are within the safe operating range of the chip. The purpose of initializing and configuring the test environment is to ensure that the chip is not damaged due to overvoltage, overcurrent, etc. before other tests are performed. According to the previously defined test cycle, parallel distributed test layout structure, test depth, etc., the test running stage is set, and specific test tasks are arranged. The test running stage is the stage where the test tasks are actually executed during the chip test process. According to the test plan and resources, the execution of test cases is arranged to ensure that all test tasks are completed within the specified test cycle. Ensure the safety and stability of the test environment, while improving the efficiency and quality of the test. By reasonably setting the test running stage, the test coverage rate can be maximized, while minimizing the test cycle and resource consumption.

[0070] Furthermore, the present application further includes the following steps:

[0071] Based on the target test chip, at the test marking point, the rated calculation efficiency is added; taking the rated calculation efficiency as a boundary condition, the resource configuration corresponding to the test running stage is adjusted, and the resource configuration indicators include processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints; according to the resource configuration indicators, a resource synchronization monitoring mechanism is introduced, and the resource synchronization monitoring mechanism is used to match the resource demand changes corresponding to the test running stage.

[0072] Specifically, during the testing process of the target test chip, by setting the computing efficiency as a boundary condition, the resource allocation is adjusted, and a resource synchronization monitoring mechanism is used to monitor and adjust the changes in resource requirements in real time. The rated computing efficiency refers to the computing ability of the chip under a specific workload, usually manifested as the amount of computing tasks that can be completed per unit time, measured by the number of operations per second (OPS) or other performance metrics. The rated computing efficiency is usually determined by factors such as the chip's architecture design, clock frequency, number of cores, and parallel computing ability. Adding the rated computing efficiency at the test marking points means that during the testing process, in addition to verifying functionality and stability, it is also necessary to evaluate whether the chip's performance meets expectations. The rated computing efficiency is usually manifested as the amount of tasks that can be completed per second (e.g., floating-point operations per second or instructions per second), reflecting the computing performance of the chip under ideal conditions, and as a boundary condition, it can set the expectations for the chip's performance in the test.

[0073] By using the rated computing efficiency as a boundary condition, it can be ensured that during the testing process, the resources allocated to the chip will not be lower than the minimum resource requirements needed for its rated computing efficiency. Otherwise, the test results may not accurately reflect the actual performance of the chip or may cause the testing time to be too long. During the test running stage, resource allocation refers to the reasonable allocation of the computing resources required for chip testing, including processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints, ensuring that the use of resources during the testing process does not exceed the capabilities of the chip, thereby avoiding potential performance bottlenecks or resource conflicts. The resource synchronization monitoring mechanism is used to monitor the usage of various resources in real time during the testing process and dynamically adjust the resource allocation according to the changes in resource requirements, ensuring that during the testing process, the resources can be adjusted in a timely manner according to the real-time needs of the test tasks, avoiding resource overload or waste. As the test tasks progress, the requirements for processor, memory, and I / O resources change at different stages. By using monitoring tools (such as hardware monitoring sensors, operating system resource monitoring tools) to track the usage of various resources in real time, based on the monitored changes in resource requirements, the scheduler will dynamically adjust the resource allocation to meet the needs of the test tasks.

[0074] By setting the boundary condition based on the rated computing efficiency of the target test chip and dynamically adjusting the resource allocation during the test running stage, it can ensure the optimal use of resources, avoid resource waste and bottleneck problems. The resource synchronization monitoring mechanism ensures real-time response to changes in resource requirements during the testing process, further improving the testing efficiency and stability, making the chip testing process more accurate and efficient, and ultimately improving the test coverage and test quality of the chip.

[0075] In summary, a chip testing method provided by this application has the following technical effects:

[0076] By obtaining the application requirement information of the target test chip, multiple test cases are set, and the multiple test cases include multiple test marking points; according to the test marking points, in a parallel test manner, the test cycle and the parallel distributed test layout structure are determined; according to the test marking points, in a cross test manner, the test depth and the cross distributed test layout structure are determined; based on the multiple test cases, through the test cycle and the parallel distributed test layout structure, a first coverage set is determined; based on the multiple test cases, through the test depth and the cross distributed test layout structure, a second coverage set is determined; through the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, and based on the first coverage set and the second coverage set, a test environment is simulated to perform iterative testing on the target test chip. That is to say, through the application requirement information of the target test chip, multiple test cases are determined, a distributed layout design combining parallel testing and cross testing is introduced, and combined with the evaluation of the coverage set and the iterative testing of the simulation environment, the problems of low test efficiency and insufficient coverage rate caused by the increased chip complexity are solved, and the coverage rate and efficiency of chip testing are improved.

[0077] Embodiment 2. Based on the same inventive concept as a chip testing method in the foregoing Embodiment 1, the present application further provides a chip testing device. Please refer to the attached Figure 2 , the chip testing device includes:

[0078] A test case setting module 11, which is used to obtain the application requirement information of the target test chip and set multiple test cases, and the multiple test cases include multiple test marking points.

[0079] A parallel test module 12, which is used to determine the test cycle and the parallel distributed test layout structure in a parallel test manner according to the test marking points.

[0080] A cross test module 13, which is used to determine the test depth and the cross distributed test layout structure in a cross test manner according to the test marking points.

[0081] A first coverage module 14, which is used to determine a first coverage set based on the multiple test cases through the test cycle and the parallel distributed test layout structure.

[0082] A second coverage module 15, which is used to determine a second coverage set based on the multiple test cases through the test depth and the cross distributed test layout structure.

[0083] The simulation test module 16 is used to simulate a test environment for the target test chip through the test cycle and the parallel distributed test layout structure, and the test depth and the cross distributed test layout structure, and perform iterative tests on the target test chip according to the first coverage set and the second coverage set.

[0084] Furthermore, the test case setting module 11 in the chip test device is further configured to:

[0085] Obtain a type of key requirement indicators in the application requirement information, where the type of key requirement indicators is associated with the reliability of the target test chip, and the type of key requirement indicators includes anti-vibration requirements and electromagnetic compatibility requirements; set a reliability verification link through the anti-vibration requirements and electromagnetic compatibility requirements in the type of key requirement indicators; and seamlessly integrate the reliability verification link into the test operation stage under the constraint of the resource synchronization monitoring mechanism for resource balanced scheduling.

[0086] Furthermore, the test case setting module 11 in the chip test device is further configured to:

[0087] Obtain a second type of key requirement indicators in the application requirement information, where the second type of key requirement indicators is associated with the stability of the target test chip, and the second type of key requirement indicators includes signal reception sensitivity requirements, transmit power requirements, and spectral efficiency requirements; set a stability verification link through the signal reception sensitivity requirements, transmit power requirements, and spectral efficiency requirements in the second type of key requirement indicators; and seamlessly integrate the stability verification link into the test operation stage under the constraint of the resource synchronization monitoring mechanism for resource balanced scheduling.

[0088] Furthermore, the test case setting module 11 in the chip test device is further configured to:

[0089] Based on the reliability verification link and the stability verification link, establish a resource configuration optimization function; denote the total number of the test marking points as K, and the resource configuration optimization function ( ); where is the optimal resource configuration, is the actual resource configuration corresponding to the kth test marking point, is the resource requirement corresponding to the kth test marking point, is the coefficient between the resource configuration and the comprehensive evaluation value, and the comprehensive evaluation value , where is the test result of the ith reliability verification link, is the test result of the jth stability verification link, and are the weights corresponding to the reliability verification link and the stability verification link.

[0090] Further, the parallel test module 12 in the chip testing device is further configured to:

[0091] Evaluate the precision loss based on the test marking points, and set a precision loss threshold; synchronize the test task progress in the parallel test mode; reallocate the parallel test tasks according to the precision loss threshold and the test task progress, and update the parallel distributed test layout structure.

[0092] Further, the simulation test module 16 in the chip testing device is further configured to:

[0093] Obtain the basic power consumption parameters of the target test chip; initialize and configure the test environment based on the basic power consumption parameters to establish an initial test environment, and the initial test environment has an overvoltage protection mechanism and an overcurrent protection mechanism; set the test running stage based on the initial test environment, the test period, the parallel distributed test layout structure, the test depth, and the cross-distributed test layout structure.

[0094] Further, the simulation test module 16 in the chip testing device is further configured to:

[0095] Add a rated calculation efficiency at the test marking points based on the target test chip; use the rated calculation efficiency as a boundary condition to adjust the resource configuration corresponding to the test running stage, and the resource configuration indicators include processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints; introduce a resource synchronization monitoring mechanism according to the resource configuration indicators, and the resource synchronization monitoring mechanism is used to match the resource demand changes corresponding to the test running stage.

[0096] The embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The Figure 1 A chip testing method and specific examples in the first embodiment are equally applicable to the chip testing device in this embodiment. Through the detailed description of a chip testing method above, those skilled in the art can clearly know the chip testing device in this embodiment. Therefore, for the sake of simplicity of the specification, it will not be described in detail here. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0097] Embodiment 3. Based on the inventive concept of a chip testing method in the foregoing Embodiment 1, the present application further provides an electronic device, including: at least one processor; a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the steps of the chip testing method according to any one of the foregoing Embodiment 1.

[0098] Appendix Figure 3 is a schematic structural diagram of an exemplary electronic device of the present application. In Figure 3 , the bus architecture is represented by bus 300. Bus 300 may include any number of interconnected buses and bridges. Bus 300 connects various circuits including one or more processors represented by processor 302 and a memory represented by memory 304 together. Bus 300 may also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and thus will not be further described herein. Bus interface 305 provides an interface between bus 300 and receiver 301 and transmitter 303. Receiver 301 and transmitter 303 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 302 is responsible for managing bus 300 and general processing, while memory 304 may be used to store data used by processor 302 when performing operations.

[0099] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application and its equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A chip testing method, characterized in that, Including: Obtain the application requirement information of the target test chip, and set multiple test cases, where the multiple test cases include multiple test marking points; According to the test marking points, in a parallel test manner, determine the test cycle and the parallel distributed test layout structure; According to the test marking points, in a cross-test manner, determine the test depth and the cross distributed test layout structure; Based on the multiple test cases, through the test cycle and the parallel distributed test layout structure, determine the first coverage set; Based on the multiple test cases, through the test depth and the cross distributed test layout structure, determine the second coverage set; Through the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, and based on the first coverage set and the second coverage set, simulate the test environment and perform iterative testing on the target test chip; Obtain the application requirement information of the target test chip, and set multiple test cases, further including: Obtain a type of key requirement index in the application requirement information, where the type of key requirement index is related to the reliability of the target test chip, and the type of key requirement index includes anti-vibration requirements and electromagnetic compatibility requirements; Set a reliability verification link through the anti-vibration requirements and electromagnetic compatibility requirements in the type of key requirement index; Under the constraint of the resource synchronization monitoring mechanism, seamlessly integrate the reliability verification link into the test operation stage and perform resource balanced scheduling; Obtain a type of key requirement index in the application requirement information, including: Obtain a second type of key requirement index in the application requirement information, where the second type of key requirement index is related to the stability of the target test chip, and the second type of key requirement index includes signal reception sensitivity requirements, transmit power requirements, and spectrum efficiency requirements; Set a stability verification link through the signal reception sensitivity requirements, transmit power requirements, and spectrum efficiency requirements in the second type of key requirement index; Under the constraint of the resource synchronization monitoring mechanism, seamlessly integrate the stability verification link into the test operation stage and perform resource balanced scheduling; Based on the reliability verification link and the stability verification link, establish a resource configuration optimization function; Let the total number of the test marking points be denoted as K, and the resource allocation optimization function (( ); wherein, is the optimal resource allocation, is the actual resource allocation corresponding to the k-th test marker point, is the resource requirement corresponding to the k-th test marker point, is the coefficient between the trade-off of resource allocation and the comprehensive evaluation value, and the comprehensive evaluation value , wherein, is the test result of the i-th reliability verification link, is the test result of the j-th stability verification link, and are the weights corresponding to the reliability verification link and the stability verification link.

2. The chip testing method according to claim 1, wherein Through the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, and based on the first coverage set and the second coverage set, simulate the test environment, including: Obtain the basic power consumption parameters of the target test chip; Based on the basic power consumption parameters, initialize the configuration of the test environment to establish an initialized test environment, and the initialized test environment has an overvoltage protection mechanism and an overcurrent protection mechanism; Based on the initialized test environment, through the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, set the test operation stage.

3. A chip testing method according to claim 2, wherein, Based on the initialized test environment, through the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, set the test operation stage, including: Based on the target test chip, add the rated computing efficiency at the test marking point; Take the rated computing efficiency as a boundary condition and adjust the resource allocation corresponding to the test running stage. The resource allocation metrics include processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints; According to the resource allocation metrics, introduce a resource synchronization monitoring mechanism, which is used to match the resource requirement changes corresponding to the test running stage.

4. A chip testing method according to claim 1, characterized in that, According to the test marking point, determine the test cycle and the parallel distributed test layout structure in a parallel test manner, including: Conduct an accuracy loss assessment based on the test marking point and set an accuracy loss threshold; Under the parallel test mode, synchronize the test task progress; Based on the accuracy loss threshold and the test task progress, reallocate the parallel test tasks and update the parallel distributed test layout structure.

5. A chip testing device, characterized in that, Steps for implementing the chip test method according to any one of claims 1 to 4. The chip test device includes: A test case setting module, which is used to obtain the application requirement information of the target test chip and set multiple test cases. The multiple test cases include multiple test marking points; A parallel test module, which is used to determine the test cycle and the parallel distributed test layout structure in a parallel test manner according to the test marking point; A cross test module, which is used to determine the test depth and the cross distributed test layout structure in a cross test manner according to the test marking point; A first coverage module, which is used to determine a first coverage set based on the multiple test cases through the test cycle and the parallel distributed test layout structure; A second coverage module, which is used to determine a second coverage set based on the multiple test cases through the test depth and the cross distributed test layout structure; A simulation test module, which is used to simulate a test environment based on the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, and iterate the test on the target test chip according to the first coverage set and the second coverage set.

6. An electronic device, including: At least one processor; A memory communicatively connected to the at least one processor; Wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the steps of the chip test method according to any one of claims 1 to 4.

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