A dual power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing and a use method thereof

Abstract

The application discloses a double power supply low-voltage electric appliance test system based on WTD-VMD-ZCD phase selection control closing and a use method thereof. The system comprises a test voltage source loop, a capacitor charging and discharging loop, a test current source loop and a main control module. The WTD algorithm is used to denoise and reconstruct the voltage signal generated by the test voltage source, then the BKA algorithm is used to optimize the parameters of VMD, the voltage signal denoised by WTD is decomposed by VMD, the obtained IMF components are subjected to correlation calculation, the IMF components with higher correlation than the set threshold are selected as the test voltage source signals after denoising, then the ZCD algorithm is used for zero-crossing detection, the logic control of the timing connection of the test voltage source and the test current source is performed through phase selection closing, and the test of the low-voltage electric appliance is realized. The application meets the demand of the low-voltage electric appliance on the test power supply electric parameters and test quality, realizes the accurate control of the test, and has the advantages of low cost, simple system construction and operation.

Description

Technical Field

[0001] This invention belongs to the field of low-voltage electrical appliance testing technology, specifically relating to a dual-power low-voltage electrical appliance testing system based on WTD-VMD-ZCD phase selection control closing and its usage method. Background Technology

[0002] Low-voltage electrical appliances are crucial components widely used in industrial and civil electrical equipment, providing essential protection for electrical control and control, and improving the reliability and safety of electrical equipment. With the rapid development of intelligent electrical appliances, the use of low-voltage electrical appliances is increasing dramatically, necessitating strict guarantees of their safety and reliability. Therefore, low-voltage electrical appliances must pass rigorous testing before use. Short-circuit performance testing is a critical test for verifying the performance of low-voltage electrical appliances, and it mainly includes short-circuit making capacity test, short-circuit breaking capacity test, and short-circuit carrying capacity test.

[0003] For many years, research on low-voltage electrical appliance testing systems has been relatively limited both domestically and internationally, with a focus primarily on high-voltage electrical appliance testing systems. Foreign low-voltage electrical appliance testing equipment has relatively high certification requirements and prices, while domestic testing mainly relies on electrical research institutes and testing organizations. Currently, existing low-voltage test circuits in China primarily use the power grid as the test power source, such as the test circuit described in the invention patent "A Low-Voltage Electrical Appliance Switching Capability Test System Based on Fieldbus Control Technology." Because it requires connection to the high-voltage power grid, setting up this test circuit is relatively complex. To meet the different test current and voltage requirements of various low-voltage electrical appliances, significant voltage reduction and frequent resistance changes by the transformer are necessary, posing a significant challenge to the accuracy of test parameter adjustment. Furthermore, when the test fails to switch on, it can cause a significant impact on the power grid, seriously affecting the safety and power supply quality of the power system. Therefore, the application and use of power grid-based testing has become increasingly restricted, leading to higher testing costs. In addition, the frequent testing of electrical equipment by personnel under high-voltage power grids is highly dangerous. Since various test circuits require consideration of switching on and off at the zero-crossing point of the test signal to prevent sudden current surges from damaging the system, this is also a significant concern. The article "Application Research of Phase Selection and Closing Technology for Switchgear" published in the Hubei Electric Power News analyzed the phase selection and closing technology and its control strategy, but research on phase detection and closing control is still insufficient. To promote the development of the domestic low-voltage electrical appliance industry and the standardization of low-voltage electrical appliance testing, it is necessary to design an intelligent, economical, safe, and widely applicable testing system for various low-voltage electrical appliances. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a dual-power low-voltage electrical appliance testing system based on WTD-VMD-ZCD phase selection control closing. Specifically, this invention relates to a testing system for short-circuit making capacity testing, short-circuit breaking capacity testing, and short-circuit carrying capacity testing of low-voltage electrical switches, automating and intelligentizing the low-voltage electrical appliance testing process, while simultaneously solving the problems of test power supply parameters, test effect standardization, and test costs in existing testing systems.

[0005] To achieve the above objectives, this invention provides a dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase-selective control closing. The system includes a test voltage source circuit, a capacitor charging / discharging circuit, a test current source circuit, and a main control module. The main control module includes a main controller, a power supply module, a switch control module, a data acquisition and processing module, a communication module, and a safety alarm module. The control method for the dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase-selective control closing includes the following steps:

[0006] Step 1: Use the wavelet threshold denoising algorithm (WTD) to denoise and reconstruct the measured test voltage source signal x(t) to obtain the reconstructed test voltage source signal x1(t);

[0007] Step 2: Use the Black-winged Kite Intelligent Optimization Algorithm (BKA) to optimize the parameters of Variational Mode Decomposition (VMD) to obtain the optimal number of modes K and penalty factor α;

[0008] Step 3: Decompose the signal x1(t) using the optimized VMD to obtain K IMF components;

[0009] Step 4: Calculate the correlation between the IMF component and the reconstructed test voltage source signal x1(t), and select the IMF component with a correlation higher than the set threshold as the denoised test voltage source signal x2(t).

[0010] Step 5: Perform zero-crossing detection (ZCD) on the denoised test voltage source signal x2(t), detect the zero-crossing time t, determine the phase of the signal, and calculate the opening and closing time of the switch to realize the logic control of the timing connection of the test voltage source and the test current source.

[0011] Furthermore, the test voltage source circuit is composed of a test voltage source, a voltage source protection resistor R3, a protection switch K2, a voltage sensor VS, and a low-voltage electrical test switch TS connected in sequence; the test voltage source is composed of an electric voltage regulator M, an isolation transformer T2, and a closing switch K1; the voltage sensor VS is an AC voltage sensor used to collect the test voltage source signal.

[0012] Furthermore, the capacitor charging and discharging circuit is composed of an isolation transformer T2, two sets of rectifier diodes D1 and D2, a capacitor bank Cs, a charging and discharging resistor, and a charging and discharging switch; the capacitor bank Cs is composed of capacitors Cs1 and Cs2 connected in series.

[0013] Furthermore, the test current source circuit is composed of an LC oscillation test current source, a current sensor CS, a low-voltage electrical test switch TS, a closing switch K3, and a protection switch K4 connected in sequence; the LC oscillation test current source is composed of a capacitor bank Cs and an inductor Ls connected in sequence; the current sensor CS is a Rogowski coil used to collect the test current signal.

[0014] Furthermore, the switch control module is controlled by a switch control board for capacitor charging and discharging control and test timing logic control.

[0015] Furthermore, the data acquisition and processing module includes a data acquisition section and a data processing section.

[0016] Furthermore, the communication module includes a main controller setting a serial communication mode with the A / D converter through a serial peripheral interface (SPI) to read the result after AD conversion; the communication module also includes RS-485 communication with the host computer via a peripheral interface to complete the interaction function.

[0017] Furthermore, the safety alarm module includes two parts: a preset alarm threshold function and a system emergency stop button function.

[0018] Furthermore, in step 1, the test voltage source signal x(t) is decomposed, denoised, and reconstructed using the coif3 wavelet basis, a 3-level decomposition layer, a fixed threshold (sqtwolog) function, and a soft threshold function.

[0019] Furthermore, in step 2, the BKA algorithm optimizes the parameters of VMD using the minimum envelope entropy as the fitness function.

[0020] Furthermore, in step 3, the optimized VMD decomposes the signal x1(t) into K modal components u. k For each mode, calculate the one-sided spectrum and estimate the center frequency w. k The fundamental frequency band is obtained, and then the variational constrained model is obtained by calculating the square norm of the fundamental frequency band gradient and estimating the bandwidth of each mode. A quadratic penalty factor α and a Lagrange multiplier λ are then introduced, transforming the problem into an unconstrained variational problem, resulting in an augmented Lagrange expression. This expression is then iteratively updated using the alternating direction method of the multiplication operator. k w k , λ, until the relative error e is less than the convergence error ε.

[0021] Furthermore, in step 4, the correlation between the IMF component and the reconstructed test voltage source signal is calculated, and the IMF component with a correlation higher than the set threshold of 0.95 is selected as the denoised test voltage source signal x2(t) using loop statements and conditional statements.

[0022] Furthermore, in step 5, the ZCD algorithm uses the rising zero-crossing detection method to detect the positive and negative signs of the time points before and after the signal x2(t), thereby determining the rising zero-crossing time t, determining the phase of the signal, determining the opening and closing time of the switch by calculation, and switching the closing and opening switches K1 and K3 on and off according to the opening and closing time and the test timing logic, thereby realizing the test of low-voltage electrical appliances.

[0023] This invention also provides a method for using a dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing, comprising the following steps:

[0024] (1) After the test system is powered on, it performs the function initialization steps, including setting the relevant registers, clearing variables and initializing the communication protocol. In addition, it also includes initializing the main control switch device of the test circuit.

[0025] (2) The lower computer of the main controller establishes communication with the upper computer and waits for it to send test parameter commands. After receiving the test parameters, it performs the charging action. The charging status process is fed back to the upper computer in real time until the charging is completed.

[0026] (3) Start the test operation, and automatically save the test data and upload it to the host computer to generate an electronic spreadsheet. After the test is completed, the main controller will perform the capacitor discharge operation and reset the main control switch of the circuit so that the next test can be performed.

[0027] Compared with the prior art, the present invention has the following technical advantages:

[0028] (1) Based on the test of low-voltage electrical appliances, the present invention designs a dual-power test circuit that is different from the previous single-power test circuit. This test circuit more accurately simulates the voltage and current state of low-voltage electrical appliances under actual conditions.

[0029] (2) The present invention consists of an electric voltage regulator and an isolation transformer as the test voltage source and an LC oscillation circuit as the test current source. Its test circuit is simple to construct and has a low cost.

[0030] (3) The present invention adopts the method of transformer transformation and charging the capacitor stack Cs with alternating voltage positive and negative half waves respectively, which improves the charging efficiency and solves the requirement of test current for low voltage electrical appliance tests. At the same time, the test current source has a capacitor discharge switch, which can release the remaining electrical energy of the capacitor after the test, thereby ensuring the safety of the operator.

[0031] (4) The present invention adopts a dual denoising method of wavelet threshold denoising and variational mode decomposition, which effectively filters out the noise in the test voltage source signal. Then, the modal components are selected by correlation calculation to obtain the denoised test voltage source signal. This method does not change the phase of the processed signal and is very suitable for the denoising of single-frequency sinusoidal test voltage source signal. Then, the opening and closing time of the switch is determined by zero-crossing detection to achieve precise control of dual power supply for low-voltage electrical appliance testing.

[0032] (5) The safety alarm module of the test system of the present invention monitors the test process, ensuring that the test is carried out automatically and safely and can be stopped in an emergency.

[0033] (6) This invention meets the requirements of low-voltage electrical appliances in terms of test power parameters and test quality, realizes precise control of the test, and is low in cost, simple and easy to build and operate. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing, according to the present invention.

[0035] Figure 2 This is a flowchart of the WTD-VMD-ZCD phase selection and closing control of a dual-power low-voltage electrical test system based on WTD-VMD-ZCD phase selection control closing according to the present invention.

[0036] Figure 3 This is a schematic diagram of the main control module of a dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing according to the present invention. Detailed Implementation

[0037] like Figures 1 to 3 As shown, this invention provides a dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing. The system includes a test voltage source circuit, a capacitor charging and discharging circuit, a test current source circuit, and a main control module. The main control module includes a main controller, a power supply module, a switch control module, a data acquisition and processing module, a communication module, and a safety alarm module.

[0038] The test voltage source circuit is composed of a test voltage source, a voltage source protection resistor R3, a protection switch K2, a voltage sensor VS, and a low-voltage electrical test switch TS connected in sequence; the test voltage source is composed of an electric voltage regulator M, an isolation transformer T2, and a closing switch K1; the voltage sensor VS is an AC voltage sensor used to collect the test voltage source signal.

[0039] Specifically, the test voltage source obtains the required test voltage value through the joint voltage regulation of the electric voltage regulator M and the isolation transformer T2, generating a sinusoidal test voltage source signal with a power frequency of 50Hz. This signal is controlled by the closing switch K1. The test voltage source signal is fed into the low-voltage electrical test switch TS through the voltage source protection resistor R3 and the protection switch K2, and then the test voltage source signal is collected by the AC voltage sensor VS.

[0040] The capacitor charging and discharging circuit is composed of an isolation transformer T2, two sets of rectifier diodes D1 and D2, a capacitor bank Cs, a charging and discharging resistor, and a charging and discharging switch; the capacitor bank Cs is composed of capacitors Cs1 and Cs2 connected in series.

[0041] Specifically, the capacitor charging and discharging circuit includes a capacitor charging process and a capacitor charging and discharging process. During the capacitor charging process, an alternating voltage is used to charge the capacitor stack Cs in positive and negative half-waves respectively. The discharge switch S3 is in the open state. The charging switches S1 and S2 are closed in sequence. The positive half-wave current of the charging voltage passes through D1, S2, Cs1, and R1 to charge capacitor Cs1, while the negative half-wave current passes through R1, Cs2, S2, and D2 to charge capacitor Cs2. After charging to the required voltage value, switches S1 and S2 are immediately opened, so that capacitors Cs1 and Cs2 are charged, completing the capacitor charging process. During the capacitor discharging process, the capacitor stack Cs is discharged through R2 and S3 by closing the discharge switch S3.

[0042] The test current source circuit consists of an LC oscillation test current source, a current sensor CS, a low-voltage electrical test switch TS, a closing switch K3, and a protection switch K4 connected in sequence; the LC oscillation test current source consists of a capacitor bank Cs and an inductor Ls connected in sequence; the current sensor CS is a Rogowski coil used to collect the test current signal.

[0043] Specifically, the LC oscillation test current source uses an LC oscillation circuit capable of storing the energy generated during circuit resonance. The LC oscillation circuit is equivalent to a capacitor discharging through an inductor and the resistance present in the closed loop. Since the resistance in the oscillation circuit is relatively small, mainly consisting of the resistance of the conductor and contact loss resistance, the relationship between the discharge current I and the charging voltage U of the test current source is as follows, ignoring this loss:

[0044]

[0045] In the formula, B is the attenuation ratio, which is set to 1.2 here, L is the inductance value, C is the capacitance value, and I is the effective value of the test current;

[0046] The frequency relationship of the test current source is as follows:

[0047]

[0048] By properly configuring the parameters of the capacitor stack Cs and the inductor Ls, a sinusoidal power frequency test current signal with an initial phase of zero required for the test can be generated through oscillation. The test current signal is then collected by the current sensor CS.

[0049] The switch control module is controlled by a switch control board for capacitor charging and discharging control and test timing logic control.

[0050] Specifically, the switch control module uses a switch control board to control capacitor charging and discharging and test timing logic. The capacitor charging and discharging control realizes the charging and discharging process of the capacitor stack Cs by controlling the charging and discharging switches S1, S2 and S3. The test timing logic control provides test voltage and test current from dual power supplies according to the opening and closing time and the test timing logic control.

[0051] The data acquisition and processing module includes a data acquisition section and a data processing section.

[0052] Specifically, the acquisition section acquires the test voltage source signal and test current signal based on high-precision voltage and current sensors. After signal conditioning circuit processing, the signal is output to the main controller after A / D conversion. The data processing section includes signal denoising and zero-crossing detection steps to determine the opening and closing time of the circuit breaker. At the same time, the test signal is recorded and saved to verify the effectiveness and reliability of the test voltage and test current.

[0053] The communication module includes a main controller that sets a serial communication mode with the A / D converter through the serial peripheral interface SPI to read the result after AD conversion; the communication module also includes RS-485 communication with the host computer through the peripheral interface to complete the interaction function.

[0054] Specifically, the communication module uses a wired connection to achieve interconnection and communication with the test system, and uses a host computer to monitor and control the charging and discharging process of the capacitor and the test process of the low-voltage electrical appliances.

[0055] The safety alarm module includes two parts: a preset alarm threshold function and a system emergency stop button function.

[0056] Specifically, the test process is monitored by the control module. If the test data exceeds the preset alarm threshold, the preset alarm threshold function is triggered, all switches are immediately cut off and an alarm is issued. The system emergency stop button function is used to manually stop the test system in an emergency. Its priority is set to the highest priority. When the signal of pressing the emergency stop button is received, the protection switch in the test circuit is immediately opened to ensure the safety of the operator and the test system.

[0057] The control method of the dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing includes the following steps:

[0058] Step 1: Use the wavelet threshold denoising algorithm (WTD) to denoise and reconstruct the measured test voltage source signal x(t) to obtain the reconstructed test voltage source signal x1(t);

[0059] Step 2: Use the Black-winged Kite Intelligent Optimization Algorithm (BKA) to optimize the parameters of Variational Mode Decomposition (VMD) to obtain the optimal number of modes K and penalty factor α;

[0060] Step 3: Decompose the signal x1(t) using the optimized VMD to obtain K IMF components;

[0061] Step 4: Calculate the correlation between the IMF component and the reconstructed test voltage source signal x1(t), and select the IMF component with a correlation higher than the set threshold as the denoised test voltage source signal x2(t).

[0062] Step 5: Perform zero-crossing detection (ZCD) on the denoised test voltage source signal x2(t), detect the zero-crossing time t, determine the phase of the signal, and calculate the opening and closing time of the switch to realize the logic control of the timing connection of the test voltage source and the test current source.

[0063] Step 1 uses the coif3 wavelet basis, 3-level decomposition, fixed threshold (sqtwolog) function, and soft threshold function to decompose, denoise, and reconstruct the test voltage source signal x(t).

[0064] Specifically, step 1 is as follows:

[0065] Step 1-1: Determine the wavelet basis function coif3 and the number of decomposition layers (3). Perform wavelet decomposition on x(t) under the test voltage source signal to obtain the wavelet coefficients.

[0066]

[0067] In the formula, a β+1 (n) are low-frequency approximation coefficients, b β+1 (n) represents the high-frequency detail coefficients, h represents the low-pass filter coefficients, g represents the high-pass filter coefficients, β represents the number of decomposition layers, n represents the number of sampling points, and c = 1, 2, ..., n-1;

[0068] Step 1-2: Select the fixed threshold (sqtwolog) function and the soft threshold function to perform thresholding on the wavelet coefficients;

[0069] Specifically, the fixed threshold (sqtwolog) function is as follows:

[0070]

[0071] In the formula, σ is the standard deviation of the wavelet coefficients of each layer, and N is the length of the wavelet detail coefficients at each level;

[0072] Specifically, the soft threshold function is as follows:

[0073]

[0074] In the formula, ω and ω λ , respectively, are the wavelet coefficients before and after denoising, λ is the threshold, and sgn(*) is the sign function;

[0075] Steps 1-3: Reconstruct the signal using the denoised wavelet coefficients, and obtain the reconstructed experimental voltage source signal x1(t) through inverse wavelet transform.

[0076] In step 2, the BKA algorithm optimizes the parameters of VMD using the minimum envelope entropy as the fitness function.

[0077] Specifically, the BKA algorithm first initializes the population size, maximum number of iterations, variable dimensions, and the location of the black-winged kite along with its upper and lower bounds. This location serves as the initial value for the VMD parameters to be optimized. Then, it performs an initial VMD decomposition on the signal, selecting the minimum envelope entropy as the fitness function. By exploring the black-winged kite's attack and migration behaviors, it delves into the fitness value of the kite at each location, thereby determining the optimal VMD parameters based on the minimum fitness value. The fitness function is as follows:

[0078]

[0079] In the formula, a(i) is the envelope signal of the modal components after Hilbert demodulation of the initial VMD decomposition, and p i It is the normalized form of a(i), where N is the signal length and E is the signal value. p It is the envelope entropy.

[0080] In step 3, the optimized VMD decomposes the signal x1(t) into K modal components u. k For each mode, calculate the one-sided spectrum and estimate the center frequency w. k The fundamental frequency band is obtained, and then the variational constrained model is obtained by calculating the square norm of the fundamental frequency band gradient and estimating the bandwidth of each mode. A quadratic penalty factor α and a Lagrange multiplier λ are then introduced, transforming the problem into an unconstrained variational problem, resulting in an augmented Lagrange expression. This expression is then iteratively updated using the alternating direction method of the multiplication operator. k w k , λ, until the relative error e is less than the convergence error ε.

[0081] Specifically, step 3 is as follows:

[0082] Step 3-1: Decompose the signal into K modal components, and calculate u for each modal component using the Hilbert transform. k For each modal component, estimate a center frequency w from the one-sided spectrum of (t). k Multiply the unilateral spectrum by Converted to baseband:

[0083]

[0084] In the formula, δ(t) is the unit impulse function, and * represents convolution;

[0085] Step 3-2: Calculate the square norm of the fundamental frequency band gradient and estimate the bandwidth corresponding to each modal component, resulting in the following variational constraint problem model:

[0086]

[0087] In the formula, st represents the constraint condition, and f(t) represents the noisy signal to be decomposed;

[0088] Step 3-3: Introducing the quadratic penalty factor α and the Lagrange multiplication operator λ(t), the problem becomes an unconstrained variational problem. The augmented Lagrange expression is as follows:

[0089]

[0090] In the formula, k is the number of iterations, and <*> represents the inner product operation;

[0091] Steps 3-4: Iterate the augmented Lagrange expression using the alternating direction method of multiplication operators, updating u. k w k , until the relative error e is less than the convergence error ε, u k w k The formulas for λ and the first convergence condition are as follows:

[0092]

[0093]

[0094]

[0095]

[0096] In the formula, f(ω) is the Fourier transform of f(t), and u i (ω) is u i The Fourier transform of λ(t), where λ(ω) is the Fourier transform of λ(t), τ is the noise tolerance parameter, and ε is the convergence tolerance.

[0097] In step 4, the correlation between the IMF component and the reconstructed test voltage source signal is calculated. The IMF component with a correlation higher than the set threshold of 0.95 is selected as the denoised test voltage source signal x2(t) using loop statements and conditional statements.

[0098] Specifically, the correlation calculation formula is as follows:

[0099]

[0100] In the formula, x1(t) is the reconstructed test voltage source signal, u k (t) represents the k-th IMF component, and N is the signal length.

[0101] In step 5, the ZCD algorithm uses the rising zero-crossing detection method to detect the positive and negative signs of the signal x2(t) before and after the time point, thereby determining the rising zero-crossing time t, determining the phase of the signal, determining the opening and closing time of the switch by calculation, and switching the closing and opening switches K1 and K3 on and off according to the opening and closing time and the test timing logic, thereby realizing the test of low-voltage electrical appliances.

[0102] Specifically, the formula for calculating the opening and closing time t′ is as follows:

[0103] t' = t + nT;

[0104] In the formula, t is the zero-crossing time of the detection, and the period T = 1 / f u f u The test voltage is the power frequency, and n is a positive integer.

[0105] The specific experimental operation process of the experimental system of this invention is as follows: First, after the experimental system is powered on, it needs to perform a function initialization step, mainly including setting relevant registers, clearing variables, and initializing the communication protocol. In addition, it also includes initializing the main control switch device of the test circuit. Second, the lower-level controller establishes communication with the upper-level controller and waits for the upper-level controller to send test parameter commands. After receiving the test parameters, it performs a charging action, and the charging status is fed back to the upper-level controller in real time until charging is complete. Then, the test operation begins, and the test data is automatically saved and uploaded to the upper-level controller, generating an electronic spreadsheet. After the test is completed, the main controller will perform a capacitor discharge operation and reset the main control switch of the circuit for the next test.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing, characterized in that, It includes a test voltage source circuit, a capacitor charging and discharging circuit, a test current source circuit, and a main control module; The test voltage source circuit is composed of a test voltage source, a voltage source protection resistor R3, a protection switch K2, a voltage sensor VS, and a low-voltage electrical test switch TS connected in sequence. The capacitor charging and discharging circuit is composed of an isolation transformer T2, two sets of rectifier diodes D1 and D2, a capacitor bank Cs, a charging and discharging resistor, and a charging and discharging switch. The test current source circuit is composed of an LC oscillation test current source, a current sensor CS, a low-voltage electrical test switch TS, a closing switch K3, and a protection switch K4 connected in sequence. The main control module includes a main controller, a power supply module, a switch control module, a data acquisition and processing module, a communication module, and a safety alarm module; The control method of the dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing includes the following steps: Step 1: Use the wavelet threshold denoising algorithm (WTD) to denoise and reconstruct the measured test voltage source signal x(t) to obtain the reconstructed test voltage source signal x1(t); Step 2: Use the Black-winged Kite Intelligent Optimization Algorithm (BKA) to optimize the parameters of Variational Mode Decomposition (VMD) to obtain the optimal number of modes K and penalty factor α; Step 3: Decompose the signal x1(t) using the optimized VMD to obtain K IMF components; Step 4: Calculate the correlation between the IMF component and the reconstructed test voltage source signal x1(t), and select the IMF component with a correlation higher than the set threshold as the denoised test voltage source signal x2(t). Step 5: Perform zero-crossing detection (ZCD) on the denoised test voltage source signal x2(t), detect the zero-crossing time t, determine the phase of the signal, and calculate the opening and closing time of the switch to realize the logic control of the timing connection of the test voltage source and the test current source.

2. The dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing as described in claim 1, characterized in that, Step 1 uses the coif3 wavelet basis, 3-level decomposition, fixed threshold function, and soft threshold function to decompose, denoise, and reconstruct the test voltage source signal x(t).

3. The dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing as described in claim 1, characterized in that, In step 2, the BKA algorithm optimizes the parameters of VMD using the minimum envelope entropy as the fitness function.

4. The dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing as described in claim 1, characterized in that, In step 3, the optimized VMD decomposes the signal x1(t) into K modal components u. k For each mode, calculate the one-sided spectrum and estimate the center frequency w. k The fundamental frequency band is obtained, and then the variational constrained model is obtained by calculating the square norm of the fundamental frequency band gradient and estimating the bandwidth of each mode. A quadratic penalty factor α and a Lagrange multiplier λ are then introduced, transforming the problem into an unconstrained variational problem, resulting in an augmented Lagrange expression. This expression is then iteratively updated using the alternating direction method of the multiplication operator. k w k , λ, until the relative error e is less than the convergence error ε.

5. The dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing as described in claim 1, characterized in that, In step 4, the correlation between the IMF component and the reconstructed test voltage source signal is calculated. The IMF component with a correlation higher than the set threshold of 0.95 is selected as the denoised test voltage source signal x2(t) using loop statements and conditional statements.

6. The dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing as described in claim 1, characterized in that, In step 5, the ZCD algorithm uses the rising zero-crossing detection method to detect the positive and negative signs of the signal x2(t) before and after the time point, thereby determining the rising zero-crossing time t, determining the phase of the signal, determining the opening and closing time of the switch by calculation, and switching the closing and opening switches K1 and K3 on and off according to the opening and closing time and the test timing logic, thereby realizing the test of low-voltage electrical appliances.

7. A method of using a dual-power low-voltage electrical appliance test system based on WTD-VMD-ZCD phase selection control closing according to any one of claims 1-6, characterized in that, Includes the following steps: (1) After the test system is powered on, it performs the function initialization steps, including setting the relevant registers, clearing variables and initializing the communication protocol. In addition, it also includes initializing the main control switch device of the test circuit. (2) The lower computer of the main controller establishes communication with the upper computer and waits for it to send test parameter commands. After receiving the test parameters, it performs the charging action. The charging status process is fed back to the upper computer in real time until the charging is completed. (3) Start the test operation, and automatically save the test data and upload it to the host computer to generate an electronic spreadsheet. After the test is completed, the main controller will perform the capacitor discharge operation and reset the main control switch of the circuit so that the next test can be performed.

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