Solid-state storage device control method and device and storage medium

Abstract

The invention relates to the technical field of computers, in particular to a solid-state storage device control method and device and a storage medium. The method comprises the following steps: determining a current interface rate and a highest initial interface rate corresponding to a target storage chip; reading an interface rate table corresponding to a storage unit where the target storage chip is located; the interface rate table comprises a corresponding relation between the storage chip and the interface rate gear, and one storage chip corresponds to a plurality of interface rate gears; and determining a target reading rate according to the current interface rate, the interface rate table and the highest initial interface rate, and reading data in the target storage chip by using the target reading rate. The embodiment of the invention is used for solving the problem that the storage chip and the interface rate in the solid-state storage device cannot be considered at the same time.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a control method, device and storage medium of a solid-state storage device. Background Art

[0002] With the exponential growth of data volume, solid-state drives (SSDs) with higher performance than traditional hard drives have become mainstream data storage devices. Adding NAND flash memory chips to SSDs can increase the capacity specifications of SSDs, but too many NAND flash memory chips will affect the interface rate of SSDs, resulting in reduced data reading performance of SSDs.

[0003] At present, the way to improve the data reading performance of solid-state drives is usually to use the controller of the solid-state storage device to filter out some NAND flash memory chips for data transmission to reduce the input and output bus load of the solid-state drive. However, this data transmission method will still limit the data reading performance of the solid-state drive in the scenario of large data reading, and the problem has not been fundamentally solved. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a control method, device and storage medium of a solid-state storage device.

[0005] In a first aspect, the present application provides a control method for a solid-state storage device, the solid-state storage device comprising at least one storage unit, one storage unit comprising at least one storage chip, the control method comprising: determining a current interface rate and a maximum initial interface rate corresponding to a target storage chip; reading an interface rate table corresponding to the storage unit where the target storage chip is located; the interface rate table comprising a correspondence between storage chips and interface rate gears, one storage chip corresponding to multiple interface rate gears; determining a target read rate based on the current interface rate, the interface rate table, and the maximum initial interface rate, and using the target read rate to read data in the target storage chip.

[0006] It can be seen from the above scheme that, by using the current interface rate, the interface rate table and the highest initial interface rate, a suitable target read rate can be determined for the target storage chip to read the data in the target storage chip. In this way, the problem of limited read performance in the big data read scenario caused by screening some storage chips for data transmission is avoided, so that the data read performance of the solid-state drive can be guaranteed as much as possible in the dimension of controlling the interface rate.

[0007] In some embodiments, data in a target memory chip is read using a target read rate, including: reading a unit of data in the target memory chip using the target read rate, and when a unit of data is read successfully, obtaining the number of bits of error data in the unit of data; determining a secondary read rate for the next unit of data based on the number of bits; reading the next unit of data using the secondary read rate, and when the next unit of data is read successfully, returning to the step of obtaining the number of bits of error data until the data in the target memory chip is read.

[0008] It can be seen from the above scheme that when a unit of data is read successfully, the secondary read rate for reading the next unit of data is adjusted in time according to the number of error bits in the successfully read unit of data. That is to say, the read rate can be adjusted once each time a unit of data is read, which greatly improves the flexibility of adjusting the read rate.

[0009] In some embodiments, the secondary read rate of the next unit data is determined based on the number of bits, including: when the number of bits is less than or equal to the error threshold, determining the target read rate as the secondary read rate; when the number of bits is greater than the error threshold, reducing the target read rate by one level to obtain the secondary read rate.

[0010] It can be seen from the above scheme that when the number of error bits in a unit of data being read is relatively small, the reading rate is not changed; when the number of error bits in a unit of data being read is relatively large, the reading rate is reduced in time, so that data can be read at the fastest reading rate while ensuring the accuracy of data reading, thereby maximally ensuring the data reading performance of the solid-state drive.

[0011] In some embodiments, the control method also includes: obtaining the minimum interface rate corresponding to the target storage chip; when a unit of data fails to be read and the target read rate is greater than the minimum interface rate, reducing the target read rate by one level to obtain a new target read rate; using the new target read rate to return to execute the reading of a unit of data until a unit of data is successfully read, returning to the step of obtaining the number of error data bits until the data in the target storage chip is read; when a unit of data fails to be read and the target read rate is equal to the minimum interface rate, recovering a unit of data by adjusting the read reference voltage, and using the minimum interface rate to read the data in the target storage chip.

[0012] It can be seen from the above scheme that when a unit of data fails to be read, the target read rate is automatically reduced by one level and read again until the reading is successful; or, until the target read rate drops to the minimum interface rate, the data is recovered by adjusting the read reference voltage, and the data in the target storage chip is read using the minimum interface rate; that is, even if the data reading fails, the data can be tried again by reducing the read rate or automatically recovering, thereby improving the success rate of data reading.

[0013] In some embodiments, the target read rate is reduced by one gear, including: when the target interface rate gear is included in the interface rate table, the target read rate is reduced by one gear according to the interface rate table; the target interface rate gear is the interface rate gear corresponding to the target storage chip; when the target interface rate gear is not included in the interface rate table, the target read rate is reduced by one gear according to a preset gradient.

[0014] It can be seen from the above scheme that since the target reading rate can be downshifted according to the interface rate table or the preset gradient, the rationality of the downshifting of the target reading rate is guaranteed.

[0015] In some embodiments, the control method also includes: obtaining the lowest interface rate gear corresponding to the target storage chip; each time the target read rate is reduced by one gear according to a preset gradient and a unit of data is read successfully, recording the intermediate interface rate gear after the reduction by one gear; taking the highest initial interface rate as the highest initial interface rate gear; generating the corresponding relationship between the target storage chip and the target interface rate gear in the interface rate table according to the highest initial interface rate gear, the intermediate interface rate gear, and the lowest interface rate gear.

[0016] It can be seen from the above scheme that the interface rate gear of the storage chip in the interface rate table can be automatically improved according to the minimum interface rate of the target storage chip, the downshifted intermediate interface rate, and the maximum initial interface rate, thereby improving the convenience of configuring the interface rate table.

[0017] In some embodiments, a target read rate is determined based on a current interface rate, an interface rate table, and a maximum initial interface rate, including: when a target interface rate gear is included in the interface rate table, and the current interface rate is included in the target interface rate gear, the current interface rate is determined as the target read rate; the target interface rate gear is an interface rate gear corresponding to a target storage chip; when the target interface rate gear is not included in the interface rate table, or the current interface rate is not included in the target interface rate gear, the maximum initial interface rate of the target storage chip is determined as the target read rate.

[0018] It can be seen from the above scheme that when the current interface rate is included in the target interface rate gear of the interface rate table, the current interface rate is determined as the target read rate; when the current interface rate is not included in the target interface rate gear of the interface rate table, the highest initial interface rate of the target storage chip is determined as the target read rate. In this way, when the current interface rate is not included in the target interface rate gear of the interface rate table, using the highest initial interface rate can ensure that when the target read rate is subsequently adjusted, it can be adjusted from the maximum read rate, thereby ensuring the rationality of the determined target read rate.

[0019] In a second aspect, the present application provides a control device for a solid-state storage device, the solid-state storage device includes at least one storage unit, and a storage unit includes at least one storage chip. The control device includes: a determination module, used to determine the current interface rate and the maximum initial interface rate corresponding to the target storage chip; an acquisition module, used to read the interface rate table corresponding to the storage unit where the target storage chip is located; the interface rate table includes the correspondence between the storage chip and the interface rate gear, and one storage chip corresponds to multiple interface rate gears; a processing module, used to determine the target read rate according to the current interface rate, the interface rate table, and the maximum initial interface rate, and use the target read rate to read the data in the target storage chip.

[0020] In some embodiments, the processing module includes an acquisition submodule, a determination submodule, and a reading submodule; the acquisition submodule is used to read a unit of data in a target storage chip using a target read rate, and when a unit of data is read successfully, obtain the number of bits of error data in the unit of data; the determination submodule is used to determine the secondary read rate of the next unit of data according to the number of bits; the reading submodule is used to read the next unit of data using the secondary read rate, and when the next unit of data is read successfully, return to execute the step of obtaining the number of error data bits until the data reading in the target storage chip is completed.

[0021] In some embodiments, the determination submodule is specifically used to: when the number of bits is less than or equal to the error threshold, determine the target read rate as the secondary read rate; when the number of bits is greater than the error threshold, reduce the target read rate by one level to obtain the secondary read rate.

[0022] In some embodiments, the processing module also includes a decreasing submodule; the obtaining submodule is also used to obtain the minimum interface rate corresponding to the target storage chip; the determining submodule is also used to reduce the target read rate by one gear to obtain a new target read rate when a unit of data fails to be read and the target read rate is greater than the minimum interface rate; the reading submodule is also used to return to execute the reading of a unit of data using the new target read rate until a unit of data is successfully read, and return to execute the step of obtaining the number of error data bits until the data in the target storage chip is read; the reading submodule is also used to recover a unit of data by adjusting the read reference voltage when a unit of data fails to be read and the target read rate is equal to the minimum interface rate, and use the minimum interface rate to read the data in the target storage chip.

[0023] In some embodiments, a determination submodule is specifically used to: when the target interface rate gear is included in the interface rate table, the target read rate is reduced by one gear according to the interface rate table; the target interface rate gear is the interface rate gear corresponding to the target storage chip; when the target interface rate gear is not included in the interface rate table, the target read rate is reduced by one gear according to a preset gradient.

[0024] In some embodiments, the control device also includes a recording module and a generating module; the acquiring module is further used to acquire the minimum interface rate gear corresponding to the target storage chip; the recording module is used to reduce the target read rate by one gear according to a preset gradient, and when a unit of data is read successfully, record the intermediate interface rate gear after reducing the gear by one gear; the determining module is further used to use the highest initial interface rate as the highest initial interface rate gear; the generating module is used to generate the correspondence between the target storage chip and the target interface rate gear in the interface rate table according to the highest initial interface rate gear, the intermediate interface rate gear, and the lowest interface rate gear.

[0025] In some embodiments, the processing module is specifically used to: when the interface rate table includes a target interface rate gear and the target interface rate gear includes the current interface rate, determine the current interface rate as the target read rate; the target interface rate gear is the interface rate gear corresponding to the target storage chip; when the interface rate table does not include the target interface rate gear, or the target interface rate gear does not include the current interface rate, determine the highest initial interface rate of the target storage chip as the target read rate.

[0026] In a third aspect, the present application provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, a control method for a solid-state storage device as in any embodiment of the first aspect is implemented.

[0027] In a fourth aspect, the present application provides a computer-readable storage medium, comprising: a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, a control method for a solid-state storage device as in any embodiment of the first aspect is implemented.

[0028] In a fifth aspect, the present application provides a computer program product, comprising: when the computer program product runs on a computer, the computer implements a control method for a solid-state storage device as in any embodiment of the first aspect.

[0029] In this application, the names of the above devices do not limit the devices or functional modules themselves. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of this application, they are within the scope of protection of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0032] Figure 1 A schematic diagram of the structure of a solid-state storage device provided in an embodiment of the present application;

[0033] Figure 2 One of the flow charts of the control method of the solid-state storage device provided in the embodiment of the present application;

[0034] Figure 3 A second flowchart of a method for controlling a solid-state storage device provided in an embodiment of the present application;

[0035] Figure 4 Flow chart 3 of the control method of the solid-state storage device provided in the embodiment of the present application;

[0036] Figure 5 Flow chart 4 of the control method of the solid-state storage device provided in an embodiment of the present application;

[0037] Figure 6 Flow chart 5 of the control method of the solid-state storage device provided in the embodiment of the present application;

[0038] Figure 7 Flow chart six of the control method of the solid-state storage device provided in the embodiment of the present application;

[0039] Figure 8 A schematic diagram of the structure of a control device for a solid-state storage device provided in an embodiment of the present application;

[0040] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. The following specific implementation is provided to help readers obtain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be clear. For example, the order of operations described herein is only an example and is not limited to those orders set forth herein, but can be changed as it will be clear after understanding the disclosure of the present application, except for operations that must occur in a specific order. In addition, for increased clarity and conciseness, the description of features known after understanding the disclosure of the present application can be omitted.

[0042] The features described herein can be implemented in different forms and should not be interpreted as being limited to the examples described herein. On the contrary, the examples described herein are provided to illustrate only some of the many possible ways of implementing the methods, devices and / or systems described herein that will be clear after understanding the disclosure of the present application. The terms used herein are only used to describe various examples and will not be used to limit disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" illustrate the existence of stated features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the existence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0043] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a sequence different from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third" and the like adopted in the present application do not limit the data and the execution order, but only distinguish the same items or similar items with basically the same functions and effects. Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the understanding based on the disclosure of the present application and the meaning generally understood by ordinary technicians in the field to which the present disclosure belongs. Unless explicitly defined as such herein, terms (such as terms defined in a general dictionary) should be interpreted as having the same meaning as their context in the relevant field and the meaning in the disclosure of the present application, and should not be idealized or overly formally interpreted. The use of the term "may" in relation to an example or embodiment here (for example, what an example or embodiment may include or implement) indicates that there is at least one example or embodiment including or implementing such a feature, and all examples are not limited thereto.

[0044] Solid-state drives, also known as solid-state storage devices, Figure 1 A schematic diagram of a solid-state storage device provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, a solid-state storage device generally includes a controller and a plurality of storage chips (i.e., NAND flash memory chips). The plurality of storage chips are generally divided into a plurality of channel groups, each channel group corresponding to a plurality of storage chips, such as Figure 1 In the example, channel group 1 includes memory chip 1 and memory chip 2; channel group 2 includes memory chip 3 and memory chip 4. Multiple memory chips are connected to the controller through the input and output bus according to the channel grouping, and are thus controlled by the controller.

[0045] Adding storage chips to a solid-state drive can increase the capacity specifications of the solid-state drive. However, too many storage chips will affect the interface rate of the solid-state drive, resulting in reduced data reading performance of the solid-state drive.

[0046] In response to the above problems, the present application provides a control method for a solid-state storage device, which can determine the current interface rate and the highest initial interface rate corresponding to the target storage chip, and read the interface rate table corresponding to the storage unit where the target storage chip is located. Among them, the interface rate table includes the correspondence between the storage chip and the interface rate gear, and one storage chip corresponds to multiple interface rate gears. Then, the target read rate is determined according to the current interface rate, the interface rate table, and the highest initial interface rate, and the target read rate is used to read the data in the target storage chip. It is possible to ensure the data reading performance of the solid-state hard disk as much as possible in the dimension of controlling the interface rate.

[0047] The control method of the solid-state storage device provided in the embodiment of the present application can be executed by the control device of the solid-state storage device, and the control device of the solid-state storage device can be hardware or software. When the control device of the solid-state storage device is hardware, it can be various electronic devices with the control function of running the solid-state storage device, including but not limited to mobile phones, computers, computers, tablet computers, televisions, smart TVs, vehicle-mounted equipment, smart vehicles, laser projection equipment, displays (monitors), electronic whiteboards (electronic bulletin boards), electronic desktops (electronic tables), etc. When the control device of the solid-state storage device is software, it can be installed in the electronic devices listed above. It can be implemented as multiple software or software modules, or it can be implemented as a single software or software module. It is not specifically limited here.

[0048] Figure 2 A flow chart of a control method for a solid-state storage device provided in an embodiment of the present application, such as Figure 2 As shown, the control method of the solid-state storage device may include the following steps.

[0049] S11. Determine the current interface rate and the highest initial interface rate corresponding to the target storage chip.

[0050] The solid-state storage device of the present application includes at least one storage unit, that is, Figure 1 The channel grouping in the solid-state storage device is a channel grouping, where a channel grouping is a storage unit; a storage unit includes at least one storage chip; and the target storage chip is any storage chip in any storage unit in the solid-state storage device.

[0051] Specifically, the method for determining the maximum initial interface rate corresponding to the target memory chip may be to perform an interface rate test on the target memory chip through relevant simulation software to obtain the maximum initial interface rate corresponding to the target memory chip.

[0052] For example, a topology structure identical to that of a solid-state storage device (such as including at least one storage unit, at least one storage chip, and a controller) can be constructed in the simulation software, and data can be written to or read from the storage chip of the solid-state storage device. The data reading and writing capabilities of each storage chip can then be evaluated to obtain the maximum initial interface rate and minimum interface rate of each storage chip.

[0053] Taking the high-speed serial interface of a common solid-state storage device as an example, the lowest interface rate that the current solid-state storage device can support can be determined based on indicators such as the degree of opening of the eye diagram, eye height, and eye width, combined with the calculation formula for the data transmission rate. At the same time, a bit error rate threshold for an error bit and a data volume threshold that reaches the bit error rate threshold during the data reading and writing process can be set; then, during the data reading and writing process, the highest initial interface rate is determined among the interface rates corresponding to different data volumes according to the data volume threshold in an increasing manner.

[0054] In addition, in the topology where each storage unit is connected to multiple storage chips, different printed circuit board (PCB) wiring branch lengths have different effects on signal integrity, and different storage chips have different PCB wiring branch lengths. Therefore, when performing software simulation, the PCB wiring branch length in the storage chip should also be considered. Generally, the shorter the PCB wiring branch length, the higher the maximum initial interface rate corresponding to the storage chip.

[0055] S12, reading the interface rate table corresponding to the storage unit where the target storage chip is located.

[0056] The interface rate table may be pre-configured or automatically generated according to the historical interface rate corresponding to the target memory chip. The interface rate table includes the correspondence between the memory chips in the memory unit and the interface rate gears, and one memory chip corresponds to multiple interface rate gears.

[0057] Exemplarily, the interface rate table may be in the form of Table 1, including the interface rate gear corresponding to each storage chip of each storage unit. For example, the interface rate gear corresponding to the first storage chip of the first storage unit includes four interface rate gears, namely A1, A2, A3, and A4.

[0058] Table 1

[0059]

[0060] S13, determining a target read rate according to the current interface rate, the interface rate table, and the highest initial interface rate, and using the target read rate to read data in the target storage chip.

[0061] Specifically, the method for determining the target read rate based on the current interface rate, the interface rate table, and the highest initial interface rate can be: when the interface rate gear corresponding to the target storage chip in the interface rate table includes the current interface rate, the current interface rate is determined as the target read rate; when the interface rate gear corresponding to the target storage chip in the interface rate table does not include the current interface rate, the highest initial interface rate is determined as the target read rate.

[0062] In the above scheme, a suitable target read rate can be determined for the target storage chip through the current interface rate, the interface rate table and the highest initial interface rate to read the data in the target storage chip. In this way, the problem of limited read performance in the big data read scenario caused by screening some storage chips for data transmission is avoided, so that the data read performance of the solid-state drive can be guaranteed as much as possible in the dimension of controlling the interface rate.

[0063] In some embodiments, Figure 3 As shown, the method of reading data in the target storage chip using the target read rate may include the following steps:

[0064] S131, read a unit of data in the target memory chip.

[0065] Specifically, when reading data in a storage chip, it is usually read in units of pages, so one unit of data may be one page of data; of course, one unit of data may also be other data measurement methods, which is not limited in this application.

[0066] S132, determine whether a unit of data is read successfully, and execute step S133 if the reading is successful; if the reading fails, execute step S136.

[0067] Specifically, the memory chip will produce a certain amount of loss after a period of reading and writing, and the signal quality may be relatively poor at a high interface rate, so data reading failure may occur. The way to determine whether a unit of data is read successfully can be to determine whether the unit of data is read successfully by the read status corresponding to the unit of data in the status register of the memory chip; or to determine whether the unit of data is read successfully by checking the error correction code (Error Correction Code, ECC) of the read unit of data, and this application does not limit this.

[0068] S133, obtaining the number of bits of erroneous data in a unit of data, and determining the secondary read rate of the next unit of data according to the number of bits.

[0069] First, the number of bits of erroneous data in a unit of data is obtained. Specifically, the number of bits of erroneous data in a unit of data can be obtained by using an error detection and correction algorithm, such as Hamming code detection and correction, BCH code detection and correction, etc.

[0070] Secondly, the secondary read rate of the next unit data is determined according to the number of bits. Specifically, the secondary read rate of the next unit data can be determined according to the number of bits by selecting a smaller interface rate as the secondary read rate when the number of bits is large, and selecting a larger interface rate as the secondary read rate when the number of bits is small.

[0071] S134, determining whether the data in the target storage chip has been read out, and returning to step S131 if it has not been completed; and terminating the reading when the reading is completed.

[0072] Specifically, the method for determining whether the data in the target storage chip has been read is to determine whether the data in the target storage chip has been read when an interrupt signal is received, or when the status register of the storage chip indicates that the read operation is completed, or when the data in the target storage chip has been read, and the present application does not limit this.

[0073] S135. Obtain the minimum interface rate corresponding to the target storage chip.

[0074] Specifically, the method for obtaining the minimum interface rate of the target storage chip is detailed in step S11, which will not be repeated here.

[0075] S136, determining whether the target read rate is greater than the minimum interface rate, and executing step S137 when the target read rate is greater than the minimum interface rate; executing step S138 when the target read rate is equal to the minimum interface rate.

[0076] S137, lowering the target reading rate by one gear to obtain a new target reading rate, and returning to execute step S134.

[0077] Specifically, the target read rate can be reduced by one gear, the target read rate can be reduced by one gear according to the interface rate table, or the target read rate can be reduced by one gear according to the preset gradient to obtain a new target read rate. The preset gradient is pre-set by relevant personnel according to actual conditions. For example, when the unit of the interface rate is million transmissions per second (MT / s), the preset gradient can be 50MT / S, 100MT / S, 133MT / S, 166MT / S, 200MT / S, 266MT / S, 333MT / S, 400MT / S, 533MT / S, 667MT / S, 800MT / S, 1066MT / S, 1200MT / S, 1333MT / S, 1466MT / S, 1600MT / S, 1800MT / S, 2000MT / S, 2200MT / S.

[0078] S138. Recover a unit of data by adjusting the read reference voltage, read the data in the target memory chip using the lowest interface rate, and return to step S134.

[0079] In the above scheme, on the one hand, when a unit of data is read successfully, the secondary read rate of the next unit of data is adjusted in time according to the number of error bits in the successfully read unit of data, that is, the read rate can be adjusted once each time a unit of data is read, which greatly improves the flexibility of adjusting the read rate. On the other hand, when a unit of data fails to be read, the automatic target read rate is reduced by one gear and read again until the reading is successful; or, until the target read rate drops to the minimum interface rate, the data is restored by adjusting the read reference voltage, and the data in the target storage chip is read at the minimum interface rate; that is, even if the data reading fails, the data can be re-read by reducing the read rate or automatically recovering, thereby improving the success rate of data reading.

[0080] In some embodiments, Figure 4 As shown, the method of determining the secondary read rate of the next unit data according to the number of bits may include the following steps:

[0081] S1331 . When the number of bits is less than or equal to the error threshold, determine the target read rate as the secondary read rate.

[0082] The error threshold is preset, for example, a default value, or a value set by relevant personnel according to actual conditions. For another example, the error threshold is 80% of the number of bits of the maximum error tolerance of the error correction system.

[0083] S1332: When the number of bits is greater than the error threshold, the target read rate is reduced by one level to obtain a secondary read rate.

[0084] Similar to step S137, the target reading rate can be reduced by one gear according to the interface rate table or according to a preset gradient to obtain a secondary reading rate.

[0085] In the above scheme, when the number of error bits in a unit of data being read is relatively small, the reading rate is not changed; when the number of error bits in a unit of data being read is relatively large, the reading rate is timely reduced, so that data can be read at the fastest reading rate while ensuring the accuracy of data reading, thereby maximally ensuring the data reading performance of the solid-state drive.

[0086] In some embodiments, Figure 5 As shown, the method of reducing the target reading rate by one gear may include the following steps:

[0087] S1. When the target interface rate level is included in the interface rate table, the target read rate is reduced by one level according to the interface rate table.

[0088] The target interface rate gear is the interface rate gear corresponding to the target storage chip.

[0089] S2. When the target interface rate level is not included in the interface rate table, the target read rate is reduced by one level according to a preset gradient.

[0090] In the above scheme, since the target reading rate can be downshifted according to the interface rate table or the preset gradient, the rationality of the downshift of the target reading rate is ensured.

[0091] In some embodiments, Figure 6 As shown, after reading the data in the target storage chip using the target read rate, the control method of the solid-state storage device may further include the following steps:

[0092] S01. Obtain the lowest interface rate gear corresponding to the target storage chip.

[0093] Specifically, the method for obtaining the minimum interface rate gear corresponding to the target memory chip may be to first obtain the minimum interface rate of the target memory chip, and then use the minimum interface rate of the target memory chip as the minimum interface rate gear.

[0094] S02. Every time the target reading rate is reduced by one gear according to a preset gradient and a unit of data is read successfully, the intermediate interface rate gear after the gear is reduced by one gear is recorded.

[0095] Specifically, each time the interface rate is reduced by one gear and a unit of data is read successfully, an intermediate interface rate is recorded and the intermediate interface rate is used as an intermediate interface rate gear. Therefore, a memory chip can correspond to multiple intermediate interface rate gears.

[0096] S03. Use the highest initial interface rate as the highest initial interface rate gear.

[0097] S04. Generate a corresponding relationship between the target storage chip and the target interface rate gear in an interface rate table according to the highest initial interface rate gear, the middle interface rate gear, and the lowest interface rate gear.

[0098] Exemplarily, the generated interface rate table can be as shown in Table 2 below. For example, when the target storage chip is the first storage chip, the corresponding interface rate gears include a high initial interface rate gear, a first intermediate interface rate gear, a second intermediate interface rate gear, and a lowest interface rate gear.

[0099] Table 2

[0100]

[0101]

[0102] In the above scheme, the interface rate gear of the storage chip in the interface rate table can be automatically improved according to the minimum interface rate of the target storage chip, the downshifted intermediate interface rate, and the maximum initial interface rate, thereby improving the convenience of configuring the interface rate table.

[0103] In some embodiments, Figure 7 As shown, the method of determining the target read rate according to the current interface rate, the interface rate table, and the highest initial interface rate may include the following steps:

[0104] S141. Determine whether the interface rate table includes the target interface rate gear, and execute step S142 if it does; and execute step S144 if it does not.

[0105] The target interface rate gear is the interface rate gear corresponding to the target storage chip.

[0106] Specifically, the method for determining whether the interface rate table includes the target interface rate gear is to search for the target storage chip in the interface rate table. If found, it is determined that the interface rate table includes the target interface rate gear; if not found, it is determined that the interface rate table does not include the target interface rate gear.

[0107] S142, determine whether the target interface rate gear includes the current interface rate, and execute step S143 if it does, and execute step S144 if it does not.

[0108] Specifically, the method for determining whether the target interface rate gear includes the current interface rate can be to search for the current interface rate in the target interface rate gear. If found, it is determined that the target interface rate gear includes the current interface rate; if not found, it is determined that the target interface rate gear does not include the current interface rate.

[0109] S143: Determine the current interface rate as the target reading rate.

[0110] S144. Determine the highest initial interface rate of the target storage chip as the target read rate.

[0111] In the above scheme, when the current interface rate is included in the target interface rate gear of the interface rate table, the current interface rate is determined as the target read rate; when the current interface rate is not included in the target interface rate gear of the interface rate table, the highest initial interface rate of the target storage chip is determined as the target read rate. In this way, when the current interface rate is not included in the target interface rate gear of the interface rate table, the use of the highest initial interface rate can ensure that when the target read rate is subsequently adjusted, it can be adjusted from the maximum read rate, thereby ensuring the rationality of the determined target read rate.

[0112] The embodiment of the present application can divide the functional modules of the control device of the solid-state storage device according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing unit. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0113] Figure 8 A schematic diagram of a control device for a solid-state storage device provided in an embodiment of the present application, wherein the solid-state storage device includes at least one storage unit, and a storage unit includes at least one storage chip, such as Figure 8 As shown, the control device of the solid-state storage device includes a determination module 81 , an acquisition module 82 , and a processing module 83 .

[0114] A determination module 81 is used to determine the current interface rate and the highest initial interface rate corresponding to the target storage chip; an acquisition module 82 is used to read the interface rate table corresponding to the storage unit where the target storage chip is located; the interface rate table includes the correspondence between the storage chip and the interface rate gear, and one storage chip corresponds to multiple interface rate gears; a processing module 83 is used to determine the target read rate according to the current interface rate, the interface rate table, and the highest initial interface rate, and use the target read rate to read the data in the target storage chip.

[0115] In some embodiments, the processing module 83 includes an acquisition submodule, a determination submodule, and a reading submodule; the acquisition submodule is used to read a unit of data in the target storage chip using a target read rate, and when a unit of data is read successfully, obtain the number of bits of error data in the unit of data; the determination submodule is used to determine the secondary read rate of the next unit of data according to the number of bits; the reading submodule is used to read the next unit of data using the secondary read rate, and when the next unit of data is read successfully, return to execute the step of obtaining the number of error data bits until the data reading in the target storage chip is completed.

[0116] In some embodiments, the determination submodule is specifically used to: when the number of bits is less than or equal to the error threshold, determine the target read rate as the secondary read rate; when the number of bits is greater than the error threshold, reduce the target read rate by one level to obtain the secondary read rate.

[0117] In some embodiments, the processing module 83 also includes a decreasing submodule; an obtaining submodule is also used to obtain the minimum interface rate corresponding to the target storage chip; the determining submodule is also used to reduce the target read rate by one gear to obtain a new target read rate when a unit of data fails to be read and the target read rate is greater than the minimum interface rate; the reading submodule is also used to return to execute the reading of a unit of data using the new target read rate until a unit of data is successfully read, and return to execute the step of obtaining the number of error data bits until the data in the target storage chip is read; the reading submodule is also used to recover a unit of data by adjusting the read reference voltage when a unit of data fails to be read and the target read rate is equal to the minimum interface rate, and use the minimum interface rate to read the data in the target storage chip.

[0118] In some embodiments, a determination submodule is specifically used to: when the target interface rate gear is included in the interface rate table, the target read rate is reduced by one gear according to the interface rate table; the target interface rate gear is the interface rate gear corresponding to the target storage chip; when the target interface rate gear is not included in the interface rate table, the target read rate is reduced by one gear according to a preset gradient.

[0119] In some embodiments, the control device also includes a recording module and a generating module; the acquisition module 82 is also used to obtain the minimum interface rate gear corresponding to the target storage chip; the recording module is used to reduce the target read rate by one gear according to a preset gradient, and when a unit of data is read successfully, record the intermediate interface rate gear after reducing the gear by one gear; the determination module 81 is also used to use the highest initial interface rate as the highest initial interface rate gear; the generating module is used to generate the correspondence between the target storage chip and the target interface rate gear in the interface rate table according to the highest initial interface rate gear, the intermediate interface rate gear, and the lowest interface rate gear.

[0120] In some embodiments, the processing module 83 is specifically used to: when the interface rate table includes a target interface rate gear and the target interface rate gear includes the current interface rate, determine the current interface rate as the target read rate; the target interface rate gear is the interface rate gear corresponding to the target storage chip; when the interface rate table does not include the target interface rate gear, or the target interface rate gear does not include the current interface rate, determine the highest initial interface rate of the target storage chip as the target read rate.

[0121] The control device of the solid-state storage device provided in this embodiment can execute the control method of the solid-state storage device provided in the above method embodiment. Its implementation principle and technical effect are similar to the above method and will not be repeated here.

[0122] Fig. 9 An electronic device according to an exemplary embodiment may include a processor 702, and the processor 702 is used to execute application code to implement the control method of the solid-state storage device in the present application.

[0123] The processor 702 may be a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application.

[0124] like Fig. 9 As shown, the electronic device may further include a memory 703. The memory 703 is used to store application program codes for executing the solution of the present application, and the execution is controlled by the processor 702.

[0125] The memory 703 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 703 may exist independently and be connected to the processor 702 via the bus 704. The memory 703 may also be integrated with the processor 702.

[0126] like Fig. 9 As shown, the electronic device may further include a communication interface 701, wherein the communication interface 701, the processor 702, and the memory 703 may be coupled to each other, for example, via a bus 704. The communication interface 701 is used to exchange information with other devices, for example, to support information exchange between the electronic device and other devices.

[0127] It should be pointed out that Fig. 9 The device structure shown in the figure does not constitute a limitation on the electronic device, except Fig. 9 In addition to the components shown, the electronic device may include more or fewer components than shown, or combine certain components, or arrange the components differently. The electronic device provided in this embodiment may execute the control method of the solid-state storage device provided in the above method embodiment, and its implementation principle and technical effect are similar to the above method, which will not be described in detail here.

[0128] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each process of the control method of the solid-state storage device in the above method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0129] The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0130] An embodiment of the present application also provides a non-volatile computer storage medium, which stores computer executable instructions, and the computer executable instructions are executed by one or more processors. For example, the one or more processors can execute the control method of the solid-state storage device in any of the above method embodiments, for example, execute the control method of the solid-state storage device in any of the above method embodiments, for example, execute the various steps described above.

[0131] An embodiment of the present application provides a computer program product, which stores a computer program. When the computer program is executed by a processor, the various processes in the above method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0132] The above-described device or equipment embodiments are merely illustrative, wherein the unit modules described as separate components may or may not be physically separated, and the components displayed as module units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0133] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute various embodiments or certain parts of the embodiments.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A control method for a solid-state storage device, characterized in that: The solid-state storage device includes at least one storage unit, and one storage unit includes at least one storage chip; Determine the current interface rate and the maximum initial interface rate corresponding to the target storage chip; Reading an interface rate table corresponding to the storage unit where the target storage chip is located; the interface rate table includes a correspondence between storage chips and interface rate gears, and one storage chip corresponds to multiple interface rate gears; A target read rate is determined according to the current interface rate, the interface rate table, and the highest initial interface rate, and the target read rate is used to read data in the target storage chip.

2. The control method according to claim 1, characterized in that: The step of reading the data in the target storage chip using the target read rate includes: Reading a unit of data in the target storage chip using the target read rate, and obtaining the number of bits of error data in the unit of data when the unit of data is read successfully; determining a secondary read rate of the next unit data according to the number of bits; The next unit data is read using the secondary read rate, and when the next unit data is read successfully, the step of obtaining the number of error data bits is returned to be executed until the data reading in the target memory chip is completed.

3. The control method according to claim 2, characterized in that: The determining the secondary read rate of the next unit data according to the number of bits includes: When the number of bits is less than or equal to an error threshold, determining the target read rate as a secondary read rate; When the number of bits is greater than the error threshold, the target read rate is reduced by one level to obtain a secondary read rate.

4. The control method according to claim 2, characterized in that: The method further comprises: Obtaining the minimum interface rate corresponding to the target storage chip; When the reading of the one unit of data fails and the target reading rate is greater than the minimum interface rate, the target reading rate is reduced by one gear to obtain a new target reading rate; Using the new target read rate, returning to read the one unit of data, until the one unit of data is read successfully, returning to execute the step of obtaining the number of error data bits, until the data in the target memory chip is read completely; When the reading of the one unit data fails and the target reading rate is equal to the minimum interface rate, the one unit data is recovered by adjusting the read reference voltage, and the data in the target memory chip is read using the minimum interface rate.

5. The control method according to claim 3 or 4, characterized in that: The step of reducing the target reading rate by one gear comprises: When the interface rate table includes a target interface rate gear, the target read rate is reduced by one gear according to the interface rate table; the target interface rate gear is the interface rate gear corresponding to the target storage chip; When the target interface rate level is not included in the interface rate table, the target read rate is reduced by one level according to a preset gradient.

6. The control method according to claim 5, characterized in that: The method further comprises: Obtaining the lowest interface rate gear corresponding to the target storage chip; Each time the target reading rate is reduced by one gear according to a preset gradient and a unit of data is read successfully, the intermediate interface rate gear after the gear is reduced by one gear is recorded; Using the highest initial interface rate as the highest initial interface rate gear; A correspondence between the target storage chip and the target interface rate gear in the interface rate table is generated according to the highest initial interface rate gear, the middle interface rate gear, and the lowest interface rate gear.

7. A control device for a solid-state storage device, characterized in that: The solid-state storage device includes at least one storage unit, one storage unit includes at least one storage chip, and the control device includes: A determination module, used to determine the current interface rate and the highest initial interface rate corresponding to the target storage chip; An acquisition module is used to read an interface rate table corresponding to the storage unit where the target storage chip is located; the interface rate table includes a correspondence between storage chips and interface rate gears, and one storage chip corresponds to multiple interface rate gears; The processing module is used to determine a target read rate according to the current interface rate, the interface rate table, and the highest initial interface rate, and use the target read rate to read data in the target storage chip.

8. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements a control method for a solid-state storage device as claimed in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the control method of the solid-state storage device according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that When the computer program product is executed on a computer, the computer is enabled to implement the control method of the solid-state storage device according to any one of claims 1 to 6.

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