Automatic design method and device for complex special instruction of hardware, medium and product

Abstract

The invention discloses an automatic design method and device for a complex special instruction of hardware, a medium and a product, and relates to special hardware design, special instruction design or instruction set extension. The method comprises the steps that an analysis program collects dynamic information; basic blocks in the program are converted into a data dependency graph based on the intermediate representation of the compiler, and seeds are extracted; adopting a genetic algorithm to obtain candidate items of full input and output limitation based on the seeds; scoring the candidate items by adopting a specially designed cost model to serve as a screening basis; the overlapping problem of candidate items is solved through maximum weighted independent set analysis; and fusing the sub-graphs corresponding to the special instruction, generating a special function unit, and completing the automatic design of the complex special instruction of the hardware. According to the method, the similarity between the basic blocks can be explored, and common and frequently executed code snippets are found from a program to serve as special instructions; searching can cover a target program to the maximum degree, and the program is fully accelerated.

Description

Technical Field

[0001] The present application relates to special hardware design, special instruction design or instruction set expansion, and in particular to a method, device, medium and product for automatically designing complex special instructions for hardware. Background Art

[0002] Recently, there has been a growing trend to integrate specialized instructions into a general instruction set architecture (ISA), which has led to the rise of computing platforms such as application-specific instruction set processors (ASIPs). This trend is driven by practical needs in various application areas such as image processing and advanced encryption standards. Representative instruction set extensions include Intel's SSE, GPU (Graphics Processing Unit) tensor cores, Intel's AMX, and Qualcomm's HVX. Among them, Intel's SSE is used for stream processing applications, GPU tensor cores are used for deep learning, and Intel's AMX and Qualcomm's HVX are also used for deep learning. However, specialized instructions require a deep understanding of the application's algorithms, data structures, and performance bottlenecks, involving a lot of manual work.

[0003] At present, the exploration and design of dedicated instructions automated by intermediate representation (IR) has become a trend. However, in order to extract valuable dedicated instructions and verify their performance, power consumption and area, several challenges need to be addressed. First, dedicated instructions can be extracted from any part of the application, which requires searching the entire code to identify candidate instructions and select the best instructions from them. In addition, given the similarity of instruction sequences, this process involves graph isomorphism judgment, which is an NP (Nondeterministic polynominal) problem. These factors together lead to a large and complex search space. Secondly, dedicated instructions should maximize performance benefits while minimizing overhead. Dedicated instructions can benefit by reducing addressing and decoding overhead, reducing register accesses, and exploiting operational parallelism. The more operations in a dedicated instruction, the greater these benefits may be. However, given the limited hardware area, it is necessary to limit the number and size (number of operations) of dedicated instructions.

[0004] Current research has not yet fully addressed these challenges. Among them, some methods use heuristic algorithms to extract candidate instructions to avoid extensive searches. However, these methods over-cut the search space, resulting in the neglect of some design points. The number of inputs and outputs of each dedicated instruction should be limited. On the one hand, the inputs and outputs should meet the restrictions of specific design requirements, such as scalar instructions with limited operands; on the other hand, reducing inputs and outputs can reduce data movement (between general registers and special registers / buffers) and swizzle instructions, otherwise it will reduce the performance gain brought by dedicated instructions. Related work does not consider the restrictions on the number of inputs and outputs. There are also some methods that can extract candidates with precise input and output numbers, but they cannot exploit the similarity between basic blocks in the search process, and only fuse after obtaining dedicated instructions, which can only reduce the hardware area overhead and cannot help the search process. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present application provides a method, device, medium and product for automatically designing complex special instructions for hardware.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a method for automatically designing complex special instructions for hardware, comprising:

[0008] Analyze the program and collect dynamic information; the dynamic information includes the execution times of basic blocks;

[0009] Converting a program into an intermediate representation of a compiler, and based on the intermediate representation, converting basic blocks in the program into a data dependency graph;

[0010] Using prohibition instructions to divide the data dependency graph into subgraphs; the subgraphs only contain arithmetic instructions; the prohibition instructions include memory access instructions and branch instructions;

[0011] A seed growing method is used to obtain candidate items based on the subgraph; the seed growing method is a genetic algorithm embedded with a seed multi-component simultaneous growing algorithm;

[0012] Obtaining arithmetic instructions corresponding to the candidate items, evaluating the arithmetic instructions corresponding to the candidate items using a cost model, and taking the candidate item with the highest evaluation score as a dedicated instruction;

[0013] The subgraphs corresponding to the special instructions are integrated to generate special function units, thereby completing the automatic design of complex special instructions for hardware.

[0014] Optionally, a seed growing method is used to obtain candidate items based on the subgraph, specifically including:

[0015] Extracting a seed from the subgraph; the seed has one or more;

[0016] Calling a genetic algorithm to grow the seed, and calling the seed multi-component simultaneous growth algorithm to explore the code similarity between basic blocks in the process of calling the genetic algorithm, so as to obtain a growing subgraph that appears repeatedly in the code and meets predefined conditions; the genetic algorithm includes selection, mutation and crossover operations;

[0017] Defining a seed component; the seed component defined is an instance of a seed existing in the same or different basic blocks;

[0018] The growing subgraph connecting nodes with the seed component is used as the candidate.

[0019] Optionally, extracting a seed from the subgraph specifically includes:

[0020] Extracting recurring instruction pairs from the subgraph as seeds;

[0021] A greedy strategy is used to iteratively extract the instruction pair with the longest total delay in the subgraph as a seed.

[0022] Optionally, a greedy strategy is used to iteratively extract the instruction pair with the longest total delay in the subgraph as a seed, specifically including:

[0023] All nodes in the subgraph are traversed, the node pairs with the longest total delay are identified and extracted, and the node pairs with the longest total delay are removed from the subgraph. This process is repeated until all nodes in the subgraph are traversed, and the instructions corresponding to all nodes with the longest total delay extracted from the subgraph are used as the seeds.

[0024] Optionally, the method for automatically designing complex dedicated instructions for hardware further includes:

[0025] After all seeds are grown by the seed growth method to obtain candidate items, a conflict graph is constructed for all candidate items, the evaluation scores are used as weights, and the independent set with the largest weight and maximum sum is extracted from the conflict graph, and the candidate items in the independent set are used as the region of interest; the independent set refers to a set of nodes in which no edge exists between any two nodes in the subgraph; the conflict refers to the subgraphs corresponding to the two candidate items containing the same node;

[0026] Deleting the node corresponding to the region of interest in the subgraph, and returning to the step of extracting seeds from the subgraph until no seeds can be extracted;

[0027] The regions of interest are merged to achieve reuse of dedicated functional units.

[0028] Optionally, the method for automatically designing complex dedicated instructions for hardware is implemented based on a framework for automatically extracting and verifying instructions; the framework takes the intermediate representation of the compiler as input.

[0029] Optionally, the obtained candidates do not overlap; overlap of candidates means that subgraphs corresponding to different candidates share one or more nodes.

[0030] In a second aspect, the present application provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-mentioned method for automatically designing complex special instructions for hardware.

[0031] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned method for automatically designing complex special instructions for the hardware provided above.

[0032] In a fourth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above-mentioned method for automatically designing complex special-purpose instructions for hardware.

[0033] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0034] The present application provides a method, device, medium and product for automatic design of complex special instructions for hardware, which can find common and frequently executed code fragments from the program as candidates for special instructions, and overcome the overlapping problem of candidates through maximum weighted independent set analysis. By using a cost model to compare and select the best instructions (i.e., special instructions) among these candidates, the maximum performance under predefined input and output constraints can be pursued. Through the seed growth method, the similarity between basic blocks can be explored, and the iterative search method can be used to solve the problem of excessive reduction of the search space, resulting in the neglect of design points, and to explore special instructions with potential benefits as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 This is a workflow diagram of a method for automatically designing complex special instructions for hardware based on CCExplorer in one embodiment of the present application;

[0037] Figure 2 A flowchart of a method for automatically designing complex special instructions for hardware provided in one embodiment of the present application;

[0038] Figure 3 A data dependency graph provided for another embodiment of the present application;

[0039] Figure 4 A schematic diagram of a seed multi-component simultaneous growth algorithm program provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of three candidate items 0, 1 and 2 provided in an embodiment of the present application;

[0041] Figure 6 A conflict graph of three candidate items and a schematic diagram of the selected maximum weighted independent set provided in another embodiment of the present application;

[0042] Figure 7 A schematic diagram of candidate instructions provided for another embodiment of the present application;

[0043] Figure 8 A schematic diagram of an implementation method of a complex dedicated instruction automatic design method for hardware provided by another embodiment of the present application;

[0044] Fig. 9 A schematic diagram of region of interest fusion provided in another embodiment of the present application;

[0045] Fig.10 A schematic diagram of a non-convex subgraph provided in another embodiment of the present application;

[0046] Fig.11 A schematic diagram of the structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0049] In order to better present the concept of this application, several basic terms are introduced first:

[0050] (1) Candidates. Candidates are subgraphs derived from basic blocks. In this work, they only contain arithmetic operations. For example, Figure 7 In , all subgraphs 0-3 and repeated subgraphs can be candidates. Based on the cost model, they are evaluated for their potential benefits as dedicated instructions. Among them, Figure 7 Part (A) is the subgraph of basic block 0. Figure 7 (B) is the subgraph of basic block 1, Figure 7 (C) is a repeated subgraph.

[0051] (2) Region of Interest. The region of interest is used to implement the dedicated instruction, which is the most promising candidate selected from all extracted candidates.

[0052] (3) Candidate components. The subgraph corresponding to the candidate may appear repeatedly in the application, and each subgraph instance is called a candidate component. Figure 7 There are five add-getelementptr instruction pairs in , so add-getelementptr is a candidate with five candidate components. The candidate components can be distributed in the same or different basic blocks.

[0053] (4) Seeds and seed components. A seed is a repeated subgraph that contains only two connected nodes. For example, Figure 7 Only the first three sub-graphs in the panel shown in part (C) can be seeds. Seed components are similar to candidate components and represent different seed instances.

[0054] In order to implement the complex custom instruction automatic design method for hardware provided in the embodiment of the present application, CCExplorer (Complex Custom Instruction Explorer) can be designed. CCExplorer is a framework for automatically extracting and verifying custom instructions. Figure 1 The workflow of the entire framework is demonstrated. CCExplorer takes the intermediate representation (IR) of LLVM (Low Level Virtual Machine) as input. CCExplorer first analyzes the program, collects dynamic information, such as the number of executions of basic blocks, and converts the basic blocks into data dependency graphs based on the intermediate representation of the compiler. These data dependency graphs are then split into subgraphs using prohibition instructions so that these subgraphs only contain arithmetic instructions to effectively reduce the search space. CCExplorer uses a seed growth method to quickly and automatically select non-overlapping candidates and select the best from them as dedicated instructions. Overlap means that the subgraphs corresponding to different candidates share one or more nodes, such as Figure 5Candidates 0 and 1 both contain nodes A and B. The quality (or benefit) of dedicated instructions is evaluated by a cost model. The entire search process is iterative to avoid missing design points and achieve high coverage of arithmetic operations. Then all selected dedicated instructions are fused in the post-processing process (the fusion process uses the method in existing work to fuse different new instructions) to generate dedicated functional units to minimize the area cost of hardware implementation. Finally, a simulator that can directly execute the compiler's IR and any custom instructions is used for verification.

[0055] Based on this, the present application can quickly and automatically explore and verify complex dedicated instructions in the early stages of design, automatically identify common and frequently executed operations in applications as dedicated instructions, and ensure that dedicated instructions comply with predefined input and output quantity restrictions.

[0056] In an exemplary embodiment, Figure 2 As shown, a method for automatically designing complex special instructions for hardware is provided. The method is executed by a computer device, and can be executed by a computer device such as a terminal or a server alone, or by a terminal and a server together. In the embodiment of the present application, the method is applied to a server as an example for explanation, and includes the following steps 200 to 205. Among them:

[0057] Step 200: Analyze the program and collect dynamic information, including the execution times of basic blocks.

[0058] Step 201, converting the program into an intermediate representation of the compiler, and based on the intermediate representation, converting the basic blocks in the program into a data dependency graph.

[0059] Step 202: Use prohibition instructions to split the data dependency graph into subgraphs. The subgraphs only contain arithmetic instructions.

[0060] Step 203: A seed growing method is used to obtain candidate items based on the subgraph. The seed growing method is a genetic algorithm embedded with a seed multi-component simultaneous growing algorithm.

[0061] Step 204 , obtaining arithmetic instructions corresponding to the candidate items, using the cost model to evaluate the arithmetic instructions corresponding to the candidate items, and taking the candidate item with the highest evaluation score as the dedicated instruction.

[0062] Step 205, merging the subgraphs corresponding to the dedicated instructions, generating dedicated functional units, and completing the automatic design of complex dedicated instructions for hardware.

[0063] Implementing the above steps 200 to 205 can discover common and frequently executed code snippets from the program as candidates for special instructions, overcome the problem of overlapping candidates, solve the problem of excessive reduction of the search space leading to neglect of design points, and explore the similarities between basic blocks.

[0064] In another exemplary embodiment of the present application, the implementation process of the above step 203 can be described as follows:

[0065] Extract seeds from a subgraph.

[0066] Calling a genetic algorithm to grow the seed, and calling the seed multi-component simultaneous growth algorithm to explore the code similarity between basic blocks in the process of calling the genetic algorithm, so as to obtain a growing subgraph that appears repeatedly in the code and meets predefined conditions; the genetic algorithm includes selection, mutation and crossover operations;

[0067] Defining a seed component; the seed component defined is an instance of a seed existing in the same or different basic blocks;

[0068] The growing subgraph connecting nodes with the seed component is used as the candidate.

[0069] In another exemplary embodiment of the present application, in order to avoid over-cutting the search space (or searching as many design points as possible), an algorithm is needed that can include all design points from fine-grained to coarse-grained, such as: fine-grained new instructions formed by the fusion of two instructions, coarse-grained new instructions generated by the fusion of the entire basic block, or a design in between. Enumerating all design points can certainly not miss any design point, but the search space is too large to complete the search within a reasonable time, so it is also necessary to ensure that the algorithm can complete the search quickly. Since the basic block is composed of instructions, two instructions with data dependencies can be used as the starting point, and new instructions can be continuously added to form a larger candidate (a subgraph containing more instructions). This process can be implemented using the seed growth method. However, larger candidates do not mean greater performance benefits, so these candidates need to be scored to obtain instructions that can generate more benefits, and the scoring is implemented through a cost model.

[0070] Based on the above description, in this embodiment, the seed growing method uses a genetic algorithm to grow seeds into larger subgraphs that meet predefined input and output constraints. A cost model is integrated into the genetic algorithm to evaluate and screen these subgraphs. The genetic algorithm uses the seed multi-component simultaneous growing algorithm proposed in this application to solve the graph similarity check problem.

[0071] Since this embodiment only focuses on arithmetic instructions, the prohibition instruction is used to divide the data dependency graph of the basic block into subgraphs in the above step 202. Then, two methods are used to extract seeds from these subgraphs.

[0072] The first approach is to extract recurring pairs of instructions from a subgraph as seeds. When the seeds grow into a larger graph, all seed components should grow simultaneously, and the graphs need to be checked for similarity. These instruction pairs may overlap, and the instruction pairs that appear earlier in the program order are selected and the others are discarded. It is worth noting that not all basic blocks contain repeated instruction pairs, so the second approach is used when these basic blocks are hot spots and specialized instructions need to be extracted.

[0073] The second method uses a greedy strategy to iteratively extract the instruction pair with the longest total delay in the subgraph, which can be summarized as follows:

[0074] (1) Identify and extract the node pairs with the longest total delay.

[0075] (2) Remove these nodes from the subgraph.

[0076] (3) If there are still unvisited nodes, repeat step (1); otherwise, the extraction is completed.

[0077] In another exemplary embodiment of the present application, it is introduced how to implement the seed growth method using a genetic algorithm. The first step is to encode the data dependency graph, and the encoding should be able to represent the seed growth process. Figure 3 Part (A) of Figure 2 shows a subgraph containing eight nodes, encoded as 00001100, where the solid black lines represent seed nodes. Figure 3 Part (B) of shows the subgraph (red and black nodes) grown from the seed, which will be encoded as 00111100. In the subgraph, the order of the nodes corresponds to the order in which the instructions appear in the intermediate representation. Based on this, the implementation process of the seed growth method is:

[0078] 1) Seed growth. Figure 3 (B) to Figure 3 Part (E) of the diagram depicts various scenarios of trying to integrate red nodes to build new subgraphs during the seed growing process. For simplicity, the example only considers the case of growing one seed component. Assume that the design goal is to find a subgraph with at most eight inputs and only one output.

[0079] Figure 3 Part (B) and Figure 3 Part (C) of shows two valid subgraphs. After adding the red node to the seed, both subgraphs have five inputs and one output, and all nodes are connected, acyclic, and convex. Convex means that there is no path between any two nodes in the graph that is outside the subgraph. In contrast, Figure 3The subgraph in part (D) of is invalid because the newly added node is not connected to the seed, and Figure 3 The subgraph in part (E) of has nine inputs. Among them, Figure 3 Parts (A) to (E) of are data dependency graphs, each containing eight nodes. Solid black circles represent nodes of seed components, red circles represent nodes from which seeds grow, and dashed black circles represent nodes that are not considered. Black arrows indicate the direction of data dependency, and input and output nodes are omitted.

[0080] 2) Implementation. Initialize the genetic algorithm with the seed code to ensure that the randomly generated code during the genetic algorithm execution contains the seed. The genetic algorithm includes selection, mutation and crossover operations. Before executing the genetic algorithm, we search to obtain the best parameters for these operations. The cost model is used to score the subgraph and determine whether the subgraph meets the predefined conditions. The genetic algorithm will be executed once for each seed and output the best subgraph with the highest score as a candidate.

[0081] 3) Challenges. The seed growth method needs to consider the similarity of the graph, which poses the following challenges to the implementation of the genetic algorithm:

[0082] First, different lengths of basic blocks lead to variations in encoding length, which is unavoidable.

[0083] Second, seed components appear in different basic blocks, so the contexts are different. When adding a new node to a seed component, the instruction corresponding to the node may not exist in the basic blocks to which other seed components belong, or may exist but the position is unknown, which brings difficulties to seed growth.

[0084] Furthermore, it is necessary to check whether these subgraphs are still isomorphic when the seeds are grown. However, graph isomorphism is NP-hard. To this end, this application proposes a seed multi-component simultaneous growth algorithm.

[0085] Figure 4 The implementation flow of the algorithm for simultaneous growth of multiple components of a seed is shown, which is embedded in a genetic algorithm. The components of the seed should be grown simultaneously in different basic blocks. To achieve this, a candidate component is selected for growth, and then other components are checked to see if they can grow into the same subgraph. If the basic block containing the seed component is smaller, then the subgraph grown from the seed will also be smaller. In this case, the application uses the SelectCandidateComponent function to select the component defined as seed. x The seed component of the basic block bb that contains the most instructions x (correspond Figure 4 The GenerateNewCode function generates the code based on the seed. x Generate a new code (corresponding to Figure 4 6th line), the encoding length is the same as bb x The Decode function then extracts the newly added nodes and constructs the subgraph g. x (correspond Figure 4 The encoding generated by the genetic algorithm does not guarantee that the subgraph g x Nodes and seeds in x connection, so use the CheckConnectivity function to determine g x Is it connected? If it is not a connected graph, the seed multi-component simultaneous growth algorithm will end and return directly (corresponding to Figure 4 8 and 9 of ). Figure 4 Lines 10 to 16 of traverse the other seed components and use the Grow function to seed each seed component. i Constructing graph g i (correspond Figure 4 If there is no way to construct a connected, acyclic, and convex subgraph g i The Grow function will return empty if the corresponding node instruction is required. The Grow function ensures that the subgraph g i and subgraph g x In other words, the subgraph g i and subgraph g x This is a relaxed way of checking graph similarity. If a subgraph g is identical in number and type of instructions, but the instructions may have different orders and dependencies, i is not empty, then the subgraph g i and subgraph g x are considered similar, and then the subgraph g i Add to include with subgraph g x In the set R of similar repeated subgraphs (corresponding to Figure 4 Finally, the CostModel function is called to score the candidate R using the cost model (corresponding to Figure 4 18 of ). This application does not strictly guarantee graph isomorphism, because this application can assume that if two subgraphs are identical in the number and type of operations, they can share hardware area using multiplexers.

[0086] In the execution of the genetic algorithm, when calling the seed multi-component simultaneous growth algorithm, seed x The genetic algorithm will generate many encodings based on the seed, and each encoding will call the seed multi-component simultaneous growth algorithm to check how many seed components can be grown into subgraph g. x , and the valid subgraph g iAdd to the set R. R represents a candidate, and each subgraph in it is a candidate component. The number of elements in R can be less than or equal to the number of elements in seeds. The genetic algorithm compares and maintains the R with the highest score as output.

[0087] Based on the above description, in the process of continuously adding instructions, it is easier to count and control the number of inputs and outputs of candidates, that is, count once each time a new candidate is generated. The statistics of the number of inputs and outputs are integrated into the cost model to achieve the screening of candidates that meet the specific number of inputs and outputs and score and compare the candidates that meet the conditions. In addition, finding repeated candidates from the program involves the judgment of graph isomorphism, which is an NP problem that is difficult to solve, but this problem can also be solved using the growth process. When implementing, first select the instruction pairs that appear repeatedly in the program as the starting point, and then add the same instructions to these instruction pairs to determine whether the newly generated subgraphs are similar. The similarity judgment algorithm is the seed multi-component simultaneous growth algorithm.

[0088] In another exemplary embodiment of the present application, the cost model adopted above aims to achieve optimal performance under predefined input and output constraints, which can be summarized as formula (1).

[0089] score = ∏ constraint i ×merit (1)

[0090] In the public, score represents the evaluation score, constraint i represents the i-th constraint item, and merit represents the benefit item. In this embodiment, four constraints are used: convex, input-output constraint (io_num), acyclic, and connected. If the input and output of the subgraph exceed the limit, the input-output constraint will be 0. Convexity ensures that the subgraph can become a dedicated instruction. Fig.10 As shown in Figure 1, non-convex means that there is a path (3->2->0) between two nodes (3 and 0) outside the subgraph. In this case, node 2 requires both the output of the candidate (consisting of nodes 0, 1, and 3) and the input of the subgraph, so the candidate cannot be used as a new instruction. Merit is only in the ∏ constraint i It works when it is equal to 1.

[0091]

[0092] Formula (2) shows the calculation method of the benefit item merit, where: Measure the potential performance improvement of the i-th candidate component, is the number of executions of the basic block containing the i-th component, io_score i is the Euclidean distance used to evaluate the input and output formats of the ith component with respect to a predefined threshold.

[0093]

[0094] Formula (3) calculation α is an empirical parameter. Compute the total latency of executing all instructions sequentially and along the critical path in the ith component, respectively.

[0095]

[0096] Formula (4) - Formula (6) together constitute io_score i The calculation method of . Represent the number of inputs and outputs of the i-th candidate component, respectively, and is the predefined maximum threshold. i is the coordinate corresponding to the number of inputs and outputs With threshold coordinates io_score is the Euclidean distance between the threshold coordinates and the origin (0,0). i It is a value between 0 and 1, indicating that the closer to the predefined threshold of input and output number, the better. It is worth noting that io_score i and io_num can be preset to 1, so that the cost model ignores the impact of the number of inputs and outputs of the subgraph. pow and sqrt represent exponentiation and square root operations respectively.

[0097] In another exemplary embodiment of the present application, when the seed growth method is applied to each seed separately, the influence of other seeds during the seed growth period is not considered, which may lead to overlap between candidate items. Figure 5 As shown, candidate 0 and candidate 1 have two common nodes, A and B. These overlapping nodes cannot be accelerated by multiple dedicated instructions, so the best one needs to be selected. Based on this, maximum weighted independent set analysis and iterative search are performed to eliminate the overlap between candidates. Among them:

[0098] (1) Maximum weighted independent set analysis. Two candidates with overlapping nodes are considered as conflicts, and a conflict graph is established. Figure 6As shown, candidate 0 and candidate 1 conflict, so there is an edge between their corresponding nodes. Selecting one or more non-conflicting best candidates can be viewed as solving the maximum weighted independent set problem, which is used to identify the independent set with the maximum total score. A weighted independent set is a set of nodes in a graph, each with a weight, and no edges between them. In this embodiment, nodes 0 and 1, and nodes 1 and 2 are two independent sets, and the scores generated by the cost model are used as weights to implement the maximum weighted independent set analysis method based on the Bron-Kerbosch algorithm to find the independent set with the maximum total score. For example, Figure 6 There are two independent sets in , the independent set containing candidates 1 and 2 has a total score of 9, which is higher than the independent set containing candidates 0 and 2, so it will be selected.

[0099] (2) Iterative search. Some candidates may still have the potential to be accelerated after resolving candidate conflicts, such as Figure 5 The remaining three nodes of candidate 0 in the subgraph (excluding nodes A and B). In this case, an iterative method can be used. Each iteration starts from seed extraction to the end of maximum weighted independent set analysis, after which the nodes contained in the extracted region of interest are removed from the subgraph. If it is still possible to extract seeds from the remaining nodes, a new iteration is restarted.

[0100] In another exemplary embodiment of the present application, after extracting the regions of interest, the method proposed by Novia is used to merge the regions of interest to achieve reuse of dedicated functional units, thereby reducing the hardware implementation area overhead. When extracting candidate items, the method provided by the present application considers the similarity of the graphs to keep the candidate components with the same type and number of nodes, but this merging process can merge different graphs. Fig. 9 As shown, the region of interest 1 and the region of interest 2 are two instructions, but when implemented in hardware, the hardware implementation corresponding to the division and subtraction operations can be shared.

[0101] In another exemplary embodiment of the present application, the results were verified using a simulator. Compared with the case where no special instructions were introduced, CCExplorer achieved an average 1.36 times performance improvement and 17.12% power consumption reduction on some common algorithms. An average 1.50 times performance improvement and 30.36% power consumption reduction were achieved on some deep neural network operators. Table 1 shows these benchmark programs.

[0102] Table 1 Benchmark test program table

[0103] Some common algorithms Neural Network Operators Breadth-First Search Average Pooling Layer Fast Fourier Transform Reshape Dense matrix multiplication Fully connected layer Sparse Matrix-Vector Multiplication Residual calculation Molecular dynamics (K-nearest neighbor algorithm) Depthwise Convolution Molecular dynamics (grid algorithm) Point-wise convolution 2D template calculation Convolutional Layer 3D template calculation

[0104] like Figure 8As shown in Figure 1, CCExplorer takes the intermediate representation of the LLVM compiler as input and finds the dedicated instructions that meet the number of repetitions and the number of inputs and outputs. Figure 8 There are dedicated instructions for 6 inputs / 1 output and dedicated instructions for 12 inputs / 3 outputs.

[0105] In summary, the present application has the following advantages over the prior art:

[0106] 1. This application establishes CCExplorer, which can automatically explore dedicated instructions and evaluate their performance, power consumption and area end-to-end.

[0107] 2. This application proposes a seed growth method that has the ability to consider code similarity across basic blocks in the process of screening candidates, and can find common and frequently executed code snippets from the program as dedicated instructions. This method can extract code snippets that specify the number of inputs and outputs and appear repeatedly in the code.

[0108] 3. This application proposes an iterative search strategy to fully explore possible special instructions based on solving the problem of overlapping special instruction candidates.

[0109] In an exemplary embodiment, a computer device is provided. The computer device may be a server or a terminal. The internal structure diagram thereof may be as follows: Fig.11 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store complex special instructions and automatic data of hardware. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for automatically designing complex special instructions for hardware is implemented.

[0110] Those skilled in the art will understand that Fig.11The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components. In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0111] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0112] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0113] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0114] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0115] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0116] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A method for automatically designing complex special instructions for hardware, characterized in that: The complex dedicated instruction automatic design method of the hardware includes: Analyze the program and collect dynamic information; the dynamic information includes the execution times of basic blocks; Converting a program into an intermediate representation of a compiler, and based on the intermediate representation, converting basic blocks in the program into a data dependency graph; Using prohibition instructions to divide the data dependency graph into subgraphs; the subgraphs only contain arithmetic instructions; the prohibition instructions include memory access instructions and branch instructions; A seed growing method is used to obtain candidate items based on the subgraph; the seed growing method is a genetic algorithm embedded with a seed multi-component simultaneous growing algorithm; Obtaining arithmetic instructions corresponding to the candidate items, evaluating the arithmetic instructions corresponding to the candidate items using a cost model, and taking the candidate item with the highest evaluation score as a dedicated instruction; The subgraphs corresponding to the special instructions are integrated to generate special function units, thereby completing the automatic design of complex special instructions for hardware.

2. The method for automatically designing complex special instructions for hardware according to claim 1, characterized in that: A seed growing method is used to obtain candidate items based on the subgraph, specifically including: Extracting a seed from the subgraph; the seed has one or more; Calling a genetic algorithm to grow the seed, and calling the seed multi-component simultaneous growth algorithm to explore the code similarity between basic blocks in the process of calling the genetic algorithm, so as to obtain a growing subgraph that appears repeatedly in the code and meets predefined conditions; the genetic algorithm includes selection, mutation and crossover operations; Defining a seed component; the seed component defined is an instance of a seed existing in the same or different basic blocks; The growing subgraph connecting nodes with the seed component is used as the candidate.

3. The method for automatically designing complex special instructions for hardware according to claim 2, characterized in that: Extracting a seed from the subgraph specifically includes: Extracting recurring instruction pairs from the subgraph as seeds; A greedy strategy is used to iteratively extract the instruction pair with the longest total delay in the subgraph as a seed.

4. The method for automatically designing complex special instructions for hardware according to claim 3, characterized in that: Use a greedy strategy to iteratively extract the instruction pair with the longest total delay in the subgraph as a seed, specifically including All nodes in the subgraph are traversed, the node pairs with the longest total delay are identified and extracted, and the node pairs with the longest total delay are removed from the subgraph. This process is repeated until all nodes in the subgraph are traversed, and the instructions corresponding to all nodes with the longest total delay extracted from the subgraph are used as the seeds.

5. The method for automatically designing complex special instructions for hardware according to claim 2, characterized in that: The complex dedicated instruction automatic design method for the hardware also includes: After all seeds are grown by the seed growth method to obtain candidate items, a conflict graph is constructed for all candidate items, the evaluation scores are used as weights, and an independent set with the largest sum of weights is extracted from the conflict graph, and the candidate items in the independent set are used as the region of interest; the independent set refers to a set of nodes in which no edge exists between any two nodes in the subgraph; the conflict refers to the subgraphs corresponding to the two candidate items containing the same node; Deleting the node corresponding to the region of interest in the subgraph, and returning to the step of extracting seeds from the subgraph until no seeds can be extracted; The regions of interest are merged to achieve reuse of dedicated functional units.

6. The method for automatically designing complex special instructions for hardware according to claim 1, characterized in that: The complex dedicated instruction automatic design method for hardware is implemented based on a framework for automatically extracting and verifying instructions; the framework takes the intermediate representation of the compiler as input.

7. The method for automatically designing complex special instructions for hardware according to claim 1, characterized in that: The obtained candidates do not overlap; overlap of candidates means that the subgraphs corresponding to different candidates share one or more nodes.

8. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the complex dedicated instruction automatic design method for hardware according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for automatically designing complex special instructions for hardware according to any one of claims 1 to 7 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for automatically designing complex special instructions for hardware according to any one of claims 1 to 7 is implemented.

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