Device interconnection system, data processing method, device and equipment, medium and product

Abstract

The present application discloses a device interconnection system, a data processing method, an apparatus and equipment, a medium and a product, and relates to the field of data processing technology. The device interconnection system includes a processor and multiple computing devices. The processor is connected to the processor memory, and the computing device is connected to the computing device memory. The processor and the multiple computing devices are connected via a bus that complies with a preset protocol. The computing device includes a target port, and different computing devices are directly connected via the target port. Different computing devices transmit data directly via the target port. The processor memory and the multiple computing device memories are addressed using a unified addressing method. When the computing device memory is accessed, the corresponding computing device performs address mapping between the unified addressing and the internal address space of the computing device. The present application improves the data transmission efficiency between different computing devices and simplifies the address access method and data transmission method.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a device interconnection system, a data processing method, an apparatus and equipment, a medium, and a product. Background Art

[0002] In device interconnection systems in related technologies, the processor and multiple computing devices are connected via a bus that complies with a pre-defined protocol, such as PCIe (Peripheral Component Interconnect Express). Data transmission between the processor and a computing device, as well as between different computing devices, must proceed through this bus, resulting in high bus pressure and low data transmission efficiency between different computing devices.

[0003] Therefore, how to improve the data transmission efficiency between different computing devices in a device interconnection system is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a data processing method, apparatus and device, storage medium and computer program product, which improve the data transmission efficiency between different computing devices in a device interconnection system.

[0005] To achieve the above objectives, the present application provides a device interconnection system, comprising a processor and multiple computing devices, wherein the processor is connected to a processor memory, the computing devices are connected to computing device memories, and the processor and the multiple computing devices are connected via a bus that complies with a preset protocol;

[0006] The computing device includes a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port;

[0007] The processor memory and the multiple computing device memories are addressed in a unified addressing manner. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0008] The computing device includes a first target port and a second target port. The computing device receives data sent by other computing devices through the first target port, and sends data to other computing devices through the second target port.

[0009] The processor includes a processor core, a port module, and a first memory controller that are interconnected. The processor is connected to the processor memory through the first memory controller. The port module includes a plurality of first ports that comply with a preset protocol.

[0010] The computing device includes a second port that complies with a preset protocol, the target port, an address translation unit, a computing unit, and a second memory controller, the address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller, and the computing device is connected to the computing device memory through the second memory controller;

[0011] The processor is connected to second ports of different computing devices respectively through the plurality of first ports.

[0012] The processor further includes a unified addressing management module, and the unified addressing management module is used to uniformly address the processor memory and the memories of the plurality of computing devices;

[0013] The computing device also includes a memory decoder, the computing unit is connected to the second port and the target port through the memory decoder, the second memory controller is connected to the computing unit, the second port and the target port through the memory decoder, and the memory decoder is used to perform address mapping between unified addressing and the internal address space of the computing device according to the usage scenario.

[0014] The memory decoder in the computing device is specifically used for:

[0015] When the processor accesses the computing device memory of the current computing device, converting the unified addressing into an address on the internal bus of the device;

[0016] When a computing unit of the current computing device accesses a computing device memory of the current computing device, converting the unified addressing into an address on an internal bus of the device;

[0017] When a computing unit of the current computing device accesses the processor memory, no address translation is performed;

[0018] When a computing unit of a current computing device accesses a computing device memory of another computing device, no address translation is performed;

[0019] When a computing unit of another computing device accesses the computing device memory of the current computing device, the unified addressing is converted into an address on the internal bus of the device.

[0020] Wherein, the computing device is a field programmable gate array.

[0021] The i-1th computing device is connected to the i-th computing device, 1<i≤N, and N is the number of computing devices included in the device interconnection system.

[0022] The computing device includes a first target port and a second target port, the second target port of the i-1th computing device is connected to the first target port of the i-th computing device, and the i-1th computing device sends data to the i-th computing device through the second target port of the i-1th computing device and the first target port of the i-th computing device.

[0023] Wherein, the processor is used to: write input data into the processor memory;

[0024] The first computing device is configured to obtain input data from the processor memory via a bus conforming to a preset protocol, perform calculations of its corresponding hidden layer on the obtained data to obtain result data, and store the result data in its corresponding computing device memory;

[0025] The i-th computing device is configured to: obtain result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, perform calculation of its corresponding hidden layer on the obtained data to obtain result data, and store the result data in the corresponding computing device memory;

[0026] The Nth computing device writes the result data obtained by the calculation as output data into the processor memory via a bus that complies with a preset protocol.

[0027] To achieve the above-mentioned objectives, the present application provides a data processing method, which is applied to a computing device in a device interconnection system, wherein the device interconnection system includes a processor and multiple computing devices, wherein the processor is connected to a processor memory, and the computing devices are connected to a computing device memory. The processor and the multiple computing devices are connected via a bus that conforms to a preset protocol, and the computing devices include a target port, and the i-1th computing device is connected to the i-th computing device via the target port, where 1<i≤N, and N is the number of computing devices included in the device interconnection system;

[0028] The method comprises:

[0029] The first computing device obtains input data from the processor memory via a bus that complies with a preset protocol, performs calculations of its corresponding hidden layer on the obtained data to obtain result data, and stores the result data in its corresponding computing device memory;

[0030] The i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs calculation of its own corresponding hidden layer on the obtained data to obtain the result data, and stores the result data in the corresponding computing device memory;

[0031] The Nth computing device writes the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0032] Wherein, the processor memory and the memories of the plurality of computing devices are addressed in a unified addressing manner;

[0033] The method further comprises:

[0034] Obtaining an address mapping table; wherein the address mapping table includes a correspondence between a starting source address and a starting destination address in different usage scenarios;

[0035] Matching a corresponding target usage scenario in the address mapping table according to a target starting source address of the data access request;

[0036] The target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table.

[0037] Wherein, if the target usage scenario is that the processor accesses the computing device memory of the current computing device, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes:

[0038] The target starting source address is converted into an address on the internal bus of the device as the target starting destination address.

[0039] Wherein, if the target usage scenario is that a computing unit of the current computing device accesses a computing device memory of the current computing device, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes:

[0040] The target starting source address is converted into an address on the internal bus of the device as the target starting destination address.

[0041] If the target usage scenario is that a computing unit of the current computing device accesses the processor memory, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes:

[0042] The target starting source address is directly used as the target starting destination address.

[0043] If the target usage scenario is that a computing unit of the current computing device accesses a computing device memory of another computing device, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes:

[0044] The target starting source address is directly used as the target starting destination address.

[0045] If the target usage scenario is that a computing unit of another computing device accesses a computing device memory of the current computing device, determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table includes:

[0046] The target starting source address is converted into an address on the internal bus of the device as the target starting destination address.

[0047] To achieve the above-mentioned objectives, the present application provides a data processing apparatus, which is applied to a computing device in a device interconnection system. The device interconnection system includes a processor and multiple computing devices. The processor is connected to a processor memory, and the computing devices are connected to a computing device memory. The processor and the multiple computing devices are connected via a bus that conforms to a preset protocol. The computing devices include a target port, and the i-1th computing device is connected to the i-th computing device via the target port, where 1 < i ≤ N, and N is the number of computing devices included in the device interconnection system.

[0048] an acquisition unit, configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or to acquire result data calculated by other computing devices from other computing devices via the target port;

[0049] A computing unit, configured to perform calculations on the acquired data at its corresponding hidden layer to obtain result data and store the result data in the memory of its corresponding computing device;

[0050] The output unit is used to write the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0051] To achieve the above objectives, the present application provides an electronic device, comprising:

[0052] memory for storing computer programs;

[0053] A processor is used to implement the steps of the above-mentioned data processing method when executing the computer program.

[0054] To achieve the above objectives, the present application provides a non-volatile storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above data processing method are implemented.

[0055] To achieve the above objectives, the present application provides a computer program product, including a computer program, which implements the steps of the above data processing method when executed by a processor.

[0056] From the above scheme, it can be seen that a device interconnection system provided by the present application includes a processor and multiple computing devices, the processor is connected to the processor memory, the computing device is connected to the computing device memory, and the processor and the multiple computing devices are connected through a bus that complies with a preset protocol; the computing device includes a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port; the processor memory and the multiple computing device memories are addressed in a unified addressing manner, and when the computing device memory is accessed, the corresponding computing device performs address mapping between the unified addressing and the internal address space of the computing device.

[0057] This application adds a target port to the computing device, and different computing devices are directly connected through the target port. Different computing devices transmit data directly through the target port, without passing through a bus that complies with a preset protocol and connects the processor, which reduces the transmission pressure of the bus and improves the data transmission efficiency between different computing devices. In addition, this application uses a unified addressing method to address the processor memory and the computing device memory, and the computing device performs address mapping between the unified addressing and the internal address space of the computing device, which simplifies the address access method and data transmission method. This application also discloses a data processing method, an apparatus, an electronic device, a non-volatile storage medium, and a computer program product, which can also achieve the above-mentioned technical effects.

[0058] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. The drawings are used to provide a further understanding of the present disclosure and constitute part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation of the present disclosure. In the drawings:

[0060] Figure 1 This is an architectural diagram of a device interconnection system in the related art;

[0061] Figure 2 A schematic diagram of a computing process of a device interconnection system in an application scenario in the related art;

[0062] Figure 3 A schematic diagram of a connection between a processor and a single computing device in a device interconnection system in the related art;

[0063] Figure 4 A flowchart of the overall operation of the device interconnection system in the related art;

[0064] Figure 5 is an architecture diagram of a device interconnection system according to an exemplary embodiment;

[0065] Figure 6 FIG1 is a schematic diagram showing a connection between a single computing device and a processor according to an exemplary embodiment;

[0066] Figure 7 is an architecture diagram of another device interconnection system according to an exemplary embodiment;

[0067] Figure 8 An architectural diagram of a device interconnection system in an application scenario provided by this application;

[0068] Figure 9 is a calculation flow chart of a calculation unit according to an exemplary embodiment;

[0069] Figure 10 FIG1 is a schematic diagram showing another connection between a single computing device and a processor according to an exemplary embodiment;

[0070] Figure 11 The present invention is an overall flow chart showing the operation of a device interconnection system according to an exemplary embodiment;

[0071] Figure 12 is a flow chart of a data processing method according to an exemplary embodiment;

[0072] Figure 13 is a structural diagram of a data processing device according to an exemplary embodiment;

[0073] Figure 14 The figure is a structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. In addition, in the embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0075] In related technologies, the architecture diagram of the device interconnection system is as follows: Figure 1 As shown, the processor is connected to the processor memory. The processor and multiple computing devices are connected via a bus that conforms to a preset protocol. The preset protocol may be the PCIe protocol, meaning that multiple computing devices are plugged into the host's PCIe slots. The processor is responsible for launching the AI ​​computing program and scheduling different computing devices to perform calculations. The processor places the source data to be calculated in the host memory and then notifies the computing devices to read it. The computing devices read the source data via a bus that conforms to the preset protocol, perform the calculations, and then write the results to the processor memory or other computing devices via the bus that conforms to the preset protocol.

[0076] In actual computing scenarios, computing tasks are performed by computing devices, and various data are stored in the processor memory or the computing device's internal memory. Within the same host, data is transferred between various devices and memory via a bus that conforms to a preset protocol (such as the PCIe bus). Figure 2 The following figure shows a calculation process in an application scenario, including the following steps:

[0077] ①The processor writes the input data to the processor memory.

[0078] ② Computing device 1 reads input data from the processor memory through a bus that complies with the preset protocol, performs operations (convolution, pooling, etc.) on hidden layer 1, and obtains the result data of hidden layer 1.

[0079] ③ Computing device 2 reads the data of hidden layer 1 from computing device 1 through a bus that complies with the preset protocol, performs operations (convolution, pooling, etc.) on hidden layer 2, and obtains the result data of hidden layer 2.

[0080] ④ Computing device 3 reads the data of hidden layer 2 from computing device 2 through a bus that complies with the preset protocol, performs operations (convolution, pooling, etc.) on hidden layer 3, and obtains the result data of hidden layer 3.

[0081] ⑤ The computing device 4 reads the data of the hidden layer 3 from the computing device 3 through a bus that complies with the preset protocol, performs the final operation, and obtains the final result data.

[0082] ⑥ The computing device 4 writes the result data to the processor memory via a bus that complies with the preset protocol.

[0083] In the above scheme, the computation load is distributed to multiple computing devices, and pipeline operations can be performed. For example, the processor can continuously provide new input data. While computing device 1 is performing hidden layer 1 operations on the current batch of data, computing device 2 is performing hidden layer 2 operations on the previous batch of data. And so on, at a certain point in time, Figure 2 The computing scenario in the example can calculate 4 batches of data at the same time, making full use of the computing power of the computing device.

[0084] However, this approach encounters a problem: nearly every data transfer step (except step 1) requires the use of the pre-defined protocol bus. As the entire process becomes streamlined, it's possible for four computing devices to simultaneously request access to the pre-defined protocol bus. This creates a bottleneck for the entire system. For example, one computing device may need to wait for data transfers from the other three devices before it can begin processing, significantly slowing down the overall system's computing speed.

[0085] Take the connection between the processor and a single computing device as an example, Figure 3 As shown in the figure, computing devices generally provide at least two base address registers (BARs) for the processor to access. One is the VRAM (Video Random Access Memory) BAR. After the processor maps the address to this BAR, it can directly read and write the contents of the computing device's memory through address access. This is referred to as the computing device memory, which includes the page table. The other is the register BAR. After the processor maps the address to this BAR, it can use it to read and write various configurations in the computing device and operate various functions, such as initiating data transfers, reading interrupt status, and restarting the device.

[0086] A computing device contains multiple functional modules. The artificial intelligence (AI) computing unit is responsible for performing specific AI calculations, the communication component (MailBox) assists other modules in communicating with the processor, the microcontroller unit (MCU) handles functions such as restart and power management, the DMA (Direct Memory Access) data transfer module accesses processor memory via DMA, and the address translation unit helps other modules convert virtual addresses into physical addresses for accessing computing device memory or processor memory. The computing device also includes an interrupt management module and a module that assists the processor in accessing VRAM.

[0087] The processor includes a virtual memory space, which maps video random access memory (VRAM) and registers. Software running on the processor can be divided into three main components. The Kernel Mode Driver (KMD) has the highest system privileges. The Linux DRM driver is responsible for memory management, the compute device driver handles initialization tasks such as bar mapping and firmware loading, and the IOCTL driver assists the User Mode Driver (UMD) with address translation, allocating VRAM address segments for various functions. It also creates pages for the compute device and writes them to VRAM, enabling the compute unit and MCU in the compute device to access VRAM or host memory. The KMD also handles error interrupts. The UMD serves as an intermediate layer. The runtime library provides application programming interfaces (APIs) and device management. The compute module is responsible for device management, data stream creation (queues), computational model deployment, and computation initiation. The address mapping module maps memory to the compute device. Applications, at the top layer, directly call the standard Glibc dynamic library and the APIs provided by the UMD to perform user-defined computational tasks, including AI computing applications.

[0088] Figure 4The simple workflow of the relevant technical solution is demonstrated, including system startup, initialization, and calculation. The initialization process includes: loading the KMD, which performs basic initialization of the computing device, such as mapping the bar and loading firmware; launching the application; calling the UMD interfaces such as DeviceInit (device initialization), SetDevice (device setting), CreateEngine (engine creation), CreateContext (context creation), StreamCreate (stream creation), and DeployNetwork (network deployment); and allocating buffers in both processor memory and VRAM to store source and result data. The calculation process includes: writing source data to processor memory; initiating calculations (writing registers to notify the computing device to read source data from processor memory into VRAM and perform calculations); waiting for the computing device to complete the calculations and writing the results from VRAM to the result data buffer in processor memory; and determining whether the calculations are complete. If so, the system exits; otherwise, the system returns to writing source data to processor memory. As can be seen, each initialization process takes a long time, but is executed only a limited number of times, so it has little impact on overall computing performance. However, the time consumed by each calculation process has a significant impact on overall computing performance, as it is typically executed many times.

[0089] In the above-mentioned device interconnection system, whether it is data transmission between the processor and the computing device, or data transmission between different computing devices, it must be carried out through a bus that complies with the preset protocol, resulting in high transmission pressure on the bus and low data transmission efficiency between different computing devices.

[0090] Therefore, the present application adds a target port to the computing device, and different computing devices are directly connected through the target port. Data is transmitted directly between different computing devices through the target port without passing through a bus that complies with a preset protocol and connects the processor, thereby reducing the transmission pressure of the bus and improving the data transmission efficiency between different computing devices.

[0091] This embodiment discloses a device interconnection system, such as Figure 5 As shown, it includes a processor and multiple computing devices, the processor is connected to the processor memory, the computing devices are connected to the computing device memory, and the processor and the multiple computing devices are connected via a bus that complies with a preset protocol;

[0092] The computing device includes a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port;

[0093] The processor memory and the multiple computing device memories are addressed in a unified addressing manner. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0094] The computing device in this embodiment may be a GPU (Graphics Processing Unit). Preferably, the computing device may be an FPGA (Field-Programmable Gate Array). FPGAs offer greater implementation flexibility compared to GPUs. The processor and multiple computing devices are connected via a bus conforming to a preset protocol, which may be a PCIe bus. The processor is connected to the processor memory, and each computing device is connected to its own computing device memory. In this embodiment, the processor memory and computing device memory may be DDR (Double Data Rate Synchronous Dynamic Random-Access Memory).

[0095] In this embodiment, a new target port is added to the computing device, and the target ports of different computing devices are directly connected through SUB (Super United Bus, a customized consistent interconnect bus). Different computing devices can directly transmit data through the target port via the SUB bus without passing through a bus that complies with a preset protocol and is connected to the processor, thereby reducing the transmission pressure of the bus and improving the data transmission efficiency between different computing devices.

[0096] As a preferred embodiment, the computing device includes a first target port and a second target port, the computing device receives data sent by other computing devices through the first target port, and the computing device sends data to other computing devices through the second target port.

[0097] In a specific implementation, two target ports can be set on each computing device, namely a first target port and a second target port. The first target port is used to receive data, and the second target port is used to send data, thereby realizing port isolation between receiving data and sending data, and being able to receive and send data at the same time, further improving the data transmission efficiency between different computing devices.

[0098] As a feasible implementation method, the processor includes an interconnected processor core, a port module, and a first memory controller. The processor is connected to the processor memory through the first memory controller. The port module includes multiple first ports that comply with a preset protocol. The computing device includes a second port that complies with a preset protocol, the target port, an address translation unit, a computing unit, and a second memory controller. The address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller. The computing device is connected to the computing device memory through the second memory controller. The processor is connected to the second ports of different computing devices through multiple first ports.

[0099] In a specific implementation, for a single computing device, the connection method between it and the processor is as follows: Figure 6 As shown. The processor includes a processor core, a port module, and a first memory controller, which are interconnected. The port module includes multiple first ports that comply with a preset protocol, which are used to connect to multiple different computing devices respectively. The first memory controller is connected to the processor memory and is used to realize reading and writing of data in the processor memory. The computing device includes a second port that complies with a preset protocol, a target port, a computing unit, and a second memory controller. The second port is connected to the corresponding first port in the processor and is used to transmit data with the processor. The target port is connected to other computing devices and is used to transmit data with other computing devices. The address conversion unit is connected to the computing unit, the second port, the target port, and the second memory controller. The address conversion unit is used to realize conversion between virtual addresses and physical addresses. The computing unit is used to perform data calculations using the received data. The second memory controller and other components can be connected through an internal bus interface. The second memory controller is connected to the computing device memory and is used to realize reading and writing of data in the computing device memory.

[0100] It is understandable that the processor memory and computing device memory belong to different internal buses, and their addresses are independent of each other, or rather, belong to different address spaces. However, during the computation process, data stored in these memories must be transferred between them. To simplify data transmission, this embodiment employs global unified addressing, which assigns non-overlapping addresses within the same address space to data stored in the processor memory and data stored in the computing device memory. This simplifies address access and data transmission when writing processor applications, the computing device's computing unit, and configuring programs running in the address translation unit.

[0101] As a preferred embodiment, the processor also includes a unified addressing management module, which is used to uniformly address the processor memory and the memories of multiple computing devices; the computing device also includes a memory decoder, the computing unit is connected to the second port and the target port through the memory decoder, and the second memory controller is connected to the computing unit, the second port and the target port through the memory decoder, and the memory decoder is used to perform address mapping between unified addressing and the internal address space of the computing device according to the usage scenario.

[0102] In a specific implementation, a memory decoder is added inside the computing device, between the address translation unit and the internal bus interface. Its main function is to perform address mapping between the processor address space and the computing device address space, as well as between the address spaces of different computing devices. At the same time, an address mapping table is added to the computing device memory, including the correspondence between the starting source address and the starting destination address in different usage scenarios. The memory decoder performs address mapping based on the address mapping table. In the processor, a unified addressing management module is added to the user mode driver, which calls the interface provided by the memory decoder configuration driver, generates an address mapping table, and configures the address of the address mapping table to the memory decoder.

[0103] As a feasible implementation manner, the memory decoder in the computing device is specifically used to: when the processor accesses the computing device memory of the current computing device, convert the unified addressing into an address on the device internal bus; when the computing unit of the current computing device accesses the computing device memory of the current computing device, convert the unified addressing into an address on the device internal bus; when the computing unit of the current computing device accesses the computing device memory of the current computing device, no address conversion is performed; when the computing unit of the current computing device accesses the computing device memory of other computing devices, no address conversion is performed; when the computing units of other computing devices access the computing device memory of the current computing device, convert the unified addressing into an address on the device internal bus.

[0104] In specific implementations, the memory decoder is responsible for handling address translation between address spaces and determining the access port in the following usage scenarios:

[0105] ① When the processor accesses the memory of the computing device, it converts the unified address into the address on the internal bus of the device and accesses the internal bus interface of the device.

[0106] ② When the computing unit of the current computing device accesses the computing device memory of the current computing device, the unified address is converted into an address on the internal bus of the device, and the internal bus interface of the device is accessed.

[0107] ③ When the computing unit of the current computing device accesses the processor memory, it does not perform any address conversion and accesses the port that complies with the preset protocol.

[0108] ④ When the computing unit of the current computing device accesses the computing device memory of other computing devices, it accesses the target port without performing any address conversion.

[0109] ⑤ When the computing unit of other computing devices accesses the computing device memory of the current computing device (through the SUB bus), the unified address is converted into the address on the internal bus of the device and the internal bus interface of the device is accessed.

[0110] The processor software writes the address mapping method into the address mapping table, and then configures the address of the address mapping table itself to the computing device by writing registers. After obtaining the address of the address mapping table, the computing device reads the contents of the address mapping table and performs address translation, access port selection, and other configurations (such as whether to enable caching) based on the start and destination addresses in the table entries. It is important to note that the number of table entries does not necessarily match the number of usage scenarios; the same usage scenario can have multiple table entries. The source addresses of all table entries cannot overlap, so the source address is used to index the table entries.

[0111] For example, the address mapping table is shown in Table 1:

[0112] Table 1

[0113]

[0114] It should be noted that not all addresses require an entry in Table 1. Instead, a base address plus offset method can be used. For example, the address mapping table contains an entry with a starting source address of 0x00010000, an address length of 0x00001000, and a starting destination address of 0. When an address access is made to 0x00010800, it will be hit by the above entry because it falls within the range of 0x00010000 to 0x00011000. The offset of this address relative to the starting source address is 0x800, so the destination address is the starting destination address (0) plus 0x800.

[0115] It can be seen that the unified addressing of the memory decoder plus the address mapping table can simplify the memory management method, making it easier for software engineers to make the processor program and the program running in the computing unit of the computing device work together when writing the two, thereby reducing the possibility of problems.

[0116] The embodiments of the present application add a new target port to the computing device, allowing different computing devices to be directly connected through the target port. Data can be directly transmitted between different computing devices through the target port without having to pass through a bus that connects the processor and complies with a preset protocol. This reduces the transmission pressure on the bus and improves the efficiency of data transmission between different computing devices. Furthermore, the embodiments of the present application use a unified addressing method to address the processor memory and the computing device memory. The computing device performs address mapping between the unified addressing and the internal address space of the computing device, simplifying the address access method and data transmission method.

[0117] This embodiment discloses a device interconnection system, such as Figure 7 As shown, it includes a processor and multiple computing devices, the processor is connected to the processor memory, the computing devices are connected to the computing device memory, and the processor and the multiple computing devices are connected via a bus that complies with a preset protocol;

[0118] The computing device includes a target port, and the i-1th computing device is connected to the i-th computing device through the target port, 1<i≤N, N is the number of computing devices included in the device interconnection system;

[0119] The processor memory and the multiple computing device memories are addressed in a unified addressing manner. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0120] In this embodiment, multiple computing devices are serially connected through target ports. For a single computing device, it only needs to receive data sent by one other computing device and only needs to send data to one other computing device, which reduces the amount of data transmitted between different computing devices, reduces the transmission pressure of the SUB bus between the target ports, and further improves the data transmission efficiency between computing devices.

[0121] As a preferred embodiment, the computing device includes a first target port and a second target port, the second target port of the i-1th computing device is connected to the first target port of the i-th computing device, and the i-1th computing device sends data to the i-th computing device through the second target port of the i-1th computing device and the first target port of the i-th computing device.

[0122] In a specific implementation, two target ports can be set on each computing device, namely a first target port and a second target port. The first target port is used to receive data, and the second target port is used to send data, thereby realizing port isolation between receiving data and sending data, and being able to receive and send data at the same time, further improving the data transmission efficiency between different computing devices.

[0123] The following describes an application scenario of this embodiment. Figure 8 As shown, target port 1 of computing device 1 is connected to target port 0 of computing device 2, target port 1 of computing device 2 is connected to target port 0 of computing device 3, target port 1 of computing device 3 is connected to target port 0 of computing device 4, and target port 0 of computing device 1 and target port 1 of computing device 4 are left vacant.

[0124] As a feasible implementation method, the processor is used to: write input data into the processor memory; the first computing device is used to: obtain input data from the processor memory through a bus that complies with a preset protocol, perform calculations of its own corresponding hidden layer on the obtained data to obtain result data, and store the result data in its own corresponding computing device memory; the i-th computing device is used to: obtain result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, perform calculations of its own corresponding hidden layer on the obtained data to obtain result data, and store the result data in its own corresponding computing device memory; wherein, the N-th computing device writes the calculated result data as output data into the processor memory through a bus that complies with the preset protocol.

[0125] The coordinated calculation process of each computing device is as follows:

[0126] ①The processor writes the input data to the processor memory.

[0127] ② Computing device 1 reads input data from the processor memory through a bus that complies with the preset protocol, performs operations (convolution, pooling, etc.) on hidden layer 1, and obtains the result data of hidden layer 1.

[0128] ③ Computing device 2 reads the data of hidden layer 1 from computing device 1 through the SUB bus, performs operations (such as convolution and pooling) on ​​hidden layer 2, and obtains the result data of hidden layer 2.

[0129] ④ Computing device 3 reads the data of hidden layer 2 from computing device 2 via the SUB bus, performs operations (convolution, pooling, etc.) on hidden layer 3, and obtains the result data of hidden layer 3.

[0130] ⑤ The computing device 4 reads the data of the hidden layer 3 from the computing device 3 via the SUB bus, performs the final operation, and obtains the final result data.

[0131] ⑥ The computing device 4 writes the result data to the processor memory via a bus that complies with the preset protocol.

[0132] The calculation process of the calculation unit in each computing device is as follows Figure 9As shown in the figure, the circles represent data, and the arrows represent the relationships between the data and the computational process. The raw data is first stored in the input layer. After being calculated in multiple hidden layers, the final results are stored in the output layer. The hidden layers can be convolutional layers, pooling layers, fully connected layers, or any combination of other computational methods.

[0133] Take the connection between the processor and a single computing device as an example, Figure 10 As shown, computing devices typically provide at least two base address registers (BARs) for the processor to access. One is the VRAM (Video Random Access Memory) BAR. After the processor maps the address to this BAR, it can directly read and write the contents of the computing device's memory through address access. This is referred to as the computing device memory, which includes the page table and address mapping table. The other is the register BAR. After the processor maps the address to this BAR, it can use it to read and write various configurations in the computing device and operate various functions, such as initiating data transfers, reading interrupt status, and restarting the device.

[0134] A computing device contains multiple functional modules. The artificial intelligence (AI) computing unit is responsible for performing specific AI calculations, the communication component (MailBox) facilitates communication between other modules and the processor, the microcontroller unit (MCU) handles functions such as restarting and power management, the DMA (Direct Memory Access) data transfer module accesses processor memory via DMA, and the address translation unit helps other modules convert virtual addresses into physical addresses for accessing computing device memory or processor memory. The computing device also includes an interrupt management module and a module for assisting the processor in accessing VRAM. The computing device also includes a memory decoder, which maps addresses between the processor address space and the computing device address space, as well as between the address spaces of different computing devices. The target port control module controls the target port for data transmission between different computing devices.

[0135] The processor includes a virtual memory space that maps video random access memory (VRAM) and registers. Software running on the processor can be divided into three main parts. The KMD (Keeper-Modified Device) has the highest system privileges. The Linux DRM driver is responsible for memory management, the compute device driver handles initialization tasks such as bar mapping and firmware loading, and the IOCTL driver assists the UMD with address translation, allocating VRAM address segments for various functions, creating pages for the compute device, and writing to VRAM to facilitate access to VRAM or host memory by the compute unit and MCU within the compute device. The memory decoder configuration driver assists the UMD with configuring the memory decoder and related address mapping tables. The KMD also handles error interrupts and other tasks. The UMD serves as an intermediary layer. The runtime library provides APIs and device management to applications, while the compute module manages device management, creates data streams (queues), deploys computational models, and initiates computations. The address mapping module maps memory to the compute device. The unified addressing management module calls the interfaces provided by the memory decoder configuration driver to generate address mapping tables and assign addresses from the address mapping tables to the memory decoder. Applications, located at the top layer, directly call the standard Glibc dynamic library and APIs provided by the UMD to perform user-defined computational tasks, including AI computing applications.

[0136] The overall flow chart of the equipment interconnection system operation is as follows Figure 11 As shown, the system starts, initializes, and computes. The initialization process includes loading the KMD, which performs basic initialization on the compute device, such as mapping the bar and loading firmware. Applications are launched, and the UMD interfaces, such as DeviceInit (device initialization), SetDevice (device setup), CreateEngine (engine creation), CreateContext (context creation), StreamCreate (stream creation), and DeployNetwork (network deployment), are called. Buffers for storing source and result data are allocated in both the processor and compute device memory, addresses are created, and register configurations are written to the compute device. The compute process includes writing source data to the processor memory, initiating computations on all compute devices sequentially (i.e., writing registers to notify the compute device to read source data from the processor memory or other compute device memory and perform computations), waiting for the compute device to complete computation, and writing the result from its own compute device memory to the result data buffer (cache) of the other compute devices or the processor memory. The computation is then determined to be complete. If so, the system exits; otherwise, the system returns to the step of writing source data to the processor memory.

[0137] It can be seen that in this embodiment, multiple computing devices are serially connected through the target port, and each computing device implements a streamlined computing task. Data transmission between adjacent computing devices does not need to pass through the bus that connects the processor and complies with the preset protocol, which reduces the transmission pressure of the bus and improves the data transmission efficiency between adjacent computing devices.

[0138] An embodiment of the present application discloses a data processing method, which is applied to a computing device in a device interconnection system. The device interconnection system includes a processor and multiple computing devices. The processor is connected to a processor memory, and the computing devices are connected to a computing device memory. The processor and the multiple computing devices are connected via a bus that complies with a preset protocol. The computing devices include a target port, and the i-1th computing device is connected to the i-th computing device via the target port, where 1<i≤N, and N is the number of computing devices included in the device interconnection system.

[0139] See also Figure 12 , according to a flowchart of a data processing method shown in an exemplary embodiment, such as Figure 12 Shown, including:

[0140] S101: The first computing device obtains input data from the processor memory via a bus that complies with a preset protocol, performs calculations on the obtained data at its corresponding hidden layer to obtain result data, and stores the result data in the memory of the computing device corresponding to the first computing device;

[0141] S102: The i-th computing device obtains result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs calculation of its own corresponding hidden layer on the obtained data to obtain result data, and stores the result data in the corresponding computing device memory;

[0142] S103: The Nth computing device writes the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0143] In a specific implementation, the first computing device obtains input data from the processor memory via a bus that complies with a preset protocol, uses the computing unit therein to perform calculations of its own corresponding hidden layer on the obtained data to obtain result data, and stores the result data in the memory of the computing device corresponding to itself. The hidden layer of the computing unit can be any one or a combination of convolutional layers, pooling layers, fully connected layers, or other computing methods. The first computing device sends the calculated result data to the first target port of the second computing device via its own second target port, and the second computing device uses the computing unit therein to perform calculations of its own corresponding hidden layer on the obtained data to obtain result data, and stores the result data in the memory of the computing device corresponding to itself. This process is repeated until the Nth computing device obtains the result data and writes it as output data to the processor memory via a bus that complies with a preset protocol.

[0144] It can be seen that in this embodiment, multiple computing devices are serially connected through the target port, and each computing device implements a streamlined computing task. Data transmission between adjacent computing devices does not need to pass through the bus that connects the processor and complies with the preset protocol, which reduces the transmission pressure of the bus and improves the data transmission efficiency between adjacent computing devices.

[0145] On the basis of the above embodiments, as a preferred implementation mode, the processor memory and the multiple computing device memories are addressed in a unified addressing manner; the method further includes: obtaining an address mapping table; wherein the address mapping table includes the correspondence between the starting source address and the starting destination address under different usage scenarios; matching the corresponding target usage scenario in the address mapping table according to the target starting source address of the data access request; determining the target starting destination address corresponding to the target starting source address according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table.

[0146] In practice, global unified addressing is used, assigning non-overlapping addresses within the same address space to data stored in the processor memory and the computing device memory. This simplifies address access and data transfer when writing processor applications, the computing unit of the computing device, and configuring programs running in the address translation unit. The processor software writes the address mapping method into an address mapping table, including the correspondence between the starting source address and the starting destination address in different usage scenarios. The address of the address mapping table itself is then configured in the computing device by writing registers. After obtaining the address of the address mapping table, the computing device reads the contents of the address mapping table and performs address translation, access port selection, and other configurations (such as whether to enable cache) based on the starting and destination addresses in the table entry.

[0147] As a feasible implementation method, if the target usage scenario is that the processor accesses the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined based on the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table, including: converting the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0148] In a specific implementation, when the processor accesses the computing device's memory, it converts the unified addressing into an address on the device's internal bus and accesses the device's internal bus interface. This usage scenario can be applied to the step of "the first computing device obtains input data from the processor's memory via a bus that complies with a preset protocol."

[0149] As a feasible implementation method, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: converting the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0150] In a specific implementation, when the computing unit of the current computing device accesses the computing device memory of the current computing device, the unified address is converted into an address on the device's internal bus and the internal bus interface of the device is accessed. This usage scenario can be applied to the step of "the computing device storing the calculation result in its corresponding computing device memory."

[0151] As a feasible implementation method, if the target usage scenario is that the computing unit of the current computing device accesses the processor memory, then the target starting destination address corresponding to the target starting source address is determined based on the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: directly using the target starting source address as the target starting destination address.

[0152] In a specific implementation, when the computing unit of the current computing device accesses the processor memory, it does not perform any address translation and accesses the port that complies with the preset protocol. This usage scenario can be applied to the step where "the Nth computing device writes the calculated result data as output data to the processor memory via a bus that complies with the preset protocol."

[0153] As a feasible implementation method, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of other computing devices, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including: directly using the target starting source address as the target starting destination address.

[0154] In a specific implementation, when the computing unit of the current computing device accesses the computing device memory of another computing device, it accesses the target port without performing any address translation. This usage scenario can be applied to the step of "the i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port."

[0155] As a feasible implementation method, if the target usage scenario is that the computing unit of other computing devices accesses the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table, including: converting the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0156] In a specific implementation, when a computing unit of another computing device accesses the computing device memory of the current computing device (via the SUB bus), the unified address is converted into an address on the device's internal bus, and the internal bus interface is accessed. This usage scenario can be applied to the step of "the i-th computing device retrieves the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device via the target port."

[0157] It can be seen that the unified addressing of the memory decoder plus the address mapping table can simplify the memory management method, making it easier for software engineers to make the processor program and the program running in the computing unit of the computing device work together when writing the two, thereby reducing the possibility of problems.

[0158] The following is an introduction to a data processing device provided in an embodiment of the present application. The data processing device described below and the data processing method described above can be referenced with each other. The data processing device provided in this embodiment is applied to a computing device in a device interconnection system, wherein the device interconnection system includes a processor and multiple computing devices, wherein the processor is connected to a processor memory, the computing device is connected to a computing device memory, the processor and the multiple computing devices are connected via a bus that complies with a preset protocol, the computing device includes a target port, the i-1th computing device is connected to the i-th computing device via the target port, 1<i≤N, and N is the number of computing devices included in the device interconnection system.

[0159] See also Figure 13 , a structural diagram of a data processing device according to an exemplary embodiment is shown as follows. Figure 13 Shown, including:

[0160] An acquisition unit 100 is configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or to acquire result data calculated by other computing devices from other computing devices via the target port;

[0161] The computing unit 200 is configured to perform calculations on the acquired data at its corresponding hidden layer to obtain result data and store the result data in the memory of its corresponding computing device;

[0162] The output unit 300 is used to write the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

[0163] It can be seen that in this embodiment, multiple computing devices are serially connected through the target port, and each computing device implements a streamlined computing task. Data transmission between adjacent computing devices does not need to pass through the bus that connects the processor and complies with the preset protocol, which reduces the transmission pressure of the bus and improves the data transmission efficiency between adjacent computing devices.

[0164] Based on the above embodiment, as a preferred implementation, the processor memory and the multiple computing device memories are addressed in a unified addressing manner;

[0165] The device further comprises:

[0166] An address mapping unit is used to obtain an address mapping table; wherein the address mapping table includes a correspondence between a starting source address and a starting destination address under different usage scenarios; the corresponding target usage scenario is matched in the address mapping table according to the target starting source address of the data access request; and the target starting destination address corresponding to the target starting source address is determined according to the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table.

[0167] Based on the above embodiments, as a preferred implementation, if the target usage scenario is that the processor accesses the computing device memory of the current computing device, the address mapping unit is specifically used to: convert the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0168] Based on the above embodiments, as a preferred implementation, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of the current computing device, the address mapping unit is specifically used to: convert the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0169] Based on the above embodiment, as a preferred implementation, if the target usage scenario is that the computing unit of the current computing device accesses the processor memory, the address mapping unit is specifically used to: directly use the target starting source address as the target starting destination address.

[0170] Based on the above embodiments, as a preferred implementation, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of other computing devices, the address mapping unit is specifically used to: directly use the target starting source address as the target starting destination address.

[0171] Based on the above embodiments, as a preferred implementation, if the target usage scenario is that the computing unit of another computing device accesses the computing device memory of the current computing device, the address mapping unit is specifically used to: convert the target starting source address into an address on the internal bus of the device as the target starting destination address.

[0172] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0173] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiment of the present application, the embodiment of the present application further provides an electronic device, Figure 14 FIG. 1 is a structural diagram of an electronic device according to an exemplary embodiment. Figure 14As shown, the electronic equipment includes:

[0174] Communication interface 1, capable of exchanging information with other devices such as network devices;

[0175] The processor 2 is connected to the communication interface 1 to implement information exchange with other devices and is used to execute the data processing method provided by one or more of the above technical solutions when running a computer program. The computer program is stored in the memory 3.

[0176] Of course, in actual application, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 14 Various buses are labeled as bus system 4.

[0177] The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program used to operate on the electronic device.

[0178] It is understood that the memory 3 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a magnetic disk or a magnetic tape. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory 3 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0179] The method disclosed in the above-mentioned embodiment of the present application can be applied to processor 2 or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above-mentioned method can be completed by the integrated logic circuit of the hardware in processor 2 or instructions in the form of software. The above-mentioned processor 2 can be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the above-mentioned method in combination with its hardware.

[0180] When the processor 2 executes the program, the corresponding processes in the various methods of the embodiments of the present application are implemented. For the sake of brevity, they are not repeated here.

[0181] In an exemplary embodiment, the present application further provides a non-volatile storage medium storing a computer program, which can be executed by the processor 2 to complete the steps of the aforementioned method.

[0182] In an exemplary embodiment, the present application further provides a computer program product, including a computer program, which is executed by the processor 2 to complete the steps of the aforementioned method.

[0183] Those skilled in the art will understand that all or part of the steps of the above-mentioned method embodiments can be implemented by hardware related to computer program instructions, and the aforementioned computer program can be stored in a non-volatile storage medium. When the computer program is executed, it executes the steps of the above-mentioned method embodiments. Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a non-volatile storage medium and includes a number of instructions for enabling an electronic device (which can be a personal computer, a server, a network device, etc.) to execute all or part of the methods described in each embodiment of the present application.

[0184] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A device interconnection system, characterized in that: The system comprises a processor and a plurality of computing devices, wherein the processor is connected to a processor memory, the computing devices are connected to a computing device memory, and the processor and the plurality of computing devices are connected via a bus conforming to a preset protocol; The computing device includes a target port, different computing devices are directly connected through the target port, and different computing devices directly transmit data through the target port; The processor memory and the memories of the plurality of computing devices are addressed in a unified addressing manner, and when the memory of the computing device is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device by the corresponding computing device; The (i-1)th computing device is connected to the (i)th computing device, 1 < i ≤ N, N is the number of computing devices included in the device interconnection system, the computing devices include a first target port and a second target port, the second target port of the (i-1)th computing device is connected to the first target port of the (i)th computing device, and the (i-1)th computing device sends data to the (i)th computing device through the second target port of the (i-1)th computing device and the first target port of the (i)th computing device; The processor is used to: write input data into the processor memory; The first computing device is configured to obtain input data from the processor memory via a bus conforming to a preset protocol, perform calculations of its corresponding hidden layer on the obtained data to obtain result data, and store the result data in its corresponding computing device memory; The i-th computing device is configured to: obtain result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, perform calculation of its corresponding hidden layer on the obtained data to obtain result data, and store the result data in the corresponding computing device memory; The Nth computing device writes the result data obtained by the calculation as output data into the processor memory via a bus that complies with a preset protocol.

2. The device interconnection system according to claim 1, characterized in that: The computing device includes a first target port and a second target port. The computing device receives data sent by other computing devices through the first target port, and sends data to other computing devices through the second target port.

3. The device interconnection system according to claim 1, characterized in that: The processor includes a processor core, a port module, and a first memory controller that are interconnected. The processor is connected to the processor memory via the first memory controller. The port module includes a plurality of first ports that comply with a preset protocol. The computing device includes a second port that complies with a preset protocol, the target port, an address translation unit, a computing unit, and a second memory controller, the address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller, and the computing device is connected to the computing device memory through the second memory controller; The processor is connected to second ports of different computing devices respectively through the plurality of first ports.

4. The device interconnection system according to claim 3, characterized in that: The processor further includes a unified addressing management module, the unified addressing management module being configured to uniformly address the processor memory and the memories of the plurality of computing devices; The computing device also includes a memory decoder, the computing unit is connected to the second port and the target port through the memory decoder, the second memory controller is connected to the computing unit, the second port and the target port through the memory decoder, and the memory decoder is used to perform address mapping between unified addressing and the internal address space of the computing device according to the usage scenario.

5. The device interconnection system according to claim 4, characterized in that: The memory decoder in the computing device is specifically used for: When the processor accesses the computing device memory of the current computing device, converting the unified addressing into an address on the internal bus of the device; When a computing unit of the current computing device accesses a computing device memory of the current computing device, converting the unified addressing into an address on an internal bus of the device; When a computing unit of the current computing device accesses the processor memory, no address translation is performed; When a computing unit of a current computing device accesses a computing device memory of another computing device, no address translation is performed; When a computing unit of another computing device accesses the computing device memory of the current computing device, the unified addressing is converted into an address on the internal bus of the device.

6. The device interconnection system according to claim 1, characterized in that: The computing device is a field programmable gate array.

7. A data processing method, characterized in that: A computing device used in a device interconnection system, the device interconnection system comprising a processor and multiple computing devices, the processor being connected to a processor memory, the computing devices being connected to computing device memories, the processor and the multiple computing devices being connected via a bus conforming to a preset protocol, the computing devices comprising a target port, the i-1th computing device being connected to the ith computing device via the target port, 1<i≤N, where N is the number of computing devices included in the device interconnection system; The method comprises: The first computing device obtains input data from the processor memory via a bus that complies with a preset protocol, performs calculations of its corresponding hidden layer on the obtained data to obtain result data, and stores the result data in its corresponding computing device memory; The i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs calculation of its own corresponding hidden layer on the obtained data to obtain the result data, and stores the result data in the corresponding computing device memory; The Nth computing device writes the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

8. The data processing method according to claim 7, characterized in that: The processor memory and the memories of the plurality of computing devices are addressed in a unified addressing manner; The method further comprises: Obtaining an address mapping table; wherein the address mapping table includes a correspondence between a starting source address and a starting destination address in different usage scenarios; Matching a corresponding target usage scenario in the address mapping table according to a target starting source address of the data access request; The target starting destination address corresponding to the target starting source address is determined according to the corresponding relationship between the starting source address and the starting destination address in the target usage scenario in the address mapping table.

9. The data processing method according to claim 8, characterized in that: If the target usage scenario is that the processor accesses a computing device memory of the current computing device, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target starting source address is converted into an address on the internal bus of the device as the target starting destination address.

10. The data processing method according to claim 8, characterized in that: If the target usage scenario is a computing unit of the current computing device accessing a computing device memory of the current computing device, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target starting source address is converted into an address on the internal bus of the device as the target starting destination address.

11. The data processing method according to claim 8, characterized in that: If the target usage scenario is a computing unit of a current computing device accessing the processor memory, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target starting source address is directly used as the target starting destination address.

12. The data processing method according to claim 8, characterized in that: If the target usage scenario is a computing unit of the current computing device accessing a computing device memory of another computing device, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target starting source address is directly used as the target starting destination address.

13. The data processing method according to claim 8, characterized in that: If the target usage scenario is a computing unit of another computing device accessing a computing device memory of the current computing device, determining a target starting destination address corresponding to the target starting source address according to a corresponding relationship between a starting source address and a starting destination address in the target usage scenario in the address mapping table includes: The target starting source address is converted into an address on the internal bus of the device as the target starting destination address.

14. A data processing device, characterized in that: A computing device used in a device interconnection system, the device interconnection system comprising a processor and multiple computing devices, the processor being connected to a processor memory, the computing devices being connected to computing device memories, the processor and the multiple computing devices being connected via a bus conforming to a preset protocol, the computing devices comprising a target port, the i-1th computing device being connected to the ith computing device via the target port, 1<i≤N, where N is the number of computing devices included in the device interconnection system; an acquisition unit, configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or to acquire result data calculated by other computing devices from other computing devices via the target port; A computing unit, configured to perform calculations on the acquired data at its corresponding hidden layer to obtain result data and store the result data in the memory of its corresponding computing device; The output unit is used to write the calculated result data as output data into the processor memory via a bus that complies with a preset protocol.

15. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the data processing method according to any one of claims 7 to 13 when executing the computer program.

16. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, which implements the steps of the data processing method according to any one of claims 7 to 13 when executed.

17. A computer program product, characterized in that The invention comprises a computer program, which implements the steps of the data processing method according to any one of claims 7 to 13 when the computer program is executed.

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