Computing device, method, system, circuit, chip and equipment

Abstract

The embodiment of the invention discloses a computing device, a computing method, a computing system, a computing circuit, a computing chip and computing equipment, which can be used for directly computing a vector in a compression format so as to improve the computing efficiency of the vector in the compression format. The calculation device comprises a position coordinate comparison circuit and a logic operation circuit, the position coordinate comparison circuit is used for comparing the position coordinates of the element values in the first vector with the position coordinates of the element values in the second vector to obtain a coordinate comparison result; and the logical operation circuit is used for performing operation on the first element value and the second element value according to the first comparison result to obtain an operation value and outputting an operation result to the buffer, and the operation result is related to the operation value. Compared with a traditional method that the vector in the compression format needs to be decompressed firstly and then the decompressed vector is subjected to vector calculation, the method has the advantage that the calculation efficiency of the vector in the compression format can be effectively improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202111349874.4, and the original application date is November 15, 2021. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computers, and in particular to a computing device, method, system, circuit, chip and equipment. Background Art

[0003] Vector computing is an important computing type in different application scenarios such as artificial intelligence, scientific computing, and graphics computing. The element values ​​in a vector may contain two types of values: zero element values ​​and non-zero element values. When there are a large number of zero element values ​​in a vector, in order to save storage space, only the non-zero element values ​​in the vector can be stored, that is, the vector is compressed and stored in a compressed format.

[0004] In current technology, the common method for calculating compressed vectors is to first decompress the compressed vectors, that is, convert the compressed vectors into uncompressed vectors, and then perform vector calculations on the uncompressed vectors. In the vector calculation process, since the compressed vectors need to be decompressed, and the decompressed data will occupy a very large memory space, the calculation speed of the vectors will be limited by the memory access bandwidth. When the memory access bandwidth is fixed, the calculation speed of the vectors cannot be improved, resulting in low computing efficiency. Summary of the invention

[0005] The embodiments of the present application provide a computing device, method, system, circuit, chip and equipment that can directly calculate vectors in compressed format without decompressing the compressed vectors, thereby improving the computing performance of matrices in compressed format.

[0006] In a first aspect, an embodiment of the present application provides a computing device, comprising: a position coordinate comparison circuit and a logic operation circuit; wherein the position coordinate comparison circuit is used to compare the position coordinates of an element value in a first vector with the position coordinates of an element value in a second vector to obtain a first coordinate comparison result, wherein the first vector and the second vector are both vectors in compressed format, the first vector includes a first element value and a first position coordinate of the first element value, the second vector includes a second element value and a second position coordinate of the second element value, the first coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same; the logic operation circuit is used to operate the first element value and the second element value according to the first comparison result to obtain an operation value, and output the operation result to a buffer, the buffer is used to cache the operation result, and the operation result is related to the operation value. In this embodiment, the computing device can calculate vectors in a compressed format. When calculating two vectors in a compressed format, the computing device compares the position coordinates of each element value in the two vectors, adds the two element values ​​corresponding to the same position coordinates in the two vectors, and thus obtains the calculation result of the two vectors in a compressed format. Compared with the traditional method of first decompressing the vector in a compressed format and then performing vector calculation on the decompressed vector, the computing device provided in the embodiment of the present application can effectively improve the computing efficiency of the vector in a compressed format.

[0007] In an optional implementation, the logic operation circuit includes an accumulator; the position coordinate comparison circuit is also used to receive an addition instruction, and transmit the first comparison result to the accumulator according to the addition instruction; the accumulator is used to add the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, and output the sum to the buffer, wherein the operation result includes the third element value and the third position coordinate of the third element value, the third element value is the sum, the third position coordinate is the same as the first position coordinate, and the operation result is the result vector after the first vector and the second vector are added. In this embodiment, the computing device can perform addition operations on vectors in compressed format, and the computing device can be applied to application scenarios of vector addition calculations.

[0008] In an optional implementation, the accumulator is also used to output an invalid signal for the zero element value when the third element value is a zero element value, and the invalid signal indicates that the element value in the result matrix does not contain the zero element value and the position coordinates corresponding to the zero element value. In this embodiment, each third element value is obtained by adding two element values, so the third element value may be a zero element value. The accumulator is also used to delete the zero element value and the position coordinates corresponding to the zero element value when the third element value is a zero element value, so that the calculation result output by the computing device does not contain the zero element value, so as to output a vector in a compressed format, thereby saving transmission resources or facilitating the next calculation operation.

[0009] In an optional implementation, the accumulator does not output the zero element value and the position coordinates corresponding to the zero element value to the buffer based on the invalid signal, so that the buffer does not cache the zero element value and the position coordinates corresponding to the zero element value, thereby achieving the purpose of not including the zero element value in the calculation result.

[0010] In an optional implementation, the first coordinate comparison result also includes the second comparison result, the first vector includes the fourth element value and the fourth position coordinate of the fourth element value, and the second comparison result is used to indicate that the position coordinates identical to the fourth position coordinates are not matched in the second vector; the accumulator is also used to output the fourth element value and the fourth position coordinates to the buffer according to the second comparison result, and the operation result includes the fourth element value and the fourth position coordinates. In this embodiment, the accumulator retains the position coordinates that are not matched in the two vectors and the element values ​​corresponding to the position coordinates, and directly writes them into the buffer, so that the fourth element value is used as an element value in the operation result. Even if the multiple position coordinates in the first vector and the multiple position coordinates in the second vector cannot be completely matched one by one, the computing device can also perform addition calculations to increase the vector calculation scenario.

[0011] In an optional implementation, the logic operation circuit includes a multiplier; the position coordinate comparison circuit is also used to receive a multiplication instruction and transmit the first comparison result to the multiplier according to the multiplication instruction; the multiplier is used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the product value is the above operation value, the operation result includes the fifth element value and the fifth position coordinate of the fifth element value, the fifth element value is the product value, and the fifth position coordinate is the same as the first position coordinate. In this embodiment, the computing device can perform multiplication operations on vectors in a compressed format, and the computing device can be applied to application scenarios of vector multiplication calculations.

[0012] In an optional implementation, the logic operation circuit includes an inner product operation circuit; a position coordinate comparison circuit, further used to receive an inner product instruction, and transmit the first comparison result to the inner product operation circuit according to the inner product instruction; the inner product operation circuit, used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the product value is the above-mentioned operation value, the operation result is the accumulated value of multiple product values, each product value is a product value of a first element value and a second element value, and the operation result of the inner product of the first vector and the second vector is a scalar (a numerical value). In this embodiment, the computing device can perform an inner product operation on a vector in a compressed format, and the computing device can be applied to an application scenario of inner product calculation of a vector.

[0013] In an optional implementation, the logic operation circuit includes a multiplier and an accumulator, and the first coordinate comparison result also includes a third comparison result; the position coordinate comparison circuit is also used to receive a multiplication and addition calculation instruction, and transmit the first comparison result to the multiplier according to the multiplication and addition calculation instruction; the multiplier is also used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, to obtain the fifth element value and the fifth position coordinate of the fifth element value, and the fifth position coordinate is the same as the first position coordinate; the position coordinate comparison circuit is also used to compare the sixth position coordinate with the fifth position coordinate to obtain a third comparison result, and transmit the third comparison result to the accumulator. An adder, the third comparison result indicates that the sixth position coordinate is the same as the fifth position coordinate, the sixth position coordinate is the position coordinate in the third vector, and the third vector includes the sixth element value and the sixth position coordinate corresponding to the sixth element value; an accumulator, used to add the sixth element value and the fifth element value according to the third comparison result to obtain the sum of the sixth element value and the fifth element value, wherein the above-mentioned operation value includes the product value of the first element value and the second element value, and the sum of the sixth element value and the fifth element value, and the operation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value, the seventh element value is the sum of the sixth element value and the fifth element value, and the seventh position coordinate is the same as the sixth position coordinate. In this embodiment, the computing device can perform multiplication and addition operations on vectors in a compressed format, and the computing device can be applied to application scenarios of vector multiplication and addition calculations.

[0014] In an optional implementation, the first coordinate comparison result also includes a fourth comparison result, the third vector includes an eighth element value and an eighth position coordinate of the eighth element value, and the fourth comparison result is used to indicate that the position coordinates identical to the eighth position coordinates are not matched in the third vector; the accumulator is also used to output the eighth element value and the eighth position coordinates to the buffer according to the fourth comparison result, and the operation result includes the eighth element value and the eighth position coordinates. In this embodiment, the accumulator reserves the position coordinates that are not matched in the two vectors and the element values ​​corresponding to the position coordinates, and directly writes them into the buffer, so that the eighth element value is used as an element value in the operation result, even if the multiple position coordinates in the third vector and the multiple position coordinates in the result vector (i.e., the result vector after the multiplication of the first vector and the second vector) cannot be completely matched one by one, the computing device can also perform addition calculations to increase the vector calculation scenario.

[0015] In an optional implementation, the position coordinate comparison circuit is also used to compare the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result, wherein the first matrix includes a first vector, the second matrix includes a second vector, the first matrix and the second matrix are both matrices in compressed format, and the second coordinate comparison result includes the first coordinate comparison result. In this embodiment, a matrix in compressed format can be split into multiple vectors in compressed format, so a matrix in compressed format can be regarded as multiple vectors in compressed format, and thus, the above-mentioned multiple operations on vectors in compressed format can be extended to the calculation of matrices in compressed format. The computing device can operate on two matrices in compressed format, thereby increasing the application scenarios of the computing device and effectively improving the computing efficiency of vectors in compressed format.

[0016] In an optional implementation, the position coordinate comparison circuit includes a row coordinate comparison circuit and a column coordinate comparison circuit; the dimension of the first matrix is ​​M×N, and the dimension of the second matrix is ​​K×L; the row coordinate comparison circuit is used to compare the row coordinates of the mth row in the first matrix with the row coordinates of the fth row in the second matrix to obtain a row comparison result, and the row comparison result indicates that the row coordinates of the mth row are the same as the row coordinates of the fth row, wherein m is less than or equal to M, and f is less than or equal to K;

[0017] A column coordinate comparison circuit is used to compare the column coordinates of each element value in the mth row and the column coordinates of each element value in the fth row according to the row comparison result to obtain a column comparison result, wherein the column comparison result indicates that the nth column coordinate of the mth row is the same as the lth column coordinate of the fth row, and the first comparison result includes the row comparison result and the column comparison result; an accumulator is also used to add the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row according to the first comparison result to obtain a third element value, wherein the element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, wherein n is less than or equal to N, and l is less than or equal to L. In this embodiment, the position coordinate comparison circuit does not need to traverse and match each position coordinate in the first matrix with each position coordinate in the second matrix, and the row coordinate comparison circuit first compares the row coordinates in the first matrix and the second matrix, and then compares the column coordinates in the position coordinates with the same row coordinates, thereby reducing the number of comparisons of the position coordinates and saving computing resources.

[0018] In an optional implementation, the row comparison result includes a first signal and a first numerical value, and the column comparison result includes a second signal and a second numerical value, wherein the first signal is used to indicate the validity of the first numerical value, and the first numerical value is equal to the value of the row coordinate of the mth row, and the second signal is used to indicate the validity of the second numerical value, and the second numerical value is equal to the value of the above-mentioned nth column coordinate.

[0019] In a second aspect, an embodiment of the present application provides a calculation method, which is applied to a calculation device, and the method includes:

[0020] Obtain a calculation instruction, which includes a first vector and a second vector in a compressed format; compare the position coordinates of the element value in the first vector with the position coordinates of the element value in the second vector to obtain a first coordinate comparison result, wherein the first vector includes the first element value and the first position coordinate of the first element value, the second vector includes the second element value and the second position coordinate of the second element value, and the first coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same; operate the first element value and the second element value according to the first comparison result to obtain an operation value, and output the operation results of the first vector and the second vector to a buffer, and the operation result is related to the operation value.

[0021] In an optional implementation, the above-mentioned calculation instruction is an addition instruction, and the above-mentioned operation on the first element value and the second element value according to the first comparison result to obtain the operation value may include: adding the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, wherein the operation value is the sum value, and the operation result includes the third element value and the third position coordinates of the third element value, the third element value is the sum value, and the third position coordinates are the same as the first position coordinates.

[0022] In an optional implementation, the method further includes: when the third element value is a zero element value, outputting an invalid signal for the zero element value, the invalid signal indicating that the element value in the calculation result does not include the zero element value and the position coordinates corresponding to the zero element value.

[0023] In an optional implementation, the method further includes: avoiding outputting zero element values ​​and position coordinates corresponding to the zero element values ​​to a buffer according to an invalid signal.

[0024] In an optional implementation, the first coordinate comparison result also includes a second comparison result, the first vector includes a fourth element value and a fourth position coordinate of the fourth element value, and the second comparison result is used to indicate that a position coordinate identical to the fourth position coordinate is not matched in the second vector; the above method also includes: according to the second comparison result, outputting the fourth element value and the fourth position coordinate to a cache, and the operation result includes the fourth element value and the fourth position coordinate.

[0025] In an optional implementation, the operation instruction is a multiplication instruction, and the above-mentioned operation on the first element value and the second element value according to the first comparison result to obtain the operation value may include: multiplying the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, wherein the product value is the operation value, and the operation result includes the fifth element value and the fifth position coordinates of the fifth element value, the fifth element value is the product value, and the fifth position coordinates are the same as the first position coordinates.

[0026] In an optional implementation, the above-mentioned operation instruction is an inner product instruction, and the first element value and the second element value are multiplied according to the first comparison result to obtain the product value of the first element value and the second element value. The product value is the above-mentioned operation value, and the operation result is the accumulated value of multiple product values.

[0027] In an optional implementation, the operation instruction is a multiplication-addition instruction, and the first coordinate comparison result also includes a third comparison result; and the first element value and the second element value are operated according to the first comparison result to obtain an operation value, including:

[0028] According to the first comparison result, the first element value and the second element value are multiplied to obtain a product value of the first element value and the second element value, the operation value is the product value, the product value is used as the fifth element value, and the fifth position coordinate corresponding to the fifth element value is the same as the first position coordinate; the sixth position coordinate is compared with the fifth position coordinate to obtain a third comparison result, and the third comparison result is transmitted to the accumulator, the third comparison result indicates that the sixth position coordinate is the same as the fifth position coordinate, the sixth position coordinate is the position coordinate in the third vector, and the third vector includes the sixth element value and the sixth position coordinate corresponding to the sixth element value;

[0029] According to the third comparison result, the sixth element value and the fifth element value are added to obtain the sum of the sixth element value and the fifth element value. The calculated value includes the sum of the sixth element value and the fifth element value. The calculation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value. The seventh position coordinate is the same as the sixth position coordinate.

[0030] In an optional implementation, the above-mentioned operation instruction includes a first matrix and a second matrix in compressed format, the first matrix includes a first vector, and the second matrix includes a second vector. The above-mentioned comparison of the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector to obtain the first comparison result may include: comparing the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result, and the second coordinate comparison result includes the first coordinate comparison result.

[0031] In an optional implementation, the dimension of the first matrix is ​​M×N, and the dimension of the second matrix is ​​K×L; the above-mentioned comparing the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain the second coordinate comparison result may include: comparing the row coordinates of the mth row in the first matrix and the row coordinates of the fth row in the second matrix to obtain a row comparison result, the row comparison result indicating that the row coordinates of the mth row are the same as the row coordinates of the fth row, wherein m is less than or equal to M, and f is less than or equal to K; comparing the column coordinates of each element value in the mth row and the column coordinates of each element value in the fth row according to the row comparison result. The column coordinates of each element value are compared to obtain a column comparison result, and the column comparison result indicates that the nth column coordinate of the mth row is the same as the lth column coordinate of the fth row, and the first comparison result includes the row comparison result and the column comparison result; according to the first comparison result, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row are added to obtain a third element value, the element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, wherein n is less than or equal to N, and l is less than or equal to L.

[0032] In an optional implementation, the row comparison result includes a first signal and a first numerical value, and the column comparison result includes a second signal and a second numerical value, wherein the first signal is used to indicate the validity of the first numerical value, and the first numerical value is equal to the value of the row coordinate of the mth row, and the second signal is used to indicate the validity of the second numerical value, and the second numerical value is equal to the nth column coordinate.

[0033] In a third aspect, an embodiment of the present application provides a computing device, which includes: a position coordinate comparison circuit and an accumulator; the position coordinate comparison circuit is used to compare the position coordinates of an element value in a first matrix with the position coordinates of an element value in a second matrix to obtain a coordinate comparison result, wherein the first matrix and the second matrix are matrices in a compressed format, the first matrix includes a first element value and a first position coordinate of the first element value, the first element value is any element value in the first matrix, the second matrix includes a second element value and a second position coordinate of the second element value, the second element value is any element value in the second matrix, and the coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same; the accumulator is used to add the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, and output the sum to a buffer, the buffer is used to cache a result matrix, wherein the result matrix includes a third element value and a third position coordinate of the third element value, the third element value is the sum of the first element value and the second element value, and the third position coordinate is the same as the first position coordinate. In this embodiment, the computing device can calculate matrices in compressed format. When calculating the addition of two matrices in compressed format, the computing device compares the position coordinates of the element values ​​in the two matrices, and adds the two element values ​​corresponding to the same position coordinates in the two matrices, thereby obtaining a result matrix for calculating the two matrices in compressed format. Compared with the traditional method of first decompressing the matrix in compressed format and then performing matrix calculation on the decompressed matrix, the computing device provided in the embodiment of the present application can effectively improve the computing performance of the matrix in compressed format.

[0034] In an optional implementation, the accumulator is further used to output an invalid signal for the zero element value when the third element value is a zero element value, and the invalid signal indicates that the element value in the result matrix does not contain the zero element value and the position coordinates corresponding to the zero element value. In this embodiment, each third element value is obtained by adding two element values, so the third element value may be a zero element value. The accumulator is also used to delete the zero element value and the position coordinates corresponding to the zero element value when the third element value is a zero element value, so that the result matrix output by the computing device does not contain the zero element value, so as to output a matrix in a compressed format, thereby saving transmission resources or facilitating the next calculation operation.

[0035] In an optional implementation, the accumulator does not output the zero element value and the position coordinates corresponding to the zero element value to the buffer according to the invalid signal.

[0036] In an optional implementation, the coordinate comparison result also includes a second comparison result, the first matrix includes a fourth element value and a fourth position coordinate of the fourth element value, wherein the fourth element value is any element value in the first matrix, and the second comparison result is used to indicate that the position coordinates identical to the fourth position coordinates are not matched in the second matrix; the accumulator is also used to output the fourth element value and the fourth position coordinates to a buffer according to the second comparison result, and the buffer is used to cache the result matrix, and the result matrix includes the fourth element value and the fourth position coordinates. In this embodiment, the accumulator reserves the position coordinates that are not matched in the two matrices and the element values ​​corresponding to the position coordinates, and directly writes them into the buffer, thereby using the fourth element value as an element value in the result matrix, and even if the multiple position coordinates in the first matrix and the multiple position coordinates in the second matrix cannot be completely matched one by one, the computing device can also perform addition calculations, thereby increasing the matrix calculation scenario.

[0037] In an optional implementation, the position coordinate comparison circuit is further used to read that both the first matrix and the second matrix include position coordinates, and based on the triggering of the position coordinates, perform an operation of comparing the position coordinates in the first matrix and the position coordinates in the second matrix. In this embodiment, the position coordinate comparison circuit receives the first matrix and the second matrix, and since both the first matrix and the second matrix include position coordinates, when the position coordinate comparison circuit reads that the first matrix and the second matrix include position coordinates, it triggers the position coordinate circuit to compare the position coordinates in the first matrix and the position coordinates in the second matrix.

[0038] In an optional implementation, the position coordinate comparison circuit includes a row coordinate comparison circuit and a column coordinate comparison circuit, the dimension of the first matrix is ​​M×N, the dimension of the second matrix is ​​K×L, M×N and K×L may be the same or different, the row coordinate comparison circuit is used to compare the row coordinates of the mth row in the first matrix with the row coordinates of the fth row in the second matrix to obtain a row comparison result, the row comparison result indicates that the row coordinates of the mth row are the same as the row coordinates of the fth row; wherein m is less than or equal to M, and f is less than or equal to K; the column coordinate comparison circuit is used to compare the column coordinates of each element value in the mth row and the fth row according to the row comparison result. The column coordinates of each element value in the f-th row are compared to obtain a column comparison result, the column comparison result indicates that the n-th column coordinate of the m-th row is the same as the l-th column coordinate of the f-th row, and the first comparison result includes the row comparison result and the column comparison result; the accumulator is further used to add the element value corresponding to the n-th column coordinate of the m-th row and the element value corresponding to the l-th column coordinate of the f-th row according to the column comparison result to obtain a third element value, the element value corresponding to the n-th column coordinate of the m-th row is the first element value, and the element value corresponding to the l-th column coordinate of the f-th row is the second element value, wherein n is less than or equal to N, and l is less than or equal to L. In this embodiment, the position coordinate comparison circuit does not need to traverse and match each position coordinate in the first matrix with each position coordinate in the second matrix, and the row coordinate comparison circuit first compares the row coordinates in the first matrix and the second matrix, and then compares the column coordinates in the position coordinates with the same row coordinates, thereby reducing the number of comparisons of the position coordinates and saving computing resources.

[0039] In an optional implementation, the row comparison result includes a first signal and a first numerical value, and the column comparison result includes a second signal and a second numerical value, wherein the first signal is used to indicate the validity of the first numerical value, and the first numerical value is equal to the value of the row coordinate of the mth row, and the second signal is used to indicate the validity of the second numerical value, and the second numerical value is equal to the value of the nth column coordinate.

[0040] In a fourth aspect, an embodiment of the present application provides a matrix calculation method, which is applied to a computing device, and the method includes: first, the computing device obtains a calculation instruction, which includes a first matrix and a second matrix in a compressed format, and then compares the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain a coordinate comparison result, the first matrix includes the first element value and the first position coordinates of the first element value, and the second matrix includes the second element value and the second position coordinates of the second element value; the coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same; finally, the first element value and the second element value are added according to the first comparison result, and the obtained sum is output to a buffer, which is used to cache a result matrix, wherein the result matrix includes a third element value and a third position coordinate of the third element value, the third element value is the sum of the first element value and the second element value, and the third position coordinate is the same as the first position coordinate.

[0041] In an optional implementation, the method further includes: when the third element value is a zero element value, the computing device may output an invalid signal for the zero element value, wherein the invalid signal indicates that the element value in the result matrix does not contain a zero element value.

[0042] In an optional implementation, the above method also includes: avoiding outputting the zero element value and the position coordinates corresponding to the zero element value to the buffer according to the invalid signal, so that the result matrix does not contain the zero element value, and the result matrix is ​​a matrix in a compressed format, thereby saving transmission resources or facilitating the next calculation operation.

[0043] In an optional implementation, the coordinate comparison result also includes a second comparison result, the first matrix includes a fourth element value and a fourth position coordinate of the fourth element value; the second comparison result is used to indicate that the position coordinates identical to the fourth position coordinates are not matched in the second matrix, and the above method may also include: the computing device outputs the fourth element value and the fourth position coordinates to a buffer according to the second comparison result, the buffer is used to cache the result matrix, and the result matrix includes the fourth element value and the fourth position coordinates. In this embodiment, the accumulator retains the position coordinates that are not matched in the two matrices and the element values ​​corresponding to the position coordinates, and directly writes them into the buffer, so that the fourth element value is used as an element value in the result matrix, and even if the multiple position coordinates in the first matrix and the multiple position coordinates in the second matrix cannot be completely matched one by one, the computing device can also perform addition calculations to increase matrix calculation scenarios.

[0044] In an optional implementation, the dimension of the first matrix is ​​M×N, and the dimension of the second matrix is ​​K×L. The above-mentioned comparison of the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain the coordinate comparison result may specifically include: first, the computing device compares the row coordinates of the mth row in the first matrix with the row coordinates of the fth row in the second matrix to obtain a row comparison result, and the row comparison result indicates that the row coordinates of the mth row are the same as the row coordinates of the fth row; wherein m is less than or equal to M, and f is less than or equal to K; then, the computing device compares the row coordinates of the mth row according to the row comparison result. The column coordinates of each element value in the m-th row are compared with the column coordinates of each element value in the f-th row to obtain a column comparison result, and the column comparison result indicates that the n-th column coordinate of the m-th row is the same as the l-th column coordinate of the f-th row; the computing device adds the element value corresponding to the n-th column coordinate of the m-th row and the element value corresponding to the l-th column coordinate of the f-th row according to the column comparison result to obtain a third element value, the element value corresponding to the n-th column coordinate of the m-th row is the first element value, and the element value corresponding to the l-th column coordinate of the f-th row is the second element value, wherein n is less than or equal to N, and l is less than or equal to L.

[0045] In an optional implementation, the row comparison result includes a first signal and a first numerical value, and the column comparison result includes a second signal and a second numerical value, wherein the first signal is used to indicate that the row coordinates of the mth row are the same as the row coordinates of the fth row in the second matrix, and the first numerical value is equal to the row coordinates of the mth row, and the second signal is used to indicate that the nth column coordinates of the mth row are the same as the lth column coordinates of the fth row, and the second numerical value is equal to the nth column coordinate.

[0046] In a fifth aspect, a computing circuit is provided, which is used to execute the operating steps of the computing method provided by the above-mentioned second aspect or any possible implementation of the second aspect, or the computing circuit is used to execute the operating steps of the computing method provided by the above-mentioned fourth aspect or any possible implementation of the fourth aspect.

[0047] In a sixth aspect, a computing system is provided, the system comprising a processor and a computing device, the processor being used to send computing instructions to the computing device, the computing device being used to execute the operating steps of the computing method provided by the second aspect or any possible implementation of the second aspect, or the computing device being used to execute the operating steps of the computing method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0048] In the seventh aspect, a chip is provided, the chip including a processor, a computing device integrated in the processor, the computing device being used to execute the operating steps of the computing method provided by the above-mentioned second aspect or any possible implementation of the second aspect, or the computing device being used to execute the operating steps of the computing method provided by the above-mentioned fourth aspect or any possible implementation of the fourth aspect.

[0049] In an eighth aspect, a computing device is provided, the computing device comprising the computing system as described in the sixth aspect above, or the chip as described in the seventh aspect above.

[0050] In a ninth aspect, a readable storage medium is provided, wherein instructions are stored in the readable storage medium. When the readable storage medium is run on a device, the device executes the operation steps of the matrix calculation method provided by the second aspect or any possible implementation of the second aspect, or the device executes the operation steps of the calculation method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0051] In the tenth aspect, a computer program product is provided. When the computer program product runs on a computer, the computer executes the operating steps of the computing method provided by the second aspect or any possible implementation of the second aspect, or the computer executes the operating steps of the computing method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0052] It can be understood that any of the computing devices, computer storage media or computer program products provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above and will not be repeated here.

[0053] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1a A schematic diagram of a matrix in COO compression format in an embodiment of the present application;

[0055] Figure 1b A schematic diagram of a matrix in CSR compression format in an embodiment of the present application;

[0056] Figure 1c Schematic diagram of a matrix in CSC compression format in an embodiment of the present application;

[0057] Figure 1d A schematic diagram of splitting a matrix in a compressed format into vectors in a compressed format in an embodiment of the present application;

[0058] Figure 2 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0059] Figure 3 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0060] Figure 4 A schematic diagram of the structure of an embodiment of a computing device provided in an embodiment of the present application;

[0061] Figure 5 A schematic diagram of a position coordinate comparison circuit provided in an embodiment of the present application obtaining a first coordinate comparison result;

[0062] Figure 6 A schematic diagram of the structure of an embodiment of a logic operation circuit provided in an embodiment of the present application;

[0063] Figure 7 and Figure 8 Schematic diagrams of two examples of addition operations of a first vector and a second vector provided in an embodiment of the present application;

[0064] Fig. 9 A schematic diagram of an example of a multiplication operation of a first vector and a second vector provided in an embodiment of the present application;

[0065] Fig.10 A schematic diagram of an example of an inner product operation of a first vector and a second vector provided in an embodiment of the present application;

[0066] Fig.11 A schematic diagram of an example of multiplication and addition operations of a first vector, a second vector and a third vector provided in an embodiment of the present application;

[0067] Fig.12 A schematic diagram of the structure of another embodiment of a computing device according to an embodiment of the present application;

[0068] Fig.13 A schematic diagram of a matrix F in a compressed format provided in an embodiment of the present application;

[0069] Fig.14a A schematic diagram of a first matrix and a second matrix in an embodiment of the present application;

[0070] Fig.14b , Fig.14c and Fig.14d Schematic diagram of three examples of obtaining a result matrix by adding a first matrix and a second matrix in an embodiment of the present application;

[0071] Fig.15 This is a schematic diagram of the structure of the position coordinate comparison circuit in the embodiment of the present application;

[0072] Fig.16a A schematic diagram of comparing row coordinates in a first matrix and row coordinates in a second matrix in an embodiment of the application;

[0073] Fig.16b A schematic diagram of a row coordinate comparison circuit performing row coordinate comparison in an embodiment of the present application;

[0074] Fig.17a A schematic diagram of comparing column coordinates in two rows with equal row coordinates in a first matrix and a second matrix in an embodiment of the present application;

[0075] Fig.17b A schematic diagram of a column coordinate comparison circuit performing column coordinate comparison in an embodiment of the present application;

[0076] Fig.18 This is a schematic diagram of the structure of the accumulator in the embodiment of the present application;

[0077] Fig.19 It is a schematic diagram of an accumulator outputting an element value to a second buffer according to a comparison result of a column coordinate in an embodiment of the present application;

[0078] Fig. 20 A schematic diagram of the structure of another embodiment of a computing device in an embodiment of the present application;

[0079] Fig.21 A schematic diagram of a step flow chart of an embodiment of a calculation method in an embodiment of the present application;

[0080] Fig. 22 This is a schematic diagram of the steps of another embodiment of a calculation method in the embodiment of the present application. DETAILED DESCRIPTION

[0081] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The terms "first", "second", etc. in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0082] In order to better understand the present application, the relevant terms involved in the present application are firstly explained by way of example.

[0083] Matrix: An M×N matrix of dimension is a rectangular array of elements arranged in M ​​rows and N columns. For example, matrix A is shown in equation (1) below, and matrix B is shown in equation (2) below.

[0084]

[0085] Matrix addition and subtraction: Matrices of the same dimension can be added and subtracted with each other, specifically, the elements at each position are added and subtracted. For example, matrix A and matrix B are both m×n matrices. The matrix C is obtained by adding matrix A and matrix B as shown in the following formula (3).

[0086]

[0087] A row vector is a matrix with a dimension of 1×M, where M is a positive integer. For example, a row vector is as shown in the following formula (5):

[0088] X=[x 1 x 2 ...x M ], formula (5).

[0089] A column vector is a matrix with a dimension of M×1, where M is a positive integer. For example, a column vector is shown in the following formula (6):

[0090]

[0091] Compressed Matrix: When a matrix contains both zero and non-zero values, in order to save storage space, the non-zero values ​​can be stored in a certain format instead of zero values. This process is called compressing the matrix, and the compressed matrix is ​​called a compressed matrix. Methods for compressing matrices include but are not limited to coordinate representation (COO), compressed sparse row (CSR), compressed sparse column (CSC), etc.

[0092] The following is an exemplary description of the three compression methods, namely COO, CSR and CSC.

[0093] COO: A matrix is ​​represented by a triple. A triple contains three values: row number, column number, and element value. The row number and column number are used to identify the position of the element value. For example, the triple is (row number, column number, element value), or the triple is (element value, row number, column number), etc. The specific order of the three values ​​in the triple is not limited. For example, see Figure 1a , Figure 1aA matrix Y with a dimension of 4×4 is shown in the figure, which includes zero element values ​​and non-zero element values, wherein the non-zero element values ​​are: 1, 2, 3, 4, 5, 6, 7, 8, 9. For example, the position of the non-zero element value "1" is the 0th row and the 0th column, and the triple is represented by (0, 0, 1). The position of the non-zero element value "2" is the 0th row and the 1st column, and the triple is represented by (0, 1, 2). The position of the non-zero element value "3" is the 1st row and the 1st column, and the triple is represented by (1, 1, 3). Each element value is not described one by one here. For example, the triple form of the matrix in the compressed format is: (0, 0, 1), (0, 1, 2), (1, 1, 3), (1, 2, 4), (2, 0, 5), (2, 2, 6), (2, 3, 7), (3, 1, 8), (3, 3, 9).

[0094] Optionally, the compressed matrix Y can be expressed as shown in the following equation (8).

[0095] row coordinates = ([0,0,1,1,2,2,2,3,3]);

[0096] Column coordinates = ([0,1,1,2,0,2,3,1,3]);

[0097] Element value = ([1,2,3,4,5,6,7,8,9]), formula (8).

[0098] CSR: The matrix is ​​represented by three types of data: element value, column number, and row offset value. The element value and column number in CSR are similar to those in the COO method. The difference between CSR and COO is that the row offset indicates the starting offset position of the first element of a row among all element values. See Figure 1b As shown, first, Figure 1b The non-zero element values ​​in the matrix Y shown in are arranged in rows, and all the element values ​​are: 1, 2, 3, 4, 5, 6, 7, 8, 9. The first non-zero element value in the first row is "1", and the offset of element value "1" in all element values ​​is "0". Similarly, the first non-zero element value in the second row is "3", and the offset of element value "3" in all element values ​​is "2". The first non-zero element value in the third row is "5", and the offset of element value "5" in all element values ​​is "4". The first non-zero element value in the fourth row is "8", and the offset of element value "8" in all element values ​​is "7". Finally, the total number of non-zero element values ​​in the matrix (such as "9") is added to the last position of the row where the row offset is located.

[0099] The compressed matrix Y can be expressed as shown in the following equation (9).

[0100] row_offset = ([0,2,4,7,9]);

[0101] Column coordinates = ([0,1,1,2,0,2,3,1,3]);

[0102] Element value = ([1,2,3,4,5,6,7,8,9]), formula (9).

[0103] CSC: The matrix is ​​represented by three types of data: element value, row number, and column offset value. The element value and row number in CSR are similar to those in the COO method. The difference between CSC and COO is that the column offset indicates the starting offset position of the first element of a column among all element values. See Figure 1c As shown, first, Figure 1c The non-zero element values ​​in the matrix Y shown in are arranged by columns, and all the element values ​​are: 1, 5, 2, 3, 8, 4, 6, 7, 9. The first non-zero element value in the first column is "1", and the offset of element value "1" in all element values ​​is "0". Similarly, the first non-zero element value in the second column is "5", and the offset of element value "5" in all element values ​​is "2". The first non-zero element value in the third column is "2", and the offset of element value "2" in all element values ​​is "5". The first non-zero element value in the fourth column is "3", and the offset of element value "3" in all element values ​​is "7". Finally, the total number of non-zero element values ​​in the matrix (such as "9") is added to the last position of the row where the column offset is located.

[0104] The compressed matrix Y can be expressed as shown in the following equation (10).

[0105] column_offset = ([0,2,5,7,9]);

[0106] row coordinates = ([0,0,1,1,2,2,2,3,3]);

[0107] Element value = ([1,5,2,3,8,4,6,7,9]), formula (10).

[0108] Through the description of the above three matrix compression methods, it can be seen that each element value in the matrix of COO compression format has corresponding row coordinates (row number) and column coordinates (column number). Each element value in the matrix of CSR compression format will have corresponding column coordinates. Each element value in the matrix of CSC compression format will have corresponding row coordinates.

[0109] Matrices in uncompressed format: see Figure 1aThe matrix Y shown in FIG. 1 includes zero element values ​​and non-zero element values ​​in the non-compressed format. It should be noted that, in general, a matrix in a compressed format is also referred to as a sparse matrix, and a matrix in an non-compressed format is also referred to as a dense matrix.

[0110] A vector in a compressed format. In this embodiment, the vector in a compressed format may be a vector obtained by compressing a vector in an uncompressed format. For example, a vector in an uncompressed format [1,2,0,3,0,5]. This vector in uncompressed format It includes 6 element values. If To compress and retain only the non-zero element values ​​in the vector, it is necessary to mark the position of each non-zero element value by the position coordinate. In an example, the compressed vector It is expressed by the following formula (11).

[0111] element value = ([1,2,3,5]);

[0112] Position coordinates = ([0,1,4,6]), formula (11).

[0113] In the above formula 11, the element value "1" is located at the "0"th position, so the position coordinate corresponding to the element value "1" is "0"; similarly, the element value "2" is located at the "1"th position, and the position coordinate corresponding to the element value "2" is "1", and so on. The specific examples are not listed one by one.

[0114] For example, see Figure 1d To understand, Figure 1d Schematic diagram of an example of a compressed matrix. The compressed vector is obtained by splitting the compressed matrix. The compressed matrix can be split into multiple compressed row vectors, or split into multiple compressed column vectors. The compressed vector takes the column vector as an example. The four coordinate values ​​a in the first column are 00 =1,a 10 =2, a 20 =5, a 30 =7, where the element value a 00 , a 10 , a 20 and a 30 The corresponding position coordinates are (i 0 ,j 0 ), (i 1 ,j 0 ), (i 2 ,j 0 ) and (i 3 ,j 0 ), for example, (i 0 ,j 0 )=(1,1),(i1 ,j 0 )=(3,1),(i 2 ,j 0 )=(4,1),(i 3 ,j 0 )=(5,1). Since the column coordinates of each element in the compressed format column vector are the same, each element value in the compressed format vector can only carry the row coordinates, and the position coordinates are the row coordinates in the compressed format matrix. If the compressed format vector is a row vector, the compressed format vector can only carry the column coordinates, and the position coordinates are the column coordinates in the compressed format matrix. In an example, the compressed format vector is shown in the following formula (12).

[0115] element value = ([1,2,5,7]);

[0116] Position coordinates = ([1,3,4,5]), formula (12).

[0117] The vector in the compressed format is also called a sparse vector, and the vector in the uncompressed format is also called a dense vector.

[0118] Figure 2 This is a schematic diagram of the structure of a computing device provided in this embodiment. The computing device may be a terminal, a network device, a server, or other device with computing capabilities. Figure 2 The computing device may include a memory 201 , a processor 202 , a communication interface 203 and a bus 204 , and the memory 201 , the processor 202 and the communication interface 203 are interconnected via the bus 204 .

[0119] Among them, the memory 201 can be used to store data, software programs and modules, mainly including a program storage area and a data storage area. The program storage area can store an operating system, software applications and intermediate layer software required for at least one function, etc., and the data storage area can store data created when the device is used. For example, the operating system can include a Linux operating system, a Unix operating system, or a Window operating system, etc.; the software application required for at least one function can include applications related to artificial intelligence, applications related to high performance computing (HPC), applications related to deep learning, or applications related to scientific computing, etc., and the intermediate layer software can include linear algebra library functions, etc. In a possible exemplary embodiment, the memory 201 includes but is not limited to static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM) or high-speed random access memory, etc. Further, the memory 201 can also include other non-volatile memories, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0120] In addition, the processor 202 is used to control and manage the operation of the computing device, such as by running or executing software programs and / or modules stored in the memory 201, and calling the data stored in the memory 201, to perform various functions of the computing device and process data. In a possible exemplary embodiment, the processor 202 includes but is not limited to a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, logic circuits or any combination thereof. It can implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. The processor 202 can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0121] The communication interface 203 is used to enable the computing device to communicate with an external device. Among them, the communication interface 203 may include an input interface and an output interface. The input interface can be used to obtain the first vector (or first matrix) and the second matrix vector (or second matrix) in the compressed format in the following embodiments. In some feasible embodiments, the input interface may have only one input interface or multiple input interfaces. The output interface can be used to output the operation results in the following embodiments. In some feasible embodiments, the operation results can be directly output by the processor, or they can be first stored in the memory and then output through the memory. In other feasible embodiments, there can be only one output interface or multiple output interfaces.

[0122] The bus 204 may be a Peripheral Component Interconnect Express (PCIe) bus, or an extended industry standard architecture (EISA) bus, etc. The bus 204 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 2 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0123] In this embodiment, the processor 202 may include a computing device, which may be an ASIC, an FPGA, or a logic circuit, etc. Of course, the device may also be implemented by software, and this embodiment of the present application does not specifically limit this. The computing device may be used to calculate vector and matrix calculations involved in artificial intelligence, scientific computing, graphic computing, etc.

[0124] Furthermore, the processor 202 may also include one or more other processing units such as a CPU, a GPU or an NPU. Figure 3 As shown, taking the processor 202 including the CPU 1 and the computing device 2 as an example, the computing device 2 can be integrated with the CPU 1 (for example, the computing device 2 is integrated inside the SoC where the CPU 1 is located), or can be separately set up in parallel with the CPU 1 (for example, the computing device 2 is set in the form of a PCIe card). Figure 3 (a) and Figure 3 As shown in (b) in FIG. 1 , the CPU 1 may further include a controller 11 , one or more arithmetic logic units (ALU) 12 , a cache 13 , and a memory management unit (MMU) 14 . Figure 3In the description, the memory 201 is taken as a dynamic random access memory DRAM as an example.

[0125] In an embodiment of the present application, the computing device is capable of calculating vectors in a compressed format. When calculating two vectors in a compressed format, the computing device compares the position coordinates of each element value in the two vectors, and performs operations on the two element values ​​corresponding to the same position coordinates in the two vectors, thereby obtaining the calculation results of the two vectors in a compressed format. Compared with the traditional method of first decompressing the vector in a compressed format and then performing vector calculation on the decompressed vector, the computing device provided in the embodiment of the present application can effectively improve the computing efficiency of the vector in a compressed format.

[0126] The present application embodiment provides a computing device. Figure 4 As shown, the computing device includes a position coordinate comparison circuit 401 and a logic operation circuit 402. Optionally, the computing device also includes a first buffer 403 and a second buffer 404, wherein the first buffer 403, the position coordinate comparison circuit 401, the accumulator 4021 and the second buffer 404 are connected in sequence. The first buffer 403 and the second buffer 404 can be buffers (such as registers) in the computing device, or the first buffer 403 can also be Figure 3 The buffer 13 in the central processing unit 1 is shown in FIG. The first buffer 403 is used to buffer the first vector and the second vector, and the second buffer 404 is used to buffer the calculation result after the first vector and the second vector are calculated.

[0127] The position coordinate comparison circuit 401 is used to receive the first vector and the second vector from the first buffer 403, compare the position coordinates of the element value in the first vector with the position coordinates of the element value in the second vector, and obtain a first coordinate comparison result, wherein the first vector and the second vector are both vectors in compressed format, the first vector includes the first element value and the first position coordinate of the first element value, the second vector includes the second element value and the second position coordinate of the second element value, and the first coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same.

[0128] For example, the first vector is denoted as The second vector is denoted by The lengths of the first vector and the second vector are T. It should be noted that the embodiment of the present application does not limit The length and Length, The length and The lengths of can be the same or different. In this embodiment, and The length of T is just an example for convenience of explanation, and and They may all be row vectors or column vectors, and there is no specific limitation. including a first element value and a first position coordinate corresponding to the first element value, exemplarily, The multiple first element values ​​in and the first position coordinates corresponding to each first element value are shown in the following Table 1. The multiple second element values ​​in and the second position coordinates corresponding to each second element value are shown in the following Table 2.

[0129] Table 1

[0130] First element value <![CDATA[a 0 ]]> <![CDATA[a 1 ]]> <![CDATA[a 2 ]]> … <![CDATA[a T-1 ]]> First position coordinates <![CDATA[h 0 ]]> <![CDATA[h 1 ]]> <![CDATA[h 2 ]]> … <![CDATA[h T-1 ]]>

[0131] Table 2

[0132] The second element value <![CDATA[b 0 ]]> <![CDATA[b 1 ]]> <![CDATA[b 2 ]]> … <![CDATA[b T-1 ]]> Second position coordinates <![CDATA[p 0 ]]> <![CDATA[p 1 ]]> <![CDATA[p 2 ]]> … <![CDATA[p T-1 ]]>

[0133] The position coordinate comparison circuit 401 compares the first position coordinates in Table 1 and the second position coordinates in Table 2. If there are y pairs of position coordinates matching among the T first position coordinates and the T second position coordinates, y is an integer greater than or equal to 0 and less than or equal to T. Figure 5 As shown, Figure 5 Schematic diagram of coordinate comparison performed by the position coordinate comparison circuit 401. For example, T is described by taking 4 as an example. The coordinates of the four positions in h are 0 ,h 1 ,h 2 ,h 3 , The coordinates of the four positions in the sequence are p 0 , p 1 , p 2 , p 3 The position coordinate comparison circuit 401 outputs a first comparison result to the logic operation circuit 402. The first comparison result includes the comparison result of the position coordinates, a third signal (e.g., recorded as "valid") and a third value (e.g., recorded as "t"), and the third signal is used to indicate the validity of the t value. The third value is used to indicate the specific value of the position coordinates. The comparison result of the position coordinates can be recorded as: (isequal" 0 .index_01,index_02), (isequal" 1 .index_11,index_12), (isequal" 2 .index_21,index_22), (isequal" 3 .index_31,index_32). For example, when (isequal" 0.index_01,index_02)=(1,h 0 , p 0 ), it means the position coordinate h in the first vector 0 and the position coordinates p in the second vector 0 If they are equal, the position coordinate comparison circuit 401 also outputs "valid" 0 =1,t 0 , where t 0 and h 0 Equal (ie t 0 and p 0 Similarly, when (isequal" 1 .index_11,index_12)=(1,h 1 , p 1 ), it means the position coordinate h in the first vector 1 and the position coordinates p in the second vector 1 The position coordinate comparison circuit 401 also outputs valid" 1 =1,t 1 , where t 1 and h 1 Equal (ie t 1 and p 1 are also equal); and so on, the comparison results of the position coordinates are not described one by one. Wherein, valid"=1 indicates that the corresponding output t value is valid, and valid"=0 indicates that the corresponding output t value is invalid.

[0134] Understandably, Figure 5 In the figure, the position coordinate comparison circuit 401 outputs a total of 8 groups of valid" values ​​and t values, and outputs 4 groups of isequal" comparison results. The reason why the position coordinate comparison circuit 401 outputs 8 groups of valid" is that the number of groups and the bit width of the signal output by the position coordinate comparison circuit 401 are fixed, and the position coordinate comparison circuit 401 reads T position coordinates in the first vector and T position coordinates in the second vector. If none of the T position coordinates in the first vector and the T position coordinates in the second vector match, then the number of valid" is at most 2T (i.e., 8), so 2T valid" output positions can be reserved. The reason why the position coordinate comparison circuit 401 outputs 4 groups of isequal" comparison results is that if the T position coordinates in the first vector and the T position coordinates in the second vector all match one by one, then at most T groups (i.e., 4 groups) of position coordinates should all match one by one, so 4 output positions of isequal" comparison results can be reserved.

[0135] Example 1: The position coordinate comparison circuit receives two input arrays as follows:

[0136] {h 0 ,h 1 ,h 2 ,h 3} = {1, 2, 3, 4};

[0137] {p 0 , p 1 , p 2 , p 3}={1,2,5,7}.

[0138] The results of the position coordinate comparison circuit output are as follows:

[0139] (isequal" 0 .index_01,index_02)=(1,h 0 , p 0 );

[0140] (isequal" 1 .index_11,index_12)=(1,h 1 , p 1 );

[0141] (isequal" 2 .index_21,index_22)=(0,h 2 , p 2 );

[0142] (isequal" 3 .index_31,index_32)=(0,h 3 , p 3 );

[0143] (valid 0 , t 0 ) = (1, 1);

[0144] (valid 1 , t 1 ) = (1, 2);

[0145] (valid 2 , t 2 ) = (1, 3);

[0146] (valid 3 , t 3 ) = (1, 4);

[0147] (valid 4 , t 4 ) = (1, 5);

[0148] (valid 5 , t 5 ) = (1, 7);

[0149] (valid 6 , t 6 ) = (0, -1);

[0150] (valid 7 , t 7 )=(0,-1).

[0151] The comparison results of the position coordinates can indicate which pairs of position coordinates are equal, such as h 0 and p 0 Equal, h 1 and p 1 The above "isequal" comparison result shows the final comparison result, and does not focus on the comparison process. For example, "valid" 3 =1,t 2 =h 2 Indication 2 is a valid value and combined with (isequal" 2 .index_21,index_22)=(0,h 2 , p 2 ) This comparison result shows that the position coordinate comparison circuit 401 does not match h 2 Equal position coordinates (and not matched to p 2 As can be seen from the above example 1, the position coordinate comparison circuit 401 matches 2 pairs of equal position coordinates, but 4 position coordinates are not matched to equal values, so the number of valid values ​​is 6 (valid" 0 to valid" 5 ), and valid" 6 and valid 7 The values ​​of are all 0, which means that t 6 and t 7 An invalid value (for example, an invalid value can be represented by "-1").

[0152] The logic operation circuit 402 is used to operate the first element value and the second element value according to the first comparison result to obtain an operation value, and output the operation result to the second buffer 404, and the operation result is related to the operation value.

[0153] In the embodiment of the present application, the above-mentioned operations include but are not limited to addition operations, multiplication operations, inner product operations, and multiplication-addition operations. Figure 6As shown, the logic operation circuit 402 includes at least one of an accumulator 4021, a multiplier 4022, and an inner product operation circuit 4023. The above-mentioned various operations are described below by way of example.

[0154] Example 1: Addition operation An exemplary description is given.

[0155] In an optional embodiment, the position coordinate comparison circuit 401 is further used to receive an addition instruction, where the addition instruction includes a first vector and a second vector, and transmit the first comparison result to the accumulator 4021 according to the addition instruction.

[0156] The accumulator 4021 is used to receive the first vector, the second vector and the first comparison result, where the first comparison result is used to indicate that the first position coordinates are the same as the second position coordinates. Exemplarily, the first comparison result a includes the (isequal" in the above example 1 0 .index_01,index_02)=(1,h 0 , p 0 )、(valid′ 0 , t 0 )=(1,1). The accumulator 4021 adds the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, and outputs the sum to the second buffer 404, which is used to cache the operation result (the result vector after the first vector and the second vector are added), wherein the operation result includes the third element value and the third position coordinate of the third element value, the third element value is the sum, and the third position coordinate is the same as the first position coordinate.

[0157] For example, please refer to Table 1, Table 2 and Figure 7 It is understood that if the first comparison result indicates that the first position coordinates in the first vector and the second position coordinates in the second vector can be matched one by one, such as h 0 =p 0 ,h 1 =p 1 ,h 2 =p 2 ,…,h T-1 =p T-1 .but The calculation results can be shown in Table 3 below.

[0158] Table 3

[0159] The third element value <![CDATA[c 0 ]]> <![CDATA[c 1 ]]> <![CDATA[c 2 ]]> … <![CDATA[c T-1 ]]> The third position coordinates <![CDATA[q 0 ]]> <![CDATA[q 1 ]]> <![CDATA[q 2 ]]> … <![CDATA[q T-1 ]]>

[0160] Among them, in the above Table 3, c 0 =a 0+b 0 , c 1 =a 1 +b 1 , c 2 =a 2 +b 2 , …, c T-1 =a T-1 +b T-1 ; and q 0 =h 0 (q 0 =p 0 ), q 1 =h 1 (q 1 =p 1 ), q 2 =h 2 (q 2 =p 2 ), …, q T-1 =h T-1 (q T-1 =p T-1 ).

[0161] Figure 7 Take 4 as an example, if a 0 is 10, b 0 is 2, then c 0 =10+2=12,q 0 =1. Figure 7 The examples in the article are not listed one by one, but are just examples to illustrate.

[0162] Optionally, if the first position coordinates in the first vector and the second position coordinates in the second vector are not all matched one by one, but The position coordinates of a part in can match the same position coordinates, and The position coordinates of the other part in The first vector includes a fourth element value and a fourth position coordinate of the fourth element value, and the first coordinate comparison result also includes a second comparison result, and the second comparison result is used to indicate that the position coordinates that are the same as the fourth position coordinates are not matched in the second vector. Exemplarily, the second comparison result a includes (isequal" in the above example 1 2 .index_21,index_22)=(0,h 2 , p 2 ) and (valid" 2 , t 2 )=(1,3) etc.

[0163] The accumulator 4021 is also used to output the fourth element value and the fourth position coordinate to the second buffer 404 according to the second comparison result, and the operation result includes the fourth element value and the fourth position coordinate. That is to say, the third element value and the corresponding position coordinate, the fourth element value and the corresponding position coordinate are stored in the second buffer, wherein the third element value is the sum of the first element value and the second element value, and the fourth element value is equal to the first element value or the second element value. In this embodiment, the accumulator 4021 reserves the position coordinates that are not matched in the two vectors and the element values ​​corresponding to the position coordinates, and directly writes them into the second buffer 404, so that each fourth element value is also used as an element value in the operation result. Even if the multiple position coordinates in the first vector and the multiple position coordinates in the second vector cannot be completely matched one by one, the computing device can also perform addition calculations to increase vector calculation scenarios.

[0164] See also Figure 8 As shown, the operation result is the result after the position coordinates are sorted in ascending order. For example, if the position coordinate "1" of the first element value "10" and the position coordinate "1" of the second element value "2" are equal, the accumulator 4021 outputs the third element value "12" (the first element value "10" + the second element value "2") and the corresponding third position coordinate "1" to the second buffer 404; if the first position coordinate "2" of the first element value "7" and the second position coordinate "2" of the second element value "3" are equal, the accumulator 4021 outputs the third element value "10" (the first element value "7" + the second element value "3") and the third position coordinate "2" to the second buffer 404. For another example, if the position coordinate "3" of the first element value "8" does not match the second position coordinate equal to it, the accumulator 4021 retains the first element value "8" and the corresponding position coordinate "3" and directly transmits them to the second buffer 404. Figure 8 The examples in the second buffer are not described one by one. The length of the result vector (i.e., the operation result) is greater than or equal to T and less than or equal to 2T.

[0165] Optionally, since each third element value is obtained by adding two element values, the third element value may be a zero element value. In order to save transmission resources or facilitate the next calculation operation, the computing device may compress the above result vector to output a vector in a compressed format. Exemplarily, the accumulator 4021 is also used to output an invalid signal when the third element value is a zero element value. The invalid signal indicates that the accumulator 4021 will not output the zero element value and the position coordinates corresponding to the zero element value to the second buffer 404, so that the calculation result output by the computing device does not contain a zero element value. For example, (isequal" 0 .index_01,index_02)=(1,h 0, p 0 ), (valid" 0 , t 0 )=(1,1).h 0 =p 0 , and h 0 The corresponding first element value is "1", p 0 The corresponding first element value is "-1", then the third element value is "0" (1+(-1)), and the accumulator 4021 will be valid" 0 The value of is set from "1" to "0" (invalid signal), and the accumulator 4021 is set according to the invalid signal (valid" 0 =0) to avoid outputting the zero element value and the position coordinates corresponding to the zero element value to the second buffer 404, so that the second buffer 404 does not cache the zero element value.

[0166] Example 2: Multiplication operation An exemplary description is given.

[0167] In an optional embodiment, the position coordinate comparison circuit 401 is further used to receive a multiplication instruction, where the multiplication instruction includes a first vector and a second vector, and transmit the first comparison result to the multiplier 4022 according to the multiplication instruction.

[0168] Multiplier 4022 is used to receive the first vector, the second vector and the first comparison result, and multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, and output the product value (calculation value) to the second buffer 404. The calculation result includes the fifth element value (such as recorded as "d") and the fifth position coordinates of the fifth element value (such as recorded as "s"), the fifth element value is the above-mentioned product value, and the fifth position coordinates are the same as the first position coordinates.

[0169] Please understand it in combination with Table 1 and Table 2 above. 0 =p 0 ,h 1 =p 1 ,h 3 =p 2 , then the fifth element value is d 0 =a 0 ×b 0 , d 0 The corresponding fifth coordinate value is s 0 (s 0 =h 0 ); the fifth element value d 1 =a 1 ×b 1 , d 1 The corresponding fifth coordinate value is s 1 (s 1 =h1 ); the fifth element value d 2 =a 3 ×b 2 , d 2 The corresponding fifth coordinate value is s 2 (s 2 =h 3 The multiplier 4022 does not calculate the element values ​​corresponding to the position coordinates that do not match in the first vector and the second vector.

[0170] Please refer to Figure 9. In a specific example, the first comparison result includes 3 pairs of equal position coordinates. The multiplier 4022 performs multiplication operations on two operation values ​​with equal position coordinates according to the first comparison result. For example, the position coordinate "1" of the first element value "10" and the position coordinate "1" of the second element value "2" are equal, then the multiplier 4022 multiplies the first element value "10" and the second element value "2" to obtain the product value "20", and outputs the product value (fifth element value) and the corresponding position coordinate "1" (fifth position coordinate) to the second buffer 404. If the first position coordinate "3" of the first element value "8" does not match an equal position coordinate, the multiplier 4022 will not calculate the first element value "8"; similarly, the second position coordinate "7" of the second element value "11" does not match an equal position coordinate, then the multiplier 4022 will not calculate the second element value "11". For Fig. 9 The examples shown are not described one by one here. In this embodiment, if the lengths of the first vector and the second vector are both T, then The length of the operation result is greater than or equal to 0 and less than or equal to T.

[0171] Example 3: Inner product operation An exemplary description is given.

[0172] In an optional embodiment, the position coordinate comparison circuit 401 is further used to receive an inner product instruction, the inner product instruction includes a first vector and a second vector, and transmit the first comparison result to the inner product operation circuit 4023 according to the inner product instruction.

[0173] The inner product operation circuit 4023 is used to receive the first vector, the second vector and the first comparison result, and multiply the first element value and the second element value according to the first comparison result to obtain a product value (operation value), and output the operation result to the second buffer 404. The operation result is the accumulated value of multiple product values, and each product value is the product value of a pair of first element values ​​and second element values ​​with the same position coordinates. Please understand in combination with the above Table 1 and Table 2, if the vector and vector There are x pairs of position coordinates matching, such as h 0 =p0 ,h 1 =p 1 ,h 3 =p 2 ,but The calculation result is shown in the following formula (13).

[0174]

[0175] vector and vector The result of the inner product operation is a scalar. For example, see Fig.10 As shown, =10×2+7×3+6×10=101.

[0176] Example 4: Multiplication and addition operations An exemplary description is given.

[0177] In this embodiment, three vectors are involved, and all of the three vectors are vectors in compressed format. Second vector and the third vector Multiplier 4022 is used to and Perform multiplication operation, accumulator 4021 is used to The results and Perform addition operation.

[0178] The position coordinate comparison circuit 401 is further used to receive a multiplication-addition calculation instruction, which includes a first vector and a second vector, and transmit the first comparison result to the multiplier 4022 according to the multiplication-addition calculation instruction.

[0179] The multiplier 4022 is further configured to receive the first vector, the second vector, and the first comparison result, and multiply the first element value and the second element value according to the first comparison result to obtain a product value (operation value) of the first element value and the second element value, wherein the product value is the fifth element value, and the fifth position coordinate corresponding to the fifth position coordinate is the same as the first position coordinate. The multiplier 4022 transmits the fifth operation value and the fifth position coordinate to the second buffer 404.

[0180] vector and vector Please refer to the multiplication operation in Example 2 above. This is not repeated here.

[0181] The second buffer 404 will The result (such as denoted as a vector ) is output to the first buffer 403.

[0182] The position coordinate comparison circuit 401 is also used to receive the vector from the first buffer 403 and vector Alignment Vector The sixth position coordinates and vector in The fifth position coordinate in is compared to obtain a third comparison result, and the third comparison result is transmitted to the accumulator 4021, the third comparison result indicating that the sixth position coordinate is the same as the fifth position coordinate.

[0183] Accumulator 4021 is used to add the sixth element value and the fifth element value according to the third comparison result to obtain the sum of the sixth element value and the fifth element value. The calculation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value. The seventh position coordinate is the same as the sixth position coordinate.

[0184] vector and vector The description of the addition operation of and the vector addition operation in the above example 1 are not repeated here.

[0185] See also Fig.11 As shown in the figure, the multiplication and addition operation is illustrated. and vector There are 3 pairs of position coordinates that are the same. For example, the position coordinate "1" of the first element value "10" and the position coordinate "1" of the second element value "2" are equal, then the multiplier 4022 multiplies the first element value "10" and the second element value "2" to obtain the product value "20", and outputs the product value (the fifth element value) and the corresponding position coordinate "1" (the fifth position coordinate) to the second buffer 404; similarly, the position coordinate "2" of the first element value "7" and the position coordinate "2" of the second element value "3" are equal, then the multiplier 402 2 multiplies the first element value "7" and the second element value "3" to obtain the product value "21", and outputs the product value "21" and the corresponding position coordinate "2" to the second buffer 404, etc. Finally, the multiplier 4022 outputs three fifth element values ​​20, 21, 60 (6×10) and the fifth position coordinates ("1", "2", "5") corresponding to each fifth element value to the second buffer 404, and the second buffer 404 transmits the three fifth element values ​​and the fifth position coordinates corresponding to each element value to the first buffer 403.

[0186] Position coordinate comparison circuit 401 compares vector and vector Compare the position coordinates in the vector and vector There are 2 pairs of identical position coordinates in the accumulator. For example, the fifth position coordinate "1" corresponding to the fifth element value "20" and the sixth position coordinate "1" corresponding to the sixth element value "7" are identical; the fifth position coordinate "5" corresponding to the fifth element value "60" and the sixth position coordinate "5" corresponding to the sixth element value "2" are identical; then the accumulator 4021 outputs the sum "27" of the fifth element value "20" and the sixth element value "7" and the position coordinate "1" corresponding to the sum to the second buffer 404, and outputs the sum "62" of the fifth element value "60" and the sixth element value "2" and the position coordinate "5" corresponding to the sum to the second buffer 404, and outputs the fifth element value "21" and the corresponding position coordinate "2" that do not match the position coordinate, the sixth element values ​​"11" and "14" and the corresponding sixth position coordinates "3" and "4" to the second buffer 404. The final calculation result cached in the second buffer 404 is As shown in the following formula (14).

[0187] Seventh element value = ([27,21,11,14,62])

[0188] The seventh position coordinates = ([1, 2, 3, 4, 5]), formula (14).

[0189] In this embodiment, the computing device can perform a variety of operations on vectors in compressed format, for example, the various operations include addition, multiplication, inner product, and multiplication-addition operations. When the computing device performs operations on two vectors in compressed format, the position coordinates of each element value in the two vectors are compared, and two element values ​​corresponding to the same position coordinates in the two vectors are correlated, thereby obtaining a result vector of the two vectors in compressed format. Compared with the traditional method of first decompressing the vector in compressed format and then performing vector calculation on the decompressed vector, the computing device provided in the embodiment of the present application can effectively improve the computing performance of the vector in compressed format.

[0190] Optionally, see Fig.12As shown, the computing device includes a data cache and queue unit 406, and the cache and queue unit 406 is connected to the position coordinate comparison circuit 401 and the logic operation circuit 402 respectively. When the lengths of the first vector and the second vector are both r×T, r is a positive integer. The position coordinate comparison circuit 401 compares the position coordinates in the first vector and the second vector, and the maximum number of position coordinates that can be matched is r×T, and the maximum number of position coordinates that can be matched is 0. The position coordinate comparison circuit 401 outputs the first vector, the second vector and the first coordinate comparison result to the data cache and queue unit 406, and the data cache and queue unit 406 repacks the first vector and the second vector into a vector of length T. Then the vector of length T and the first coordinate comparison result are output to the logic operation circuit 402, and the logic operation circuit 402 performs vector correlation operations. In this embodiment, the computing device can repack the vector through the data cache and queue unit 406. Even if the input vector length is longer than the vector length that the logic operation circuit can process, the vector length can be adapted to the length that the logic operation circuit can calculate, thereby improving the utilization rate of the computing device.

[0191] The above embodiments provide exemplary explanations of various operations on vectors in compressed format. A matrix in compressed format can be split into multiple vectors in compressed format, so a matrix in compressed format can be regarded as multiple vectors in compressed format. Thus, the above various operations on vectors in compressed format can be extended to the calculation of matrices in compressed format. In a specific embodiment, the computing device in the present application can also be used for matrix calculations. Taking addition as an example, the addition of compressed matrices is exemplified below.

[0192] The position coordinate comparison circuit 401 is used to compare the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain a coordinate comparison result (also referred to as a "second coordinate comparison result" in this embodiment). The first matrix and the second matrix are both compressed matrices.

[0193] As described above for the example of a compressed matrix, each element value in the compressed matrix has a corresponding position coordinate. Fig.13 As shown, Fig.13 A schematic diagram of a matrix in compressed format. Fig.13The dimension of the compressed format matrix F shown in the figure is M×N, and the matrix F has a total of M rows and N columns. The matrix F includes M×N element values, and each element value has a position coordinate, and the position coordinate is used to indicate the position of the corresponding element value in the matrix F′ of the uncompressed format corresponding to the matrix F. The position coordinate includes row coordinates and column coordinates. It should be understood that the row coordinate indicates the "row" where the corresponding element value is located in the uncompressed format matrix F′, and the column coordinate indicates the "column" where the corresponding element value is located in the uncompressed format matrix F′. In the matrix F, the M rows include i in sequence. 0 ,i 1 ,…,i (M-1) These M row coordinates, each row has N columns, and the N columns include j in order. 0 , j 1 , …, j (N-1) These N column coordinates. Taking row 0 as an example, the element values ​​included in row 0 include a 00 , a 01 , …, a 0(N-1) These N element values. The position coordinates of each element value in the N element values ​​in row 0 are as follows: (i 0 ,j 0 ), (i 0 ,j 1 ),…,(i 0 ,j (N-1) ). Similarly, the values ​​of the N elements in the Mth row are: a (M-1)0 , a (M-1)1 , …, a (M-1)(N-1) The position coordinates of each element value in the Mth row are: (i (M-1) ,j 0 ), (i (M-1) ,j 1 ),…,(i (M-1) ,j (N-1) ). For example, the element value a 01 The position coordinates of (i 0 ,j 1 ), if i 0 =1,j 1 =1, it means that the element value a 01 The position in the matrix F' is row 1 and column 1. It should be understood that Fig.13The compressed matrix shown is essentially the same as the compressed matrix in the COO format described above, except that it is expressed in a different form, such as placing element values ​​with the same row coordinates in the same row. For example, the matrix is ​​expressed in the COO format as: (0, 0, 1), (1, 0, 2), (2, 1, 3), (1, 2, 4), (2, 0, 5), (2, 2, 6), (2, 3, 7), (3, 1, 8), (3, 3, 9), (3, 0, 6). When compressing data, the element values ​​in the same row are regarded as the element values ​​in the same row. For example, the row coordinates of the four triplets (0, 1, 3), (0, 0, 5), (0, 2, 6) and (0, 3, 7) are the same, so the element values ​​of these four triplets are placed in the same row, and the element values ​​"3", "5", "6" and "7" are the element values ​​in the same row. The position coordinates of "3" are (0, 1), the position coordinates of "5" are (0, 0), the position coordinates of "6" are (0, 2), the position coordinates of "7" are (0, 3), and so on.

[0194] Exemplarily, the dimension of the first matrix is ​​M×N, the dimension of the second matrix is ​​K×L, and the compression format of the first matrix and the second matrix is ​​described by taking COO as an example. The dimension of the first matrix and the dimension of the second matrix may be the same or different, and there is no specific limitation. For the convenience of explanation, in this embodiment, M, N, K, and L are all described by taking 4 as an example, that is, the dimensions of the first matrix and the second matrix are both 4×4. The first matrix includes a first element value and a first position coordinate of the first element value, wherein the first element value is any element value in the first matrix, and the second matrix includes a second element value and a position coordinate of the second element value, wherein the second element value is any element value in the second matrix. For example, each matrix in the first matrix and the second matrix includes 4 rows, each row contains 4 element values, and each matrix contains 16 element values. Taking the first matrix as an example, the 4 element values ​​of the 0th row are respectively: a 00 , a 01 , a 02 , a 03 Among them, a 00 The position coordinates of (i 0 ,j 0 ), a 01 The position coordinates of (i 0 ,j 1 ), a 02 The position coordinates of (i 0 ,j 2 ), a 03 The position coordinates of (i 0 ,j 3 ), the other element values ​​in the first matrix and the position coordinates corresponding to each element value are not described one by one. Taking the second matrix as an example, the 4 element values ​​of the 0th row are respectively: b00 , b 01 , b 02 , b 03 Among them, b 00 The position coordinates are (k 0 ,l 0 ), b 01 The position coordinates are (k 0 ,l 1 ), b 02 The position coordinates are (k 0 ,l 2 ), b 03 The position coordinates are (k 0 ,l 3 ), the other element values ​​in the second matrix and the position coordinates corresponding to each element value are not described one by one with examples.

[0195] For example, see Fig.14a For understanding, the process of comparing the position coordinates in the two matrices by the position coordinate comparison circuit 401 is illustrated. The position coordinate comparison circuit 401 receives the first matrix and the second matrix from the first buffer 403, and can first compare the row coordinates in the position coordinates in the two matrices. If the row coordinates are equal (or the same), then compare the column coordinates corresponding to the two equal row coordinates. For example, the row coordinates in the 0th row of the first matrix and the second matrix are i and i respectively. 0 and k 0 , if i 0 and k 0 If they are equal, the position coordinate comparison circuit 401 compares the column coordinates (j 0 , j 1 , j 2 , j 3 ) and the column coordinates in row 0 of the second matrix (l 0 , l 1 , l 2 , l 3 ). If j 0 and l 0 If they are equal, then the element value a 00 The position coordinates (i 0 ,j 0 ) and element value b 00 The position coordinates (k 0 ,l 0 ) are the same; if j 0 and l 0 If they are not equal, continue to add j in order. 0 and the next column coordinate l in row 0 of the second matrix 1If the two columns currently being compared have the same coordinates, the position coordinates of the two element values ​​corresponding to the column coordinates are determined to be the same. If the two columns currently being compared have different coordinates, j is continued to be compared. 0 and the next column coordinate l in row 0 of the second matrix 2 The comparison is performed until the column coordinates in the first matrix are compared with all the elements in the 0th row in the second matrix. Here, only the position coordinates in the 0th row in the first matrix and the 0th row in the second matrix are compared for exemplary description, and the comparison of other position coordinates in the two matrices is not given one by one. The coordinate comparison results include at least the following two situations.

[0196] In the first case, the coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same. 0 ,j 1 ) is (0,2), the position coordinates in the second matrix (k 0 ,l 0 ) is (0,2), then the position coordinate (i 0 ,j 1 ) and position coordinates (k 0 ,l 0 ) are equal; for example, the position coordinates (i 1 ,j 0 ) is (1,3), which is consistent with the position coordinates (k 1 ,l 2 ) is also (1,3), then the position coordinate (i 1 ,j 0 ) and position coordinates (k 1 ,l 2 )equal.

[0197] The accumulator 4021 is used to receive the first matrix and the second matrix, and add the first element value and the second element value according to the first comparison result to obtain a result matrix. The result matrix includes a third element value and a third position coordinate of the third element value, the third element value is the sum of the first element value and the second element value, and the third position coordinate is the same as the first position coordinate (or the second position coordinate). The accumulator 4021 writes the third element value and the third position coordinate into the second buffer 404, and the second buffer 404 is used to store the result matrix. For example, refer to Fig.14b As shown, the accumulator 4021 adds the position coordinates (i 0 ,j 1 ) corresponds to the element value a 01 (such as "1") and the position coordinates in the second matrix (k 0 ,l 0 ) corresponds to the element value b00 (such as "2") add, and get the "third element value" (such as "c 00 ”), c 00 (such as "3") The position coordinate is marked as (u 0 ,v 0 ), (u 0 ,v 0 ) is also (0,2). For another example, the accumulator 4021 adds the position coordinate (i 1 ,j 0 ) corresponds to the element value a 10 (such as "2") and the position coordinates in the second matrix (k 1 ,l 2 ) corresponds to the element value b 12 (such as "5") add, and get the "third element value" (such as "c 10 ”), c 10 (such as "7") The position coordinate is marked as (u 1 ,v 0 ), (u 1 ,v 0 ) is also (1, 3) and so on. If each position coordinate in the first matrix can be matched to the same position coordinate in the second matrix, that is, the 16 position coordinates in the first matrix are matched one by one with the 16 position coordinates in the second matrix (equal), then the accumulator 4021 adds the element values ​​with the same position coordinates in the two matrices to obtain a new element value (the third element value), and the third position coordinate does not change relative to the first position coordinate (or the second position coordinate), thereby obtaining the result matrix C1, and each third element value in the result matrix C1 and the third position coordinate corresponding to each third element value are not illustrated one by one.

[0198] Optionally, since each third element value is obtained by adding two element values, the third element value may be a zero element value. In order to save transmission resources or facilitate the next calculation operation, the computing device may compress the result matrix to output a matrix in a compressed format. Exemplarily, the accumulator 4021 is also used to output an invalid signal when the third element value is a zero element value, and the invalid signal indicates that the zero element value and the position coordinates corresponding to the zero element value will not be output to the second buffer 404, so that the result matrix output by the computing device does not contain a zero element value. Please refer to Fig.14c As shown, for example, c 03 , c 13 , c 22 , c 33 All of them are zero element values, and the resulting matrix C2 does not contain these 4 zero element values ​​and the position coordinates corresponding to each zero element value.

[0199] In the second case, the coordinate comparison result also includes a second comparison result, the first matrix includes a fourth element value and a fourth position coordinate of the fourth element value, wherein the fourth element value is any element value in the first matrix. The second comparison result indicates that no position coordinates identical to the fourth position coordinates are matched in the second matrix.

[0200] The accumulator 4021 is further used to write the fourth element value and the fourth position coordinate into the second buffer 404 according to the second comparison result. The second buffer 404 is used to cache the result matrix, and the result matrix includes the fourth element value and the fourth position coordinate corresponding to the fourth element value. It should be understood that in this case, the element values ​​with the same position coordinates in the two matrices are added to obtain the sum of the two element values ​​(the third element value), and the accumulator 4021 writes the position coordinate and the sum into the second buffer 404. The accumulator 4021 retains the position coordinates and the element values ​​corresponding to the position coordinates that do not match in the two matrices, and directly writes the element value (the fourth element value) into the second buffer 404, thereby using the fourth element value as an element value in the result matrix C3. For example, please combine Fig.14d To understand, the element values ​​of the 0th row in the first matrix and the second matrix are used as an example for explanation. The position coordinates of the first 3 columns in the 0th row of the first matrix match (are the same as) the position coordinates of the first 3 columns in the 0th row of the second matrix. For example, the position coordinates (i 0 ,j 0 ) and the position coordinates in the second matrix (k 0 ,l 0 ) are the same, the accumulator will be a 00 and b 00 Add, c 00 for a 00 and b 00 The sum of (u 0 ,v 0 ) and (i 0 ,j 0 ). Similarly, (i 0 ,j 1 ) and (k 0 ,l 1 ) are the same, then the accumulator 4021 will a 01 and b 01 Add, c 01 for a 01 and b 01 The sum of (u 0 ,v 1 ) and (i 0 ,j 1 ) are the same; (i 0 ,j 2 ) and (k 0 ,l2 ) are the same, then the accumulator 4021 will a 02 and b 02 Add, c 02 for a 02 and b 02 The sum of (u 0 ,v 2 ) and (i 0 ,j 2 ) are the same. However, the position coordinates of the 4th column in the 0th row of the first matrix are different from the position coordinates of the 4th column in the 0th row of the second matrix. That is, the position coordinates of the 4th column in the 0th row of the first matrix (i 0 ,j 3 ) does not match the same position coordinates in the second matrix, the accumulator 4021 adds the position coordinates (i 0 ,j 3 ) and the coordinate value corresponding to the position coordinate is written into the second buffer 404, that is, c in the result matrix C3 03 With a in the first matrix 03 Same, c 03 The position coordinates (u 0 ,v 3 ) and a 03 The position coordinates (i 0 ,j 3 ) is the same; similarly, the position coordinates of the 4th column in the 0th row of the second matrix (k 0 ,l 3 ) does not match the same position coordinates in the first matrix, the accumulator 4021 adds the position coordinates (k 0 ,l 3 ) and the coordinate value corresponding to the position coordinate are also written into the second buffer 404, that is, c in the result matrix C3 04 and b in the second matrix 03 Same, c 04 The position coordinates (u 0 ,v 4 ) and b 03 The position coordinates (k 0 ,l 3 ) are the same. Similarly, other element values ​​in the first matrix and the second matrix, and element values ​​in the result matrix C3 are illustrated one by one without further elaboration.

[0201] The following is an example of the structure and function of the position coordinate comparison circuit. Fig.15As shown, the position coordinate comparison circuit 401 may include a row coordinate comparison circuit 4011 and a column coordinate comparison circuit 4012. Among them, the row coordinate comparison circuit 4011 is used to compare which pairs of row coordinates in the first matrix and the second matrix are the same (or equal), and which row coordinates are different, so as to obtain the comparison result of the row coordinates. The column coordinate comparison circuit 4012 is used to compare the two column coordinates in the position coordinates with the same two row coordinates to obtain the comparison result of the column coordinates. In the case of the same row coordinates, if the two column coordinates are the same, the two position coordinates corresponding to the two column coordinates are the same; if the two column coordinates are different, the two position coordinates corresponding to the two column coordinates are different. In this embodiment, the position coordinate comparison circuit does not need to traverse and match each position coordinate in the first matrix with each position coordinate in the second matrix. By first comparing the first coordinates (such as row coordinates) in the first matrix and the second matrix, and then comparing the second coordinates (such as column coordinates) in the position coordinates with the same first coordinates, the number of comparisons of the position coordinates is reduced, saving computing resources.

[0202] It should be understood that in this embodiment, the position coordinate comparison circuit 401 is not limited to comparing the row coordinates first and then the column coordinates, or comparing the column coordinates first and then the row coordinates. For example, in mode A, the first matrix and the second matrix are used to compress the element values ​​corresponding to the same row coordinates to the same row. Each matrix in a compressed format can be regarded as consisting of a plurality of row vectors, and the position coordinate comparison circuit 401 first compares the row coordinates of the two row vectors in the two matrices through the row coordinate comparison circuit 4011. If the row coordinates of the two row vectors are the same, the column coordinates of each element value in the two row vectors are continued to be compared through the column coordinate comparison circuit 4012. For example, in mode B, the first matrix and the second matrix are used to compress the element values ​​corresponding to the same column coordinates to the same column. For example, each matrix in a compressed format can be regarded as consisting of a plurality of column vectors, and the position coordinate comparison circuit 401 first compares the column coordinates of the two column vectors in the two matrices through the row coordinate comparison circuit 4012. If the column coordinates of the two column vectors are the same, the row coordinates of each element value in the two column vectors are continued to be compared through the row coordinate comparison circuit 4011. In this embodiment, the above-mentioned method A is taken as an example for description.

[0203] Exemplarily, the row coordinate comparison circuit 4011 is used to compare the row coordinates of the mth row in the first matrix with the row coordinates of the fth row in the second matrix to obtain a first row comparison result, wherein the first row comparison result indicates that the row coordinates of the mth row are the same as the row coordinates of the fth row; wherein m is an integer less than or equal to M, and f is an integer less than or equal to K. The mth row is any row in the first matrix, and the fth row is any row in the second matrix.

[0204] See also Fig.16b As shown, Fig.16bFIG. 4 is a schematic diagram of row coordinate comparison circuit 4011 performing row coordinate comparison. Row coordinate comparison circuit 4011 receives a first matrix and a second matrix from a first buffer. The four row coordinates in the first matrix are i 0 ,i 1 ,i 2 ,i 3 , the 4 row coordinates in the second matrix are k in sequence 0 , k 1 , k 2 , k 3 The row coordinate comparison circuit 4011 outputs the first row comparison result, which includes the row coordinate comparison result, a first signal (e.g., denoted as "valid"), and a first value (e.g., denoted as "u"). The first signal is used to indicate the validity of the u value. The first value is used to indicate the value of the row coordinate. The first row comparison result indicates that the row coordinates of the mth row are equal to the row coordinates of the fth row. For example, please refer to Fig.16a As shown, the row coordinate comparison result is recorded as: 0 .index_01,index_02), (isequal 1 .index_11,index_12), (isequal 2 .index_21,index_22), (isequal 3 .index_31,index_32). For example, when (isequal 0 .index_01,index_02)=(1,i 0 , k 0 ), it means the row coordinate i of the 0th row in the first matrix 0 and the row coordinate k of row 0 in the second matrix 0 If they are equal, the row coordinate comparison circuit 4011 also outputs valid 0 =1,u 0 , where u 0 and i 0 Equal (i.e. u 0 and k 0 Similarly, when (isequal 1 .index_11,index_12)=(1,i 1 , k 1 ), it means the row coordinate i of the first row in the first matrix 1 and the row coordinate k of the first row 1 Equal, and output valid 1 =1,u 1 , where u 1 and i 1 Equal (i.e. u1 and k 1 Also equal); and so on, the comparison results of the row coordinates are not described one by one. Wherein, valid=1 indicates that the corresponding output u value is valid, and when valid=0 indicates that the corresponding output u value is invalid.

[0205] It should be noted that Fig.16b In the figure, the row coordinate comparison circuit 4011 outputs a total of 8 groups of valid values ​​and u values, and outputs 4 groups of isequal comparison results. The reason why the row coordinate comparison circuit 4011 outputs 8 groups of valid values ​​is that the number of groups and the bit width of the signal output by the row coordinate comparison circuit 4011 are fixed. The row coordinate comparison circuit 4011 receives 4 row coordinates in the first matrix and 4 row coordinates in the second matrix. If the 4 row coordinates in the first matrix and the 4 row coordinates in the second matrix do not match, the number of valid values ​​should be at most 8, so 8 valid output positions can be reserved. The reason why the row coordinate comparison circuit 4011 outputs 4 groups of isequal comparison results is that if the 4 row coordinates in the first matrix and the 4 row coordinates in the second matrix all match one by one, there should be at most 4 groups of row coordinates that all match one by one, so 4 output positions of isequal comparison results can be reserved. Based on the above Fig.16a For example, when i 0 and k 0 When equal, valid 0 =1,u 0 and i 0 equal; when i 1 and k 1 When equal, valid 1 =1,u 1 and i 1 equal; when i 2 and k 2 When equal, valid 2 =1,u 2 and i 2 equal; when i 3 and k 3 When equal, valid 3 =1,u 3 and i 3 That is to say, the 4 row coordinates in the first matrix and the 4 row coordinates in the second matrix have been matched one by one, so valid 4 、valid 5 、valid 6 、valid 7 are equal to 0, used to indicate u 3 、u 4 、u 5 、u6 is an invalid value, u 3 、u 4 、u 5 、u 6 Both can be a preset value (eg, "-1"), which indicates that u is invalid, and the specific value of the preset value is not limited.

[0206] Exemplarily, the row coordinate comparison circuit receives two input arrays as shown below:

[0207] {i 0 ,i 1 ,i 2 ,i 3} = {1, 2, 3, 4};

[0208] {k 0 , k 1 , k 2 , k 3}={1,2,3,4}.

[0209] The results output by the row coordinate comparison circuit are as follows:

[0210] (isequal 0 .index_01,index_02)=(1,i 0 , k 0 );

[0211] (isequal 1 .index_11,index_12)=(1,i 1 , k 1 );

[0212] (isequal 2 .index_21,index_22)=(1,i 2 , k 2 );

[0213] (isequal 3 .index_31,index_32)=(1,i 3 , k 3 );

[0214] (valid 0 ,u 0 ) = (1, 1);

[0215] (valid 1 ,u 1 ) = (1, 2);

[0216] (valid 2 ,u2 ) = (1, 3);

[0217] (valid 3 ,u 3 ) = (1, 4);

[0218] (valid 4 ,u 4 ) = (0, -1);

[0219] (valid 5 ,u 5 ) = (0, -1);

[0220] (valid 6 ,u 6 ) = (0, -1);

[0221] (valid 7 ,u 7 )=(0,-1).

[0222] The column coordinate comparison circuit 4012 is used to compare the column coordinate of each element value in the mth row with the column coordinate of each element value in the fth row according to the first row comparison result to obtain a first column comparison result.

[0223] Exemplarily, the column coordinate comparison circuit 4012 may include a plurality of column coordinate comparison units (such as column coordinate comparison unit a, column coordinate comparison unit b, column coordinate comparison unit c, etc.), each of which is used to compare the column coordinates in two row vectors. The two row vectors may be understood as the vectors in the above embodiment. and vector For example, the mth row in the first matrix can be regarded as a row vector, and the fth row in the second matrix can also be regarded as a row vector. 0 Equal to k 0 , valid 0 =1,u 0 ), the column coordinate comparison unit a compares the column coordinates of the element value in the 0th row of the first matrix with the column coordinates of the element value in the 0th row of the second matrix. For example, the column coordinate comparison unit a reads the column coordinates in the 0th row of the first matrix: 0 , j 1 , j 2 , j 3 ; Column coordinate comparison unit a reads the column coordinate in row 0 of the second matrix: l 0 , l 1 , l 2 , l 3 . Column coordinate comparison unit a to column coordinate (j 0 , j1 , j 2 , j 3 ) and column coordinates (l 0 , l 1 , l 2 , l 3 ) to obtain the comparison result of column coordinates. The representation form of the comparison result of column coordinates is similar to the representation form of the comparison result of row coordinates.

[0224] Exemplarily, the column coordinate comparison circuit 4012 outputs a first column comparison result and / or a second column comparison result. The first column comparison result is used to indicate that the two compared column coordinates are equal, and the second column comparison result is used to indicate that no equal column coordinates are matched. The first column comparison result includes a column coordinate comparison result, a second signal (denoted as "valid'"), and a second numerical value (such as "v"). The second signal is used to indicate the validity of the v value, and the second numerical value is used to indicate the value of the column coordinate. The logic of the column coordinate comparison circuit 4012 for column coordinate comparison is similar to the logic of the row coordinate comparison circuit for row coordinate comparison, and the logic of the row coordinate comparison circuit can be understood by referring to the logic of the row coordinate comparison circuit. Exemplarily, Fig.17a and Fig. 9 To understand, the comparison result of column coordinates is recorded as: (isequal′ 0 .index_01,index_02);(isequal′ 1 .index_11,index_12); (isequal′ 2 .index_21,index_22);(isequal′ 3 .index_31,index_32). The comparison result of the column coordinates indicates which pairs of column coordinates are equal, such as j 0 and l 0 Equal, j 2 and l 1 Equal. And valid′ 3 =1,v 3 =j 3 Instructions 3 is a valid value, and for j 3 , the column coordinate comparison unit a does not match the same column coordinates; similarly, valid′ 4 =1,v 4 = l 2 Instructions 2 is a valid value, and for l 2 , the column coordinate comparison unit a does not match the same column coordinates. That is, the column coordinate comparison unit a matches 2 pairs of equal column coordinates, but there are 4 column coordinates that do not match the same value, then the number of valid values ​​is 6 (valid′0 to valid′ 5 ), and valid′ 6 and valid′ 7 The values ​​of are all 0, which means that v 6 and v 7 is an invalid value (for example, "-1").

[0225] Exemplarily, the column coordinate comparison circuit receives two input arrays as shown below:

[0226] {j 0 , j 1 , j 2 , j 3} = {1, 2, 3, 4};

[0227] {l 0 , l 1 , l 2 , l 3}={1,3,5,7}.

[0228] The results output by the row coordinate comparison circuit are as follows:

[0229] (isequal′ 0 .index_01,index_02)=(1,j 0 , l 0 );

[0230] (isequal′ 1 .index_11,index_12)=(1,j 2 , l 1 );

[0231] (isequal′ 2 .index_21,index_22)=(0,j 1 , l 2 );

[0232] (isequal′ 3 .index_31,index_32)=(0,j 3 , l 3 );

[0233] (valid 0 , v 0 ) = (1, 1);

[0234] (valid 1 , v 1 ) = (1, 2);

[0235] (valid2 , v 2 ) = (1, 3);

[0236] (valid 3 , v 3 ) = (1, 4);

[0237] (valid 4 , v 4 ) = (1, 5);

[0238] (valid 5 , v 5 ) = (1, 7);

[0239] (valid 6 , v 6 ) = (0, -1);

[0240] (valid 7 , v 7 )=(0,-1).

[0241] The above-mentioned result of comparing the column coordinates of two vectors with equal row coordinates (e.g., row 0 in the first matrix and row 0 in the second matrix) by using the column coordinate comparison unit a is exemplarily described. It should be understood that while the column coordinate comparison unit a is performing the column coordinate comparison, other column coordinate comparison units (e.g., column coordinate comparison unit b, column coordinate comparison unit c, etc.) also perform the column coordinate comparison synchronously. For example, if the row coordinates of the first row in the first matrix and the row coordinates of the first row in the second matrix are equal, then the column coordinate comparison unit b can compare the column coordinates of the two row vectors, row 1 in the first matrix and row 1 in the second matrix. The process of comparing the column coordinates by other column coordinate comparison units is similar to the process of comparing the column coordinates by the above-mentioned column coordinate comparison unit a. The descriptions are not repeated one by one here, and only the column coordinate comparison unit a is used to exemplarily describe the comparison of the column coordinates of the 0th row in the first matrix and the 0th row in the second matrix.

[0242] Accumulator 4021 is used to add the element value corresponding to the n-th column coordinate of the m-th row and the element value corresponding to the l-th column coordinate of the f-th row according to the first column comparison result to obtain a third element value, wherein the first column comparison result indicates that the n-th column coordinate of the m-th row is the same as the l-th column coordinate of the f-th row, the element value corresponding to the n-th column coordinate of the m-th row is the first element value, and the element value corresponding to the l-th column coordinate of the f-th row is the second element value, wherein n is less than or equal to N, and l is less than or equal to L.

[0243] As an example, the structure of the above accumulator is described below. Fig.10 As shown, the accumulator 4021 includes a plurality of adders (also referred to as an "adder array"), Fig.10 The size of the adder array shown in the example is 1x4, and the adder array of size 1x4 can support the addition of four arrays (such as (a 0 ,b 0 )、(a 1 ,b 1 )、(a 2 ,b 2 )、(a 3 ,b 3 )), and adds the two values ​​of each of the four arrays, and the adder array outputs the sum of the four arrays (e.g., c 0 、c 1 、c 2 、c 3 ), for example, a 0 +b 0 =c 0 Etc. Similarly, the adder array can be expanded to an adder array of size MxN, such as the adder array expanded to an adder array of size 4x4, etc. The size of the adder array is designed according to actual needs.

[0244] The accumulator 4021 is further used to output the third element value and the third position coordinate of the third element value to the second buffer 404. Optionally, the accumulator 4021 is further used to output the fourth element value that does not match the fourth position coordinate and the fourth position coordinate to the second buffer 404 according to the second column comparison result. Fig.19 and Fig.14b To understand, Fig.19 Schematic diagram of the accumulator 4021 outputting element values ​​to the second buffer according to the first column comparison result and / or the second column comparison result. The size of the second buffer 404 is P×Q, where P is equal to (M+K) and Q is equal to (N+L). In this embodiment, taking the dimensions of the first matrix and the second matrix as M×N as an example, P is equal to 2M and Q is equal to 2N. The accumulator 4021 receives two matrices and coordinate comparison results in compressed format from the position coordinate comparison circuit 401. For example, the accumulator 4021 outputs the ... second result a (such as j 0 and l 1 equal), 00 and b 01 Input to an adder a, adder a adds a 00 and b 01 Add together to get a sum (such as c 00 ), accumulator 4021 will sum the value c 00 And the c 00 The corresponding position coordinates (with a 00The accumulator 4021 outputs the two element values ​​with the same position coordinates to the second buffer 404. That is, the accumulator 4021 inputs the two element values ​​with the same position coordinates to the adder, and the adder obtains the sum value, and then the accumulator 4021 outputs the sum value and the position coordinates corresponding to the sum value to the second buffer 404. 00 The position coordinates of a 00 For example, the second column comparison result a represents the column coordinate l in the second matrix. 0 No equal value is matched in the first matrix, and the accumulator 4021 directly adds b to the value according to the comparison result a in the second column. 00 and the b 00 The position coordinates (k 0 , l 0 ) is output to the second buffer 404. Please combine again Fig.14a and Fig.17b To understand, take the coordinate comparison result of the 0th row in the first matrix and the 0th row in the second matrix as an example, the accumulator 4021 outputs c 0 、c 1 、c 2 、c 3 、c 4 、c 5 and the position coordinates corresponding to the five element values ​​to the second buffer 404. The five element values ​​and the corresponding position coordinates include: 0 and position coordinates (u 0 ,v 0 ), where c 0 Equal to b 00 ,(u 0 ,v 0 ) is equal to (k 0 ,l 0 );c 1 and position coordinates (u 0 ,v 1 ), where c 1 for a 00 and b 01 The sum of (u 0 ,v 1 ) is equal to (i 0 , j 0 );c 2 and position coordinates (u 0 ,v 2 ), where c 2 for a 01 and b 02 The sum of (u 0 ,v 1 ) is equal to (i 0 ,j 1 );c 3 and position coordinates (u0 ,v 3 ), where c 3 for a 02 and b 03 The sum of (u 0 ,v 3 ) is equal to (i 0 ,j 2 ). Optionally, if the above five values ​​are all non-zero element values, the accumulator 4021 outputs a valid signal (such as valid"=1) for each non-zero element value; if there is a zero element value in the above sum, the accumulator 4021 outputs an invalid signal (such as valid"=0) for the zero element value. The second buffer 404 stores multiple element values, the position coordinates corresponding to each element value, and the validity of each element value (valid"=1 or valid"=0). Based on the validity of each element value, the final result matrix does not contain zero element values ​​(zero element values ​​are invalid values).

[0245] Optionally, the comparison result of the row coordinates further includes a second row comparison result, and the second row comparison result indicates that the row coordinates of the wth row in the first matrix are not matched to an equal coordinate value in the second matrix, then the accumulator 4021 is further used to directly output all element values ​​and the position coordinates of each element value in the wth row in the first matrix to the second buffer 404, wherein the wth row is any row in the first matrix. For example, refer to Fig.14a To understand, the row coordinate i in the first matrix 0 and the row coordinate k in the second matrix 0 , k 1 , k 2 and k 3 are not equal, then the accumulator 4021 adds each element value a in the wth row 00 and a 00 The position coordinates (i 0 ,j 0 ), element value a 01 and a 01 The position coordinates (i 0 ,j 1 ), element value a 02 and a 02 The position coordinates (i 0 ,j 2 ), element value a 03 and a 03 The position coordinates (i 0 ,j 3 ) are output to the second buffer 404.

[0246] It should be noted that the precision of the element value and the position coordinate is not limited in the embodiments of the present application, and the element value and the position coordinate can be of any precision. For example, the precision of the element value is double precision FP64, the precision of the position coordinate is int32 precision, etc.

[0247] Optionally, in order to enable the computing device to support the calculation of matrices in multiple compression formats and increase the application scenarios of the computing device, please refer to Fig. 20 As shown, the computing device further includes a format conversion unit 405. The format conversion unit 405 is used to convert a matrix in a non-target compression format into a matrix in a target compression format (COO format). For example, when at least one of the first matrix and the second matrix is ​​in a CSC format or a CSR format, the format conversion unit 405 converts the first matrix and / or the second matrix into a COO format. The function of the format conversion unit 405 can be described by the above Figure 3 Alternatively, the function of the format conversion unit 405 may be implemented by a logic circuit within the computing device.

[0248] Based on the computing device provided in this application, great benefits can be obtained in multiple matrix computing scenarios. For example, the computing device can be used in artificial intelligence (AI) training and reasoning scenarios, which can fully support matrix calculations in compressed formats and matrix calculations in uncompressed formats. The computing device in this application can directly calculate the matrix in compressed format without the need to decompress the matrix in compressed format, so that the computing efficiency can be improved by more than 4 times. In addition, for scenarios such as scientific computing, whether it is a matrix calculation in an uncompressed format with high computing power requirements or a matrix calculation scenario with limited memory bandwidth, the computing device in this application can directly access the matrix in compressed format from the memory, thereby improving the computing benefits.

[0249] An embodiment of a computing device is described above, and a method executed by the computing device is described below. Fig.21 As shown, the present application embodiment provides a calculation method, and the execution subject of the method can be Figure 2 The computing device shown, optionally, the execution subject of the method is Figure 3 The computing device shown in , optionally, the execution subject of the method may be Figure 4 The computing device shown, optionally, the execution subject of the method may be Fig. 20 The computing device shown in the figure is used to execute the following steps 2101 to 2103.

[0250] Step 2101: The computing device obtains a computing instruction, where the computing instruction includes a first vector and a second vector in a compressed format.

[0251] Step 2102: The computing device compares the position coordinates of the element value in the first vector with the position coordinates of the element value in the second vector to obtain a first coordinate comparison result, wherein the first vector includes the first element value and the first position coordinates of the first element value, the second vector includes the second element value and the second position coordinates of the second element value, and the first coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same.

[0252] Step 2103: The computing device operates on the first element value and the second element value according to the first comparison result to obtain an operation value, and outputs the operation result of the first vector and the second vector to a buffer, where the operation result is related to the operation value.

[0253] In an optional implementation, the calculation instruction is an addition instruction, and the calculation device adds the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, wherein the calculation value is the sum value, and the calculation result includes the third element value and the third position coordinates of the third element value, the third element value is the sum value, and the third position coordinates are the same as the first position coordinates.

[0254] Optionally, when the third element value is a zero element value, the computing device outputs an invalid signal for the zero element value, the invalid signal indicating that the element value in the operation result does not include the zero element value and the position coordinates corresponding to the zero element value. The computing device avoids outputting the zero element value and the position coordinates corresponding to the zero element value to the buffer according to the invalid signal.

[0255] In an optional implementation, the first coordinate comparison result also includes the second comparison result, and the first vector includes a fourth element value and a fourth position coordinate of the fourth element value. The computing device outputs the fourth element value and the fourth position coordinate to the buffer according to the second comparison result, and the computing result includes the fourth element value and the fourth position coordinate.

[0256] In an optional implementation, the operation instruction is a multiplication instruction, and the computing device multiplies the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, wherein the product value is the operation value, and the operation result includes the fifth element value and the fifth position coordinates of the fifth element value, the fifth element value is the product value, and the fifth position coordinates are the same as the first position coordinates.

[0257] In an optional implementation, the operation instruction is an inner product instruction, and the computing device multiplies the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the product value is the operation value, and the operation result is the accumulated value of multiple product values.

[0258] In an optional implementation, the operation instruction is a multiplication-addition instruction, and the computing device multiplies the first element value and the second element value according to the first comparison result to obtain a product value of the first element value and the second element value, and the operation value is the product value, and the product value is used as the fifth element value, and the fifth position coordinates corresponding to the fifth element value are the same as the first position coordinates;

[0259] Comparing the sixth position coordinate with the fifth position coordinate to obtain a third comparison result, the third comparison result indicating that the sixth position coordinate is the same as the fifth position coordinate, the sixth position coordinate is a position coordinate in the third vector, and the third vector includes a sixth element value and the sixth position coordinate corresponding to the sixth element value;

[0260] According to the third comparison result, the sixth element value and the fifth element value are added to obtain the sum of the sixth element value and the fifth element value. The calculated value includes the sum of the sixth element value and the fifth element value. The calculation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value. The seventh position coordinate is the same as the sixth position coordinate.

[0261] In an optional implementation, the operation instruction includes a first matrix and a second matrix in a compressed format, the first matrix includes a first vector, and the second matrix includes a second vector.

[0262] The computing device is also used to compare the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result, and the second coordinate comparison result includes the first coordinate comparison result.

[0263] In an optional implementation, the dimension of the first matrix is ​​M×N, and the dimension of the second matrix is ​​K×L; comparing the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result may include the following steps:

[0264] Compare the row coordinates of the mth row in the first matrix with the row coordinates of the fth row in the second matrix to obtain a row comparison result, the row comparison result indicating that the row coordinates of the mth row and the fth row are the same, wherein m is less than or equal to M, and f is less than or equal to K;

[0265] Compare the column coordinates of each element value in the mth row and the column coordinates of each element value in the fth row according to the row comparison result to obtain a column comparison result, wherein the column comparison result indicates that the nth column coordinate of the mth row is the same as the lth column coordinate of the fth row, and the first comparison result includes the row comparison result and the column comparison result;

[0266] According to the first comparison result, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row are added to obtain the third element value, the element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, where n is less than or equal to N, and l is less than or equal to L.

[0267] See also Fig. 22 As shown, the present application also provides a calculation method, the execution subject of the method can be Figure 2 The computing device shown, optionally, the execution subject of the method is Figure 3 The computing device shown in , optionally, the execution subject of the method may be Figure 4 The computing device shown, optionally, the execution subject of the method may be Fig. 20 The computing device shown in the figure. The method includes the following steps 2201 to 2204.

[0268] Step 2201: Obtain a calculation instruction, where the calculation instruction includes a first matrix and a second matrix in a compressed format.

[0269] For the first matrix and the second matrix in this step, please refer to the exemplary description of the first matrix and the second matrix in the aforementioned device embodiment, which will not be repeated here.

[0270] Step 2202, compare the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain a coordinate comparison result, the first matrix includes the first element value and the first position coordinates of the first element value, the second matrix includes the second element value and the second position coordinates of the second element value, the coordinate comparison result includes a first comparison result, and the first comparison result is used to indicate that the first position coordinate and the second position coordinate are the same.

[0271] For this step, please refer to the detailed description of the function performed by the position coordinate comparison circuit 401 in the above-mentioned embodiment of the computing device, which will not be repeated here.

[0272] Optionally, the dimension of the first matrix is ​​M×N, the dimension of the second matrix is ​​K×L, and the position coordinates of the element values ​​in the first matrix are compared with the position coordinates of the element values ​​in the second matrix to obtain the coordinate comparison result, including:

[0273] Compare the row coordinates of the mth row in the first matrix with the row coordinates of the fth row in the second matrix to obtain a first row comparison result, the first row comparison result indicating that the row coordinates of the mth row and the fth row are the same; wherein m is less than or equal to M, and f is less than or equal to K;

[0274] According to the first row comparison result, the column coordinates of each element value in the mth row and the column coordinates of each element value in the fth row are compared to obtain the first column comparison result, which indicates that the nth column coordinate of the mth row is the same as the lth column coordinate of the fth row.

[0275] Step 2203: add the first element value and the second element value according to the first comparison result to obtain a result matrix, wherein the result matrix includes a third element value and a third position coordinate of the third element value, the third element value is the sum of the first element value and the second element value, and the third position coordinate is the same as the first position coordinate.

[0276] For this step, please refer to the specific description of the function performed by the accumulator 4021 in the above-mentioned computing device embodiment, which will not be repeated here.

[0277] Optionally, according to the comparison result of the first column, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row are added to obtain a third element value, the element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, where n is less than or equal to N, and l is less than or equal to L.

[0278] In an optional implementation, when the third element value is a zero element value, the computing device outputs an invalid signal for the zero element value, and the invalid signal indicates that the element values ​​in the result matrix do not include a zero element value.

[0279] In an optional implementation, the coordinate comparison result also includes a second comparison result, the first matrix includes a fourth element value and a fourth position coordinate of the fourth element value, and the second comparison result is used to indicate that a position coordinate identical to the fourth position coordinate is not matched in the second matrix. The matrix calculation method may also include the following step 2204.

[0280] Step 2204: output the fourth element value and the fourth position coordinate to a buffer according to the second comparison result. The buffer is used to buffer a result matrix including the fourth element value and the fourth position coordinate.

[0281] It should be noted that there is no time sequence limitation for the above steps 2203 and 2204, and steps 2203 and 2204 can be executed simultaneously.

[0282] In one embodiment of the present application, a computing circuit is provided, and the computing circuit is used in one or more steps of steps 2201 to 2204 in the above method embodiment, or one or more steps of steps 2101 to 2103. In practical applications, the computing circuit can be an ASIC, an FPGA, or a logic circuit.

[0283] In another embodiment of the present application, a computing system or chip is also provided. The structure of the system or chip can be as follows: Figure 3 As shown, it includes: a processor (taking a central processing unit as an example) 1 and a computing device 1. The processor 1 is used to send a computing instruction to the computing device 1, and the computing device 2 is used to execute one or more steps of steps 2201 to 2204 in the above method embodiment, or one or more steps of steps 2101 to 2103.

[0284] In another embodiment of the present application, a computing device is provided, the structure of which can be as follows: Figure 2 As shown, the device may specifically be a PCIe card, a SoC, a processor, and a server including the above hardware. Figure 2 The device includes: a memory 201, a processor 202, a communication interface 203 and a bus 204. The communication interface 203 may include an input interface and an output interface.

[0285] Among them, the processor 202 can be configured to perform one or more steps of steps 2201-step 2204 in the above method embodiment, or one or more steps of steps 2101-step 2103. In some feasible embodiments, the processor 202 may include a computing unit, which can be used to support the processor to perform one or more steps in the above method embodiment. In practical applications, the computing unit can be an ASIC, FPGA or logic circuit, etc. Of course, the computing unit can also be implemented by software, and the embodiments of the present application do not specifically limit this.

[0286] It should be noted that the various components of the above-mentioned computing circuit, computing system, computing device, etc. provided in the embodiments of the present application are respectively used to implement the functions of the corresponding steps of the aforementioned method embodiments.

[0287] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0288] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A computing device, characterized in that: include: Position coordinate comparison circuit and logic operation circuit; The position coordinate comparison circuit is used to compare the position coordinates of the element value in the first vector and the position coordinates of the element value in the second vector to obtain a first coordinate comparison result, wherein the first vector and the second vector are both vectors in a compressed format, the first vector includes a first element value and a first position coordinate of the first element value, and the second vector includes a second element value and a second position coordinate of the second element value; When the first coordinate comparison result is a first comparison result indicating that the first position coordinate and the second position coordinate are the same, the logic operation circuit is used to operate on the first element value and the second element value to obtain an operation value, and output the operation results of the first vector and the second vector to a cache, and the operation results are related to the operation value.

2. The computing device according to claim 1, wherein: The logic operation circuit includes an accumulator; The position coordinate comparison circuit is further used to receive an addition instruction, and transmit the first comparison result to the accumulator according to the addition instruction; The accumulator is used to add the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, and the sum is the calculation value, wherein the calculation result includes a third element value and a third position coordinate of the third element value, the third element value is the sum, and the third position coordinate is the same as the first position coordinate.

3. The computing device according to claim 2, characterized in that The accumulator is further used to output an invalid signal for the zero element value when the third element value is a zero element value, wherein the invalid signal indicates that the element value in the result matrix does not include the zero element value and the position coordinates corresponding to the zero element value.

4. The computing device according to claim 3, characterized in that The accumulator does not output the zero element value and the position coordinates corresponding to the zero element value to the buffer according to the invalid signal.

5. The computing device according to claim 2, characterized in that The first vector includes a fourth element value and a fourth position coordinate of the fourth element value, and the first coordinate comparison result also includes a second comparison result, and the second comparison result is used to indicate that a position coordinate identical to the fourth position coordinate is not matched in the second vector; The accumulator is further used to output the fourth element value and the fourth position coordinate to the buffer according to the second comparison result, and the operation result includes the fourth element value and the fourth position coordinate.

6. The computing device according to claim 1, wherein: The logic operation circuit includes a multiplier; The position coordinate comparison circuit is further used to receive a multiplication instruction, and transmit the first comparison result to the multiplier according to the multiplication instruction; The multiplier is used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the product value is the calculation value, the calculation result includes the fifth element value and the fifth position coordinates of the fifth element value, the fifth element value is the product value, and the fifth position coordinates are the same as the first position coordinates.

7. The computing device according to claim 1, wherein: The logic operation circuit includes an inner product operation circuit; The position coordinate comparison circuit is further used to receive an inner product instruction, and transmit the first comparison result to the inner product operation circuit according to the inner product instruction; The inner product operation circuit is used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the product value is the operation value, and the operation result is the accumulated value of multiple product values.

8. The computing device according to claim 1, wherein: The logic operation circuit includes a multiplier and an accumulator, and the first coordinate comparison result also includes a third comparison result; The position coordinate comparison circuit is further used to receive a multiplication and addition calculation instruction, and transmit the first comparison result to the multiplier according to the multiplication and addition calculation instruction; The multiplier is further used for multiplying the first element value and the second element value according to the first comparison result to obtain a product value of the first element value and the second element value, the operation value includes the product value, the product value is a fifth element value, and the fifth position coordinate is the same as the first position coordinate; The position coordinate comparison circuit is further used for comparing the sixth position coordinate with the fifth position coordinate to obtain a third comparison result, and transmitting the third comparison result to the accumulator, wherein the third comparison result indicates that the sixth position coordinate is the same as the fifth position coordinate, the sixth position coordinate is a position coordinate in a third vector, and the third vector includes a sixth element value and the sixth position coordinate corresponding to the sixth element value; The accumulator is used to add the sixth element value and the fifth element value according to the third comparison result to obtain the sum of the sixth element value and the fifth element value, the calculation value includes the sum of the sixth element value and the fifth element value, the calculation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value, the seventh element value is the sum of the sixth element value and the fifth element value, and the seventh position coordinate is the same as the sixth position coordinate.

9. The computing device according to any one of claims 1 to 8, characterized in that: The position coordinate comparison circuit is also used to compare the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result, wherein the first matrix includes the first vector, the second matrix includes the second vector, the first matrix and the second matrix are both matrices in compressed format, and the second coordinate comparison result includes the first coordinate comparison result.

10. The computing device according to claim 9, characterized in that The position coordinate comparison circuit includes a row coordinate comparison circuit and a column coordinate comparison circuit; the dimension of the first matrix is ​​M×N, and the dimension of the second matrix is ​​K×L; The row coordinate comparison circuit is used to compare the row coordinates of the m-th row in the first matrix with the row coordinates of the f-th row in the second matrix to obtain a row comparison result, wherein the row comparison result indicates that the row coordinates of the m-th row are the same as the row coordinates of the f-th row, wherein m is less than or equal to M, and f is less than or equal to K; The column coordinate comparison circuit is used to compare the column coordinates of each element value in the m-th row and the column coordinates of each element value in the f-th row according to the row comparison result to obtain a column comparison result, wherein the column comparison result indicates that the n-th column coordinate of the m-th row is the same as the l-th column coordinate of the f-th row, and the first comparison result includes the row comparison result and the column comparison result; The accumulator is further used to add the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row according to the first comparison result to obtain the third element value, the element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, wherein n is less than or equal to N, and l is less than or equal to L.

11. The computing device according to claim 10, characterized in that The row comparison result includes a first signal and a first numerical value, and the column comparison result includes a second signal and a second numerical value, wherein the first signal is used to indicate the validity of the first numerical value, and the first numerical value is equal to the value of the row coordinate of the mth row, and the second signal is used to indicate the validity of the second numerical value, and the second numerical value is equal to the nth column coordinate.

12. A calculation method, characterized in that: The method is applied to a computing device, and the method comprises: Obtaining a computation instruction, the computation instruction including a first vector and a second vector in a compressed format; Comparing the position coordinates of the element value in the first vector and the position coordinates of the element value in the second vector to obtain a first coordinate comparison result, wherein the first vector includes a first element value and a first position coordinate of the first element value, and the second vector includes a second element value and a second position coordinate of the second element value; When the first coordinate comparison result is a first comparison result indicating that the first position coordinate and the second position coordinate are the same, the first element value and the second element value are operated to obtain an operation value, and the operation results of the first vector and the second vector are output to a cache, and the operation results are related to the operation value.

13. The method according to claim 12, characterized in that The calculation instruction is an addition instruction, and the operation on the first element value and the second element value according to the first comparison result to obtain an operation value includes: The first element value and the second element value are added according to the first comparison result to obtain the sum of the first element value and the second element value, wherein the calculated value is the sum, and the calculated result includes a third element value and a third position coordinate of the third element value, the third element value is the sum, and the third position coordinate is the same as the first position coordinate.

14. The method according to claim 13, characterized in that The method further comprises: When the third element value is a zero element value, an invalid signal is output for the zero element value, wherein the invalid signal indicates that the element value in the calculation result does not include the zero element value and the position coordinates corresponding to the zero element value.

15. The method according to claim 14, characterized in that The method further comprises: Avoid outputting the zero element value and the position coordinates corresponding to the zero element value to the buffer according to the invalid signal.

16. The method according to claim 13, characterized in that The first coordinate comparison result also includes a second comparison result, the first vector includes a fourth element value and a fourth position coordinate of the fourth element value, and the second comparison result is used to indicate that a position coordinate identical to the fourth position coordinate is not matched in the second vector; the method further includes: According to the second comparison result, the fourth element value and the fourth position coordinate are output to the register, and the operation result includes the fourth element value and the fourth position coordinate.

17. The method according to claim 12, characterized in that The operation instruction is a multiplication instruction, and the operation is performed on the first element value and the second element value according to the first comparison result to obtain an operation value, including: The first element value and the second element value are multiplied according to the first comparison result to obtain a product value of the first element value and the second element value, wherein the product value is the calculation value, and the calculation result includes a fifth element value and a fifth position coordinate of the fifth element value, the fifth element value is the product value, and the fifth position coordinate is the same as the first position coordinate.

18. The method according to claim 12, characterized in that The operation instruction is an inner product instruction, The first element value and the second element value are multiplied according to the first comparison result to obtain a product value of the first element value and the second element value, the product value is the calculation value, and the calculation result is the accumulated value of multiple product values.

19. The method according to claim 12, characterized in that The operation instruction is a multiplication-addition instruction, the first coordinate comparison result also includes a third comparison result; and the operation on the first element value and the second element value according to the first comparison result to obtain an operation value includes: According to the first comparison result, the first element value and the second element value are multiplied to obtain a product value of the first element value and the second element value, the operation value is the product value, the product value is used as the fifth element value, and the fifth position coordinates corresponding to the fifth element value are the same as the first position coordinates; Comparing the sixth position coordinate with the fifth position coordinate to obtain a third comparison result, wherein the third comparison result indicates that the sixth position coordinate is the same as the fifth position coordinate, the sixth position coordinate is a position coordinate in a third vector, and the third vector includes a sixth element value and the sixth position coordinate corresponding to the sixth element value; The sixth element value and the fifth element value are added according to the third comparison result to obtain the sum of the sixth element value and the fifth element value, the calculated value includes the sum of the sixth element value and the fifth element value, the calculated result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value, the seventh element value is the sum of the sixth element value and the fifth element value, and the seventh position coordinate is the same as the sixth position coordinate.

20. The method according to any one of claims 12 to 19, characterized in that The operation instruction includes a first matrix and a second matrix in a compressed format, the first matrix includes the first vector, the second matrix includes the second vector, and the comparing the position coordinates of the element value in the first vector with the position coordinates of the element value in the second vector to obtain a first comparison result includes: The position coordinates of the element values ​​in the first matrix are compared with the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result, wherein the second coordinate comparison result includes the first coordinate comparison result.

21. The method according to claim 20, characterized in that The dimension of the first matrix is ​​M×N, and the dimension of the second matrix is ​​K×L; comparing the position coordinates of the element values ​​in the first matrix with the position coordinates of the element values ​​in the second matrix to obtain the second coordinate comparison result includes: Comparing the row coordinates of the m-th row in the first matrix with the row coordinates of the f-th row in the second matrix to obtain a row comparison result, wherein the row comparison result indicates that the row coordinates of the m-th row are the same as the row coordinates of the f-th row, wherein m is less than or equal to M, and f is less than or equal to K; Comparing the column coordinates of each element value in the m-th row and the column coordinates of each element value in the f-th row according to the row comparison result to obtain a column comparison result, wherein the column comparison result indicates that the n-th column coordinate of the m-th row is the same as the l-th column coordinate of the f-th row, and the first comparison result includes the row comparison result and the column comparison result; According to the first comparison result, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row are added to obtain the third element value, the element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, wherein n is less than or equal to N, and l is less than or equal to L.

22. The method according to claim 21, characterized in that The row comparison result includes a first signal and a first numerical value, and the column comparison result includes a second signal and a second numerical value, wherein the first signal is used to indicate the validity of the first numerical value, and the first numerical value is equal to the value of the row coordinate of the mth row, and the second signal is used to indicate the validity of the second numerical value, and the second numerical value is equal to the nth column coordinate.

23. A computing circuit, characterized in that: The computing circuit is configured to execute the method according to any one of claims 12 to 22.

24. A computing system, characterized in that: The system comprises a processor and a computing device, wherein the processor is used to send computing instructions to the computing device, and the computing device is used to execute the method according to any one of claims 12 to 22.

25. A chip, characterized in that: The chip comprises a processor, in which a computing device is integrated, and the computing device is used to execute the computing method as claimed in any one of claims 12 to 22.

26. A matrix computing device, characterized in that: The device comprises the computing system of claim 24 or the chip of claim 25.

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