A computing device, method, system, circuit, chip, and apparatus

Abstract

This application discloses a computing device, method, system, circuit, chip, and apparatus that can directly perform calculations on compressed vectors, thereby improving the computational performance of compressed vectors. The computing device includes: a position coordinate comparison circuit and a logic operation circuit. The position coordinate comparison circuit compares the position coordinates of element values ​​in a first vector and the position coordinates of element values ​​in a second vector to obtain a coordinate comparison result. The logic operation circuit performs operations on the first and second element values ​​based on the first comparison result to obtain an operation value, and outputs the operation result to a buffer. The operation result is related to the operation value. Compared to the traditional method that requires decompressing the compressed vector first and then performing vector calculations on the decompressed vector, this method effectively improves the computational performance of compressed vectors.

Description

[0001] This application is a divisional application. The original application, application number 202111349874.4, was filed on November 15, 2021. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computers, and more particularly to a computing device, method, system, circuit, chip, and apparatus. Background Technology

[0003] Vector computation is an important type of computation in various application scenarios such as artificial intelligence, scientific computing, and graphics computing. The element values ​​in a vector may include both zero and non-zero values. When a vector has a large number of zero values, in order to save storage space, only the non-zero values ​​in the vector can be stored, that is, the vector is compressed and stored in a compressed format.

[0004] In current technology, the common method for calculating compressed vectors is to first decompress the compressed vectors, that is, to convert them into uncompressed vectors, and then perform vector calculations on the uncompressed vectors. During vector calculation, because the decompression operation is required, and the decompressed data occupies a very large amount of memory, the calculation speed is limited by memory access bandwidth. With a fixed memory access bandwidth, the calculation speed cannot be improved, resulting in low computational efficiency. Summary of the Invention

[0005] This application provides a computing device, method, system, circuit, chip, and apparatus that can directly perform calculations on compressed vectors without decompressing them, thereby improving the computational performance of compressed matrices.

[0006] In a first aspect, embodiments of this application provide a computing device, including: a position coordinate comparison circuit and a logic operation circuit; wherein, the position coordinate comparison circuit is used to compare the position coordinates of element values ​​in a first vector and the position coordinates of element values ​​in a second vector to obtain a first coordinate comparison result, wherein the first vector and the second vector are both compressed vectors, the first vector includes a first element value and a first position coordinate of the first element value, the second vector includes a second element value and a second position coordinate of the second element value, and the first coordinate comparison result includes a first comparison result, which is used to indicate that the first position coordinates and the second position coordinates are the same; the logic operation circuit is used to perform operations on the first element value and the second element value according to the first comparison result to obtain an operation value, and output the operation result to a buffer, the buffer being used to cache the operation result, and the operation result being related to the operation value. In this embodiment, the computing device can perform calculations on compressed vectors. When calculating two compressed vectors, the computing device compares the position coordinates of each element value in the two vectors, adds the two element values ​​corresponding to the same position coordinates in the two vectors, and thus obtains the calculation result of the two compressed vectors. Compared with the traditional method that requires decompressing the compressed vectors first and then performing vector calculations on the decompressed vectors, the computing device provided in this embodiment can effectively improve the calculation efficiency of compressed vectors.

[0007] In one optional implementation, the logic operation circuit includes an accumulator; a position coordinate comparison circuit, further configured to receive an addition instruction and transmit a first comparison result to the accumulator according to the addition instruction; the accumulator, configured to add the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, and output the sum to a buffer, wherein the operation result includes a third element value and the third position coordinate of the third element value, the third element value is the sum, the third position coordinate is the same as the first position coordinate, and the operation result is the result vector after adding the first vector and the second vector. In this embodiment, the computing device can perform addition operations on compressed format vectors, and the computing device can be applied to application scenarios of vector addition calculation.

[0008] In an optional implementation, the accumulator is further configured to output an invalid signal when the third element is zero, indicating that the elements in the result matrix do not contain zero values ​​and their corresponding coordinates. In this embodiment, each third element is obtained by adding two element values, so the third element may be zero. The accumulator is also configured to delete the zero value and its corresponding coordinates when the third element is zero, so that the calculation result output by the computing device does not contain zero values, thus outputting a compressed vector, thereby saving transmission resources or facilitating subsequent calculation operations.

[0009] In one alternative implementation, the accumulator does not output the zero element value and its corresponding position coordinates to the buffer based on the invalid signal, thereby preventing the buffer from caching the zero element value and its corresponding position coordinates, thus achieving the goal of not including the zero element value in the calculation result.

[0010] In an optional implementation, the first coordinate comparison result further includes a second comparison result. The first vector includes a fourth element value and the fourth position coordinate of the fourth element value. The second comparison result is used to indicate that no position coordinate matching the fourth position coordinate is found in the second vector. The accumulator is also used to output the fourth element value and the fourth position coordinate to a buffer based on the second comparison result. The calculation result includes the fourth element value and the fourth position coordinate. In this embodiment, the accumulator retains the position coordinates that do not match in the two vectors and the element value corresponding to those position coordinates, and directly writes them into the buffer. Thus, the fourth element value is used as an element value in the calculation result. Even if multiple position coordinates in the first vector and multiple position coordinates in the second vector cannot be completely matched one-to-one, the computing device can still perform addition calculations, increasing the vector calculation scenarios.

[0011] In one optional implementation, the logic operation circuit includes a multiplier; a position coordinate comparison circuit, further configured to receive a multiplication instruction and transmit a first comparison result to the multiplier according to the multiplication instruction; the multiplier, configured to multiply a first element value and a second element value according to the first comparison result to obtain the product of the first element value and the second element value, the product value being the aforementioned operational value, and the operational result including a fifth element value and the fifth position coordinate of the fifth element value, the fifth element value being the product value, and the fifth position coordinate being the same as the first position coordinate. In this embodiment, the computing device can perform multiplication operations on compressed format vectors, and the computing device can be applied to application scenarios of vector multiplication calculations.

[0012] In one optional implementation, the logic operation circuit includes an inner product operation circuit; a position coordinate comparison circuit, further configured to receive an inner product instruction and transmit a first comparison result to the inner product operation circuit according to the inner product instruction; the inner product operation circuit is configured to multiply a first element value and a second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the product value being the above-mentioned operation value, and the operation result being the sum of multiple product values, each product value being the product of a first element value and a second element value, and the operation result of the inner product of the first vector and the second vector is a scalar (a numerical value). In this embodiment, the computing device can perform inner product operations on compressed vectors, and the computing device can be applied to application scenarios of inner product calculation of vectors.

[0013] In one optional implementation, the logic operation circuit includes a multiplier and an accumulator, and the first coordinate comparison result also includes a third comparison result; the position coordinate comparison circuit is further used to receive a multiplication-addition calculation instruction and transmit the first comparison result to the multiplier according to the multiplication-addition calculation instruction; the multiplier is further used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, and obtain the fifth element value and the fifth position coordinate of the fifth element value, the fifth position coordinate being the same as the first position coordinate; the position coordinate comparison circuit is further used to compare the sixth position coordinate with the fifth position coordinate to obtain the third comparison result, and transmit the third comparison result to the accumulator. The system includes an adder, where the third comparison result indicates that the sixth and fifth position coordinates are the same. The sixth position coordinate is the position coordinate in the third vector, which includes the sixth element value and its corresponding sixth position coordinate. An accumulator is used to add the sixth and fifth element values ​​according to the third comparison result, obtaining a sum of the sixth and fifth element values. The calculated value includes the product of the first and second element values, and the sum of the sixth and fifth element values. The result includes a seventh element value and its corresponding seventh position coordinate. The seventh element value is the sum of the sixth and fifth element values, and its seventh position coordinate is the same as the sixth position coordinate. In this embodiment, the computing device can perform multiplication and addition operations on compressed vectors, and can be applied to vector multiplication and addition calculation scenarios.

[0014] In an optional implementation, the first coordinate comparison result further includes a fourth comparison result. The third vector includes an eighth element value and the eighth position coordinate of the eighth element value. The fourth comparison result is used to indicate that no position coordinate matching the eighth position coordinate is found in the third vector. The accumulator is also used to output the eighth element value and the eighth position coordinate to a buffer based on the fourth comparison result. The calculation result includes the eighth element value and the eighth position coordinate. In this embodiment, the accumulator retains the unmatched position coordinates in the two vectors and the element value corresponding to those position coordinates, and directly writes them into the buffer. Thus, the eighth element value is used as an element value in the calculation result. Even if multiple position coordinates in the third vector and multiple position coordinates in the result vector (i.e., the result vector after multiplying the first and second vectors) cannot be completely matched one-to-one, the computing device can still perform addition calculations, increasing the vector calculation scenarios.

[0015] In an optional implementation, the position coordinate comparison circuit is further used to compare the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result. The first matrix includes a first vector, the second matrix includes a second vector, both the first and second matrices are compressed matrices, and the second coordinate comparison result includes the first coordinate comparison result. In this embodiment, the compressed matrix can be decomposed into multiple compressed vectors; therefore, a compressed matrix can be considered as multiple compressed vectors. Thus, the aforementioned operations on compressed vectors can be extended to the calculation of compressed matrices. The computing device can perform operations on two compressed matrices, thereby increasing the application scenarios of the computing device and effectively improving the computational performance of compressed vectors.

[0016] In one optional implementation, the position coordinate comparison circuit includes a row coordinate comparison circuit and a column coordinate comparison circuit; the first matrix has a dimension of M×N, and the second matrix has a dimension of K×L; the row coordinate comparison circuit is used to compare the row coordinates of the m-th row in the first matrix and the row coordinates of the f-th row in the second matrix to obtain a row comparison result, which indicates that the row coordinates of the m-th row and the row coordinates of the f-th row are the same, where m is less than or equal to M, and f is less than or equal to K;

[0017] The column coordinate comparison circuit is used to compare the column coordinates of each element value in row m with the column coordinates of each element value in row f based on the row comparison results, and obtain the column comparison results. The column comparison results indicate that the nth column coordinate of row m is the same as the lth column coordinate of row f. The first comparison result includes the row comparison result and the column comparison result. The accumulator is also used to add the element value corresponding to the nth column coordinate of row m and the element value corresponding to the lth column coordinate of row f based on the first comparison results, and obtain the third element value. The element value corresponding to the nth column coordinate of row m is the first element value, and the element value corresponding to the lth column coordinate of row f is the second element value, where n is less than or equal to N, and l is less than or equal to L. In this embodiment, the position coordinate comparison circuit does not need to traverse and match each position coordinate in the first matrix with each position coordinate in the second matrix. By first comparing the row coordinates in the first matrix and the second matrix through the row coordinate comparison circuit, and then comparing the column coordinates of the position coordinates with the same row coordinates, the number of position coordinate comparisons is reduced, saving computational resources.

[0018] In one optional implementation, the row alignment result includes a first signal and a first value, and the column alignment result includes a second signal and a second value, wherein the first signal is used to indicate the validity of the first value, which is equal to the value of the row coordinate of the m-th row, and the second signal is used to indicate the validity of the second value, which is equal to the value of the aforementioned n-th column coordinate.

[0019] Secondly, embodiments of this application provide a calculation method applied to a computing device, the method comprising:

[0020] Obtain calculation instructions, which include a first vector and a second vector in compressed format; compare the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector to obtain a first coordinate comparison result, wherein the first vector includes a first element value and a first position coordinate of the first element value, the second vector includes a second element value and a second position coordinate of the second element value, and the first coordinate comparison result includes a first comparison result, which is used to indicate that the first position coordinates and the second position coordinates are the same; perform operations on the first element value and the second element value according to the first comparison result to obtain an operation value, and output the operation result of the first vector and the second vector to a buffer, wherein the operation result is related to the operation value.

[0021] In one optional implementation, the above calculation instruction is an addition instruction. The above operation on the first element value and the second element value according to the first comparison result to obtain the operation value may include: adding the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, wherein the operation value is the sum value, and the operation result includes the third element value and the third position coordinate of the third element value, the third element value is the sum value, and the third position coordinate is the same as the first position coordinate.

[0022] In an optional implementation, the method further includes: when the third element value is zero, outputting an invalid signal for the zero element value, the invalid signal indicating that the element values ​​in the calculation result do not include the zero element value and the position coordinates corresponding to the zero element value.

[0023] In an alternative implementation, the method further includes: avoiding outputting zero element values ​​and the corresponding position coordinates to the buffer based on invalid signals.

[0024] In an optional implementation, the first coordinate comparison result further includes a second comparison result. The first vector includes a fourth element value and a fourth position coordinate of the fourth element value. The second comparison result is used to indicate that no position coordinate matching the fourth position coordinate is found in the second vector. The method further includes: outputting the fourth element value and the fourth position coordinate to a buffer based on the second comparison result, and the calculation result includes the fourth element value and the fourth position coordinate.

[0025] In one optional implementation, the operation instruction is a multiplication instruction. The operation on the first element value and the second element value based on the first comparison result to obtain the operation value may include: multiplying the first element value and the second element value based on the first comparison result to obtain the product value of the first element value and the second element value, wherein the product value is the operation value, and the operation result includes the fifth element value and the fifth position coordinate of the fifth element value, the fifth element value is the product value, and the fifth position coordinate is the same as the first position coordinate.

[0026] In one optional implementation, the above-mentioned operation instruction is an inner product instruction, which multiplies the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value. This product value is the above-mentioned operation value, and the operation result is the sum of multiple product values.

[0027] In an optional implementation, the above-mentioned operation instruction is a multiply-add instruction, and the first coordinate comparison result also includes a third comparison result; the first element value and the second element value are operated on according to the first comparison result to obtain the operation value, including:

[0028] Based on the first comparison result, the first element value and the second element value are multiplied to obtain the product value of the first element value and the second element value. The product value is used as the fifth element value. The fifth position coordinate corresponding to the fifth element value is the same as the first position coordinate. The sixth position coordinate is compared with the fifth position coordinate to obtain the third comparison result. The third comparison result is transmitted to the accumulator. The third comparison result indicates that the sixth position coordinate and the fifth position coordinate are the same. The sixth position coordinate is the position coordinate in the third vector. The third vector includes the sixth element value and the sixth position coordinate corresponding to the sixth element value.

[0029] Based on the third comparison result, the sixth element value and the fifth element value are added together to obtain the sum of the sixth element value and the fifth element value. The operation value includes the sum of the sixth element value and the fifth element value. The operation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value, and the seventh position coordinate is the same as the sixth position coordinate.

[0030] In one optional implementation, the above-mentioned operation instructions include a first matrix and a second matrix in compressed format. The first matrix includes a first vector, and the second matrix includes a second vector. The comparison of the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector to obtain a first comparison result may include: comparing the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result. The second coordinate comparison result includes the first coordinate comparison result.

[0031] In one optional implementation, the first matrix has a dimension of M×N, and the second matrix has a dimension of K×L. The comparison of the position coordinates of elements in the first matrix and the second matrix to obtain the second coordinate comparison result may include: comparing the row coordinates of the m-th row in the first matrix and the row coordinates of the f-th row in the second matrix to obtain a row comparison result. The row comparison result indicates that the row coordinates of the m-th row and the f-th row are the same, where m is less than or equal to M, and f is less than or equal to K; and based on the row comparison result, the column coordinates of each element value in the m-th row and the column coordinates of the f-th row are compared. The column coordinates of each element value are compared to obtain the column comparison result. The column comparison result indicates that the nth column coordinate of the mth row is the same as the lth column coordinate of the fth row. The first comparison result includes the row comparison result and the column comparison result. Based on the first comparison result, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row are added to obtain the third element value. The element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, where n is less than or equal to N and l is less than or equal to L.

[0032] In one optional implementation, the row alignment result includes a first signal and a first value, and the column alignment result includes a second signal and a second value, wherein the first signal is used to indicate the validity of the first value, which is equal to the row coordinate of the m-th row, and the second signal is used to indicate the validity of the second value, which is equal to the column coordinate of the n-th column.

[0033] Thirdly, embodiments of this application provide a computing device, which includes: a position coordinate comparison circuit and an accumulator; the position coordinate comparison circuit is used to compare the position coordinates of element values ​​in a first matrix and the position coordinates of element values ​​in a second matrix to obtain a coordinate comparison result, wherein the first matrix and the second matrix are both compressed matrixes, the first matrix includes a first element value and a first position coordinate of the first element value, the first element value is any element value in the first matrix, the second matrix includes a second element value and a second position coordinate of the second element value, the second element value is any element value in the second matrix, the coordinate comparison result includes a first comparison result, the first comparison result is used to indicate that the first position coordinates and the second position coordinates are the same; the accumulator is used to add the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, and output the sum to a buffer, the buffer is used to cache the result matrix, wherein the result matrix includes a third element value and a third position coordinate of the third element value, the third element value is the sum of the first element value and the second element value, and the third position coordinate is the same as the first position coordinate. In this embodiment, the computing device can perform calculations on compressed matrices. When calculating the addition of two compressed matrices, the computing device compares the position coordinates of each element value in the two matrices and adds the two element values ​​corresponding to the same position coordinates in the two matrices to obtain the result matrix of the calculation of the two compressed matrices. Compared with the traditional method that requires decompressing the compressed matrix first and then performing matrix calculations on the decompressed matrix, the computing device provided in this embodiment can effectively improve the calculation performance of compressed matrices.

[0034] In an optional implementation, the accumulator is further configured to output an invalid signal when the third element is zero, indicating that the elements in the result matrix do not contain a zero element and its corresponding position coordinates. In this embodiment, each third element is obtained by adding two element values, so the third element may be zero. The accumulator is also configured to delete the zero element and its corresponding position coordinates when the third element is zero, thereby ensuring that the result matrix output by the computing device does not contain zero elements, thus outputting a compressed matrix, saving transmission resources or facilitating subsequent calculation operations.

[0035] In one alternative implementation, the accumulator does not output the zero element value and the corresponding position coordinates to the buffer based on the invalid signal.

[0036] In one optional implementation, the coordinate comparison result further includes a second comparison result. The first matrix includes a fourth element value and the fourth position coordinate of the fourth element value, wherein the fourth element value is any element value in the first matrix. The second comparison result is used to indicate that no position coordinate matching the fourth position coordinate is found in the second matrix. The accumulator is also used to output the fourth element value and the fourth position coordinate to a buffer based on the second comparison result. The buffer is used to cache the result matrix, which includes the fourth element value and the fourth position coordinate. In this embodiment, the accumulator retains the position coordinates that do not match in the two matrices and the element value corresponding to those position coordinates, and directly writes them into the buffer, thereby using the fourth element value as an element value in the result matrix. Even if multiple position coordinates in the first matrix and multiple position coordinates in the second matrix cannot be completely matched one-to-one, the computing device can still perform addition calculations, increasing the matrix calculation scenarios.

[0037] In one optional implementation, the position coordinate comparison circuit is further configured to read that both the first matrix and the second matrix contain position coordinates, and, based on the triggering of the position coordinates, perform an operation to compare the position coordinates in the first matrix and the position coordinates in the second matrix. In this embodiment, the position coordinate comparison circuit receives the first matrix and the second matrix. Since both the first matrix and the second matrix contain position coordinates, when the position coordinate comparison circuit reads that the first matrix and the second matrix contain position coordinates, it will trigger the position coordinate circuit to perform a comparison operation on the position coordinates in the first matrix and the position coordinates in the second matrix.

[0038] In one optional implementation, the position coordinate comparison circuit includes a row coordinate comparison circuit and a column coordinate comparison circuit. The first matrix has a dimension of M×N, and the second matrix has a dimension of K×L. M×N and K×L can be the same or different. The row coordinate comparison circuit is used to compare the row coordinates of the m-th row in the first matrix and the row coordinates of the f-th row in the second matrix to obtain a row comparison result. The row comparison result indicates that the row coordinates of the m-th row and the row coordinates of the f-th row are the same; where m is less than or equal to M, and f is less than or equal to K. The column coordinate comparison circuit is used to compare the column coordinates of each element value in the m-th row with the row coordinates of the second matrix based on the row comparison result. The column coordinates of each element value in row f are compared to obtain a column comparison result. The column comparison result indicates that the nth column coordinate of row m is the same as the lth column coordinate of row f. The first comparison result includes the row comparison result and the column comparison result. The accumulator is also used to add the element value corresponding to the nth column coordinate of row m and the element value corresponding to the lth column coordinate of row f according to the column comparison result to obtain a third element value. The element value corresponding to the nth column coordinate of row m is the first element value, and the element value corresponding to the lth column coordinate of row f is the second element value, where n is less than or equal to N, and l is less than or equal to L. In this embodiment, the position coordinate comparison circuit does not need to traverse and match each position coordinate in the first matrix with each position coordinate in the second matrix. By comparing the row coordinates in the first matrix and the second matrix first through the row coordinate comparison circuit, and then comparing the column coordinates of the position coordinates with the same row coordinates, the number of position coordinate comparisons is reduced, saving computational resources.

[0039] In one alternative implementation, the row alignment result includes a first signal and a first value, and the column alignment result includes a second signal and a second value, wherein the first signal is used to indicate the validity of the first value, which is equal to the value of the row coordinate of the m-th row, and the second signal is used to indicate the validity of the second value, which is equal to the value of the column coordinate of the n-th column.

[0040] Fourthly, embodiments of this application provide a matrix calculation method applied to a computing device. The method includes: first, the computing device acquires a calculation instruction, which includes a first matrix and a second matrix in compressed format; then, it compares the position coordinates of element values ​​in the first matrix and the position coordinates of element values ​​in the second matrix to obtain a coordinate comparison result; the first matrix includes a first element value and a first position coordinate of the first element value, and the second matrix includes a second element value and a second position coordinate of the second element value; the coordinate comparison result includes a first comparison result, which indicates that the first position coordinate and the second position coordinate are the same; finally, the first element value and the second element value are added according to the first comparison result, and the sum is output to a buffer, which is used to cache the result matrix, wherein the result matrix includes a third element value and a third position coordinate of the third element value, the third element value is the sum of the first element value and the second element value, and the third position coordinate is the same as the first position coordinate.

[0041] In an alternative implementation, the method further includes: when the third element value is zero, the computing device can output an invalid signal for the zero element value, the invalid signal indicating that the element values ​​in the result matrix do not include zero element values.

[0042] In an optional implementation, the method further includes: avoiding outputting the zero element value and the corresponding position coordinates to the buffer based on the invalid signal, so that the result matrix does not contain the zero element value, and the result matrix is ​​a compressed matrix, thereby saving transmission resources or facilitating the next calculation operation.

[0043] In one optional implementation, the coordinate comparison result further includes a second comparison result. The first matrix includes a fourth element value and the fourth position coordinate of the fourth element value. The second comparison result is used to indicate that no position coordinate matching the fourth position coordinate is found in the second matrix. The method may further include: the computing device outputs the fourth element value and the fourth position coordinate to a buffer based on the second comparison result. The buffer is used to cache the result matrix, which includes the fourth element value and the fourth position coordinate. In this embodiment, the accumulator retains the unmatched position coordinates in the two matrices and the element value corresponding to those position coordinates, and directly writes them into the buffer. Thus, the fourth element value is used as an element value in the result matrix. Even if multiple position coordinates in the first matrix and multiple position coordinates in the second matrix cannot be completely matched one-to-one, the computing device can still perform addition calculations, increasing the matrix calculation scenarios.

[0044] In one optional implementation, the first matrix has a dimension of M×N, and the second matrix has a dimension of K×L. The comparison of the position coordinates of elements in the first matrix and the second matrix to obtain the coordinate comparison result can specifically include: First, the computing device compares the row coordinates of the m-th row in the first matrix and the row coordinates of the f-th row in the second matrix to obtain a row comparison result, indicating that the row coordinates of the m-th row and the f-th row are the same; where m is less than or equal to M, and f is less than or equal to K; then, the computing device adjusts the row coordinates of the m-th row according to the row comparison result. The column coordinates of each element value in row m are compared with the column coordinates of each element value in row f to obtain a column comparison result. The column comparison result indicates that the nth column coordinate of row m is the same as the lth column coordinate of row f. The computing device adds the element value corresponding to the nth column coordinate of row m and the element value corresponding to the lth column coordinate of row f according to the column comparison result to obtain the third element value. The element value corresponding to the nth column coordinate of row m is the first element value, and the element value corresponding to the lth column coordinate of row f is the second element value, where n is less than or equal to N and l is less than or equal to L.

[0045] In one optional implementation, the row alignment result includes a first signal and a first value, and the column alignment result includes a second signal and a second value. The first signal indicates that the row coordinate of the m-th row is the same as the row coordinate of the f-th row in the second matrix, and the first value is equal to the row coordinate of the m-th row. The second signal indicates that the n-th column coordinate of the m-th row is the same as the l-th column coordinate of the f-th row, and the second value is equal to the n-th column coordinate.

[0046] Fifthly, a computing circuit is provided, which is used to execute the operation steps of the computing method provided by the second aspect or any possible implementation of the second aspect, or the computing circuit is used to execute the operation steps of the computing method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0047] A sixth aspect provides a computing system, the system including a processor and a computing device, the processor being configured to send computing instructions to the computing device, and the computing device being configured to execute the operation steps of the computing method provided by the second aspect or any possible implementation thereof, or the computing device being configured to execute the operation steps of the computing method provided by the fourth aspect or any possible implementation thereof.

[0048] In a seventh aspect, a chip is provided, the chip including a processor, the processor integrating a computing device, the computing device being used to execute the operation steps of the computing method provided by the second aspect or any possible implementation of the second aspect, or the computing device being used to execute the operation steps of the computing method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0049] Eighthly, a computing device is provided, comprising a computing system as described in the sixth aspect above, or a chip as described in the seventh aspect above.

[0050] A ninth aspect provides a readable storage medium storing instructions that, when the readable storage medium is operated on a device, cause the device to perform the operation steps of the matrix calculation method provided by the second aspect or any possible implementation thereof, or cause the device to perform the operation steps of the calculation method provided by the fourth aspect or any possible implementation thereof.

[0051] In a tenth aspect, a computer program product is provided that, when run on a computer, causes the computer to perform the operation steps of the computation method provided by the second aspect or any possible implementation thereof, or causes the computer to perform the operation steps of the computation method provided by the fourth aspect or any possible implementation thereof.

[0052] Understandably, any of the computing devices, computer storage media, or computer program products provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0053] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0054] Figure 1a This is a schematic diagram of the matrix of COO compression format in the embodiments of this application;

[0055] Figure 1b This is a schematic diagram of the matrix of CSR compression format in the embodiments of this application;

[0056] Figure 1c This is a schematic diagram of the matrix in CSC compression format in the embodiments of this application;

[0057] Figure 1d This is a schematic diagram illustrating the splitting of a compressed matrix into compressed vectors in an embodiment of this application.

[0058] Figure 2 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0059] Figure 3 This is a schematic diagram of the structure of a processor provided in an embodiment of this application;

[0060] Figure 4 This is a schematic diagram of the structure of one embodiment of a computing device provided in this application.

[0061] Figure 5 This is a schematic diagram of the position coordinate comparison circuit provided in the embodiments of this application obtaining the first coordinate comparison result;

[0062] Figure 6 This is a schematic diagram of the structure of one embodiment of the logic operation circuit provided in this application.

[0063] Figure 7 and Figure 8 This is a schematic diagram illustrating two examples of addition operations on the first and second vectors provided in the embodiments of this application;

[0064] Figure 9 This is a schematic diagram illustrating an example of the multiplication operation between the first vector and the second vector provided in the embodiments of this application.

[0065] Figure 10 This is a schematic diagram illustrating an example of the inner product operation of the first and second vectors provided in the embodiments of this application.

[0066] Figure 11 This is a schematic diagram illustrating an example of a multiplication and addition operation between a first vector, a second vector, and a third vector provided in an embodiment of this application.

[0067] Figure 12 This is a schematic diagram of another embodiment of a computing device according to the present application.

[0068] Figure 13 This is a schematic diagram of a compressed matrix F provided in an embodiment of this application;

[0069] Figure 14a This is a schematic diagram of the first and second matrices in the embodiments of this application;

[0070] Figure 14b , Figure 14c and Figure 14d These are schematic diagrams illustrating three examples of the result matrix obtained by adding the first matrix and the second matrix in the embodiments of this application;

[0071] Figure 15 This is a schematic diagram of the position coordinate comparison circuit in the embodiment of this application;

[0072] Figure 16a A schematic diagram illustrating the comparison of row coordinates in the first matrix and row coordinates in the second matrix in the application embodiment;

[0073] Figure 16b This is a schematic diagram of the row coordinate comparison circuit performing row coordinate comparison in an embodiment of this application;

[0074] Figure 17a This is a schematic diagram showing the comparison of column coordinates in rows where the row coordinates are equal in the first and second matrices in this embodiment of the application.

[0075] Figure 17b This is a schematic diagram of the column coordinate comparison circuit performing column coordinate comparison in an embodiment of this application;

[0076] Figure 18 This is a schematic diagram of the accumulator structure in an embodiment of this application;

[0077] Figure 19 This is a schematic diagram of the accumulator outputting element values ​​to the second buffer based on the comparison results of column coordinates in an embodiment of this application;

[0078] Figure 20 This is a schematic diagram of another embodiment of a computing device according to the present application.

[0079] Figure 21 This is a flowchart illustrating the steps of one embodiment of a calculation method in this application.

[0080] Figure 22 This is a flowchart illustrating the steps of another embodiment of a calculation method in this application. Detailed Implementation

[0081] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0082] To better understand this application, the relevant terms used in this application will first be explained by way of example.

[0083] Matrix: An M×N matrix is ​​a rectangular array of elements arranged in M ​​rows and N columns. For example, matrix A is shown in equation (1) and matrix B is shown in equation (2).

[0084]

[0085] Matrix addition and subtraction: Matrices with the same dimension can be added or subtracted from each other, specifically by adding or subtracting the elements at each position. For example, matrices A and B are both m×n matrices. Adding matrices A and B together yields matrix C, as shown in equation (3) below.

[0086]

[0087] A row vector is a matrix of dimension 1×M, where M is a positive integer. For example, a row vector is shown in equation (5):

[0088] X = [x1 x2 ... x] M Equation (5).

[0089] A column vector is a matrix of dimension M×1, where M is a positive integer. For example, a column vector is shown in equation (6):

[0090]

[0091] Compressed matrices: When a matrix contains both zero and non-zero elements, to save storage space, the non-zero elements are typically stored in a specific format, while the zero elements are not. This process is called matrix compression, and the compressed matrix is ​​called a compressed matrix. Methods for matrix compression include, but are not limited to, coordinate (COO) representation, compressed sparse row (CSR), and compressed sparse column (CSC).

[0092] The following provides illustrative examples of the three compression methods: COO, CSR, and CSC.

[0093] COO: Matrices are represented using triples. A triple consists of three values: row number, column number, and element value. The row and column numbers identify the position of the element value. For example, a triple is (row number, column number, element value), or (element value, row number, column number), etc. The specific order of the three values ​​in the triple is not limited. For an example, please refer to [link to example]. Figure 1a , Figure 1a The image shows a 4×4 matrix Y containing zero and non-zero elements. The non-zero values ​​are: 1, 2, 3, 4, 5, 6, 7, 8, 9. For example, the non-zero value "1" is located in row 0, column 0, and its triplet is (0, 0, 1). The non-zero value "2" is located in row 0, column 1, and its triplet is (0, 1, 2). The non-zero value "3" is located in row 1, column 1, and its triplet is (1, 1, 3). Each element value is not described in detail here. For example, the triplet form of the compressed matrix is: (0, 0, 1), (0, 1, 2), (1, 1, 3), (1, 2, 4), (2, 0, 5), (2, 2, 6), (2, 3, 7), (3, 1, 8), (3, 3, 9).

[0094] Alternatively, the compressed matrix Y can be represented as shown in equation (8).

[0095] Row coordinates = ([0,0,1,1,2,2,2,3,3]);

[0096] Column coordinates = ([0,1,1,2,0,2,3,1,3]);

[0097] Element value = ([1,2,3,4,5,6,7,8,9]), equation (8).

[0098] CSR: A matrix is ​​represented using three types of data: element values, column numbers, and row offsets. The element values ​​and column numbers in CSR are represented similarly to those in the COO method described above. The difference between CSR and COO is that the row offset in CSR represents the starting offset position of the first element in a given row relative to all element values. Please refer to [link / reference]. Figure 1b As shown, firstly, Figure 1b The non-zero elements in matrix Y shown are arranged row-wise, resulting in the following values: 1, 2, 3, 4, 5, 6, 7, 8, 9. The first non-zero element in the first row is "1", and its offset from all other elements is "0". Similarly, the first non-zero element in the second row is "3", and its offset from all other elements is "2". The first non-zero element in the third row is "5", and its offset from all other elements is "4". The first non-zero element in the fourth row is "8", and its offset from all other elements is "7". Finally, the total number of non-zero elements in the matrix (e.g., "9") is appended to the end of the row containing the offset.

[0099] The compressed matrix Y can be represented as shown in equation (9).

[0100] Row offset = ([0,2,4,7,9]);

[0101] Column coordinates = ([0,1,1,2,0,2,3,1,3]);

[0102] Element value = ([1,2,3,4,5,6,7,8,9]), equation (9).

[0103] CSC: A matrix is ​​represented using three types of data: element values, row numbers, and column offsets. The element values ​​and row numbers in CSC are represented similarly to those in the COO method. The difference between CSC and COO is that the column offset represents the starting offset position of the first element in a given column relative to all element values. Please refer to [link to relevant documentation]. Figure 1c As shown, firstly, Figure 1cThe non-zero elements in matrix Y shown are arranged column-wise, resulting in the following values: 1, 5, 2, 3, 8, 4, 6, 7, 9. The first non-zero element in the first column is "1", with its offset from all other elements being "0". Similarly, the first non-zero element in the second column is "5", with its offset from all other elements being "2". The first non-zero element in the third column is "2", with its offset from all other elements being "5". The first non-zero element in the fourth column is "3", with its offset from all other elements being "7". Finally, the total number of non-zero elements in the matrix (e.g., "9") is appended to the end of the row containing the column offsets.

[0104] The compressed matrix Y can be represented as shown in equation (10).

[0105] Column offset = ([0,2,5,7,9]);

[0106] Row coordinates = ([0,0,1,1,2,2,2,3,3]);

[0107] Element value = ([1,5,2,3,8,4,6,7,9]), equation (10).

[0108] As explained by the three matrix compression methods above, each element in a COO compressed matrix has a corresponding row coordinate (row number) and column coordinate (column number). Each element in a CSR compressed matrix has a corresponding column coordinate. Each element in a CSC compressed matrix has a corresponding row coordinate.

[0109] Uncompressed matrix format: Please refer to Figure 1a The matrix Y shown is an uncompressed matrix that includes both zero and non-zero elements. It should be noted that, generally, a compressed matrix is ​​also called a sparse matrix, while an uncompressed matrix can be called a dense matrix.

[0110] The compressed vector in this embodiment can be a vector obtained by compressing an uncompressed vector. For example, an uncompressed vector... [1,2,0,3,0,5]. This is the uncompressed vector format. It includes 6 element values. If... To compress a vector and retain only its non-zero elements, the position of each non-zero element needs to be marked with coordinates. In one example, the compressed vector... It is represented by the following formula (11).

[0111] Element value = ([1,2,3,5]);

[0112] Position coordinates = ([0,1,4,6]), Equation (11).

[0113] In Equation 11 above, the element value "1" is located at the "0" position, so the position coordinate of the element value "1" is "0"; similarly, the element value "2" is located at the "1" position, so the position coordinate of the element value "2" is "1", and so on. Specific examples will not be elaborated here.

[0114] For example, please refer to Figure 1d To understand, Figure 1d This is a schematic diagram illustrating an example of a compressed matrix. A compressed vector is obtained by splitting a compressed matrix. A compressed matrix can be split into multiple compressed row vectors, or multiple compressed column vectors. Taking a column vector as an example, the first column contains four coordinate values ​​'a'. 00 =1, a 10 =2, a 20 =5, a 30 =7, where the element value a 00 a 10 a 20 and a 30 The corresponding position coordinates are (i0,j0), (i1,j0), (i2,j0), and (i3,j0), respectively. For example, (i0,j0) = (1,1), (i1,j0) = (3,1), (i2,j0) = (4,1), and (i3,j0) = (5,1). Since the column coordinates of each element in the compressed format column vector are the same, each element value in the compressed format vector can carry only the row coordinates, and the position coordinates are the row coordinates in the compressed format matrix. If the compressed format vector is a row vector, then the compressed format vector can carry only the column coordinates, and the position coordinates are the column coordinates in the compressed format matrix. In one example, the compressed format vector is shown in the following equation (12).

[0115] Element value = ([1,2,5,7]);

[0116] Position coordinates = ([1,3,4,5]), Equation (12).

[0117] The compressed vectors described above are also called sparse vectors, while the uncompressed vectors are also called dense vectors.

[0118] Figure 2 This is a schematic diagram of a computing device provided in this embodiment. The computing device can be a terminal, network device, or server, or other device with computing capabilities. See also... Figure 2The computing device may include a memory 201, a processor 202, a communication interface 203, and a bus 204, wherein the memory 201, the processor 202, and the communication interface 203 are interconnected via the bus 204.

[0119] The memory 201 can be used to store data, software programs, and modules, mainly including a program storage area and a data storage area. The program storage area can store the operating system, software applications required for at least one function, and middleware software, etc., while the data storage area can store data created during the use of the device. For example, the operating system may include Linux, Unix, or Windows operating systems, etc.; the software applications required for at least one function may include applications related to artificial intelligence, high-performance computing (HPC), deep learning, or scientific computing, etc.; the middleware software may include linear algebra library functions, etc. In one possible example, the memory 201 includes, but is not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or high-speed random access memory, etc. Furthermore, the memory 201 may also include other non-volatile memories, such as at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0120] Additionally, the processor 202 is used to control and manage the operation of the computing device, such as by running or executing software programs and / or modules stored in the memory 201, and by calling data stored in the memory 201, to perform various functions of the computing device and process data. In one possible example, the processor 202 includes, but is not limited to, a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, logic circuits, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor 202 can also be a combination that implements computing functions, such as including one or more microprocessor combinations, digital signal processors, and microprocessors, etc.

[0121] Communication interface 203 is used to enable communication between the computing device and external devices. Communication interface 203 may include an input interface and an output interface. The input interface can be used to obtain a first vector (or first matrix) and a second matrix vector (or second matrix) in compressed format as described in the following embodiments. In some feasible embodiments, the input interface may have only one input interface or multiple input interfaces. The output interface can be used to output the calculation results as described in the following embodiments. In some feasible embodiments, the calculation results may be directly output by the processor or stored in memory first and then output via memory. In other feasible embodiments, there may be only one output interface or multiple output interfaces.

[0122] Bus 204 can be a Peripheral Component Interconnect Express (PCIe) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Bus 204 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 2 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0123] In this embodiment, the processor 202 may include a computing device, which may be an ASIC, an FPGA, or a logic circuit, etc. Of course, the device may also be implemented by software, and this application embodiment does not impose specific limitations on this. The computing device can be used to perform vector and matrix calculations involved in artificial intelligence, scientific computing, graphics computing, etc.

[0124] Furthermore, the processor 202 may also include one or more other processing units such as a CPU, GPU, or NPU. For example... Figure 3 As shown, taking the processor 202, which includes a CPU 1 and a computing device 2, as an example, the computing device 2 can be integrated with the CPU 1 (for example, the computing device 2 is integrated inside the SoC where the CPU 1 is located), or it can be set up separately alongside the CPU 1 (for example, the computing device 2 is set up in the form of a PCIe card). Specifically... Figure 3 (a) and Figure 3 As shown in (b) above. Furthermore, the CPU 1 may also include a controller 11, one or more arithmetic logic units (ALUs) 12, a cache 13, and a memory management unit (MMU) 14, etc. Figure 3 The following explanation uses memory 201 as an example of dynamic random access memory (DRAM).

[0125] In this embodiment, the computing device can perform calculations on compressed vectors. When calculating two compressed vectors, the computing device compares the position coordinates of each element value in the two vectors and performs calculations on the two element values ​​corresponding to the same position coordinates in the two vectors, thereby obtaining the calculation results of the two compressed vectors. Compared with the traditional method that requires decompressing the compressed vectors first and then performing vector calculations on the decompressed vectors, the computing device provided in this embodiment can effectively improve the calculation efficiency of compressed vectors.

[0126] This application provides a computing device. Please refer to... Figure 4 As shown, the computing device includes a position coordinate comparison circuit 401 and a logic operation circuit 402. Optionally, the computing device further includes a first buffer 403 and a second buffer 404, wherein the first buffer 403, the position coordinate comparison circuit 401, the accumulator 4021, and the second buffer 404 are connected in sequence. The first buffer 403 and the second buffer 404 can be buffers (such as registers) within the computing device, or the first buffer 403 can also be... Figure 3The diagram shows a buffer 13 in the central processing unit 1. A first buffer 403 is used to buffer a first vector and a second vector, and a second buffer 404 is used to buffer the result of calculations performed on the first and second vectors.

[0127] The position coordinate comparison circuit 401 is used to receive a first vector and a second vector from the first buffer 403, compare the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector, and obtain a first coordinate comparison result. The first vector and the second vector are both compressed vectors. The first vector includes a first element value and a first position coordinate of the first element value. The second vector includes a second element value and a second position coordinate of the second element value. The first coordinate comparison result includes a first comparison result, which is used to indicate that the first position coordinates and the second position coordinates are the same.

[0128] For example, the first vector is denoted as The second vector is denoted as The lengths of the first and second vectors are T. It should be noted that the embodiments in this application are not limited to... Length and Length, Length and The lengths can be the same or different. In this embodiment, and The length T is just an example for ease of explanation, and and Both can be row vectors or both can be column vectors; there is no specific limitation. This includes the first element value and the corresponding first position coordinates, for example, The multiple first element values ​​and the first position coordinates corresponding to each first element value are shown in Table 1 below. The multiple second element values ​​and the corresponding second position coordinates of each second element value are shown in Table 2 below.

[0129] Table 1

[0130] First element value <![CDATA[a0]]> <![CDATA[a1]]> <![CDATA[a2]]> … <![CDATA[a T-1 ]]> First position coordinates <![CDATA[h0]]> <![CDATA[h1]]> <![CDATA[h2]]> … <![CDATA[h T-1 ]]>

[0131] Table 2

[0132] Second element value <![CDATA[b0]]> <![CDATA[b1]]> <![CDATA[b2]]> … <![CDATA[b T-1 ]]> Second position coordinates <![CDATA[p0]]> <![CDATA[p1]]> <![CDATA[p2]]> … <![CDATA[p T-1 ]]>

[0133] The position coordinate comparison circuit 401 compares the first position coordinates in Table 1 and the second position coordinates in Table 2. If y pairs of position coordinates match among T first position coordinates and T second position coordinates, then y is an integer greater than or equal to 0 and less than or equal to T. Please refer to [link to relevant documentation]. Figure 5 As shown, Figure 5This is a schematic diagram of the coordinate comparison circuit 401 performing coordinate comparison. For example, T is illustrated using 4 as an example. The four position coordinates are h0, h1, h2, h3, in that order. The four position coordinates are p0, p1, p2, and p3 in sequence. The position coordinate comparison circuit 401 outputs the first comparison result to the logic operation circuit 402. The first comparison result includes the comparison result of the position coordinates, a third signal (e.g., denoted as "valid"), and a third value (e.g., denoted as "t"). The third signal is used to indicate the validity of the t value. The third value is used to indicate the specific value of the position coordinates. The comparison result of the position coordinates can be denoted as: (isequal"0.index_01,index_02), (isequal"1.index_11,index_12), (isequal"2.index_21,index_22), (isequal"... For example, when (isequal"0.index_01,index_02) = (1, h0, p0), it means that the position coordinate h0 in the first vector and the position coordinate p0 in the second vector are equal. The position coordinate comparison circuit 401 also outputs valid"0 = 1, t0, where t0 and h0 are equal (i.e., t0 and p0 are also equal). Similarly, when (isequal"1.index_11,index_12) = (1, h1, p1), it means that the position coordinate h1 in the first vector and the position coordinate p1 in the second vector are equal. The position coordinate comparison circuit 401 also outputs valid"1 = 1, t1, where t1 and h1 are equal (i.e., t1 and p1 are also equal); and so on. The comparison results of the position coordinates will not be described in detail. Among them, valid" = 1 means that the corresponding output t value is valid, and valid" = 0 means that the corresponding output t value is invalid.

[0134] Understandable Figure 5In the above, the position coordinate comparison circuit 401 outputs a total of 8 sets of valid "values" and t values, and 4 sets of isequal "comparison results". The reason for outputting 8 sets of valid "values" is that the number of signal groups and the bit width of the position coordinate comparison circuit 401 are fixed. The position coordinate comparison circuit 401 reads T position coordinates from the first vector and T position coordinates from the second vector. If none of the T position coordinates in the first vector and the T position coordinates in the second vector match, the maximum number of valid "values" is 2T (i.e., 8), thus reserving 2T output positions for valid "values". The reason for outputting 4 sets of isequal "comparison results" is that if all T position coordinates in the first vector and the T position coordinates in the second vector match one-to-one, then at most T sets (i.e., 4 sets) of position coordinates should match one-to-one, thus reserving 4 output positions for isequal "comparison results".

[0135] Example 1: The position coordinate comparison circuit receives two input arrays as shown below:

[0136] {h0, h1, h2, h3} = {1, 2, 3, 4};

[0137] {p0, p1, p2, p3}={1, 2, 5, 7}.

[0138] The output of the position coordinate comparison circuit is shown below:

[0139] (isequal"0.index_01,index_02)=(1,h0,p0);

[0140] (isequal"1.index_11,index_12)=(1,h1,p1);

[0141] (isequal"2.index_21,index_22)=(0,h2,p2);

[0142] (isequal"3.index_31,index_32)=(0,h3,p3);

[0143] (valid"0,t0)=(1,1);

[0144] (valid"1,t1)=(1,2);

[0145] (valid"2,t2)=(1,3);

[0146] (valid"3,t3)=(1,4);

[0147] (valid"4,t4)=(1,5);

[0148] (valid"5,t5)=(1,7);

[0149] (valid"6,t6)=(0,-1);

[0150] (valid"7,t7)=(0,-1).

[0151] The comparison results of position coordinates can indicate which pairs of position coordinates are equal, such as h0 and p0 being equal, and h1 and p1 being equal. The comparison results of "isequal" above show the final comparison results and do not focus on the comparison process. For example, valid"3 = 1 and t2 = h2 indicate that h2 is a valid value, and combined with the comparison result (isequal"2.index_21,index_22) = (0, h2, p2), the position coordinate comparison circuit 401 did not match a position coordinate equal to h2 (and did not match a position coordinate equal to p2). As can be seen from Example 1 above, the position coordinate comparison circuit 401 matched 2 pairs of equal position coordinates, while 4 position coordinates did not match equal values. Therefore, the number of valid values ​​is 6 (valid"0 to valid"5), while the values ​​of valid"6 and valid"7 are both 0, thus indicating that t6 and t7 are invalid values ​​(e.g., invalid values ​​can be represented by "-1").

[0152] The logic operation circuit 402 is used to perform operations on the first element value and the second element value according to the first comparison result, obtain the operation value, and output the operation result to the second buffer 404. The operation result is related to the operation value.

[0153] In this embodiment, the operations described above include, but are not limited to, addition, multiplication, inner product, and multiplication-addition operations. Optionally, please refer to... Figure 6 As shown, the logic operation circuit 402 includes at least one of an accumulator 4021, a multiplier 4022, and an inner product operation circuit 4023. Examples of the various operations described above are given below.

[0154] Example 1: Addition operations An example is provided.

[0155] In an optional embodiment, the position coordinate comparison circuit 401 is further configured to receive an addition instruction, which includes a first vector and a second vector, and to transmit the first comparison result to the accumulator 4021 according to the addition instruction.

[0156] Accumulator 4021 is used to receive a first vector, a second vector, and a first comparison result. The first comparison result indicates that the first position coordinates and the second position coordinates are the same. For example, the first comparison result 'a' includes (isequal"0.index_01,index_02) = (1,h0,p0) and (valid'0,t0) = (1,1) from Example 1 above. Accumulator 4021 adds the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value, and outputs the sum to the second buffer 404. The second buffer 404 is used to buffer the operation result (the result vector after adding the first vector and the second vector), wherein the operation result includes a third element value and the third position coordinate of the third element value. The third element value is the sum, and the third position coordinate is the same as the first position coordinate.

[0157] For example, please refer to Tables 1 and 2 above. Figure 7 To understand this, if the first comparison result indicates that multiple first position coordinates in the first vector can be matched one-to-one with multiple second position coordinates in the second vector, such as h0 = p0, h1 = p1, h2 = p2, ..., h T-1 =p T-1 .but The calculation results are shown in Table 3 below.

[0158] Table 3

[0159] Third element value <![CDATA[c0]]> <![CDATA[c1]]> <![CDATA[c2]]> … <![CDATA[c T-1 ]]> Third position coordinates <![CDATA[q0]]> <![CDATA[q1]]> <![CDATA[q2]]> … <![CDATA[q T-1 ]]>

[0160] In Table 3 above, c0 = a0 + b0, c1 = a1 + b1, c2 = a2 + b2, ..., c T-1 =a T-1 +b T-1 ; and q0 = h0 (q0 = p0), q1 = h1 (q1 = p1), q2 = h2 (q2 = p2), ..., q T-1 =h T-1 (q T-1 =p T-1 ).

[0161] Figure 7 Taking 4 as an example, if a0 is 10 and b0 is 2, then c0 = 10 + 2 = 12, q0 = 1. Regarding... Figure 7 Examples are provided, but not all will be listed here.

[0162] Optionally, if not all of the multiple first position coordinates in the first vector and the multiple second position coordinates in the second vector can be matched one-to-one, but... The location coordinates of one of the parts are in It can match the same position coordinates, while The position coordinates of another part in No matching position coordinates were found in the first vector. The first vector includes the fourth element value and the fourth position coordinate of the fourth element value. The first coordinate comparison result also includes a second comparison result, which is used to indicate that no position coordinates identical to the fourth position coordinates were matched in the second vector. For example, the second comparison result 'a' includes (isequal"2.index_21,index_22) = (0, h2, p2) and (valid"2,t2) = (1, 3) in Example 1 above.

[0163] Accumulator 4021 is also used to output the fourth element value and the fourth position coordinate to the second buffer 404 based on the second comparison result. The calculation result includes the fourth element value and the fourth position coordinate. That is, the second buffer stores the third element value and its corresponding position coordinate, and the fourth element value and its corresponding position coordinate. The third element value is the sum of the first element value and the second element value, and the fourth element value is equal to the first element value or the second element value. In this embodiment, accumulator 4021 retains the position coordinates of the two vectors that do not match and the element values ​​corresponding to those position coordinates, and directly writes them into the second buffer 404. Thus, each fourth element value is also used as an element value in the calculation result. Even if multiple position coordinates in the first vector and multiple position coordinates in the second vector cannot be completely matched one-to-one, the computing device can still perform addition calculations, increasing the vector calculation scenarios.

[0164] Please see Figure 8 As shown, the calculation result is the result sorted in ascending order of position coordinates. For example, if the position coordinate "1" of the first element value "10" is equal to the position coordinate "1" of the second element value "2", then the accumulator 4021 outputs the third element value "12" (first element value "10" + second element value "2") and the corresponding third position coordinate "1" to the second buffer 404; if the first position coordinate "2" of the first element value "7" is equal to the second position coordinate "2" of the second element value "3", then the accumulator 4021 outputs the third element value "10" (first element value "7" + second element value "3") and the third position coordinate "2" to the second buffer 404. Furthermore, if the position coordinate "3" of the first element value "8" does not match a second position coordinate, then the accumulator 4021 retains the first element value "8" and the corresponding position coordinate "3" and directly transmits them to the second buffer 404. Figure 8 The examples in the text will not be elaborated upon one by one. The second cache caches... The length of the result vector (i.e. the result of the operation) is greater than or equal to T and less than or equal to 2T.

[0165] Optionally, since each third element value is obtained by adding two element values, the third element value may be zero. To save transmission resources or facilitate subsequent calculation operations, the computing device can compress the above result vector to output a compressed vector. For example, the accumulator 4021 is also used to output an invalid signal when the third element value is zero. The invalid signal indicates that the accumulator 4021 will not output the zero element value and the position coordinates corresponding to the zero element value to the second buffer 404, so that the calculation result output by the computing device does not contain the zero element value. For example, (isequal"0.index_01,index_02)=(1,h0,p0), (valid"0,t0)=(1,1). h0 = p0, and the first element value corresponding to h0 is "1", and the first element value corresponding to p0 is "-1", then the third element value is "0" (1 + (-1)). Accumulator 4021 sets the value of valid"0 from "1" to "0" (invalid signal). Accumulator 4021 avoids outputting the zero element value and the position coordinate corresponding to the zero element value to the second buffer 404 according to the invalid signal (valid"0 = 0), so that the second buffer 404 does not buffer the zero element value.

[0166] Example 2: Multiplication Operations An example is provided.

[0167] In an optional embodiment, the position coordinate comparison circuit 401 is also used to receive a multiplication instruction, which includes a first vector and a second vector, and to transmit the first comparison result to the multiplier 4022 according to the multiplication instruction.

[0168] Multiplier 4022 is used to receive the first vector, the second vector and the first comparison result, and multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, and output the product value (operation value) to the second buffer 404. The operation result includes the fifth element value (such as denoted as "d") and the fifth position coordinate of the fifth element value (such as denoted as "s"). The fifth element value is the above product value, and the fifth position coordinate is the same as the first position coordinate.

[0169] Please refer to Tables 1 and 2 above for understanding. If h0 = p0, h1 = p1, and h3 = p2, then the fifth element value d0 = a0 × b0, and the fifth coordinate value corresponding to d0 is s0 (s0 = h0); the fifth element value d1 = a1 × b1, and the fifth coordinate value corresponding to d1 is s1 (s1 = h1); the fifth element value d2 = a3 × b2, and the fifth coordinate value corresponding to d2 is s2 (s2 = h3). Multiplier 4022 does not calculate the element values ​​corresponding to position coordinates that do not match in the first and second vectors.

[0170] Please refer to Figure 9. In a specific example, the first comparison result includes three pairs of equal position coordinates. Multiplier 4022 performs multiplication on the two operands with equal position coordinates based on the first comparison result. For example, if the position coordinate "1" of the first element value "10" is equal to the position coordinate "1" of the second element value "2", then multiplier 4022 multiplies the first element value "10" and the second element value "2" to obtain the product value "20", and outputs this product value (the fifth element value) and its corresponding position coordinate "1" (the fifth position coordinate) to the second buffer 404. However, the first position coordinate "3" of the first element value "8" does not match an equal position coordinate, so multiplier 4022 does not calculate the first element value "8"; similarly, the second position coordinate "7" of the second element value "11" also does not match an equal position coordinate, so multiplier 4022 does not calculate the second element value "11". For Figure 9 The examples shown are not illustrated here. In this embodiment, if the lengths of both the first vector and the second vector are T, then... The length of the result of the operation is greater than or equal to 0 and less than or equal to T.

[0171] Example 3: Inner product operations An example is provided.

[0172] In an optional embodiment, the position coordinate comparison circuit 401 is further configured to receive an inner product instruction, which includes a first vector and a second vector, and to transmit the first comparison result to the inner product operation circuit 4023 according to the inner product instruction.

[0173] The inner product operation circuit 4023 receives the first vector, the second vector, and the first comparison result. Based on the first comparison result, it multiplies the first element value and the second element value to obtain the product value (operated value), and outputs the result to the second buffer 404. The operation result is the sum of multiple product values, where each product value is the product of a pair of first and second element values ​​with the same position coordinates. Please refer to Tables 1 and 2 above for further understanding. If the vector... sum vector There are x pairs of matching position coordinates, such as h0 = p0, h1 = p1, h3 = p2, then The calculation result is shown in equation (13).

[0174]

[0175] vector sum vector The result of the inner product operation is a scalar. For an example, please refer to [link to example]. Figure 10 As shown, =10×2+7×3+6×10=101.

[0176] Example 4: Multiplication and addition operations An example is provided.

[0177] This embodiment involves three vectors, all of which are in compressed format. For example, the first vector... Second vector and the third vector The 4022 multiplier is used for multiplying... and The accumulator 4021 is used to perform multiplication operations. The results and Perform addition operations.

[0178] The position coordinate comparison circuit 401 is also used to receive a multiply-accumulate calculation instruction, which includes a first vector and a second vector, and to transmit the first comparison result to the multiplier 4022 according to the multiply-accumulate calculation instruction.

[0179] Multiplier 4022 is also used to receive the first vector, the second vector, and the first comparison result, and multiply the first element value and the second element value according to the first comparison result to obtain the product value (operated value) of the first element value and the second element value. The product value is the fifth element value, and the fifth position coordinate is the same as the first position coordinate. Multiplier 4022 transmits the fifth operated value and the fifth position coordinate to the second buffer 404.

[0180] vector sum vector For the multiplication operation, please refer to Example 2 above. The explanation is omitted here.

[0181] The second buffer 404 will The result (if denoted as a vector) Output to the first buffer 403.

[0182] The position coordinate comparison circuit 401 is also used to receive vectors from the first buffer 403. sum vector Comparison vectors The sixth position coordinates and vector The fifth position coordinate is used to obtain the third comparison result, and the third comparison result is transmitted to the accumulator 4021. The third comparison result indicates that the sixth position coordinate is the same as the fifth position coordinate.

[0183] Accumulator 4021 is used to add the sixth element value and the fifth element value according to the third comparison result to obtain the sum of the sixth element value and the fifth element value. The operation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value, and the seventh position coordinate is the same as the sixth position coordinate.

[0184] vector sum vector The addition operation and the vector addition operation in Example 1 above will not be repeated here.

[0185] Please see Figure 11 The following is an illustrative explanation of multiplication and addition operations. Vector sum vector There are three pairs of identical position coordinates. For example, the position coordinate "1" of the first element value "10" is equal to the position coordinate "1" of the second element value "2". Therefore, multiplier 4022 multiplies the first element value "10" and the second element value "2" to obtain the product value "20", and outputs this product value (the fifth element value) and its corresponding position coordinate "1" (the fifth position coordinate) to the second buffer 404. Similarly, the position coordinate "2" of the first element value "7" is equal to the position coordinate "2" of the second element value "3". Therefore, multiplier 4022... 2. Multiply the first element value "7" and the second element value "3" to obtain the product value "21". Output the product value "21" and the corresponding position coordinate "2" to the second buffer 404. Finally, the multiplier 4022 outputs three fifth element values ​​20, 21, and 60 (6×10) and the fifth position coordinates ("1", "2", "5") corresponding to each fifth element value to the second buffer 404. The second buffer 404 transmits the three fifth element values ​​and the fifth position coordinates corresponding to each element value to the first buffer 403.

[0186] Position coordinate comparison circuit 401 for vector sum vector The position coordinates in the vector are compared. sum vector There are two pairs of identical position coordinates. For example, the fifth position coordinate "1" corresponding to the fifth element value "20" and the sixth position coordinate "1" corresponding to the sixth element value "7" are the same; the fifth position coordinate "5" corresponding to the fifth element value "60" and the sixth position coordinate "5" corresponding to the sixth element value "2" are the same; then the accumulator 4021 outputs the sum of the fifth element value "20" and the sixth element value "7" ("27") and its corresponding position coordinate "1" to the second buffer 404, and also outputs the sum of the fifth element value "60" and the sixth element value "2" ("62") and its corresponding position coordinate "5" to the second buffer 404. It also outputs the fifth element value "21" and its corresponding position coordinate "2", and the sixth element values ​​"11" and "14" and their corresponding sixth position coordinates "3" and "4" that do not match their position coordinates to the second buffer 404. Finally, the operation result is buffered in the second buffer 404. As shown in equation (14) below.

[0187] The value of the seventh element is ([27,21,11,14,62]).

[0188] The seventh position coordinates are ([1,2,3,4,5]), equation (14).

[0189] In this embodiment, the computing device can perform various operations on compressed vectors, including addition, multiplication, inner product, and multiply-addition. When calculating two compressed vectors, the computing device compares the position coordinates of each element in the two vectors, performs correlation operations on the two elements corresponding to the same position coordinates, and obtains the result vector from the calculation of the two compressed vectors. Compared to the traditional method that requires decompressing the compressed vector first and then performing vector calculations on the decompressed vector, the computing device provided in this embodiment can effectively improve the computational efficiency of compressed vectors.

[0190] Optionally, please refer to Figure 12As shown, the computing device includes a data buffer and queue unit 406, which is connected to a position coordinate comparison circuit 401 and a logic operation circuit 402, respectively. When the lengths of the first vector and the second vector are both r×T, where r is a positive integer, the position coordinate comparison circuit 401 compares the position coordinates in the first vector and the second vector. The maximum number of matching position coordinates is r×T, and the maximum number of matching position coordinates is 0. The position coordinate comparison circuit 401 outputs the first vector, the second vector, and the first coordinate comparison result to the data buffer and queue unit 406, which repackages the first vector and the second vector into a vector of length T. Then, the vector of length T and the first coordinate comparison result are output to the logic operation circuit 402, which performs vector correlation operations. In this embodiment, the computing device can repackage the vector through the data cache and queue unit 406. Even if the length of the input vector is longer than the length of the vector that the logic operation circuit can process, the length of the vector can be adapted to the length that the logic operation circuit can calculate, thereby improving the utilization rate of the computing device.

[0191] The above embodiments provide illustrative examples of various operations on compressed vectors. A compressed matrix can be decomposed into multiple compressed vectors; therefore, a compressed matrix can be considered as multiple compressed vectors. Consequently, the aforementioned operations on compressed vectors can be extended to the calculation of compressed matrices. In a specific embodiment, the computing device in this application can also be used for matrix calculations. The following example uses addition to illustrate the addition of compressed matrices.

[0192] The position coordinate comparison circuit 401 is used to compare the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain the coordinate comparison result (also referred to as the "second coordinate comparison result" in this embodiment). Both the first matrix and the second matrix are in compressed format.

[0193] As illustrated above with an example of a compressed matrix, each element value in a compressed matrix has corresponding positional coordinates. See also... Figure 13 As shown, Figure 13 This is a schematic diagram of a matrix in compressed format. Figure 13The compressed matrix F shown is M×N in dimension, with M rows and N columns. Matrix F contains M×N element values, each with a position coordinate indicating its location within the corresponding uncompressed matrix F′. The position coordinates include row and column coordinates. It should be understood that the row coordinate indicates the "row" of the corresponding element value in the uncompressed matrix F′, and the column coordinate indicates the "column" of the corresponding element value in the uncompressed matrix F′. In matrix F, the M rows are sequentially numbered i0, i1, ..., i... (M-1) These M rows have coordinates, and each row has N columns, with the N columns sequentially numbered j0, j1, ..., j... (N-1) These are N column coordinates. Taking row 0 as an example, the element values ​​in row 0 include a in sequence. 00 a 01 , ..., a 0(N-1) These are N element values. The position coordinates of each element value in the N element values ​​in the 0th row are: (i0, j0), (i0, j1), ..., (i0, j2) in order. (N-1) Similarly, the values ​​of the N elements in the Mth row are, in order: a (M-1)0 a (M-1)1 , ..., a (M-1)(N-1) The position coordinates of each element value in the Mth row are as follows: (i (M-1) ,j0), (i (M-1) ,j1), …,(i (M-1) ,j (N-1) For example, element value a 01 The position coordinates are (i0, j1). If i0 = 1 and j1 = 1, it indicates that the element value is a. 01 Its position in matrix F′ is row 1, column 1. It should be understood that... Figure 13The compressed matrix shown is essentially the same as the COO format compressed matrix described above, only with a different representation. For example, elements with the same row coordinates are placed in the same row. For instance, the matrix in COO format is represented as: (0, 0, 1), (1, 0, 2), (2, 1, 3), (1, 2, 4), (2, 0, 5), (2, 2, 6), (2, 3, 7), (3, 1, 8), (3, 3, 9), (3, 0, 6). During data compression, elements with the same row are treated as elements within the same row. For example, if the row coordinates of the four triples (0, 1, 3), (0, 0, 5), (0, 2, 6), and (0, 3, 7) are the same, then the element values ​​of these four triples are placed in the same row. The element values ​​"3", "5", "6", and "7" are the element values ​​in the same row. The position coordinate of "3" is (0, 1), the position coordinate of "5" is (0, 0), the position coordinate of "6" is (0, 2), the position coordinate of "7" is (0, 3), and so on.

[0194] For example, the first matrix has a dimension of M×N, and the second matrix has a dimension of K×L. The compression format of the first and second matrices is illustrated using COO as an example. The dimensions of the first and second matrices can be the same or different, and are not specifically limited. For ease of explanation, in this embodiment, M, N, K, and L are all illustrated as 4, meaning that the dimensions of both the first and second matrices are 4×4. The first matrix includes a first element value and the first position coordinates of the first element value, where the first element value is any element value in the first matrix. The second matrix includes a second element value and the position coordinates of the second element value, where the second element value is any element value in the second matrix. For example, each matrix in the first and second matrices includes 4 rows, each row contains 4 element values, and each matrix contains 16 element values. Taking the first matrix as an example, the 4 element values ​​in the 0th row are, in order: a 00 a 01 a 02 a 03 Among them, a 00 The position coordinates are (i0, j0), a 01 The position coordinates are (i0, j1), a 02 The position coordinates are (i0, j2), a 03 The position coordinates are (i0, j3). The other element values ​​and their corresponding position coordinates in the first matrix are not detailed here. Taking the second matrix as an example, the four element values ​​in row 0 are, in order: b 00 b 01 b 02 b 03 Among them, b 00 The position coordinates are (k0, l0), b01 The position coordinates are (k0, l1), b 02 The position coordinates are (k0, l2), b 03 The position coordinates are (k0, l3). The other element values ​​in the second matrix and the position coordinates corresponding to each element value will not be described in detail or illustrated with examples.

[0195] For example, please refer to Figure 14a To illustrate the process, let's take a look at the comparison of position coordinates between two matrices using the position coordinate comparison circuit 401. The position coordinate comparison circuit 401 receives the first matrix and the second matrix from the first buffer 403. It first compares the row coordinates in the position coordinates of the two matrices. If the row coordinates are equal (or the same), it then compares the column coordinates corresponding to the two equal row coordinates. For example, the row coordinates in the 0th row of the first matrix and the second matrix are i0 and k0, respectively. If i0 and k0 are equal, the position coordinate comparison circuit 401 compares the column coordinates (j0, j1, j2, j3) in the 0th row of the first matrix with the column coordinates (l0, l1, l2, l3) in the 0th row of the second matrix. If j0 and l0 are equal, then the element value a... 00 The position coordinates (i0, j0) and element value b 00 The position coordinates (k0, l0) are the same. If j0 and l0 are not equal, then j0 is compared sequentially with the next column coordinate l1 in the 0th row of the second matrix. That is, if the two column coordinates being compared are the same, then the position coordinates of the two elements corresponding to that column coordinate are the same. If the two column coordinates being compared are different, then j0 is compared with the next column coordinate l2 in the 0th row of the second matrix, until all the column coordinates in the first matrix have been compared with all the elements in the 0th row of the second matrix. This is only an example of comparing the position coordinates in the 0th row of the first matrix and the 0th row of the second matrix. The comparison of other position coordinates in the two matrices is not illustrated. The coordinate comparison results include at least the following two cases.

[0196] In the first case, the coordinate comparison result includes a first comparison result, which indicates that the first position coordinates and the second position coordinates are the same. For example, if the position coordinates (i0,j1) in the first matrix are (0,2) and the position coordinates (k0,l0) in the second matrix are (0,2), then the position coordinates (i0,j1) and (k0,l0) are equal. As another example, if the position coordinates (i1,j0) in the first matrix are (1,3) and the position coordinates (k1,l2) in the second matrix are also (1,3), then the position coordinates (i1,j0) and (k1,l2) are equal.

[0197] Accumulator 4021 receives a first matrix and a second matrix, and adds the first element value and the second element value according to a first comparison result to obtain a result matrix. The result matrix includes a third element value and the third position coordinates of the third element value. The third element value is the sum of the first and second element values, and the third position coordinates are the same as the first (or second) position coordinates. Accumulator 4021 writes the third element value and the third position coordinates into a second buffer 404, which stores the result matrix. For example, please refer to [reference needed]. Figure 14b As shown, the accumulator 4021 will store the element value a corresponding to the position coordinate (i0, j1) in the first matrix. 01 (If it is "1") and the element value b corresponding to the position coordinates (k0, l0) in the second matrix. 00 Add the values ​​of the three elements together (e.g., "2") to get the "value of the third element" (e.g., denoted as "c"). 00 ”), c 00 The position coordinates of (e.g., "3") are marked as (u0, v0), and (u0, v0) is also (0, 2). For example, accumulator 4021 assigns the element value a corresponding to the position coordinates (i1, j0) in the first matrix. 10 (e.g., "2") and the element value b corresponding to the position coordinates (k1, l2) in the second matrix. 12 Add the values ​​of the three elements together (e.g., "5") to get the "value of the third element" (e.g., denoted as "c"). 10 ”), c 10 The position coordinates of (e.g., "7") are marked as (u1, v0), and (u1, v0) is also (1, 3), and so on. If each position coordinate in the first matrix can be matched with the same position coordinate in the second matrix, that is, if the 16 position coordinates in the first matrix match (are equal) the 16 position coordinates in the second matrix, then the accumulator 4021 adds the element values ​​with the same position coordinates in the two matrices to obtain a new element value (the third element value). The third position coordinate does not change relative to the first position coordinate (or the second position coordinate), thus obtaining the result matrix C1. Each third element value in the result matrix C1 and the third position coordinate corresponding to each third element value will not be illustrated with examples.

[0198] Optionally, since each third element value is obtained by adding two element values, the third element value may be zero. To save transmission resources or facilitate subsequent calculation operations, the computing device can compress the resulting matrix to output a compressed matrix. For example, the accumulator 4021 is also configured to output an invalid signal when the third element value is zero. The invalid signal indicates that the zero element value and its corresponding position coordinates will not be output to the second buffer 404, thus ensuring that the resulting matrix output by the computing device does not contain zero element values. Please refer to [link to relevant documentation]. Figure 14c As shown, for example, c03 c 13 c 22 c 33 All of them are zero element values, and the resulting matrix C2 does not contain these four zero element values ​​or the position coordinates corresponding to each zero element value.

[0199] In the second case, the coordinate comparison result also includes a second comparison result. The first matrix includes a fourth element value and the fourth position coordinate of that fourth element value, where the fourth element value is any element value in the first matrix. The second comparison result indicates that no position coordinate matching the fourth position coordinate was found in the second matrix.

[0200] Accumulator 4021 is also used to write the fourth element value and the fourth position coordinate into the second buffer 404 according to the second comparison result. The second buffer 404 is used to cache the result matrix, which includes the fourth element value and the fourth position coordinate corresponding to the fourth element value. It should be understood that in this case, the element values ​​with the same position coordinates in the two matrices are added together to obtain the sum of the two element values ​​(the third element value). Accumulator 4021 writes the position coordinate and the sum into the second buffer 404. Accumulator 4021 retains the position coordinates and the corresponding element values ​​in the two matrices that do not match, and directly writes the element value (the fourth element value) into the second buffer 404, thus using the fourth element value as an element value in the result matrix C3. For example, please refer to... Figure 14d To illustrate, let's take the element values ​​in the 0th row of the first and second matrices as an example. The coordinates of the first three columns in the 0th row of the first matrix match (are the same) the coordinates of the first three columns in the 0th row of the second matrix. For example, if the coordinates (i0, j0) in the first matrix are the same as the coordinates (k0, l0) in the second matrix, then the accumulator will... 00 and b 00 Add, c 00 For a 00 and b 00 The sum of (u0, v0) and (i0, j0) is the same. Similarly, (i0, j1) and (k0, l1) are the same, so the accumulator 4021 will add a. 01 and b 01 Add, c 01 For a 01 and b 01 If the sum of (u0,v1) and (i0,j1) is the same, and (i0,j2) and (k0,l2) are the same, then accumulator 4021 will add a. 02 and b 02 Add, c 02 For a 02 and b 02The sum of (u0, v2) and (i0, j2) is the same. However, the position coordinates of the fourth column in the 0th row of the first matrix and the fourth column in the 0th row of the second matrix are different. That is, the position coordinate (i0, j3) in the fourth column of the 0th row of the first matrix does not match a corresponding position coordinate in the second matrix. Therefore, accumulator 4021 writes the position coordinate (i0, j3) and its corresponding coordinate value into the second buffer 404, i.e., c in the result matrix C3. 03 With a in the first matrix 03 Same, c 03 The position coordinates (u0, v3) and a 03 The position coordinates (i0, j3) are the same; similarly, the position coordinates (k0, l3) in the 4th column of the 0th row of the second matrix do not match the same position coordinates in the first matrix. Therefore, the accumulator 4021 writes the position coordinates (k0, l3) and the corresponding coordinate values ​​into the second buffer 404, that is, into c in the result matrix C3. 04 With b in the second matrix 03 Same, c 04 The position coordinates (u0, v4) and b 03 The position coordinates (k0, l3) are the same. Similarly, the other element values ​​in the first and second matrices, as well as the element values ​​in the resulting matrix C3, will not be elaborated upon but illustrated with examples.

[0201] The structure and function of the position coordinate comparison circuit are illustrated below. Please refer to [link / reference]. Figure 15 As shown, the position coordinate comparison circuit 401 may include a row coordinate comparison circuit 4011 and a column coordinate comparison circuit 4012. The row coordinate comparison circuit 4011 compares which pairs of row coordinates in the first matrix and the second matrix are the same (or equal) and which are different, thus obtaining the row coordinate comparison result. The column coordinate comparison circuit 4012 compares the two column coordinates of two position coordinates with the same row coordinates, thus obtaining the column coordinate comparison result. When the row coordinates are the same, if the two column coordinates are the same, then the two position coordinates corresponding to the two column coordinates are the same; if the two column coordinates are different, then the two position coordinates corresponding to the two column coordinates are different. In this embodiment, the position coordinate comparison circuit does not need to traverse and match each position coordinate in the first matrix with each position coordinate in the second matrix. By first comparing the first coordinates (e.g., row coordinates) in the first matrix and the second matrix, and then comparing the second coordinates (e.g., column coordinates) of position coordinates with the same first coordinates, the number of position coordinate comparisons is reduced, saving computational resources.

[0202] It should be understood that in this embodiment, the position coordinate comparison circuit 401 is not limited to comparing row coordinates first and then column coordinates, or comparing column coordinates first and then row coordinates. For example, in mode A, the first and second matrices are used to compress element values ​​corresponding to the same row coordinates to the same row. Each compressed matrix can be considered as consisting of multiple row vectors. The position coordinate comparison circuit 401 first compares the row coordinates of two row vectors in the two matrices using the row coordinate comparison circuit 4011. If the row coordinates of these two row vectors are the same, the column coordinate comparison circuit 4012 continues to compare the column coordinates of each element value in these two row vectors. Similarly, in mode B, the first and second matrices are used to compress element values ​​corresponding to the same column coordinates to the same column. Each compressed matrix can be considered as consisting of multiple column vectors. The position coordinate comparison circuit 401 first compares the column coordinates of two column vectors in the two matrices using the row coordinate comparison circuit 4012. If the column coordinates of these two column vectors are the same, the row coordinate comparison circuit 4011 continues to compare the row coordinates of each element value in these two column vectors. This embodiment uses method A as an example for illustration.

[0203] For example, the row coordinate comparison circuit 4011 is used to compare the row coordinates of the m-th row in the first matrix with the row coordinates of the f-th row in the second matrix to obtain a first row comparison result. The first row comparison result indicates that the row coordinates of the m-th row and the row coordinates of the f-th row are the same; where m is an integer less than or equal to M, and f is an integer less than or equal to K. The m-th row is any row in the first matrix, and the f-th row is any row in the second matrix.

[0204] Please see Figure 16b As shown, Figure 16b This is a schematic diagram of row coordinate comparison circuit 4011 performing row coordinate comparison. Row coordinate comparison circuit 4011 receives a first matrix and a second matrix from a first buffer. The four row coordinates in the first matrix are i0, i1, i2, i3 in sequence, and the four row coordinates in the second matrix are k0, k1, k2, k3 in sequence. Row coordinate comparison circuit 4011 outputs a first row comparison result, which includes the row coordinate comparison result, a first signal (e.g., denoted as "valid"), and a first value (e.g., denoted as "u"). The first signal indicates the validity of the u value. The first value indicates the value of the row coordinate. The first row comparison result indicates that the row coordinates of row m and row f are equal. For an example, please refer to [link to example diagram]. Figure 16aAs shown, the row coordinate comparison results are denoted as: (isequal0.index_01,index_02), (isequal1.index_11,index_12), (isequal2.index_21,index_22), (isequal3.index_31,index_32). For example, when (isequal0.index_01,index_02) = (1,i0,k0), it means that the row coordinate i0 of the 0th row in the first matrix is ​​equal to the row coordinate k0 of the 0th row in the second matrix. The row coordinate comparison circuit 4011 also outputs valid0 = 1,u0, where u0 and i0 are equal (i.e., u0 and k0 are also equal). Similarly, when (isequal1.index_11,index_12) = (1, i1, k1), it means that the row coordinate i1 and the row coordinate k1 of the first row in the first matrix are equal, and the output is valid1 = 1, u1, where u1 and i1 are equal (i.e., u1 and k1 are also equal); and so on. The comparison results of row coordinates will not be elaborated one by one. Among them, valid = 1 means that the corresponding output u value is valid, and valid = 0 means that the corresponding output u value is invalid.

[0205] It should be noted that, Figure 16b In the above, the row coordinate comparison circuit 4011 outputs a total of 8 sets of valid values ​​and u values, and 4 sets of isequal comparison results. The reason for outputting 8 sets of valid values ​​is that the number of signal groups and the bit width of the row coordinate comparison circuit 4011 are fixed. The row coordinate comparison circuit 4011 receives 4 row coordinates from the first matrix and 4 row coordinates from the second matrix. If none of the 4 row coordinates in the first matrix or the second matrix match, the maximum number of valid values ​​should be 8, thus reserving 8 output positions for valid values. The reason for outputting 4 sets of isequal comparison results is that if all 4 row coordinates in the first matrix and the second matrix match one-to-one, then at most 4 sets of row coordinates should match completely, thus reserving 4 output positions for isequal comparison results. Figure 16aFor example, when i0 and k0 are equal, valid0 = 1, and u0 and i0 are equal; when i1 and k1 are equal, valid1 = 1, and u1 and i1 are equal; when i2 and k2 are equal, valid2 = 1, and u2 and i2 are equal; when i3 and k3 are equal, valid3 = 1, and u3 and i3 are equal. That is, the four row coordinates in the first matrix and the four row coordinates in the second matrix have been matched one-to-one. Therefore, valid4, valid5, valid6, and valid7 are all equal to 0, indicating that u3, u4, u5, and u6 are invalid values. u3, u4, u5, and u6 can all be a preset value (e.g., "-1"), which indicates that u is invalid. The specific value of the preset value is not limited.

[0206] For example, the row coordinate comparison circuit receives two input arrays as shown below:

[0207] {i0, i1, i2, i3} = {1, 2, 3, 4};

[0208] {k0, k1, k2, k3}={1, 2, 3, 4}.

[0209] The output of the row coordinate comparison circuit is shown below:

[0210] (isequal0.index_01,index_02)=(1,i0,k0);

[0211] (isequal1.index_11,index_12)=(1,i1,k1);

[0212] (isequal2.index_21,index_22)=(1,i2,k2);

[0213] (isequal3.index_31,index_32)=(1,i3,k3);

[0214] (valid0, u0) = (1, 1);

[0215] (valid1, u1) = (1, 2);

[0216] (valid2, u2) = (1, 3);

[0217] (valid3, u3) = (1, 4);

[0218] (valid4, u4) = (0, -1);

[0219] (valid5, u5) = (0, -1);

[0220] (valid6, u6) = (0, -1);

[0221] (valid7, u7) = (0, -1).

[0222] The column coordinate comparison circuit 4012 is used to compare the column coordinates of each element value in the m-th row with the column coordinates of each element value in the f-th row based on the first row comparison result, and obtain the first column comparison result.

[0223] For example, the column coordinate comparison circuit 4012 may include multiple column coordinate comparison units (such as column coordinate comparison unit a, column coordinate comparison unit b, column coordinate comparison unit c, etc.), each column coordinate comparison unit being used to compare the column coordinates in two row vectors. These two row vectors can be understood as the vectors in the above embodiments. sum vector For example, the m-th row in the first matrix can be considered a row vector, and the f-th row in the second matrix can also be considered a row vector. For instance, column coordinate comparison unit a receives the first row comparison result a (e.g., i0 equals k0, valid0 = 1, u0) from the row coordinate comparison circuit 4011. Then, column coordinate comparison unit a compares the column coordinates of the element values ​​in the 0th row of the first matrix and the element values ​​in the 0th row of the second matrix. For example, column coordinate comparison unit a reads the column coordinates j0, j1, j2, j3 in the 0th row of the first matrix; and reads the column coordinates l0, l1, l2, l3 in the 0th row of the second matrix. Column coordinate comparison unit a compares the column coordinates (j0, j1, j2, j3) and (l0, l1, l2, l3) to obtain the column coordinate comparison result. The representation of the column coordinate comparison result is similar to that of the row coordinate comparison result.

[0224] For example, the column coordinate comparison circuit 4012 outputs a first column comparison result and / or a second column comparison result. The first column comparison result indicates that the two compared column coordinates are equal, and the second column comparison result indicates that no equal column coordinates were found. The first column comparison result includes the column coordinate comparison result, a second signal (denoted as "valid'"), and a second value (e.g., denoted as "v"). The second signal indicates the validity of the v value, and the second value indicates the value of the column coordinate. The logic of the column coordinate comparison circuit 4012 for column coordinate comparison is similar to the logic of the row coordinate comparison circuit described above; please refer to the logic of the row coordinate comparison circuit described above for understanding. For example, Figure 17a and Figure 9To understand this, the column coordinate comparison results are denoted as: (isequal′0.index_01,index_02); (isequal′1.index_11,index_12); (isequal′2.index_21,index_22); (isequal′3.index_31,index_32). The column coordinate comparison results indicate which pairs of column coordinates are equal, such as j0 and l0 being equal, and j2 and l1 being equal. However, valid′3 = 1, v3 = j3 indicates that j3 is a valid value, and for j3, column coordinate comparison unit a did not find a matching column coordinate. Similarly, valid′4 = 1, v4 = l2 indicates that l2 is a valid value, and for l2, column coordinate comparison unit a did not find a matching column coordinate. In other words, column coordinate comparison unit a matches 2 pairs of equal column coordinates, while 4 column coordinates do not match equal values. Therefore, the number of valid values ​​is 6 (valid′0 to valid′5), while the values ​​of valid′6 and valid′7 are both 0, thus indicating that v6 and v7 are invalid values ​​(e.g., "-1").

[0225] For example, the column coordinate comparison circuit receives two input arrays as shown below:

[0226] {j0, j1, j2, j3}={1, 2, 3, 4};

[0227] {l0, l1, l2, l3}={1, 3, 5, 7}.

[0228] The output of the row coordinate comparison circuit is shown below:

[0229] (isequal′0.index_01,index_02)=(1,j0,l0);

[0230] (isequal′1.index_11,index_12)=(1,j2,l1);

[0231] (isequal′2.index_21,index_22)=(0, j1, l2);

[0232] (isequal′3.index_31,index_32)=(0,j3,l3);

[0233] (valid′0,v0)=(1,1);

[0234] (valid′1,v1)=(1,2);

[0235] (valid′2,v2)=(1,3);

[0236] (valid′3,v3)=(1,4);

[0237] (valid′4,v4)=(1,5);

[0238] (valid′5,v5)=(1,7);

[0239] (valid′6, v6)=(0,-1);

[0240] (valid′7,v7)=(0,-1).

[0241] The above example illustrates the comparison of column coordinates between two vectors with equal row coordinates (e.g., row 0 in the first matrix and row 0 in the second matrix) using column coordinate comparison unit a. It should be understood that while column coordinate comparison unit a performs the column coordinate comparison, other column coordinate comparison units (such as column coordinate comparison unit b, column coordinate comparison unit c, etc.) also perform column coordinate comparisons simultaneously. For example, if the row coordinates of row 1 in the first matrix and row 1 in the second matrix are equal, column coordinate comparison unit b can compare the column coordinates of these two row vectors. The process of other column coordinate comparison units comparing column coordinates is similar to that of column coordinate comparison unit a, and will not be elaborated here. Only the comparison of column coordinates of row 0 in the first matrix and row 0 in the second matrix using column coordinate comparison unit a is provided as an example.

[0242] Accumulator 4021 is used to add the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row according to the comparison result of the first column to obtain the third element value. The comparison result of the first column indicates that the nth column coordinate of the mth row is the same as the lth column coordinate of the fth row. The element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, where n is less than or equal to N and l is less than or equal to L.

[0243] The structure of the accumulator described above is illustrated below as an example. Figure 10 As shown, the accumulator 4021 includes multiple adders (also referred to as an "adder array"). Figure 10The example adder array shown is 1x4 in size. This 1x4 adder array can support the addition of four arrays (e.g., (a0, b0), (a1, b1), (a2, b2), (a3, b3)), and adds the two values ​​of each of these four arrays. The adder array outputs the sum of these four arrays (e.g., c0, c1, c2, c3), for example, a0 + b0 = c0, etc. Similarly, the adder array can be expanded to an MxN adder array, such as expanding it to a 4x4 adder array, etc. The size of the adder array is designed according to actual needs.

[0244] Accumulator 4021 is also used to output the third element value and its third position coordinate to the second buffer 404. Optionally, accumulator 4021 is also used to output the fourth element value corresponding to the unmatched fourth position coordinate and its fourth position coordinate to the second buffer 404 based on the comparison result of the second column. Please refer to... Figure 19 and Figure 14b To understand, Figure 19 This is a schematic diagram of accumulator 4021 outputting element values ​​to a second buffer based on the first column comparison result and / or the second column comparison result. The size of the second buffer 404 is P×Q, where P equals (M+K) and Q equals (N+L). In this embodiment, taking the first matrix and the second matrix as examples where both dimensions are M×N, P equals 2M and Q equals 2N. Accumulator 4021 receives two compressed matrix formats and coordinate comparison results from position coordinate comparison circuit 401. For example, based on the second result a (e.g., j0 and l1 are equal), accumulator 4021 outputs a... 00 and b 01 The input is fed into an adder a, and adder a will convert a... 00 and b 01 Add them together to get a sum (e.g., c). 00 The accumulator 4021 will sum the value c. 00 and the c 00 The corresponding position coordinates (and a) 00 The values ​​with the same position coordinates are output to the second buffer 404. That is, the accumulator 4021 inputs two element values ​​with the same position coordinates into the adder, the adder obtains the sum, and then the accumulator 4021 outputs the sum and its corresponding position coordinates to the second buffer 404. 00 Position coordinates and a 00 The position coordinates are the same. For example, the second column comparison result 'a' indicates that column coordinate l0 in the second matrix did not find a matching value in the first matrix. Accumulator 4021 directly sets b based on the second column comparison result 'a'. 00 and the b 00 The position coordinates (k0, l0) are output to the second buffer 404. Please combine this with... Figure 14a and Figure 17b To illustrate, taking the coordinate comparison between the 0th row of the first matrix and the 0th row of the second matrix as an example, accumulator 4021 outputs c0, c1, c2, c3, c4, c5, and the corresponding position coordinates of these five element values ​​to the second buffer 404. These five element values ​​and their corresponding position coordinates include: c0 and its position coordinates (u0, v0), where c0 equals b. 00 (u0,v0) equals (k0,l0); c1 and position coordinates (u0,v1), where c1 is a 00 and b 01 The sum of (u0, v1) equals (i0, j0); c2 and its position coordinates (u0, v2), where c2 is a 01 and b 02 The sum of (u0, v1) equals (i0, j1); c3 and its position coordinates (u0, v3), where c3 is a 02 and b 03 The sum of (u0, v3) equals (i0, j2). Optionally, if all five values ​​are non-zero, the accumulator 4021 outputs a valid signal (e.g., valid″ = 1) for each non-zero value; if the sum contains a zero value, the accumulator 4021 outputs an invalid signal (e.g., valid″ = 0) for that zero value. The second buffer 404 stores multiple element values, the position coordinates corresponding to each element value, and the validity of each element value (valid″ = 1 or valid″ = 0). Based on the validity of each element value, the final result matrix does not contain zero values ​​(zero values ​​are invalid).

[0245] Optionally, the row coordinate comparison result also includes a second row comparison result. This second row comparison result indicates that the row coordinates of row w in the first matrix do not match equal coordinate values ​​in the second matrix. In this case, accumulator 4021 is further used to directly output all element values ​​and their position coordinates from row w in the first matrix to the second buffer 404, where row w is any row in the first matrix. For example, please refer to... Figure 14a To understand this, if the row coordinates i0 in the first matrix and the row coordinates k0, k1, k2, and k3 in the second matrix are all different, then the accumulator 4021 will increment the value a of each element in the w-th row. 00 and a 00 The position coordinates are (i0, j0), and the element value is a. 01 and a 01 The position coordinates are (i0, j1), and the element value is a. 02 and a 02 The position coordinates are (i0, j2), and the element value is a. 03 and a 03The position coordinates (i0, j3) are all output to the second buffer 404.

[0246] It should be noted that the precision of the element values ​​and position coordinates is not limited in the embodiments of this application; the element values ​​and position coordinates can be of arbitrary precision. For example, the precision of the element values ​​can be double-precision FP64, and the precision of the position coordinates can be int32 precision, etc.

[0247] Optionally, to enable the computing device to support matrix calculations in various compression formats and expand the application scenarios of the computing device, please refer to [link to relevant documentation]. Figure 20 As shown, the computing device also includes a format conversion unit 405. The format conversion unit 405 is used to convert a matrix in a non-target compressed format into a matrix in a target compressed format (COO format). For example, when at least one of the first matrix and the second matrix is ​​in CSC or CSR format, the format conversion unit 405 converts the first matrix and / or the second matrix into COO format. The function of the format conversion unit 405 can be described above. Figure 3 The central processing unit 1 in the computer can be used to implement the function of the format conversion unit 405, or the function of the format conversion unit 405 can be implemented by logic circuits within the computing device.

[0248] Based on the computing device provided in this application, significant benefits can be obtained in various matrix computation scenarios. For example, when used in artificial intelligence (AI) training and inference scenarios, the computing device can fully support both compressed and uncompressed matrix computations. The computing device in this application can directly perform computations on compressed matrices without decompressing them, thus improving computational performance by more than four times. Furthermore, for scientific computing scenarios, whether it's high-performance uncompressed matrix computation or memory-bandwidth-constrained matrix computation, the computing device in this application can directly access compressed matrices from memory, further enhancing computational efficiency.

[0249] The above has described an embodiment of a computing device; the following describes the method performed by the computing device. Please refer to [link / reference needed]. Figure 21 As shown in the embodiments of this application, a calculation method is provided, and the subject executing the method can be... Figure 2 The computing device shown may optionally be the subject of the method. Figure 3 The computing device shown can optionally be used as the execution subject of the method. Figure 4 The computing device shown can optionally be the execution subject of the method. Figure 20 The computing device shown. The computing device is used to perform steps 2101 to 2103 below.

[0250] Step 2101: The computing device acquires computing instructions, which include a first vector and a second vector in compressed format.

[0251] Step 2102: The computing device compares the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector to obtain a first coordinate comparison result. The first vector includes the first element value and the first position coordinate of the first element value, and the second vector includes the second element value and the second position coordinate of the second element value. The first coordinate comparison result includes a first comparison result, which is used to indicate that the first position coordinate and the second position coordinate are the same.

[0252] Step 2103: The computing device performs calculations on the first element value and the second element value according to the first comparison result to obtain the calculated value, and outputs the calculation result of the first vector and the second vector to the buffer. The calculation result is related to the calculated value.

[0253] In one optional implementation, the calculation instruction is an addition instruction. The computing device adds the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value. The operation value is the sum, and the operation result includes the third element value and the third position coordinate of the third element value. The third element value is the sum, and the third position coordinate is the same as the first position coordinate.

[0254] Optionally, when the third element value is zero, the computing device outputs an invalid signal for the zero element value. The invalid signal indicates that the element values ​​in the calculation result do not include the zero element value and the position coordinates corresponding to the zero element value. The computing device avoids outputting the zero element value and the position coordinates corresponding to the zero element value to the buffer based on the invalid signal.

[0255] In one optional implementation, the first coordinate comparison result further includes a second comparison result, and the first vector includes a fourth element value and the fourth position coordinates of the fourth element value. Based on the second comparison result, the computing device outputs the fourth element value and the fourth position coordinates to a buffer, and the calculation result includes the fourth element value and the fourth position coordinates.

[0256] In one optional implementation, the operation instruction is a multiplication instruction. The computing device multiplies the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value. The product value is the operation value, and the operation result includes the fifth element value and the fifth position coordinate of the fifth element value. The fifth element value is the product value, and the fifth position coordinate is the same as the first position coordinate.

[0257] In one optional implementation, the operation instruction is an inner product instruction. The computing device multiplies the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value. The product value is the operation value, and the operation result is the sum of multiple product values.

[0258] In one optional implementation, the operation instruction is a multiply-add instruction. The computing device multiplies the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value. The operation value is the product value, and the product value is used as the fifth element value. The fifth position coordinate corresponding to the fifth element value is the same as the first position coordinate.

[0259] By comparing the sixth position coordinate with the fifth position coordinate, a third comparison result is obtained. The third comparison result indicates that the sixth position coordinate and the fifth position coordinate are the same. The sixth position coordinate is the position coordinate in the third vector. The third vector includes the sixth element value and the sixth position coordinate corresponding to the sixth element value.

[0260] Based on the third comparison result, the sixth element value and the fifth element value are added together to obtain the sum of the sixth element value and the fifth element value. The operation value includes the sum of the sixth element value and the fifth element value. The operation result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value, and the seventh position coordinate is the same as the sixth position coordinate.

[0261] In one alternative implementation, the operation instructions include a first matrix and a second matrix in compressed format, the first matrix including a first vector and the second matrix including a second vector.

[0262] The computing device is also used to compare the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result, which includes the first coordinate comparison result.

[0263] In one optional implementation, the first matrix has a dimension of M×N, and the second matrix has a dimension of K×L; comparing the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain the second coordinate comparison result may include the following steps:

[0264] By comparing the row coordinates of the m-th row in the first matrix with the row coordinates of the f-th row in the second matrix, a row alignment result is obtained. The row alignment result indicates that the row coordinates of the m-th row and the row coordinates of the f-th row are the same, where m is less than or equal to M and f is less than or equal to K.

[0265] Based on the row comparison results, the column coordinates of each element value in row m and the column coordinates of each element value in row f are compared to obtain the column comparison results. The column comparison results indicate that the nth column coordinate of row m is the same as the lth column coordinate of row f. The first comparison results include the row comparison results and the column comparison results.

[0266] Based on the first comparison result, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row are added together to obtain the third element value. The element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, where n is less than or equal to N and l is less than or equal to L.

[0267] Please see Figure 22 As shown, this application also provides a calculation method, the execution subject of which can be... Figure 2 The computing device shown may optionally be the subject of the method. Figure 3 The computing device shown can optionally be used as the execution subject of the method. Figure 4 The computing device shown can optionally be the execution subject of the method. Figure 20 The computing device shown. The method includes the following steps 2201 to 2204.

[0268] Step 2201: Obtain the calculation instructions, which include a first matrix and a second matrix in compressed format.

[0269] In this step, please refer to the exemplary description of the first matrix and the second matrix in the foregoing device embodiments, which will not be repeated here.

[0270] Step 2202: Compare the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain the coordinate comparison result. The first matrix includes the first element value and the first position coordinate of the first element value, and the second matrix includes the second element value and the second position coordinate of the second element value. The coordinate comparison result includes the first comparison result, which is used to indicate that the first position coordinate and the second position coordinate are the same.

[0271] Please refer to the detailed description of the function performed by the position coordinate comparison circuit 401 in the above-described computing device embodiment for this step, which will not be repeated here.

[0272] Optionally, the first matrix has a dimension of M×N, and the second matrix has a dimension of K×L. The coordinate comparison results are obtained by comparing the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix, including:

[0273] By comparing the row coordinates of the m-th row in the first matrix with the row coordinates of the f-th row in the second matrix, the first row comparison result is obtained, which indicates that the row coordinates of the m-th row and the row coordinates of the f-th row are the same; where m is less than or equal to M, and f is less than or equal to K.

[0274] Based on the comparison results of the first row, the column coordinates of each element value in the m-th row are compared with the column coordinates of each element value in the f-th row to obtain the comparison results of the first column. The comparison results of the first column indicate that the n-th column coordinate of the m-th row is the same as the l-th column coordinate of the f-th row.

[0275] Step 2203: Add the first element value and the second element value according to the first comparison result to obtain the result matrix. The result matrix includes the third element value and the third position coordinate of the third element value. The third element value is the sum of the first element value and the second element value. The third position coordinate is the same as the first position coordinate.

[0276] Please refer to the detailed description of the function performed by the accumulator 4021 in the above-described computing device embodiment for this step, which will not be repeated here.

[0277] Optionally, based on the comparison result of the first column, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the lth column coordinate of the fth row are added together to obtain the third element value. The element value corresponding to the nth column coordinate of the mth row is the first element value, and the element value corresponding to the lth column coordinate of the fth row is the second element value, where n is less than or equal to N and l is less than or equal to L.

[0278] In one alternative implementation, when the third element is zero, the computing device outputs an invalid signal for the zero element, indicating that the element values ​​in the result matrix do not include zero elements.

[0279] In an optional implementation, the coordinate comparison result further includes a second comparison result. The first matrix includes a fourth element value and a fourth position coordinate of the fourth element value. The second comparison result is used to indicate that no position coordinate matching the fourth position coordinate was found in the second matrix. The matrix calculation method may also include the following step 2204.

[0280] Step 2204: Based on the second comparison result, output the fourth element value and the fourth position coordinate to the buffer. The buffer is used to cache the result matrix, which includes the fourth element value and the fourth position coordinate.

[0281] It should be noted that there are no time restrictions on steps 2203 and 2204 above, and steps 2203 and 2204 can be executed simultaneously.

[0282] In one embodiment of this application, a computing circuit is provided. This computing circuit is used in one or more steps 2201-2204, or one or more steps 2101-2103, in the above method embodiment. In practical applications, this computing circuit can be an ASIC, an FPGA, or a logic circuit, etc.

[0283] In another embodiment of this application, a computing system or chip is also provided, the structure of which can be as follows: Figure 3 As shown, it includes: a processor (taking a central processing unit as an example) 1 and a computing device 1. The processor 1 is used to send computing instructions to the computing device 1, and the computing device 2 is used to execute one or more steps 2201-2204, or one or more steps 2101-2103, in the above method embodiment.

[0284] In another embodiment of this application, a computing device is provided, the structure of which can be as follows: Figure 2 As shown, this device can specifically be a PCIe card, a SoC, a processor, or a server that includes the aforementioned hardware. See also Figure 2 The device includes a memory 201, a processor 202, a communication interface 203, and a bus 204. The communication interface 203 may include an input interface and an output interface.

[0285] The processor 202 can be configured to execute one or more steps 2201-2204, or one or more steps 2101-2103, in the above method embodiments. In some feasible embodiments, the processor 202 may include a computing unit, which can be used to support the processor in executing one or more steps in the above method embodiments. In practical applications, the computing unit may be an ASIC, FPGA, or logic circuit, etc. Of course, the computing unit can also be implemented by software, and this application embodiment does not impose specific limitations on it.

[0286] It should be noted that the components of the computing circuit, computing system, and computing device provided in the embodiments of this application are used to implement the functions of each step in the corresponding method embodiments.

[0287] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive (SSD).

[0288] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A computing device, characterized in that, include: Position coordinate comparison circuit and logic operation circuit; The position coordinate comparison circuit is used to compare the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector to obtain a first coordinate comparison result. The first vector and the second vector are both compressed vectors. The first vector includes a first element value and a first position coordinate of the first element value. The second vector includes a second element value and a second position coordinate of the second element value. The first matrix includes the first vector, and the second matrix includes the second vector. The first matrix and the second matrix are both compressed matrices. The first vector and the second vector are both compressed column vectors, or the first vector and the second vector are both compressed row vectors. When the first coordinate comparison result is a first comparison result indicating that the first position coordinate and the second position coordinate are the same, the logic operation circuit is used to perform operations on the first element value and the second element value to obtain an operation value, and output the operation result of the first vector and the second vector to the buffer, wherein the operation result is related to the operation value; The logic operation circuit includes an accumulator; The position coordinate comparison circuit is also used to receive an addition instruction and transmit the first comparison result to the accumulator according to the addition instruction; The accumulator is used to add the first element value and the second element value according to the first comparison result to obtain the sum of the first element value and the second element value. The sum is the operation value. The operation result includes a third element value and the third position coordinate of the third element value. The third element value is the sum value. The third position coordinate is the same as the first position coordinate. The first vector includes a fourth element value and the fourth position coordinate of the fourth element value. The first coordinate comparison result also includes a second comparison result, which is used to indicate that no position coordinate matching the fourth position coordinate was found in the second vector. The accumulator is further configured to output the fourth element value and the fourth position coordinate to the buffer based on the second comparison result, wherein the calculation result includes the fourth element value and the fourth position coordinate.

2. The computing device according to claim 1, characterized in that, The accumulator is further configured to output an invalid signal for the zero element value when the third element value is zero, the invalid signal indicating that the element values ​​in the result matrix do not include the zero element value and the position coordinates corresponding to the zero element value.

3. The computing device according to claim 2, characterized in that, The accumulator does not output the zero element value and the corresponding position coordinates to the buffer based on the invalid signal.

4. The computing device according to claim 1, characterized in that, The logic operation circuit includes a multiplier; The position coordinate comparison circuit is also used to receive a multiplication instruction and transmit the first comparison result to the multiplier according to the multiplication instruction; The multiplier is used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value. The product value is the operation value. The operation result includes a fifth element value and the fifth position coordinate of the fifth element value. The fifth element value is the product value. The fifth position coordinate is the same as the first position coordinate.

5. The computing device according to claim 1, characterized in that, The logic operation circuit includes an inner product operation circuit; The position coordinate comparison circuit is also used to receive an inner product instruction and transmit the first comparison result to the inner product operation circuit according to the inner product instruction; The inner product operation circuit is used to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the product value is the operation value, and the operation result is the sum of multiple product values.

6. The computing device according to claim 1, characterized in that, The logic operation circuit includes a multiplier and an accumulator, and the first coordinate comparison result also includes a third comparison result; The position coordinate comparison circuit is also used to receive multiply-accumulate calculation instructions and transmit the first comparison result to the multiplier according to the multiply-accumulate calculation instructions; The multiplier is further configured to multiply the first element value and the second element value according to the first comparison result to obtain the product value of the first element value and the second element value, the operation value includes the product value, and the product value is the fifth element value; The position coordinate comparison circuit is also used to compare the sixth position coordinate with the fifth position coordinate to obtain a third comparison result, and transmit the third comparison result to the accumulator. The fifth position coordinate is the same as the first position coordinate. The third comparison result indicates that the sixth position coordinate and the fifth position coordinate are the same. The sixth position coordinate is the position coordinate in the third vector. The third vector includes the sixth element value and the sixth position coordinate corresponding to the sixth element value. The accumulator is used to add the sixth element value and the fifth element value according to the third comparison result to obtain the sum of the sixth element value and the fifth element value. The calculated value includes the sum of the sixth element value and the fifth element value. The calculated result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value. The seventh position coordinate is the same as the sixth position coordinate.

7. The computing device according to any one of claims 1 to 6, characterized in that, The position coordinate comparison circuit is also used to compare the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain a second coordinate comparison result, wherein the second coordinate comparison result includes the first coordinate comparison result.

8. The computing device according to claim 7, characterized in that, The position coordinate comparison circuit includes a row coordinate comparison circuit and a column coordinate comparison circuit; the dimension of the first matrix is ​​M×N, and the dimension of the second matrix is ​​K×L; The row coordinate comparison circuit is used to compare the row coordinates of the m-th row in the first matrix and the row coordinates of the f-th row in the second matrix to obtain a row comparison result. The row comparison result indicates that the row coordinates of the m-th row and the row coordinates of the f-th row are the same, wherein m is less than or equal to M, and f is less than or equal to K. The column coordinate comparison circuit is used to compare the column coordinates of each element value in the m-th row with the column coordinates of each element value in the f-th row based on the row comparison result, to obtain a column comparison result. The column comparison result indicates that the n-th column coordinate of the m-th row is compared with the n-th column coordinate of the f-th row. The first comparison result includes the row comparison result and the column comparison result if all column coordinates are the same. The accumulator is further configured to, based on the first comparison result, combine the element value corresponding to the nth column coordinate of the mth row with the element value of the fth row... The element values ​​corresponding to the column coordinates of the m-th row are added together to obtain the third element value. The element value corresponding to the n-th column coordinate of the m-th row is the first element value. The element value corresponding to each column coordinate is the second element value, wherein n is less than or equal to N. Less than or equal to L.

9. The computing device according to claim 8, characterized in that, The row comparison result includes a first signal and a first value, and the column comparison result includes a second signal and a second value. The first signal is used to indicate the validity of the first value, and the first value is equal to the row coordinate of the m-th row. The second signal is used to indicate the validity of the second value, and the second value is equal to the column coordinate of the n-th column.

10. A calculation method, characterized in that, The method is applied to a computing device, and the method includes: Obtain calculation instructions, the calculation instructions include a first vector and a second vector, wherein the first vector and the second vector are respectively compressed vectors, the compressed vectors are obtained by splitting a compressed matrix, and the compressed vectors are either compressed column vectors or compressed row vectors. By comparing the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector, a first coordinate comparison result is obtained. The first vector includes a first element value and the first position coordinate of the first element value, and the second vector includes a second element value and the second position coordinate of the second element value. The first matrix includes the first vector, and the second matrix includes the second vector. The first matrix and the second matrix are both matrices in compressed format. The first vector and the second vector are both column vectors in compressed format, or the first vector and the second vector are both row vectors in compressed format. When the first coordinate comparison result is a first comparison result indicating that the first position coordinate and the second position coordinate are the same, the first element value and the second element value are calculated to obtain the calculated value, and the calculation result of the first vector and the second vector is output to the buffer. The calculation result is related to the calculated value. The calculation instruction is an addition instruction. When the first coordinate comparison result indicates that the first position coordinates and the second position coordinates are the same, the first element value and the second element value are calculated to obtain the calculated value, including: The first element value and the second element value are added together according to the first comparison result to obtain the sum of the first element value and the second element value, wherein the operation value is the sum value, and the operation result includes a third element value and the third position coordinate of the third element value, the third element value is the sum value, and the third position coordinate is the same as the first position coordinate; the first vector includes a fourth element value and the fourth position coordinate of the fourth element value, and the first coordinate comparison result further includes a second comparison result, the second comparison result being used to indicate that no position coordinate matching the fourth position coordinate was found in the second vector; the method further includes: Based on the second comparison result, the fourth element value and the fourth position coordinates are output to the buffer, and the calculation result includes the fourth element value and the fourth position coordinates.

11. The method according to claim 10, characterized in that, The method further includes: When the third element value is zero, an invalid signal is output for the zero element value. The invalid signal indicates that the element value in the calculation result does not include the zero element value and the position coordinates corresponding to the zero element value.

12. The method according to claim 11, characterized in that, The method further includes: Based on the invalid signal, the zero element value and the corresponding position coordinates of the zero element value are avoided from being output to the buffer.

13. The method according to claim 10, characterized in that, The calculation instruction is a multiplication instruction. When the first coordinate comparison result indicates that the first position coordinates and the second position coordinates are the same, the first element value and the second element value are operated on to obtain the calculated value, including: Based on the first comparison result, the first element value and the second element value are multiplied to obtain the product value of the first element value and the second element value. The product value is the operation value. The operation result includes the fifth element value and the fifth position coordinate of the fifth element value. The fifth element value is the product value, and the fifth position coordinate is the same as the first position coordinate.

14. The method according to claim 10, characterized in that, The calculation instruction is an inner product instruction. Based on the first comparison result, the first element value and the second element value are multiplied to obtain the product value of the first element value and the second element value. The product value is the operation value, and the operation result is the sum of multiple product values.

15. The method according to claim 10, characterized in that, The calculation instruction is a multiply-add instruction, and the first coordinate comparison result also includes a third comparison result; when the first coordinate comparison result is a first comparison result indicating that the first position coordinate and the second position coordinate are the same, the first element value and the second element value are operated on to obtain the operation value, including: Based on the first comparison result, the first element value and the second element value are multiplied to obtain the product value of the first element value and the second element value. The calculated value is the product value, and the product value is used as the fifth element value. The fifth position coordinates corresponding to the fifth element value are the same as the first position coordinates. By comparing the sixth position coordinate with the fifth position coordinate, a third comparison result is obtained. The third comparison result indicates that the sixth position coordinate and the fifth position coordinate are the same. The sixth position coordinate is the position coordinate in the third vector. The third vector includes the sixth element value and the sixth position coordinate corresponding to the sixth element value. The sixth element value and the fifth element value are added together according to the third comparison result to obtain the sum of the sixth element value and the fifth element value. The calculated value includes the sum of the sixth element value and the fifth element value. The calculated result includes the seventh element value and the seventh position coordinate corresponding to the seventh element value. The seventh element value is the sum of the sixth element value and the fifth element value. The seventh position coordinate is the same as the sixth position coordinate.

16. The method according to any one of claims 10 to 15, characterized in that, The first comparison result is obtained by comparing the position coordinates of the element values ​​in the first vector and the position coordinates of the element values ​​in the second vector, including: By comparing the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix, a second coordinate comparison result is obtained, which includes the first coordinate comparison result.

17. The method according to claim 16, characterized in that, The first matrix has dimensions M×N, and the second matrix has dimensions K×L; the comparison of the position coordinates of the element values ​​in the first matrix and the position coordinates of the element values ​​in the second matrix to obtain the second coordinate comparison result includes: By comparing the row coordinates of the m-th row in the first matrix and the row coordinates of the f-th row in the second matrix, a row comparison result is obtained. The row comparison result indicates that the row coordinates of the m-th row and the row coordinates of the f-th row are the same, wherein m is less than or equal to M, and f is less than or equal to K. Based on the row comparison results, the column coordinates of each element value in the m-th row and the column coordinates of each element value in the f-th row are compared to obtain the column comparison results. These column comparison results indicate the alignment between the n-th column coordinate of the m-th row and the n-th column coordinate of the f-th row. The first comparison result includes the row comparison result and the column comparison result if all column coordinates are the same. Based on the first comparison result, the element value corresponding to the nth column coordinate of the mth row and the element value corresponding to the nth column coordinate of the fth row are compared. The element values ​​corresponding to the column coordinates of the m-th row are added together to obtain the third element value. The element value corresponding to the n-th column coordinate of the m-th row is the first element value. The element value corresponding to each column coordinate is the second element value, wherein n is less than or equal to N. Less than or equal to L.

18. The method according to claim 17, characterized in that, The row comparison result includes a first signal and a first value, and the column comparison result includes a second signal and a second value. The first signal is used to indicate the validity of the first value, and the first value is equal to the row coordinate of the m-th row. The second signal is used to indicate the validity of the second value, and the second value is equal to the column coordinate of the n-th column.

19. A computing circuit, characterized in that, The computing circuit is used to perform the method as described in any one of claims 10 to 18.

20. A computing system, characterized in that, The system includes a processor and a computing device, the processor being configured to send computing instructions to the computing device, and the computing device being configured to execute the method as described in any one of claims 10 to 18.

21. A chip, characterized in that, The chip includes a processor, in which a computing device is integrated, the computing device being used to perform the computing method as described in any one of claims 10 to 18.

22. A matrix calculation device, characterized in that, The device includes the computing system of claim 20 or the chip of claim 21.

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