Virtualized Testing and System-Process Co-optimization Methods for the Impact of Residual Stress from Back-End Processes in Chip Integration on Transistor Device Performance

Abstract

This invention discloses a virtualized testing and system-process co-optimization method for assessing the impact of residual stress from post-integration processes on transistor device performance. Starting from post-integration process simulation and quantum transport equations, this invention studies the influence of residual stress on transistor device performance and evaluates performance indicators such as current-voltage curves, carrier distribution, and density of states. The main steps include: (1) modeling and simulating the post-integration process to determine the resulting residual stress; (2) combining residual stress with deformation potential theory and incorporating it into quantum transport simulation to consider the impact of stress on the device's band structure; and (3) analyzing the simulation results to achieve virtualized testing and system-technology co-optimization of the impact of residual stress from post-integration processes on transistor device performance. This method has significant application value in the fields of process system-technology co-optimization and semiconductor device simulation and design.

Description

Technical Field

[0001] This invention relates to the field of back-end process optimization and design in chip-to-chip integration, and to a virtualized testing and system-process co-optimization method for addressing the impact of residual stress in back-end processes on transistor device performance. Background Technology

[0002] Hybrid bonding has attracted significant attention in 2.5D / 3D integrated circuits / chips in recent years due to its unique advantages such as higher interconnect density, lower power consumption, and better signal integrity. In 2022, AMD and Intel respectively adopted hybrid bonding technology to integrate memory into computing chips in a vertically stacked manner or through a multi-chip interconnect bridge (EMIB), significantly improving memory bandwidth and reducing latency. The products were named Ryzen 75800X3D and Ponte Vecchio, respectively.

[0003] Currently, most research focuses on improving the effectiveness and reliability of hybrid bonding, including increasing Cu pillar density, lowering bonding temperature, and reducing stress migration [K. Lee et al., "Novel Hybrid Bonding Technology Using Ultra-High Density Cu Nano-Pillar for Exascale 2.5D / 3D Integration," IEEE Electron Device Letter, 2016].

[0004] However, although visible damage such as voids in Cu can be significantly reduced through process optimization, stress is still introduced into the chip during the final annealing and cooling steps of hybrid bonding. This will cause changes in transistor device characteristics such as current density, Y parameter and gate capacitance by changing the energy band structure of the semiconductor, which will further affect the performance of the processor.

[0005] On the other hand, FinFETs are widely used in logic computing in commercial high-performance processors because their three-dimensional channel structure can better suppress short-channel effects than planar MOSFETs. Due to the extremely small size of FinFETs, quantum effects are very significant and cannot be ignored, such as quantum confinement and source-drain tunneling. The non-balanced Green's function method [S. Datta, Quantumtransport: atom to transistor. Cambridge University Press, 2005.] can provide a general and rigorous framework to capture these quantum effects in FinFETs and to accurately evaluate FinFET performance.

[0006] However, few studies have investigated the impact of stress caused by hybrid bonding processes on FinFET quantum transport in chips, which is essential for performance evaluation of 3D integrated circuits and further system technology co-optimization.

[0007] This invention, based on the chip-integration back-end process modeling and calculation method and the quantum transport non-equilibrium Green's function method, provides a virtualized testing and system-process co-optimization method for the impact of chip-integration back-end process residual stress on transistor device performance by calculating the residual stress of the chip-integration back-end process and combining it with the non-equilibrium Green's function. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a virtualized testing and system-process co-optimization method for addressing the impact of residual stress from back-end processes in chip integration on transistor device performance.

[0009] The technical solution adopted in this invention is as follows:

[0010] A virtualized testing and system-process co-optimization method for addressing the impact of residual stress from back-end processes in chip integration on transistor device performance mainly includes:

[0011] Modeling and simulation of the post-integration process of core-particle assembly are performed to determine the residual stress it causes;

[0012] The residual stress from the post-processing of chip integration is combined with the deformation potential theory and substituted into quantum transport simulation to consider the effect of stress on the device's band structure.

[0013] By analyzing simulation results, we can achieve virtual testing of the impact of residual stress from post-chip integration processes on transistor device performance, thereby guiding optimization.

[0014] In the above technical solution, the post-processing of chip integration is further modeled to obtain the residual strain of the copper pillar process. This residual strain is used as a strain source to perform solid mechanics numerical simulation on the entire chip integration structure to obtain the distribution of residual stress in the transistor device. The residual stress is then introduced into the deformation potential Hamiltonian of the device quantum transport simulation to consider the influence of stress on the device band structure. Subsequently, the non-equilibrium Green's function and Poisson equation considering the stress deformation potential Hamiltonian are self-consistently solved to a steady state and post-processed to obtain the device performance indicators. Finally, a comprehensive evaluation of the influence of residual stress in the post-processing of chip integration on device performance is obtained.

[0015] Furthermore, the post-integration process of the core chip is modeled and simulated to obtain the distribution of residual stress, specifically including:

[0016] (1) Model the post-process of core-particle integration. The post-process of core-particle integration includes core surface smoothing, interconnect copper pillar fabrication, room temperature oxide-oxide bonding, heating annealing, and cooling. Among them, interconnect copper pillar fabrication introduces initial stress into the core. When heating, the copper pillars at the upper and lower cores expand and form bonds. During the annealing process, the stress of the copper pillars relaxes. During the cooling step, stress is generated due to the thermal mismatch between the copper pillars and the core, which ultimately forms residual stress in the post-process of core-particle integration.

[0017] (2) Based on the above modeling, the residual stress of the post-processing of chip integration is simulated by solid mechanics numerical simulation. The stress source is the thermal mismatch stress between the copper pillar and the oxide. The numerical equation to be solved is the stress balance equation, thereby obtaining the distribution of residual stress of post-processing of chip integration in transistor devices.

[0018] Furthermore, residual process stress is incorporated into the deformation potential Hamiltonian in the quantum transport simulation of the device to account for the influence of stress on the device's band structure. Specifically, this includes the following:

[0019] The residual stress from the post-processing of the chip integration is transferred from the device coordinate system to the crystal coordinate system, and the deformation Hamiltonian is calculated based on the deformation potential theory; the system Hamiltonian is:

[0020] H = H k·p +H SO +H strain

[0021] Among them, H k·p For the six-band k·p Hamiltonian, H SO H is the orbital-self-selected coupling Hamiltonian. strain It is the Hamiltonian of the stress-strain potential.

[0022] Furthermore, the non-equilibrium Green's function and Poisson equation are solved self-consistently to obtain the steady-state simulation results of the device, and the device performance characteristics are further extracted, including gate capacitance, current-voltage relationship curve, carrier distribution, or potential distribution, to evaluate the impact of post-chip integration process stress on device performance.

[0023] Furthermore, process parameters can be adjusted based on the evaluation results of the impact of residual stress in the post-integration process on device performance, or process parameters that optimize the performance of the chip, integrated circuit and transistor device can be selected from multiple sets of process parameters to achieve system-technology synergistic optimization of the chip.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. This invention provides a virtualized testing and system-process co-optimization method for the impact of residual stress from back-end chip integration processes on transistor device performance. Compared with traditional TCAD drift-diffusion-transport simulation, this method can characterize the impact of residual stress from chip integration on device performance at the level of stress affecting band structure, and evaluate device current-voltage curves, gate capacitance, etc., which has guiding significance for further improving device performance and has important application value in the fields of back-end chip integration process optimization, device design, and reliability assessment.

[0026] 2. This invention employs deformation potential theory to characterize the effect of stress on the band structure of a device, then combines it with a six-band k·p Hamiltonian, and further solves the non-equilibrium Green's function and Poisson equation self-consistently. Compared with traditional drift-diffusion transport simulations, this method can characterize the effect of stress on the band structure and depict quantum effects in advanced transistor devices, such as source-drain tunneling and quantum confinement effects. Attached Figure Description

[0027] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0028] Figure 1 The present invention provides a typical chip integration structure, which consists of a bonded copper pillar, a back-end process dielectric layer, and a silicon substrate, wherein Figure (a) is a 3D structure and Figure (b) is a schematic diagram of its XZ cross section;

[0029] Figure 2 This invention provides a typical transistor device structure, namely a fin field-effect transistor. Figure (a) shows the 3D structure, and Figure (b) is a schematic diagram of its YZ cross-section.

[0030] Figure 3 A virtualized test flowchart for the impact of back-end processes in chip integration on semiconductor device performance, provided by this invention;

[0031] Figure 4 This is a schematic diagram of stress evolution during the post-processing of core-particle integration.

[0032] Figure 5 This diagram illustrates the key steps in the post-processing of chip integration.

[0033] Figure 6 This is the stress distribution at the silicon substrate / silicon dioxide dielectric interface of the post-processing residual stress in the chip integration of this embodiment of the invention.

[0034] Figure 7 Figure (a) shows the residual stress distribution after the chip integration process in an embodiment of the present invention, and Figure (b) shows the stress distribution at the chip scale and the stress distribution at the device scale.

[0035] Figure 8 This is a schematic diagram of the distribution of fin field-effect transistors in the die according to an embodiment of the present invention. The position of the transistor is determined by a polar coordinate system, with the center of the copper pillar as the origin. The direction in which the transistor is located and its distance from the center of the copper pillar are used as the representation of the position.

[0036] Figure 9 The following figure illustrates the effect of residual stress from the post-processing of the chip integration on the turn-on current of devices with different crystal orientations and positions in this embodiment of the invention. Figure (a) corresponds to the crystal orientation of the device as (110) / [-110], Figure (b) corresponds to the crystal orientation of the device as (001) /

[100] , and Figure (c) corresponds to the crystal orientation of the device as (111) / [-110].

[0037] Figure 10 Figure (a) shows the effect of different copper pillar spacing on the transistor turn-on current and channel stress distribution in the embodiment of the present invention, Figure (b) shows the effect of different copper pillar diameters on the transistor turn-on current and channel stress distribution, and Figure (c) shows the effect of different annealing temperatures on the transistor turn-on current and channel stress distribution. Detailed Implementation

[0038] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0039] like Figure 1 The diagram shows a typical chip integration structure, including bonded copper pillars, a back-end process dielectric layer, and a silicon substrate. Figure 1 (a) is a 3D structure. Figure 1 (b) is a schematic diagram of its XZ cross-section; a typical nanoscale semiconductor electronic device is selected, taking the FinFET as an example, such as... Figure 2 As shown, this paper provides a comprehensive and detailed description of the virtualized performance test of the device under residual stress in the post-chip integration process. The virtualized test method for the effect of residual stress in the post-chip integration process on device performance proposed in this invention is not only applicable to fin field-effect transistors, but also applicable to the vast majority of nanoscale semiconductor electronic devices.

[0040] According to a specific example of the present invention, a virtualized testing and system-process co-optimization method for the impact of residual stress from back-end processes in die-integration on transistor device performance includes the following steps:

[0041] like Figure 3As shown, a virtualized testing and system-process co-optimization method is provided to address the impact of residual stress from post-chip integration processes on transistor device performance. First, a model is created for the post-chip integration process, which typically includes chip surface smoothing, interconnect copper pillar fabrication, room temperature oxide-oxide bonding, temperature annealing, and cooling. Key steps are as follows: Figure 5 As shown, the stress change process in the corresponding copper column is as follows: Figure 4 As shown, when the temperature is increased before annealing, the copper pillar attempts to expand, but compressive stress is formed in the copper due to the constraint of the surrounding dielectric. Subsequently, during the extended annealing process, the stress in the copper pillar is observed to be relieved, and a relatively low compressive stress is obtained at high temperatures. When cooled from the annealed state to room temperature, the stress in the copper pillar rapidly increases to a high tensile value. Subsequently, the residual strain of the copper pillar obtained from the modeling (Equation 1) is used as the strain source to perform solid mechanics numerical simulation on the entire chip-integrated structure to obtain the distribution of residual stress in the transistor after chip integration. This step can be accomplished by solving the equilibrium equation (Equation 2). Subsequently, the residual stress is introduced into the Hamiltonian in the device quantum transport simulation (Equation 3), and further quantum transport simulation with self-consistent solution of the non-equilibrium Green's function (Equation 5) and Poisson equation (Equation 4) is performed. The results, such as the current (Equation 6), are further calculated to accurately evaluate the transistor device performance affected by the residual stress of the chip integration process. By changing different process parameters and conducting multiple rounds of virtualization testing, process parameters that optimize the performance of transistor devices and chips can be obtained, achieving system-technology co-optimization of post-chip integration processes and transistor device performance. Specifically:

[0042] Modeling the post-integration process of the core-particle assembly is performed. The interconnect copper pillars introduce initial stress into the core-particle assembly. During heating, the copper pillars at the upper and lower core-particle locations expand and form bonds. The stress in the copper pillars relaxes during annealing. During the cooling step, stress is generated due to thermal mismatch between the copper pillars and the core-particle assembly, ultimately forming residual stress in the post-integration process. The residual strain in the copper pillars is expressed as...

[0043] ε=α(T room -T anneal (1)

[0044] Where α is the coefficient of thermal expansion of the material, T room At room temperature, T anneal This refers to the annealing temperature.

[0045] Based on the above modeling, solid mechanics numerical simulations were performed on the residual stress from the post-integration process. Numerical methods such as the finite element method or finite difference method could be used. The stress source was the thermal mismatch stress between the copper pillar and the oxide. The numerical equation obtained was the stress balance equation, which yielded the distribution of residual stress from the post-integration process in the transistor device. The stress balance equation took the following form:

[0046]

[0047] Among them, F x，y，z It is a stress load, σ x，y，z It is normal stress, τ xy(yz)(zx) It is shear stress.

[0048] The residual stress in the core is transformed from the device coordinate system to the crystal coordinate system and substituted into the deformation potential Hamiltonian. The deformation potential Hamiltonian is then added to the six-band k·p Hamiltonian to obtain the total Hamiltonian, which is substituted into the non-equilibrium Green's function to account for the stress effect on the energy bands in the simulation. The form of the system Hamiltonian is as follows:

[0049] H = H k·p +H SO +H strain (3)

[0050] Among them, H k·p For the six-band k·p Hamiltonian, H SO H is the orbital-self-selected coupling Hamiltonian. strain It is the Hamiltonian of the stress-strain potential.

[0051] A self-consistent iterative solution is performed for the non-equilibrium Green's function and the Poisson equation. The Poisson equation is in the following form:

[0052]

[0053] Where, ε r ε is the relative permittivity of the material, ε0 is the vacuum permittivity, V is the electric potential, q is the elementary charge, and N is the relative permittivity of the material. D(A) denoted as donor (acceptor) doping concentration, and n(p) as electron (hole) concentration.

[0054] The unbalanced Green's function takes the following form:

[0055] G r =[EI-HU-∑ s -∑ D ] -1 (5)

[0056] Where E is the energy level, I is the identity matrix, H is the Hamiltonian, U is the electric potential, and ∑ s(D) The source (drain) self-energy is determined; and the convergence of the solution results is judged. The error is relative error, and the physical quantity to be judged is electric potential or current density. If the error of the current step is less than the error tolerance, it is judged as non-convergence, and the iterative calculation continues until convergence. Otherwise, the iteration ends and post-processing is performed to extract device performance such as gate capacitance, current-voltage relationship curve, carrier distribution, electric potential distribution, etc., and to evaluate the impact of post-processing stress on device performance.

[0057] The formula for calculating the current is as follows:

[0058]

[0059] in, G is the reduced Planck constant, Trace is the trace of the matrix, and G is the trace of the matrix. ＞ It is greater than the Green's function, e is the elementary charge, q is the layer number, E is the energy level, and R is the coupling matrix between layer q and layer q+1.

[0060] The evaluation results of the impact of residual stress in the post-integration process on device performance can be used to guide the optimization and adjustment of process parameters, or to further select the process parameters that optimize the performance of the chip, integrated circuit and transistor device from multiple sets of process parameters, so as to achieve system-technology synergistic optimization of the chip.

[0061] The method of the present invention is for Figure 1 and Figure 2 The simulation was performed using examples, and the relevant parameters used are listed in Table 1.

[0062] Table 1 Device-related parameters

[0063]

[0064] Figure 6 To model and simulate the stress distribution of residual stress at the silicon substrate / silicon dioxide dielectric interface after the chip integration process; Figure 7 In (a), the residual stress of the post-processing of the chip integration is distributed at the chip scale. It can be observed that there is a sudden change in stress at the interface between the transistor device and the dielectric. This is because the material of the transistor channel is silicon, and its Young's modulus is different from that of the oxide dielectric. Figure 7 In Figure (b), the residual stress from the post-processing of the chip integration is distributed at the transistor device scale, where the zz stress component is much larger than other stress components. Figure 8 This is a schematic diagram of the distribution of the fin field-effect transistor in the die. The position of the transistor is determined by a polar coordinate system, with the center of the copper pillar as the origin. The direction in which the transistor is located and its distance from the center of the copper pillar are used as the representation of its position. Figure 9 The effect of residual stress from the post-processing of the chip integration on the turn-on current of transistors at different positions in different crystal phases is shown in Figure (a), where the crystal orientation of the device is (110) / [-110], the crystal orientation of the device in Figure (b) is (001) /

[100] , and the crystal orientation of the device in Figure (c) is (111) / [-110]. Figure 10Figure (a) shows the effect of different copper pillar spacing on transistor turn-on current and channel stress distribution in this example, Figure (b) shows the effect of different copper pillar diameters on transistor turn-on current and channel stress distribution, and Figure (c) shows the effect of different annealing temperatures on transistor turn-on current and channel stress distribution.

[0065] Simulation results show that post-chip integration processes introduce stresses ranging from tens to hundreds of megapascals into transistors, with the zz stress component significantly larger than other stress components. Residual process stress leads to increased transistor turn-on current, with the largest change observed directly below the copper pillars. The impact gradually decreases as the transistor moves further away from the copper pillars. Increasing the copper pillar spacing, decreasing the copper pillar diameter, or adjusting the annealing temperature can reduce residual process stress in the transistor, thereby minimizing the impact of the process on transistor performance. This invention provides a virtualized testing and system-process co-optimization method for assessing the impact of residual process stress on transistor device performance in post-chip integration, which has significant application value in 3D integrated circuit design, semiconductor process optimization, and transistor device design.

[0066] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A virtualized testing and system-process co-optimization method for the impact of residual stress from back-end processes in chip-to-chip integration on transistor device performance, characterized in that, Modeling the post-processing of chip integration yields the residual strain of the copper pillar process, which is then used as a strain source. Solid mechanics numerical simulations are performed on the entire chip-integrated structure to obtain the distribution of residual stress in the transistor device. The residual stress is then incorporated into the deformation potential Hamiltonian of the device's quantum transport simulation to account for the stress's influence on the device's band structure. Subsequently, the non-equilibrium Green's function and Poisson equation considering the stress deformation potential Hamiltonian are self-consistently solved to a steady state, and post-processing is performed to obtain the device's performance indicators. Finally, a comprehensive evaluation of the impact of residual stress from the post-processing of chip integration on device performance is obtained. These include: Modeling and simulation of post-integration processes for core assembly are performed to determine the resulting residual stress; specifically including: (1) Model the post-process of core-particle integration. The post-process of core-particle integration includes core surface smoothing, interconnect copper pillar fabrication, room temperature oxide-oxide bonding, heating annealing, and cooling. Among them, interconnect copper pillar fabrication introduces initial stress into the core. When heating, the copper pillars at the upper and lower cores expand and form bonds. During the annealing process, the stress of the copper pillars relaxes. During the cooling step, stress is generated due to the thermal mismatch between the copper pillars and the core, which ultimately forms residual stress in the post-process of core-particle integration. (2) Based on the above modeling, the residual stress of the post-processing of chip integration is simulated by solid mechanics numerical simulation. The stress source is the thermal mismatch stress between the copper pillar and the oxide. The numerical equation to be solved is the stress balance equation. In this way, the distribution of residual stress of post-processing of chip integration in transistor devices is obtained. The residual stress from post-integration processes is combined with deformation potential theory and incorporated into quantum transport simulations to account for the impact of stress on the device's band structure; specifically, the following is included: The residual stress from the post-processing of the chip integration is transferred from the device coordinate system to the crystal coordinate system, and the deformation potential Hamiltonian is calculated based on the deformation potential theory; the system Hamiltonian is: ， in, For a six-band k·p Hamiltonian, For orbital-self-selected coupled Hamiltonians, The Hamiltonian is the stress-deformation potential. By analyzing simulation results, we can achieve virtual testing of the impact of residual stress from post-chip integration processes on transistor device performance, thereby guiding optimization.

2. The virtualized testing and system-process co-optimization method for the impact of residual stress from back-end processes in chip integration on transistor device performance, as described in claim 1, is characterized in that: The non-equilibrium Green's function and Poisson equation are solved self-consistently to obtain the steady-state simulation results of the device, and the device performance characteristics are further extracted, including gate capacitance, current-voltage relationship curve, carrier distribution, or potential distribution, to evaluate the impact of residual stress from the post-chip integration process on device performance.

3. The virtualized testing and system-process co-optimization method for the impact of residual stress from back-end processes in chip integration on transistor device performance, as described in claim 1, is characterized in that: Adjust process parameters based on the evaluation results of the impact of residual stress in the post-integration process on device performance, or further select process parameters from multiple sets of process parameters to optimize the performance of the chip, integrated circuit and transistor device, so as to achieve system-technology synergistic optimization of the chip.

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