A test case generation method, device, storage medium and electronic device

Abstract

The present invention proposes a test case generation method, device, storage medium and electronic device, which performs simulation test on a simulation object according to a basic test case to obtain a first simulation test result; determines the missing timing critical path according to the first simulation test result; obtains a trigger mode set corresponding to the missing timing critical path, the trigger mode set includes one or more trigger modes, and the trigger mode includes an execution mode of a trigger configuration and an execution mode of a trigger instruction; inserts a trigger mode in the trigger mode set into a basic test case to obtain a corrected first test case. By detecting the timing critical path, the basic test case adjustment is completed, thereby saving time for in-depth understanding of the design of the chip to be tested, thereby shortening the entire project cycle and saving personnel costs.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a test case generation method, device, storage medium and electronic device. Background Art

[0002] During the chip production process, the produced chips need to be screened and classified according to a set of standards, and then divided into different speed levels. This stage is called speed binning. At present, the method to complete speed binning is to add test circuits in advance during chip design, and perform corresponding tests after chip tape-out to complete the screening, but there are certain limitations. Specific test circuits need to be added in advance. The higher the test accuracy requirements, the more complex the test circuit. There is also a risk that the test circuit will not work, and the test cost is high.

[0003] Under this problem, how to get rid of the need to add specific test circuits in advance and quickly and efficiently obtain test cases so as to accurately complete chip testing has become a difficult problem that technical personnel in this field are concerned about. Summary of the invention

[0004] The purpose of the present invention is to provide a test case generation method, device, storage medium and electronic device to improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a test case generation method, the method comprising:

[0007] Performing simulation test on the simulation object according to the basic test case to obtain a first simulation test result, wherein the simulation object is a simulation model of the chip to be tested, and the first simulation test result includes a waveform diagram corresponding to each simulation signal;

[0008] Determine a missing timing critical path according to the first simulation test result, wherein the missing timing critical path is a timing critical path not covered by the simulation test result, and the timing critical path indicates that two corresponding simulation signals are flipped in adjacent cycles according to a predetermined order;

[0009] Acquire a trigger mode set corresponding to the missing timing critical path, wherein the trigger mode set includes one or more trigger modes, and the trigger mode includes an execution mode of a trigger configuration and an execution mode of a trigger instruction;

[0010] Insert a trigger mode in the trigger mode set into the basic test case to obtain a modified first test case.

[0011] In a second aspect, an embodiment of the present invention provides a test case generation device, the device comprising:

[0012] A first processing unit is used to perform a simulation test on a simulation object according to a basic test case to obtain a first simulation test result, wherein the simulation object is a simulation model of a chip to be tested, and the first simulation test result includes a waveform diagram corresponding to each simulation signal;

[0013] A second processing unit is used to determine a missing timing critical path according to the first simulation test result, wherein the missing timing critical path is a timing critical path not covered by the simulation test result, and the timing critical path indicates that two corresponding simulation signals are flipped in adjacent cycles according to a predetermined order;

[0014] The second processing unit is further used to obtain a trigger mode set corresponding to the missing timing critical path, wherein the trigger mode set includes one or more trigger modes, and the trigger mode includes an execution mode of a trigger configuration and an execution mode of a trigger instruction;

[0015] The second processing unit is further configured to insert a trigger mode in the trigger mode set into the basic test case to obtain a modified first test case.

[0016] In a third aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, and the computer program implements the above method when executed by a processor.

[0017] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store one or more programs; when the one or more programs are executed by the processor, the above method is implemented.

[0018] Compared with the prior art, the test case generation method, device, storage medium and electronic device provided in the embodiment of the present invention perform simulation test on the simulation object according to the basic test case to obtain the first simulation test result, wherein the simulation object is the simulation model of the chip to be tested, and the first simulation test result includes the waveform diagram corresponding to each simulation signal; determine the missing timing critical path according to the first simulation test result, wherein the missing timing critical path is the timing critical path not covered by the simulation test result, and the timing critical path indicates that the corresponding two simulation signals are flipped in adjacent cycles according to a predetermined order; obtain the trigger mode set corresponding to the missing timing critical path, the trigger mode set includes one or more trigger modes, and the trigger mode includes the execution mode of the trigger configuration and the execution mode of the trigger instruction; insert a trigger mode in the trigger mode set into the basic test case to obtain the corrected first test case. By detecting the timing critical path, the basic test case adjustment is completed, thereby saving time for in-depth understanding of the design of the chip to be tested, thereby shortening the entire project cycle, and also saving personnel costs.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0022] Figure 2 One of the flow charts of the test case generation method provided in the embodiment of the present invention.

[0023] Figure 3 The second flowchart of the test case generation method provided in the embodiment of the present invention.

[0024] Figure 4 A unit schematic diagram of a test case generating device provided in an embodiment of the present invention.

[0025] In the figure: 10 - processor; 11 - memory; 12 - bus; 13 - communication interface; 501 - first processing unit; 502 - second processing unit. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0030] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0031] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0033] Currently, building test cases requires staff to be very familiar with the internal design of the chip (IP). However, most chips are complex chips purchased from third parties (such as IP vendors), such as the central processing unit (CPU). It is not easy for staff to deeply understand the design details such as the chip pipeline, making it difficult to generate test vectors in combination with physical implementation. The speed of the chip is not only related to the chip design, but also to the physical implementation such as the clock network and power network. Therefore, it is necessary to combine IP design and physical implementation to ensure that the test vectors are accurate and effective.

[0034] To this end, an embodiment of the present invention provides a test case generation method, which generates new test vectors based on basic test cases and physical implementation for speed binning. This method is simple, easy to operate and can be quickly iterated. The basic test case can be a test case designed by a third party (such as an IP vendor) based on chip design.

[0035] An embodiment of the present invention provides an electronic device, which may be a computer device or a server device. Figure 1 , a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12, and the processor 10 is used to execute an executable module stored in the memory 11, such as a computer program.

[0036] The processor 10 may be an integrated circuit chip having the ability to process signals. In the implementation process, each step of the test case generation method may be completed by an integrated logic circuit of hardware in the processor 10 or by instructions in the form of software. The above-mentioned processor 10 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components.

[0037] The memory 11 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0038] The bus 12 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. Figure 1 Although only one bidirectional arrow is used in the figure, it does not mean that there is only one bus 12 or only one type of bus 12 .

[0039] The memory 11 is used to store programs, such as programs corresponding to the test case generation device. The test case generation device includes at least one software function module that can be stored in the memory 11 in the form of software or firmware or fixed in the operating system (OS) of the electronic device. After receiving the execution instruction, the processor 10 executes the program to implement the test case generation method.

[0040] Possibly, the electronic device provided by the embodiment of the present invention further includes a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0041] It should be understood that Figure 1 The structure shown is only a schematic diagram of a portion of the electronic device. The electronic device may also include Figure 1More or fewer components as shown, or with Figure 1 Different configurations shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0042] A test case generation method provided by an embodiment of the present invention can be applied to but not limited to Figure 1 For detailed procedures, please refer to the electronic equipment shown in Figure 2 ,The test case generation method includes : S11, S12, S13 and S14, which are described in detail as follows.

[0043] S11, performing a simulation test on the simulation object according to a basic test case to obtain a first simulation test result.

[0044] The simulation object is a simulation model of the chip to be tested, and the first simulation test result includes a waveform corresponding to each simulation signal. The waveform includes the flipping moment of the simulation signal. Optionally, the first simulation test result also includes a voltage margin waveform of the simulation test point.

[0045] Basic test cases can be run on a hardware accelerated emulator (EMU platform for short) to perform simulation tests on the simulation object.

[0046] S12, determining the missing timing critical path according to the first simulation test result.

[0047] The missing timing critical path is a timing critical path not covered by the simulation test result, and the timing critical path indicates that the two corresponding simulation signals are flipped in adjacent cycles according to a predetermined order.

[0048] S13, obtaining a trigger mode set corresponding to the missing timing critical path.

[0049] The trigger mode set includes one or more trigger modes, and the trigger mode includes the execution mode of the trigger configuration and the execution mode of the trigger instruction;

[0050] S14, inserting a trigger method in the trigger method set into the basic test case to obtain a modified first test case.

[0051] In the test case generation method provided in the embodiment of the present invention, the dependence on the test circuit is eliminated, and the basic test case adjustment is completed by detecting the timing critical path, thereby saving time for in-depth understanding of the design of the chip to be tested, thereby shortening the entire project cycle and saving personnel costs.

[0052] Please refer to Figure 3In an optional implementation, after obtaining the corrected test case, the test case generation method further includes: S15, S16, S17, S18, S19 and S20, which are specifically described as follows.

[0053] S15, performing a simulation test on the simulation object according to the first test case to obtain a second simulation test result.

[0054] The second simulation test result includes a voltage margin waveform diagram of a simulation test point.

[0055] S16, determine whether the amplitude change rate is greater than the target threshold. If yes, execute S17; if no, execute S18.

[0056] The amplitude change rate represents the change rate of the amplitude corresponding to the voltage margin waveform diagram in the second simulation test result relative to the set amplitude. Optionally, the set amplitude is the amplitude of the voltage margin waveform diagram of the simulation test point in the first simulation test result, or a preset value determined by the staff based on experience.

[0057] If it is greater than the target threshold, repeated adjustment is required, so S17 is executed.

[0058] S17, selecting one of the remaining trigger modes in the trigger mode set and inserting it into the basic test case to obtain a modified first test case.

[0059] Among them, the remaining trigger methods in the trigger method set are trigger methods that have not been inserted into basic test cases.

[0060] After selecting one of the remaining trigger modes in the trigger mode set and inserting it into the basic test case to obtain the modified first test case, S15 is repeatedly executed until the amplitude change rate is less than or equal to the target threshold, or there are no remaining trigger modes in the trigger mode set.

[0061] In an optional implementation, when the amplitude change rates of the modified first test cases corresponding to all trigger modes are greater than the target threshold, a basic test case with the smallest amplitude change rate is determined to obtain the modified first test case, and then S18 can be executed.

[0062] S18, testing the sample chip according to the first test case to obtain a third test result.

[0063] The third test result includes voltage test data of the test points of the sample chip.

[0064] S19, determining the lowest voltage moment according to the third test result.

[0065] S20, adjusting the triggering moment of the triggering mode added to the first test case according to the lowest voltage moment, so that the triggering moment is within a preset range of the lowest voltage moment.

[0066] Based on the above, regarding the content in S12, the embodiment of the present invention further provides an optional implementation, please refer to the following. S12, the step of determining the missing timing critical path according to the first simulation test result, includes:

[0067] S121, running the path detection script to identify the waveform corresponding to the target simulation signal to obtain an identification result.

[0068] The identification result includes a flipping moment of a target simulation signal, and the target simulation signal is a simulation signal related to a timing critical path.

[0069] S122, determine whether the timing critical path is satisfied according to the identification result. If not, execute S123; if satisfied, execute S124.

[0070] Optionally, determine whether the flipping moments of the two simulation signals corresponding to the timing critical path in the recognition result are consistent with the requirement that the two simulation signals in the timing critical path flip in adjacent cycles according to a predetermined order. If they are consistent, it is determined that the recognition result satisfies the timing critical path, and S124 is executed; if they are inconsistent, it is determined that it does not satisfy the timing critical path, and S123 is executed.

[0071] S123, determining the unsatisfied timing critical path as a missing timing critical path.

[0072] S124, determining that the satisfied timing critical path is a covered timing critical path.

[0073] Optionally, the test case generation method further includes: S31 and S32, which are described in detail as follows.

[0074] S31, obtaining a timing analysis report of the chip to be tested.

[0075] Among them, the timing analysis report includes a timing critical path list, and the timing critical path list includes multiple timing critical paths; the timing analysis report corresponds to speed binning.

[0076] S32, generating a path detection script according to the timing analysis report, where the path detection script is used to identify a waveform diagram corresponding to a target simulation signal.

[0077] On the basis of the above, regarding the content in S13, the embodiment of the present invention further provides an optional implementation, please refer to the following: S13, the step of obtaining a trigger mode set corresponding to the missing timing critical path includes: S131, which is as follows.

[0078] S131, abstracting the triggering mode corresponding to the missing timing critical path from the technical manual of the chip to be tested to obtain a triggering mode set.

[0079] Please refer to Table 1 below, which is a comparison of the actual results of the basic test case and the second test case. It can be seen that at the same frequency, the Vmin measured by the second test case is higher, which means that the second test case can cover more timing critical paths and can perform speed binning more accurately and effectively.

[0080]

[0081] Table 1

[0082] See also Figure 4 , Figure 4 A test case generating device is provided in an embodiment of the present invention. Optionally, the test case generating device is applied to the electronic device described above.

[0083] The test case generating device includes: a first processing unit 501 and a second processing unit 502 .

[0084] The first processing unit 501 is used to perform a simulation test on a simulation object according to a basic test case to obtain a first simulation test result, wherein the simulation object is a simulation model of a chip to be tested, and the first simulation test result includes a waveform diagram corresponding to each simulation signal;

[0085] The second processing unit 502 is used to determine the missing timing critical path according to the first simulation test result, wherein the missing timing critical path is the timing critical path not covered by the simulation test result, and the timing critical path indicates that the two corresponding simulation signals are flipped in adjacent cycles according to a predetermined order;

[0086] The second processing unit 502 is further used to obtain a trigger mode set corresponding to the missing timing critical path, the trigger mode set includes one or more trigger modes, and the trigger mode includes an execution mode of a trigger configuration and an execution mode of a trigger instruction;

[0087] The second processing unit 502 is further configured to insert a trigger mode in the trigger mode set into the basic test case to obtain a modified first test case.

[0088] Optionally, the first processing unit 501 may execute the above-mentioned S11, S15 and S18, and the second processing unit 502 may execute the above-mentioned other steps.

[0089] It should be noted that the test case generation device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above embodiment.

[0090] The embodiment of the present invention also provides a storage medium, which stores computer instructions and programs, and when the computer instructions and programs are read and run, the test case generation method of the above embodiment is executed. The storage medium may include a memory, a flash memory, a register, or a combination thereof.

[0091] The following provides an electronic device, which may be a computer device or a server device. Figure 1 As shown, the above-mentioned test case generation method can be implemented; specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 can be a CPU. The memory 11 is used to store one or more programs. When the one or more programs are executed by the processor 10, the test case generation method of the above-mentioned embodiment is executed.

[0092] In summary, the test case generation method, device, storage medium and electronic device provided by the embodiment of the present invention perform simulation test on the simulation object according to the basic test case to obtain the first simulation test result, wherein the simulation object is the simulation model of the chip to be tested, and the first simulation test result includes the waveform diagram corresponding to each simulation signal; determine the missing timing critical path according to the first simulation test result, wherein the missing timing critical path is the timing critical path not covered by the simulation test result, and the timing critical path indicates that the two corresponding simulation signals are flipped in adjacent cycles according to a predetermined order; obtain the trigger mode set corresponding to the missing timing critical path, the trigger mode set includes one or more trigger modes, and the trigger mode includes the execution mode of the trigger configuration and the execution mode of the trigger instruction; insert a trigger mode in the trigger mode set into the basic test case to obtain the corrected first test case. By detecting the timing critical path, the basic test case adjustment is completed, thereby saving time for in-depth understanding of the design of the chip to be tested, thereby shortening the entire project cycle, and also saving personnel costs.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0094] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A test case generation method, characterized in that: The method comprises: Performing simulation test on the simulation object according to the basic test case to obtain a first simulation test result, wherein the simulation object is a simulation model of the chip to be tested, and the first simulation test result includes a waveform diagram corresponding to each simulation signal; Determine a missing timing critical path according to the first simulation test result, wherein the missing timing critical path is a timing critical path not covered by the simulation test result, and the timing critical path indicates that two corresponding simulation signals are flipped in adjacent cycles according to a predetermined order; Acquire a trigger mode set corresponding to the missing timing critical path, wherein the trigger mode set includes one or more trigger modes, and the trigger mode includes an execution mode of a trigger configuration and an execution mode of a trigger instruction; Insert a trigger mode in the trigger mode set into the basic test case to obtain a modified first test case.

2. The test case generation method according to claim 1, characterized in that: After obtaining the corrected test case, the method further includes: Performing a simulation test on the simulation object according to the first test case to obtain a second simulation test result, wherein the second simulation test result includes a voltage margin waveform diagram of a simulation test point; Determine whether the amplitude change rate is greater than a target threshold, wherein the amplitude change rate represents a change rate of the amplitude corresponding to the voltage margin waveform diagram relative to a set amplitude; If it is greater than the target threshold, one of the remaining trigger modes in the trigger mode set is selected and inserted into the basic test case to obtain a corrected first test case.

3. The test case generation method according to claim 2, characterized in that: The set amplitude is the amplitude of the voltage margin waveform diagram of the simulation test point in the first simulation test result.

4. The test case generation method according to claim 2, characterized in that: The method further comprises: If it is less than or equal to the target threshold, testing the sample chip according to the first test case to obtain a third test result, wherein the third test result includes voltage test data of the test point of the sample chip; Determining the lowest voltage moment according to the third test result; According to the minimum voltage moment, the trigger moment of the trigger mode added to the first test case is adjusted so that the trigger moment is within a preset range of the minimum voltage moment.

5. The test case generation method according to any one of claims 1 to 4, characterized in that: The step of determining the missing timing critical path according to the first simulation test result includes: Run a path detection script to identify a waveform corresponding to a target simulation signal to obtain an identification result, wherein the identification result includes a flipping moment of the target simulation signal, and the target simulation signal is a simulation signal related to the timing critical path; Determining whether a timing critical path is satisfied according to the identification result; If not, the unsatisfied timing critical path is determined as a missing timing critical path.

6. The test case generation method according to claim 5, characterized in that: The method further comprises: Obtaining a timing analysis report of the chip under test, wherein the timing analysis report includes a timing critical path list, and the timing critical path list includes multiple timing critical paths; The path detection script is generated according to the timing analysis report, and the path detection script is used to identify the waveform diagram corresponding to the target simulation signal.

7. The test case generation method according to any one of claims 1 to 4, characterized in that: The step of obtaining a trigger mode set corresponding to the missing timing critical path includes: The trigger mode corresponding to the missing critical timing path is abstracted from the technical manual of the chip to be tested to obtain the trigger mode set.

8. A test case generating device, characterized in that: The device comprises: A first processing unit is used to perform a simulation test on a simulation object according to a basic test case to obtain a first simulation test result, wherein the simulation object is a simulation model of a chip to be tested, and the first simulation test result includes a waveform diagram corresponding to each simulation signal; A second processing unit is used to determine a missing timing critical path according to the first simulation test result, wherein the missing timing critical path is a timing critical path not covered by the simulation test result, and the timing critical path indicates that two corresponding simulation signals are flipped in adjacent cycles according to a predetermined order; The second processing unit is further used to obtain a trigger mode set corresponding to the missing timing critical path, wherein the trigger mode set includes one or more trigger modes, and the trigger mode includes an execution mode of a trigger configuration and an execution mode of a trigger instruction; The second processing unit is further configured to insert a trigger mode in the trigger mode set into the basic test case to obtain a modified first test case.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: A processor and a memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method according to any one of claims 1 to 7 is implemented.

Images