A Design Method for Hardware-in-the-Loop Simulation Model of High-Voltage Cascade Energy Storage System

Abstract

The present invention discloses a method for designing a hardware-in-the-loop simulation model of a high-voltage cascaded energy storage system and a simulation system. The method includes the steps of: constructing a plurality of component simulation models required in the hardware-in-the-loop simulation test according to the hardware-in-the-loop simulation test content, and obtaining the time-varying characteristics of the parameters of the component simulation models; embedding the component simulation models into a large-step simulation model or a small-step simulation model based on the hardware-in-the-loop simulation test instructions and the time-varying characteristics of the parameters of the component simulation models; obtaining the data to be exchanged between the large-step simulation model and the small-step simulation model; dividing the data to be exchanged into several groups according to the time-varying characteristics of the data to be exchanged, and establishing a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping result; performing a hardware-in-the-loop simulation test, running the large-step simulation model and the small-step simulation model, and updating the step size of the large-step simulation model.

Description

Technical Field

[0001] The present invention belongs to the technical field of hardware-in-the-loop simulation of energy storage systems, and particularly relates to a method for designing a hardware-in-the-loop simulation model of a high-voltage cascaded energy storage system and a simulation system. Background Technique

[0002] The high-voltage direct-connected cascaded energy storage system is a new energy storage system technology developed in recent years, which can be directly connected to the medium-voltage power grid (6 kV, 10 kV, 35 kV) without passing through a transformer. The high-voltage direct-connected cascaded energy storage system has significant advantages in aspects such as the conversion efficiency of the energy storage converter, the cost of large-capacity systems, the response time, the single-machine power capacity, the utilization rate of battery capacity, and the energy balance between battery clusters.

[0003] The high-voltage direct-connected cascaded energy storage system adopts the idea of soft combination of energy storage converters and battery clusters, and reasonably decomposes hundreds of thousands of battery cells and dozens of megawatt high-power converters in a megawatt-level energy storage power station into energy storage modules composed of small-capacity battery clusters and energy storage converters with power matching thereto. These energy storage modules (including battery clusters and energy storage converters) are connected in cascade form, and the voltage reaches 6 - 35 kV, so as to be directly connected to the medium-voltage power grid. By adopting technologies such as one-cluster-one-management, intelligent fault bypass, and multi-level series connection on the AC side, the organization and management of a large number of battery cells in a megawatt-level energy storage power station are realized, the inter-cluster imbalance of batteries is realized at the level of the energy storage converter, the circulating current phenomenon of battery clusters is greatly reduced, and the safety, the utilization rate of battery capacity, and the power quality of the connected electric energy of the energy storage power station are effectively improved.

[0004] In the high-voltage direct-connected cascaded energy storage system, several to hundreds of energy storage modules (the number is related to the voltage level) are cascaded in each phase and directly connected to the power grid through inductors. The number of energy storage modules in a three-phase high-voltage direct-connected cascaded energy storage system can be up to hundreds, and the number of power devices can be up to thousands. The turn-on time and time interval of these power devices are in the range of several microseconds to dozens of microseconds. Currently, the full-bridge topology shown in Figure 1 is widely adopted for cascaded energy storage modules. The system includes inductors (LA, LB, LC, etc.), switches (QF1, QL1), resistors (RA, RB, RC, etc.). Each energy storage module includes: power devices (Q1, Q2, Q3, Q4), an inductor (L1), a capacitor (C1), a battery cluster (BAT), switches (K1, K2, K3, etc.). The power of the high-voltage direct-connected cascaded energy storage system is generally above the MW level, and the cost of the energy storage system is high (in millions of yuan). In addition, some operating performances require special cooperation from the power grid. These factors make the actual test cost and trial-and-error cost of the cascaded energy storage system very high. The hardware-in-the-loop simulation technology that emerged in recent years has become an important technical means for testing the functions of cascaded energy storage systems, verifying the functions of the entire energy storage system, verifying control algorithms, and evaluating the impact of energy storage system access.

[0005] The hardware-in-the-loop simulation system mainly includes a hardware-in-the-loop simulation device, a signal collection circuit board, and a cascaded energy storage control system. They are connected by communication means such as high-speed optical fibers. Typical applications include Figure 2 . The hardware-in-the-loop simulation device can use a high-speed board (FPGA board). The simulation algorithm logic required for the cascaded energy storage system test is designed as a model and runs on the FPGA board. The logic algorithm of the simulation model is implemented using hardware logic gates. The disadvantage is that the cost of FPGA devices is relatively high. The hardware-in-the-loop simulation device can also be applied in combination with a high-speed board and a slow board (such as a CPU board). In the simulation algorithm logic required for the cascaded energy storage system test, the slow-running part (such as battery clusters, inductors, etc. in the energy storage module) establishes a simulation logic model (longer step-size simulation model) in the slow board; the fast-running part (such as power devices in the energy storage module, the network of the cascaded energy storage system, etc.) establishes a simulation algorithm logic model (shorter step-size simulation model) in the high-speed board. Among them, the running time step of the longer step-size simulation model is generally in the range of 25 - 500 us, and the time step of the shorter step-size simulation model is generally in the range of 0.1 - 5 us. The two parts of the model need to run in coordination and synchronization, and exchange data with the time step of the longer step-size simulation model. Within the step time of each longer step-size simulation model, the shorter step-size simulation model receives the data to be interacted sent by the longer step-size simulation model, and the longer step-size simulation model receives the data to be interacted sent by the shorter step-size simulation model.

[0006] A relatively large high-voltage direct-connected cascaded energy storage system includes hundreds of energy storage modules, and each energy storage module has hundreds of battery cells, several power devices, several electrical components such as capacitors, inductors, and resistors. If the system of these components is designed as a model, the model will be very large and complex. If all these models run in high-speed boards, the requirements for high-speed boards will be very high, and multiple high-speed boards are often required to achieve this, greatly increasing the cost; and for FPGA boards, the model design and development cycle is long. If the method of combining high-speed boards and slow boards is adopted, the amount of data to be interacted between the models running on the high-speed board and the models running on the slow board is very large, and the data interaction time will be very long, affecting the operation of the simulation model. The commonly used solutions in the prior art are to increase the communication bandwidth of data interaction or increase the running step size of the simulation model. However, both of these methods have certain disadvantages. The former will greatly increase the purchase cost of simulation equipment and the difficulty of hardware design, while the latter will increase the time granularity of the simulation, affecting the simulation accuracy and reliability of the simulation model.

[0007] In view of the disadvantages that the existing FPGA board simulation test equipment is expensive, and the data interaction between the FPGA board and the CPU board in the combined simulation test equipment requires a large amount of simulation step time for the long-step simulation model and the short-step simulation model during operation. According to the operating characteristics of the high-voltage direct-connected cascade energy storage system, the present invention proposes a simulation model design method that reduces data interaction time, reduces the simulation step, and improves the simulation effect. Summary of the Invention

[0008] To overcome one or more of the above technical defects, the present invention provides a hardware-in-the-loop simulation model design method for a high-voltage cascade energy storage system, which reduces data interaction time, reduces the simulation step, and improves the simulation effect.

[0009] To solve the above problems, the first aspect of the present invention provides a hardware-in-the-loop simulation model design method for a high-voltage cascade energy storage system, including the steps of:

[0010] Construct a large-step simulation model and a small-step simulation model;

[0011] According to the hardware-in-the-loop simulation test content, construct simulation models of several components required during the hardware-in-the-loop simulation test, and obtain the time-varying characteristics of the component simulation model parameters;

[0012] Based on the hardware-in-the-loop simulation test instructions and the time-varying characteristics of the component simulation model parameters, embed the component simulation model into the large-step simulation model or the small-step simulation model;

[0013] Obtain the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyze the time-varying characteristics of the data to be exchanged;

[0014] According to the time-varying characteristics of the data to be exchanged, divide the data to be exchanged into several groups, and establish a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping results;

[0015] Conduct hardware-in-the-loop simulation tests, run the large-step simulation model and the small-step simulation model, and update the step of the large-step simulation model.

[0016] Further, the obtaining of the time-varying characteristics of the component simulation model parameters includes:

[0017] Obtain the parameters of the component simulation model;

[0018] Identify the data type of the parameter, obtain the time-varying characteristic formula corresponding to the parameter data type, and analyze the data size of the parameter. Among them, the data type of the parameter includes analog quantity and switch state quantity, and the time-varying characteristic of the analog quantity is , , and the time-varying characteristic of the switch state quantity is , is the shortest time for the switching state quantity to change.

[0019] Furthermore, it further includes the steps:

[0020] Based on the hardware performance of the hardware-in-the-loop simulation device and the time-varying characteristics of the component simulation model parameters, set the first step size and the second step size. Among them, the first step size is the simulation time step size of the large-step simulation model, and the second step size is the simulation time step size of the small-step simulation model. The first step size is less than the time-varying characteristics of the parameters of the component simulation model embedded in the large-step simulation model, and the second step size is less than the time-varying characteristics of the parameters of the component simulation model embedded in the small-step simulation model.

[0021] Furthermore, the analyzing the time-varying characteristics of the data to be exchanged includes:

[0022] Identify the data type of the data to be exchanged. Among them, the data type includes analog quantity and switching state quantity. The time-varying characteristic of the analog quantity is , , and the time-varying characteristic of the switching state quantity is , is the shortest time for the switching state quantity to change.

[0023] Furthermore, the performing the hardware-in-the-loop simulation test, running the large-step simulation model and the small-step simulation model, and updating the step size of the large-step simulation model includes:

[0024] Perform the hardware-in-the-loop simulation test, run the large-step simulation model and the small-step simulation model, and obtain the actual running time within each step of the large-step simulation model and the actual running time within each step of the small-step simulation model;

[0025] Update the first step size according to the actual running time within each step of the large-step simulation model and the actual running time within each step of the small-step simulation model.

[0026] The second aspect of the present invention provides a hardware-in-the-loop simulation system for a high-voltage cascaded energy storage system, which is used to implement the above method. The hardware-in-the-loop simulation system for a high-voltage cascaded energy storage system includes a hardware-in-the-loop simulation device, a signal receiving circuit board, and a cascaded energy storage converter control system. The hardware-in-the-loop simulation device, the signal receiving circuit board, and the cascaded energy storage converter control system are connected by high-speed optical fiber communication. The hardware-in-the-loop simulation device includes a high-speed board and a slow-speed board.

[0027] The high-speed board is used to run the small-step simulation model, and the slow-speed board is used to run the large-step simulation model. When performing the hardware-in-the-loop simulation test, the large-step simulation model and the small-step simulation model are run simultaneously, and data exchange is performed between the high-speed board and the slow-speed board.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] According to the operating characteristics of the high-voltage direct-connected cascaded energy storage system, the present invention discloses a method for designing a hardware-in-the-loop simulation model of a high-voltage cascaded energy storage system. The steps include constructing a large-step simulation model and a small-step simulation model; according to the content of the hardware-in-the-loop simulation test, constructing a plurality of component simulation models required during the hardware-in-the-loop simulation test, and obtaining the time-varying characteristics of the parameters of the component simulation models; based on the hardware-in-the-loop simulation test instructions and the time-varying characteristics of the parameters of the component simulation models, embedding the component simulation models into the large-step simulation model or the small-step simulation model; obtaining the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyzing the time-varying characteristics of the data to be exchanged; according to the time-varying characteristics of the data to be exchanged, dividing the data to be exchanged into several groups, and establishing a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping results; performing a hardware-in-the-loop simulation test, running the large-step simulation model and the small-step simulation model, and updating the step size of the large-step simulation model. By analyzing the time-varying characteristics of the parameters of the component simulation models corresponding to the components of the high-voltage cascaded energy storage system, reasonably embedding each component simulation model into the large-step simulation model or the small-step simulation model, grouping the data to be exchanged according to time requirements, adopting different communication mechanisms for different grouping situations, and exchanging data according to the time required by the time simulation, the amount of data exchange is reduced, the data exchange time is reduced, thereby reducing the communication bandwidth and equipment cost, reducing the model running time, achieving the reduction of the time step of the large-step simulation model running in the slow-speed board, and improving the accuracy and effectiveness of the model. Description of the Drawings

[0030] The following further details the specific embodiments of the present invention with reference to the drawings, wherein:

[0031] Figure 1 The cascaded energy storage module with a full-bridge topology described in the background art;

[0032] Figure 2 The existing hardware-in-the-loop simulation system described in the background art;

[0033] Figure 3 The flowchart of the method for designing a hardware-in-the-loop simulation model of a high-voltage cascaded energy storage system described in Embodiment 1. Specific Embodiments

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0036] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present invention, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0037] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or device.

[0038] In the description of the present invention, it should also be noted that unless otherwise clearly specified and limited, the terms "set" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0039] Embodiment 1

[0040] This embodiment discloses a method for designing a hardware-in-the-loop simulation model of a high-voltage cascaded energy storage system, as Figure 3 , including the steps:

[0041] S1. Construct a large-step simulation model and a small-step simulation model, where the large-step simulation model is a simulation model with a longer simulation time step, and the small-step simulation model is a simulation model with a shorter simulation time step.

[0042] S2. According to the hardware-in-the-loop simulation test content, construct several component simulation models required in the hardware-in-the-loop simulation test process, and obtain the time-varying characteristics of the parameters of the component simulation models.

[0043] According to the common components in the high-voltage cascaded energy storage system and the hardware-in-the-loop simulation test instructions, obtain the components required in the hardware-in-the-loop simulation test process, and construct corresponding component simulation models based on the characteristics of each component. At the same time, the power grid system is equivalent to a power grid source model and a disturbance source model.

[0044] In this embodiment, the obtaining of the time-varying characteristics of the parameters of the component simulation models includes:

[0045] Obtain the parameters of the component simulation model. The parameters of the component simulation model include capacitor current, capacitor voltage, inductor current, inductor voltage, resistor current, resistor voltage, battery current, battery voltage, battery SOC, battery temperature, conduction state of power electronic switch devices, opening and closing states of mechanical switches, power grid source current, power grid source voltage, power grid source amplitude, power grid source frequency, disturbance source current, disturbance source voltage, disturbance source amplitude, and disturbance source frequency, etc.

[0046] Identify the data type of the parameter, obtain the time-varying characteristic formula corresponding to the parameter data type, and analyze the data size of the parameter. Among them, the data type of the parameter includes analog quantity and switch state quantity. For the analog quantity, perform frequency-domain analysis on it, and the time-varying characteristic of the analog quantity is , If an analog quantity is composed of frequency-domain quantities such as 1Hz, 50Hz, 100Hz, 1000Hz, etc., and the frequency of 1000Hz and below is concerned for the simulation test of this analog quantity, then the maximum frequency in the frequency domain is 1000Hz. For the switch state quantity, analyze the shortest time it takes to change, and the time-varying characteristic of the switch state quantity is , is the shortest time for the switch state quantity to change. If a switch state quantity can remain unchanged for one minute or one hour, but the shortest time to change is not less than 1 second, then the shortest time for it to change is 1 second. The data size of the analog quantity is 16 bits, 32 bits, or 64 bits, and the specific size is determined by the data accuracy requirement. The higher the data accuracy requirement, the more bits are required. The data size of the switch state quantity is 1 bit.

[0047] In this embodiment, it also includes the steps:

[0048] Based on the hardware performance of the hardware-in-the-loop simulation device and the time-varying characteristics of the component simulation model parameters, set a first step size and a second step size. Among them, the first step size is the simulation time step size of the large-step simulation model, and the second step size is the simulation time step size of the small-step simulation model. The first step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the large-step simulation model, and the second step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the small-step simulation model. The step size of the simulation model is smaller than the time-varying characteristics of the component simulation model parameters by at least one order of magnitude, that is .

[0049] S3. Based on the hardware-in-the-loop simulation test instructions and the time-varying characteristics of the component simulation model parameters, embed each component simulation model into the large-step simulation model or the small-step simulation model.

[0050] S4. Obtain the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyze the time-varying characteristics of the data to be exchanged.

[0051] In this embodiment, the analysis of the time-varying characteristics of the data to be exchanged includes:

[0052] Identify the data type of the data to be exchanged. Among them, the data type includes analog quantity and switch status quantity. The time-varying characteristic of the analog quantity is , and the time-varying characteristic of the switch status quantity is , is the shortest time for the switch status quantity to change..

[0053] S5. Divide the data to be exchanged into several groups according to the time-varying characteristics of the data to be exchanged, and establish a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping result. For example, the data to be exchanged within each simulation time step is taken as a group, the data to be exchanged within every two simulation time steps is taken as a group, ……, the data to be exchanged within every n simulation time steps is taken as a group. Specifically, n is valued according to actual needs.

[0054] Establish a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping result of the data to be exchanged. The grouped data of the data to be exchanged are one copy, two copies, …… n copies respectively. In each simulation time step, one copy of each of the above-mentioned grouped numbers is exchanged respectively, that is, corresponding to all grouped data, 1 / 2 grouped data, ……, 1 / n grouped data in each grouped data.

[0055] S6. Conduct hardware-in-the-loop simulation testing, run the large-step simulation model and the small-step simulation model, and update the step size of the large-step simulation model.

[0056] In this embodiment, step S6 includes:

[0057] Perform hardware-in-the-loop simulation testing, run the large-step simulation model and the small-step simulation model, repeat step S5, and obtain the actual running time within each step of the large-step simulation model and the actual running time within each step of the small-step simulation model.

[0058] According to the actual running time within each step of the large-step simulation model and the actual running time within each step of the small-step simulation model, update the first step length so that the first step length and the second step length are as small as possible, while also having enough time to run the simulation and perform data exchange.

[0059] During the actual operation of the high-voltage direct-connected cascaded energy storage system, the relationship between the parameter changes of each component and time is not consistent. Some parameters change significantly within sub-microseconds, some parameters change significantly within microseconds, some parameters change significantly within dozens or hundreds of microseconds, and some parameters are observed to change only within time ranges such as seconds, minutes, or even hours and days.

[0060] The present invention proposes a model design method that improves data exchange efficiency, reduces data exchange time, and thus reduces the simulation time step of the model in hardware-in-the-loop simulation testing, improving the model operation performance. According to the simulation requirements of the cascaded energy storage system, statistically obtain the components required for model design and construct corresponding component simulation models, and pay attention to the parameters of the component simulation models in hardware-in-the-loop simulation testing. Analyze the time characteristics of the parameters and the requirements of hardware-in-the-loop simulation testing, and allocate the component simulation models to simulation models with different time steps respectively to construct simulation models with different simulation time steps, namely the large-step simulation model and the small-step simulation model.

[0061] Analyze the parameter data that needs to be exchanged during the operation of simulation models with different simulation time steps and the time characteristics of these data to be exchanged, and determine the time requirements for data exchange. Group the data that needs to be exchanged according to the data exchange time requirements: the data that needs to be exchanged every 1 time step, the data that needs to be exchanged every 2 time steps,..., the data that needs to be exchanged every n time steps. Exchange the data according to the exchange time requirements of each group: exchange all grouped data every 1 time step, exchange all data every 2 time steps (i.e., exchange 1 / 2 of all grouped data every time step),..., exchange all data every n time steps (i.e., exchange 1 / 2 of all grouped data every time step).

[0062] Run the simulation model for trial operation, detect the actual running time of the large-step simulation model and the small-step simulation model within the time step, and thus adjust the simulation time steps, data grouping results, and communication mechanism of the two models so that the simulation time step is as small as possible while having enough margin to ensure the reliable operation of the model.

[0063] Example 2

[0064] This embodiment discloses a hardware-in-the-loop simulation system for a high-voltage cascaded energy storage system, which is used to implement the method described in Embodiment 1. The hardware-in-the-loop simulation system for the high-voltage cascaded energy storage system includes a hardware-in-the-loop simulation device, a signal receiving circuit board, and a cascaded energy storage converter control system. The hardware-in-the-loop simulation device, the signal receiving circuit board, and the cascaded energy storage converter control system are connected by high-speed optical fiber communication. The hardware-in-the-loop simulation device includes a high-speed board and a slow-speed board. The high-speed board is used to run a small-step simulation model, and the slow-speed board is used to run a large-step simulation model. When performing hardware-in-the-loop simulation tests, the large-step simulation model and the small-step simulation model are run simultaneously, and data exchange is performed between the high-speed board and the slow-speed board.

[0065] The following takes the hardware-in-the-loop simulation model design of a 35kV-25MW-50MWh star connection (a total of 192 energy storage modules in three phases, 64 energy storage modules in each phase) cascaded energy storage system as an example for illustration:

[0066] The high-speed board uses an FPGA board with a main frequency of 125MHz; the slow-speed board uses an industrial computer (a 6-core CPU with a main frequency of 4.0GHz). Communication between the high-speed board and the slow-speed board is carried out using PCIe. Each energy storage module includes 4 IGBT bridges, a capacitor bank C, an inductor L, a cluster of batteries (240 battery cells), an input switch, a pre-charge circuit, a cooling water circuit, etc.

[0067] According to the common components in the high-voltage cascaded energy storage system and the hardware-in-the-loop simulation test instructions, simulation models of components such as the power grid model, the switch connected to the power grid model, the pre-charge circuit, the energy storage access inductor, and the IGBTs in all energy storage modules are designed and embedded in the high-speed board for operation; simulation models of components such as the battery cluster Bat (240 battery cells), capacitor bank C, inductor L, input switch, pre-charge circuit, and cooling water circuit in all energy storage modules are designed and embedded in the slow-speed board for operation.

[0068] Generally speaking, the simulation time step of the small-step simulation model in the FPGA board is set to be no greater than 0.5us, and this simulation time step can meet the requirements of the hardware-in-the-loop simulation of the high-voltage cascaded energy storage system. The simulation time step of the large-step simulation model in the CPU board is generally 25~100us. For the CPU board, the smaller the simulation time step, the better the simulation effect; in this embodiment, the simulation time step of the large-step simulation model in the CPU board is initially set to 100us. And according to the actual running time of the simulation model, the data grouping and communication mechanism are adjusted to adjust the simulation time step of the simulation model in the CPU board to be as small as possible.

[0069] Obtain the data to be exchanged between the large-step simulation model and the small-step simulation model: IGBT trigger pulses, capacitor bank voltage, current flowing through the IGBT bridge, battery cluster voltage, battery cluster SOC, extreme values of battery cluster voltage SOC temperature, switch control / feedback signals within the module, grid parameter signals, small disturbance parameter signals, DA proportional bias parameters.

[0070] When using the existing technology, the amount of data to be exchanged is: , where is the data exchanged within each current 1 simulation time step, is the data exchanged within each current 2 simulation time steps... is the data exchanged within each current n simulation time steps.

[0071] Group the data to be exchanged and establish a communication mechanism (according to the simulation time step of the large-step simulation model within the CPU board):

[0072] Data that the small-step simulation model within the FPGA board needs to exchange within each 1 simulation time step: IGBT trigger pulses, switch control / feedback signals within the module.

[0073] Data that the large-step simulation model within the CPU board needs to exchange within each 1 simulation time step: capacitor bank voltage, current flowing through the IGBT bridge, battery cluster current.

[0074] Data that needs to be exchanged within every 2 simulation time steps: grid parameter signals, small disturbance parameter signals, DA proportional bias parameters.

[0075] …

[0076] Data that needs to be exchanged within every 20 simulation time steps: battery cluster voltage, battery cluster SOC, maximum and minimum values of cell voltage SOC temperature within the battery cluster.

[0077] When using the method provided by the present invention, the amount of data to be exchanged is: , where is the data exchanged within each current 1 simulation time step, is the data exchanged within each current 2 simulation time steps... is the data exchanged within each current n simulation time steps, and n is the number of parts into which the data is divided into n parts; at this time, the amount of data to be exchanged is reduced by approximately half compared to the amount of data to be exchanged when using the existing technology.

[0078] Based on the above grouping results, establish a communication mechanism between the small-step simulation model in the FPGA board and the large-step simulation model in the CPU board, and conduct hardware-in-the-loop simulation tests. At this time, the running time of the small-step simulation model in the FPGA board is less than 0.3 us, and the running time of the large-step simulation model in the CPU board is about 48.5 us. The running time of the small-step simulation model on the FPGA board meets the simulation requirements, and the running time of the large-step simulation model on the CPU board is close to 50 us, meeting the simulation requirements for running under 100 us, and the time margin is sufficient. When directly adjusting the simulation time step to 50 us without adjusting the data packets to be exchanged and the corresponding communication mechanism, since the simulation running time of the CPU board is very close to the simulation time step, there is a stability risk for the simulation model. Therefore, adjust the simulation time step to 50 us and correspondingly adjust the grouping results and communication mechanism.

[0079] After adjusting the simulation time step to 50 us:

[0080] Data that needs to be exchanged within each 1 simulation time step: IGBT trigger pulse, switch control / feedback signal within the module.

[0081] Data that needs to be exchanged within every 2 simulation time steps: capacitor bank voltage, current flowing into the IGBT bridge, battery cluster current.

[0082] Data that needs to be exchanged within every 4 simulation time steps: grid parameter signal, small disturbance parameter signal, DA proportional bias parameter.

[0083] …

[0084] Data that needs to be exchanged within every 40 simulation time steps: battery cluster voltage, battery cluster SOC, maximum and minimum values of cell voltage, SOC, and temperature within the battery cluster.

[0085] After adjusting the simulation time step, the amount of data to be exchanged is: , where is the data exchanged within the current 1 simulation time step, is the data exchanged within the current every 2 simulation time steps... is the data exchanged within the current every n simulation time steps, and n is the number of parts the data is divided into; compared with the previous amount of data to be exchanged, it is reduced by about half.

[0086] Conduct hardware-in-the-loop simulation tests, run the large-step simulation model and the small-step simulation model, and obtain that the simulation running time of the FPGA board is less than 0.3 us, and the simulation running time of the CPU board is less than 35 us. At this time, the simulation model can have sufficient time margin to maintain the simulation time step at 50 us.

[0087] For other specific implementation details, please refer to Embodiment 1 and will not be elaborated here.

[0088] The design of the existing hardware-in-the-loop simulation model for high-voltage cascaded energy storage systems usually adopts the following two common methods:

[0089] 1. Design a simulation model based on a high-speed board (such as an FPGA board), and design models for all components in the high-voltage cascaded energy storage system on the high-speed board.

[0090] 2. Adopt a combination of a high-speed board (such as an FPGA board) and a slow board (such as a CPU board). The simulation model in the high-speed board and the simulation model in the slow board reduce the data exchange time by increasing the communication bandwidth.

[0091] Compared with the above two methods, the simulation model design method proposed by the present invention analyzes the simulation requirements, analyzes each component involved in the hardware-in-the-loop simulation test of the high-voltage cascaded energy storage system, constructs the corresponding component simulation models, analyzes the time characteristics of the component simulation models (equivalent to analyzing the time characteristics of the components), and reasonably embeds each component simulation model into the simulation models with different simulation time steps on the high-speed board and the slow board. Group the data to be exchanged between the two models according to different exchange time requirements, establish different communication mechanisms for different groups, and exchange data according to the time required for time simulation, reducing the amount of data exchange and the data exchange time.

[0092] The high-speed board cards used in the hardware-in-the-loop simulation model for high-voltage cascaded energy storage systems have good rapidity (short running time steps) but are costly, and the model development time cycle of the board cards is long. The slow-speed board cards used in the hardware-in-the-loop simulation model for high-voltage cascaded energy storage systems are inexpensive but have poor rapidity (long running time steps, which become the short board of the simulation test performance). By adopting the hardware-in-the-loop simulation model design method proposed by the present invention, compared with the existing hardware-in-the-loop simulation model design method, allocating some component simulation models to the high-speed board cards (small-step simulation models) can greatly reduce the cost of the hardware-in-the-loop simulation equipment (board cards). And reasonably allocate each component simulation model to the high-speed board cards and slow-speed board cards according to the time characteristics and requirements. For the component models that need to focus on microseconds / sub-microseconds during operation, such as power electronic switch devices and their peripheral circuits (including power switch devices, cascaded inductors, etc.), power grid models, power grid disturbance models, etc., arrange them on the high-speed board cards (small-step simulation models). For the component models that need to focus on dozens of microseconds and longer during operation, such as battery and its peripheral capacitor / inductor / resistor circuits, mechanical switches, etc., arrange them on the slow-speed board cards (large-step simulation models). Group the data to be exchanged and establish different communication mechanisms according to different grouped data, which greatly reduces the data exchange time, reduces the communication bandwidth, reduces the equipment cost, thereby reducing the model running time, achieving the reduction of the time step of the running model in the slow-speed board cards, and improving the accuracy and effectiveness of the model.

[0093] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Therefore, any modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A design method for a hardware-in-the-loop simulation model of a high-voltage cascaded energy storage system, characterized in that, Including the steps: Construct a large-step simulation model and a small-step simulation model; According to the hardware-in-the-loop simulation test content, construct several component simulation models required in the hardware-in-the-loop simulation test process, and obtain the time-varying characteristics of the component simulation model parameters; Based on the hardware-in-the-loop simulation test instructions and the time-varying characteristics of the component simulation model parameters, embed the component simulation model into the large-step simulation model or the small-step simulation model; Obtain the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyze the time-varying characteristics of the data to be exchanged; According to the time-varying characteristics of the data to be exchanged, divide the data to be exchanged into several groups, and establish a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping results; Conduct a hardware-in-the-loop simulation test, run the large-step simulation model and the small-step simulation model, and update the step size of the large-step simulation model, including: Conduct a hardware-in-the-loop simulation test, run the large-step simulation model and the small-step simulation model, and obtain the actual running time within each step of the large-step simulation model and the actual running time within each step of the small-step simulation model; According to the actual running time within each step of the large-step simulation model and the actual running time within each step of the small-step simulation model, update the first step size, where the first step size is the simulation time step size of the large-step simulation model.

2. The design method of the hardware-in-the-loop simulation model for the high-voltage cascaded energy storage system according to claim 1, wherein The obtaining the time-varying characteristics of the component simulation model parameters includes: Obtain the parameters of the component simulation model; Identify the data type of the parameter, obtain the time variation characteristic formula corresponding to the parameter data type, and analyze the data size of the parameter. Among them, the data types of the parameters include analog quantities and switch status quantities. The time variation characteristic of the analog quantity is , is the maximum frequency in the frequency domain of the analog quantity. The time variation characteristic of the switch status quantity is , is the shortest time for the switch status quantity to change.

3. The design method of the high-voltage cascaded energy storage system hardware-in-the-loop simulation model according to claim 1, characterized in that It also includes the steps: Based on the hardware performance of the hardware-in-the-loop simulation device and the time-varying characteristics of the component simulation model parameters, set the first step size and the second step size, where the second step size is the simulation time step size of the small-step simulation model, the first step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the large-step simulation model, and the second step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the small-step simulation model.

4. The design method of the hardware-in-the-loop simulation model for the high-voltage cascaded energy storage system according to claim 1, wherein The analyzing the time-varying characteristics of the data to be exchanged includes: Identify the data types of the data to be exchanged, where the data types include analog quantities and switch status quantities. The time variation characteristic of the analog quantity is , is the maximum frequency in the frequency domain of the analog quantity. The time variation characteristic of the switch status quantity is , is the shortest time for the switch status quantity to change.

5. A hardware-in-the-loop simulation system for a high-voltage cascaded energy storage system, which is used to implement the method described in any one of claims 1-4. The hardware-in-the-loop simulation system for the high-voltage cascaded energy storage system includes a hardware-in-the-loop simulation device, a signal receiving circuit board, and a cascaded energy storage converter control system. The hardware-in-the-loop simulation device, the signal receiving circuit board, and the cascaded energy storage converter control system are connected by high-speed optical fiber communication. It is characterized in that, The hardware-in-the-loop simulation device includes a high-speed board and a slow-speed board, The high-speed board is used to run the small-step simulation model, the slow-speed board is used to run the large-step simulation model. When conducting a hardware-in-the-loop simulation test, the large-step simulation model and the small-step simulation model are run simultaneously, and data exchange is carried out between the high-speed board and the slow-speed board.

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