Design method of FLASH charge pump controller based on dual-core system

Abstract

The invention relates to a design method of a FLASH charge pump controller based on a dual-core system, according to the design method of the FLASH charge pump controller, by driving the charge pump controller, arbitration of work of a dual-FLASH internal charge pump based on the dual-core CPU system is achieved, and an internal state machine of the FLASH controller comprises an IDLE initial state, a programming state PROGRAM, an erasing state ERASE and a reading state READ; according to the design method, through the design method of the charge pump controller, arbitration of work of the charge pump in the dual FLASH based on the dual-core system is achieved, so that only one CPU can program or erase the flash memory at any given time, and the effect that the other CPU reads data from the flash memory and executes codes is not affected.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a design method for a FLASH charge pump controller based on a dual-core system. Background Art

[0002] FLASH is an electrically erasable / programmable non-volatile memory that can be erased and reprogrammed multiple times in blocks. It is widely used in program memory to simplify code development. Secondly, it can be used as a static data memory. For a dual-core system, it is very important to ensure the coordination between the two processing cores. Among them, how to design the logic inside the FLASH charge pump controller of the dual-core system while taking into account an efficient and reliable voltage conversion mechanism is an urgent problem to be solved. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a FLASH charge pump controller design method based on a dual-core system. The FLASH charge pump controller design method achieves arbitration of the operation of the dual FLASH internal charge pumps based on the dual-core CPU system by driving the charge pump controller. The internal state machine of the FLASH controller includes an IDLE initial state, a programming state PROGRAM, an erase state ERASE and a read state READ, and includes the following steps:

[0004] Step S1: If a read request is input in the IDLE initial state, the state jumps to the read state READ. In this state, a read completion flag is input, and the state machine jumps back to the IDLE initial state;

[0005] Step S2: If an erase request is input in the IDLE initial state, the ownership of the charge pump must be determined at the same time. If the ownership belongs to this FLASH controller, the state jumps to the erase state ERASE, otherwise the state remains IDLE;

[0006] Step S3: When the state machine is in the erase state ERASE, an erase completion flag is input and the state machine returns to IDLE;

[0007] Step S4: If a programming request is input in the IDLE initial state, the ownership of the charge pump must be determined at the same time. If the ownership belongs to this FLASH controller, the state jumps to the programming state PROGRAM, otherwise the state remains IDLE;

[0008] Step S5: When the state machine is in the programming state PROGRAM, a programming completion flag is input and the state machine returns to IDLE.

[0009] In one embodiment of the present invention, each CPU subsystem includes an independent FLASH controller, and the dual cores share a charge pump controller for arbitrating the operation of the internal charge pumps of the dual FLASH memories, wherein the controller structure includes a FLASH controller module I of the CPU I subsystem, a FLASH controller module II of the CPU II subsystem, a FLASH memory I, a FLASH memory II and a charge pump controller module; the FLASH controller module I realizes the control of BANK I of the FLASH memory I in the CPU I subsystem, the FLASH controller module II of the CPU II subsystem realizes the control of BANK II of the FLASH memory II in the CPU II subsystem, and the charge pump controller module realizes the decision on the erasing and writing control rights of the dual cores.

[0010] In one embodiment of the present invention, the charge pump controller module state machine includes an active state and a sleep state; the initial state is the active state, and if a sleep control signal is input, the state enters the sleep state; after entering the sleep state, if an active control signal is input, the state returns to the active state.

[0011] In one embodiment of the present invention, in the charge pump controller module, the user configures the charge pump erase ownership register. If the write information is configured as FLASH controller module I and the state machine is in an active state, the charge pump ownership belongs to BANK I; if the write information is configured as FLASH controller module II and the state machine is in an active state, the charge pump ownership belongs to BANK II.

[0012] In one embodiment of the present invention, the FLASH controller module I and the FLASH controller module II have the same internal structure, and both include a FLASH memory, an erase control module, a programming control module, a reading module, and an erase and read request processing module.

[0013] In one embodiment of the present invention, the charge pump controller implements control of the pump sleep / active state and arbitration of the operation of the dual FLASH internal charge pumps, and outputs arbitration signals to the FLASH controller module I and the FLASH controller module II.

[0014] The above technical solution of the present invention has the following advantages over the prior art: the design method of the FLASH charge pump controller based on the dual-core system described in the present invention achieves arbitration of the internal charge pump operation of the dual FLASH based on the dual-core system through a design method of a charge pump controller, thereby achieving that only one CPU can program or erase its flash memory at any given time without affecting the other CPU reading data from the flash memory and executing code. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0016] Figure 1 A structural diagram of a FLASH charge pump controller design method based on a dual-core system provided by an embodiment of the present invention;

[0017] Figure 2 A schematic diagram of the dual-core charge pump arbitration implementation provided by an embodiment of the present invention;

[0018] Figure 3 The internal state machine schematic diagram of the FLASH controller provided by the embodiment of the present invention;

[0019] Figure 4 A schematic diagram of a charge pump controller state machine provided by an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of charge pump configuration information provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] This embodiment provides a FLASH charge pump controller design method based on a dual-core system, including:

[0022] like Figure 1 As shown, the structural diagram of the FLASH charge pump controller design method based on the dual-core system.

[0023] like Figure 2 As shown, it is the schematic diagram of dual-core charge pump arbitration implementation.

[0024] According to the configuration of dual CPUs, the charge pump controller outputs the charge pump arbitration signal to the state machine inside the FLASH controller module I and FLASH controller module II. By controlling the operation of the state machine, the charge pump is controlled, thereby controlling the programming and erasing of the FLASH flash memory.

[0025] like Figure 3As shown in the figure, it is the principle diagram of the internal state machine of the FLASH controller. It mainly includes the initial state, programming state, erase state and read state. If a read request is input in the IDLE initial state, the state jumps to the read state READ. In this state, the read completion flag is input and the state machine jumps back to the IDLE initial state; if an erase request is input in the IDLE initial state, the ownership of the charge pump must be determined at the same time. If the ownership belongs to this FLASH controller, the state jumps to the erase state ERASE, otherwise the state remains IDLE. When the state machine is in the ERASE state, the erase completion flag is input and the state machine returns to the IDLE state; if a programming request is input in the IDLE initial state, the ownership of the charge pump must be determined at the same time. If the ownership belongs to this FLASH controller, the state jumps to the programming state PROGRAM, otherwise the state remains IDLE. When the state machine is in the PROGRAM state, the programming completion flag is input and the state machine returns to the IDLE state.

[0026] like Figure 4 The figure shows the schematic diagram of the charge pump controller state machine. It includes active state and sleep state. The initial state is active state. If the sleep control signal is input, it enters the sleep state; after entering the sleep state, if the active control signal is input, it returns to the active state. The user configures the charge pump erase ownership register. If the write information is configured as FLASH controller module I and the state machine is in the active state, the charge pump ownership belongs to BANK1; if the write information is configured as FLASH controller module II and the state machine is in the active state, the charge pump ownership belongs to BANK2.

[0027] like Figure 5 The figure shows the charge pump configuration information diagram. This register is a system control register and must be write-protected. The key configuration information is 2 bits and the reset value is 2'b00. If it is configured as 2'b10, CPU1 has exclusive control over the charge pump; if it is configured as 2'b01, CPU2 has exclusive control over the charge pump. However, please note that in order to avoid conflicts, CPU2 cannot be configured to control the charge pump when CPU1 exclusively controls the charge pump. CPU2 must wait until CPU1 configures 2'b00 to release control before configuring; vice versa.

[0028] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A FLASH charge pump controller design method based on a dual-core system, wherein the FLASH charge pump controller design method achieves arbitration of the operation of the dual FLASH internal charge pumps based on the dual-core CPU system by driving the charge pump controller, and is characterized in that: The internal state machine of the FLASH controller includes the IDLE initial state, the programming state PROGRAM, the erase state ERASE and the read state READ, including the following steps: Step S1: If a read request is input in the IDLE initial state, the state jumps to the read state READ. In this state, a read completion flag is input, and the state machine jumps back to the IDLE initial state; Step S2: If an erase request is input in the IDLE initial state, the ownership of the charge pump must be determined at the same time. If the ownership belongs to this FLASH controller, the state jumps to the erase state ERASE, otherwise the state remains IDLE; Step S3: When the state machine is in the erase state ERASE, an erase completion flag is input and the state machine returns to IDLE; Step S4: If a programming request is input in the IDLE initial state, the ownership of the charge pump must be determined at the same time. If the ownership belongs to this FLASH controller, the state jumps to the programming state PROGRAM, otherwise the state remains IDLE; Step S5: When the state machine is in the programming state PROGRAM, a programming completion flag is input and the state machine returns to IDLE.

2. The FLASH charge pump controller design method according to claim 1, characterized in that: Each CPU subsystem includes an independent FLASH controller, and the dual cores share a charge pump controller for arbitrating the operation of the internal charge pumps of the dual FLASH memories, wherein the controller structure includes FLASH controller module I of CPU I subsystem, FLASH controller module II of CPU II subsystem, FLASH memory I, FLASH memory II and a charge pump controller module; FLASH controller module I realizes the control of BANK I of FLASH memory I in CPU I subsystem, and FLASH controller module II of CPU II subsystem realizes the control of BANK II of FLASH memory II in CPU II subsystem, and the charge pump controller module realizes the decision on the erasing and writing control rights of the dual cores.

3. The FLASH charge pump controller design method according to claim 2, characterized in that: The charge pump controller module state machine includes an active state and a sleep state; the initial state is the active state, and if a sleep control signal is input, the state enters the sleep state; After entering the sleep state, if an active control signal is input, it returns to the active state.

4. The FLASH charge pump controller design method according to claim 3, characterized in that: In the charge pump controller module, the user configures the charge pump erase ownership register. If the write information is configured as FLASH controller module I and the state machine is in an active state, the charge pump ownership belongs to BANK I; if the write information is configured as FLASH controller module II and the state machine is in an active state, the charge pump ownership belongs to BANK II.

5. The FLASH charge pump controller design method according to claim 2, characterized in that: The internal structures of FLASH controller module I and FLASH controller module II are the same, and both include FLASH memory, erase control module, programming control module, reading module and erase / read request processing module.

6. The FLASH charge pump controller design method according to claim 2, characterized in that: The charge pump controller controls the pump sleep / active state and arbitrates the operation of the charge pumps inside the dual FLASH, and outputs arbitration signals to the FLASH controller module I and the FLASH controller module II.

Images