A transformer area arcless ac circuit breaker with synchronization compensation capability and control method

Abstract

This invention discloses an arc-free AC circuit breaker for distribution transformers with synchronous compensation capability and its control method. It connects a microprocessor to a voltage sensor, a current sensor, a mechanical circuit breaker, a GPS module, a wireless communication module, a thyristor drive circuit, and a power quality regulation module. The microprocessor receives the induced signals from the voltage and current sensors, the clock signal from the GPS module, and the control information from the wireless communication module. Based on these signals, the microprocessor calculates the operating status of the distribution transformer area and controls the mechanical circuit breaker, thyristor drive circuit, and power quality regulation module according to the calculation and analysis results. This solves the problem that traditional circuit breakers can no longer meet the increasing needs of photovoltaic power generation, charging piles, and other new energy sources in distribution transformer areas.

Description

Technical Field

[0001] This invention belongs to the field of circuit breaker technology, specifically relating to an arc-free AC circuit breaker for distribution transformers with synchronous compensation capability and its control method. Background Technology

[0002] Current inventions and utility models have proposed arc-free AC circuit breaker designs, such as an intelligent arc-free circuit breaker (patent number ZL200520096776.4), a three-phase arc-free circuit breaker (application number 201020652885.0), and a high-breaking capacity arc-free circuit breaker (application number CN201710544678.X). However, all of these have certain shortcomings. Due to the use of new energy sources, the number of charging piles and rooftop photovoltaic systems in power distribution areas is increasing, leading to a decline in power quality. Traditional circuit breaker interruption decisions can no longer meet the growing needs of new energy sources in these areas. The integration of new energy sources also presents new demands for arc-free AC circuit breakers. This invention designs an arc-free AC circuit breaker based on the increasing demand for new energy integration in existing power distribution areas. Summary of the Invention

[0003] To address the aforementioned shortcomings in the existing technology, this invention provides an arc-free AC circuit breaker and control method for distribution transformers with synchronous compensation capability, solving the problem that traditional circuit breakers can no longer meet the needs of the increasing number of photovoltaic, charging pile, and other new energy sources in distribution transformer areas.

[0004] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows: an arc-free AC circuit breaker for transformer substations with synchronous compensation capability, comprising a voltage sensor, a current sensor, a mechanical circuit breaker, a power quality regulation module, a GPS module, a wireless communication module, a thyristor drive circuit, a thyristor, and a microprocessor.

[0005] The microprocessor is connected to the voltage sensor, current sensor, mechanical circuit breaker, power quality regulation module, GPS module, wireless communication module and thyristor drive circuit, and the thyristor drive circuit is connected to the thyristor.

[0006] The voltage sensor is used to collect the three-phase voltage values ​​output by the transformer in the distribution area, the current sensor is used to collect the three-phase current values ​​output by the transformer in the distribution area, the GPS module is used to provide clock signals to the microprocessor, the wireless communication module is used to provide control information to the microprocessor, the microprocessor is used to calculate the operating status of the distribution area based on the three-phase voltage and current values ​​output by the transformer in the distribution area, the clock signal and the control information, and controls the mechanical circuit breaker, thyristor drive circuit and power quality adjustment module based on the calculation results, and the thyristor is used to control the current.

[0007] Furthermore: the power quality conditioning module includes power quality conditioning sub-modules installed on the three phases. The power quality conditioning sub-modules installed on each phase have the same structure, including grid-side inductor, load-side inductor, inverter inductor, filter inductor, inverter and filter capacitor;

[0008] One end of the grid-side inductor is connected to the mechanical circuit breaker, and the other end of the grid-side inductor is connected to one end of the load-side inductor, one end of the inverter inductor, and one end of the filter inductor. The other end of the inverter inductor is connected to the inverter, the other end of the filter inductor is grounded through a filter capacitor, and the other end of the load-side inductor is connected to the load of the distribution area.

[0009] Furthermore, the power quality regulation module is also equipped with a three-phase inverter, including energy storage capacitor A, energy storage capacitor B, neutral line inverter, A-phase inverter, B-phase inverter and C-phase inverter;

[0010] One end of the energy storage capacitor A is connected to the No. 2 connection terminal of the neutral line inverter, the No. 2 connection terminal of the A-phase inverter, the No. 2 connection terminal of the B-phase inverter, and the No. 2 connection terminal of the C-phase inverter, respectively. The other end of the energy storage capacitor A is connected to one end of the energy storage capacitor B, the No. 1 connection terminal of the neutral line inverter, the No. 1 connection terminal of the A-phase inverter, the No. 1 connection terminal of the B-phase inverter, and the No. 1 connection terminal of the C-phase inverter, respectively.

[0011] The other end of the energy storage capacitor B is connected to terminal 3 of the neutral line inverter, terminal 3 of the A-phase inverter, terminal 3 of the B-phase inverter, and terminal 3 of the C-phase inverter. Terminal 3 of the neutral line inverter is connected to the neutral line. Terminal 3 of the A-phase inverter is connected to the inverter inductor on phase A. Terminal 3 of the B-phase inverter is connected to the inverter inductor on phase B. Terminal 3 of the C-phase inverter is connected to the inverter inductor on phase C.

[0012] Furthermore: the neutral line inverter, A-phase inverter, B-phase inverter and C-phase inverter have the same structure, each including an upper arm diode, a lower arm diode, a first IGBT module, a second IGBT module, a third IGBT module, a fourth IGBT module, a first IGBT driver module, a second IGBT driver module, a third IGBT driver module, a fourth IGBT driver module, connection port Q1, connection port Q2, connection port Q3, connection port Q4, connection terminal 1, connection terminal 2, connection terminal 3 and connection terminal 4;

[0013] The gate of the first IGBT module is connected to the connection port Q1 through the first IGBT driving module, the collector of the first IGBT module is connected to the connection terminal 2, and the emitter of the first IGBT module is connected to the collector of the second IGBT module and the negative terminal of the upper arm diode, respectively.

[0014] The gate of the second IGBT module is connected to the connection port Q2 through the second IGBT driver module, and the emitter of the second IGBT module is connected to the collector of the third IGBT module and the connection terminal 4, respectively.

[0015] The gate of the third IGBT module is connected to the connection port Q3 through the third IGBT driver module. The emitter of the third IGBT module is connected to the positive terminal of the lower arm diode and the collector of the fourth IGBT module, respectively. The negative terminal of the lower arm diode is connected to the positive terminal of the upper arm diode and the connection terminal 1, respectively.

[0016] The gate of the fourth IGBT module is connected to the connection port Q4 through the fourth IGBT driver module, and the emitter of the fourth IGBT module is connected to the connection terminal 3.

[0017] The control method, applied to arc-free AC circuit breakers with synchronous compensation capability in distribution areas, includes the following steps:

[0018] S1. Initialization is performed through an initialization subroutine;

[0019] S2. Calculate the tripping criteria using the tripping criteria calculation subroutine;

[0020] S3. Determine if the tripping criterion is equal to 1. If yes, proceed to S4; otherwise, proceed to S5.

[0021] S4. Perform the tripping action through the tripping action subroutine, then proceed to S5;

[0022] S5. Calculate the compensation criterion through the compensation criterion calculation subroutine;

[0023] S6. In response to the compensation criterion being equal to 1, perform the compensation action through the compensation action subroutine.

[0024] Further: S1 includes the following sub-steps:

[0025] S11. Set the low-frequency interrupt clock to 100 milliseconds, set the high-frequency interrupt clock to 100 microseconds, set the compensation clock to 50 microseconds, set the wireless communication module reading interface, and set the GPS module reading interface.

[0026] S12. Set low-frequency interrupt conditions and set the low-frequency interrupt subroutine to be called when an interrupt occurs; set high-frequency interrupt conditions and set the high-frequency interrupt subroutine to be called when an interrupt occurs; set compensation interrupt conditions and set the compensation interrupt subroutine to be called when an interrupt occurs.

[0027] S13. Set variables, including:

[0028] MA represents the current time in seconds, ranging from 0 to 59; HA represents the current time in milliseconds, ranging from 0 to 999; UA represents the current time in microseconds, ranging from 0 to 999; A0 represents the zero-degree moment of phase A voltage, in milliseconds; CH represents the high-frequency interrupt counter, ranging from 0 to 999; XY represents the trip phase threshold; ZY represents the trip impedance threshold; BY represents the compensation threshold; TZ represents the trip marker; and CVA represents the sensor readout counter, ranging from 0 to 59. ~999, CZQ represents the period counter, with a value range of 0~199, SUMV represents voltage summation, SUMI represents current summation, ZSUM represents impedance, VIN

[1000] represents the current sensor reading value, FV

[1000] represents the voltage floating-point value, IIN

[1000] represents the voltage sensor reading value, FI

[1000] represents the current floating-point value, PT represents the time update data position, FTZ represents the trip calculation variable, and FBZ represents the compensation calculation variable;

[0029] S14. Initialize variables. The variables to be initialized are:

[0030] MA=0, HA=0, UA=0, A0=0, CH=0, PT=0, FTZ=0, FBZ=0, TZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0, VIN

[1000] initialized to all zeros, IIN

[1000] initialized to all zeros;

[0031] S15. Set the first parameter M1data, the second parameter M2data, the third parameter M3data, the fourth parameter M4data, the fifth parameter M5data, and the comparison variable BiJiao;

[0032] In S12, the method for calling the low-frequency interrupt subroutine is as follows:

[0033] SA1: Read the data from the wireless communication module, parse the read data according to the wireless communication protocol, and update the variables A0, XY, ZY, and BY.

[0034] The wireless communication protocol is byte-coded as follows: 55, AA, A0 high 8 bits, A0 low 8 bits, XY high 8 bits, XY low 8 bits, ZY high 8 bits, ZY low 8 bits, BY high 8 bits, BY low 8 bits, parity bit, 33, CC.

[0035] In this context, 55 and AA represent the start of the communication packet, 33 and CC represent the end of the communication packet, and the check bits are XORed bitwise from A0 high 8 bits, A0 low 8 bits, XY high 8 bits, XY low 8 bits, ZY high 8 bits, ZY low 8 bits, BY high 8 bits, and BY low 8 bits.

[0036] SA2: Read GPS module data, parse the read data according to the GPS communication protocol, and update the MA, HA, and UA variables;

[0037] The GPS communication protocol is byte-based, in the following order: 55, AA, MA, HA high 8 bits, HA low 8 bits, check bit, 33, CC;

[0038] Among them, 55 and AA indicate the start of the communication packet, and 33 and CC indicate the end of the communication packet; the parity bits are the high eight bits of MA and HA and the low eight bits of HA, which are XORed bit by bit.

[0039] SA3. Assign the value of CVA to PT;

[0040] In S12, the method for calling the high-frequency interrupt subroutine is as follows:

[0041] SB1. Assign the stored value of the voltage sensor to VIN[CVA], assign the stored value of the current sensor to IIN[CVA], and increment CVA by 1.

[0042] SB2, In response to CVA equaling 1000, set CVA = 0 and FBZ = 1;

[0043] The specific method for calling the compensation interrupt subroutine is as follows:

[0044] Set the compensation action judgment parameter CBuchang = 0, and determine whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang].

[0045] If so, the compensation action is as follows: control the IGBT module (103-2) to turn on, and control the IGBT module (103-3) to turn off;

[0046] If not, the compensation action is: control IGBT module (103-2) to turn off, and control IGBT module (103-3) to turn on.

[0047] Further: S2 includes the following sub-steps:

[0048] S21. Let CZQ equal the remainder of CVA divided by 200.

[0049] S22. In response to CZQ being less than 50, set FTZ = 1;

[0050] S23. Determine if CZQ is greater than 197. If yes, and FTZ equals 1, proceed to step S24; otherwise, proceed to step S3.

[0051] S24. Set FTZ = 0;

[0052] S25. For i = 0 to 199, calculate:

[0053] FV[i]=(VIN[CVA-197+i]–32768) / 32768;

[0054] FI[i]=(IIN[CVA-197+i]–32768) / 32768;

[0055] S26. Calculate ZSUM, specifically:

[0056] ZSUM = SUMV / SUMI

[0057] in,

[0058] S27. Determine whether ZSUM is less than ZY. If yes, set the trip criterion TZ = 1. If no, set the trip criterion TZ = 0.

[0059] Further: S4 includes the following sub-steps:

[0060] S41, control the thyristor to conduct;

[0061] S42, Control the mechanical circuit breaker to disconnect;

[0062] S43, control the thyristor to disconnect.

[0063] Further: S5 includes the following sub-steps:

[0064] S51. Obtain the 300 sample points preceding the current IIN sampling data through INDATA

[300] . The specific sampling method is as follows:

[0065] Determine if CAV is greater than or equal to 300; if yes, then set INDATA data to IIN[CAV-300]~IIN[CAV]; if no, then set INDATA

[300] data to be the concatenation of IIN[1000-CAV]~IIN

[1000] and IIN[0]~IIN[CAV];

[0066] S52. Within the range of i = 0 to 100, find the first i that simultaneously satisfies INDATA[i] * INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and let j = i;

[0067] S53. Calculate the first summation parameter SUMF1, specifically:

[0068]

[0069] In the formula, M1data[i] is a preset first parameter;

[0070] S54. Take k = 1 to 25, search for the maximum value MaxSumF2 in the second summation parameter SUMF2[k], where the expression for calculating the second summation parameter SUMF2[k] is specifically:

[0071]

[0072] In the formula, M2data[i] is a preset second parameter;

[0073] Calculate the second compensation sub-criterion BiF2, BiF2 = MaxSumF2 / SUMF1, and determine whether the second compensation sub-criterion BiF2 is greater than 0.03. If so, let the second compensation parameter BuChangF2 = 1; if not, let the second compensation parameter BuChangF2 = 0;

[0074] S55. Take k = 1 to 15, search for the maximum value MaxSumF3 in the third summation parameter SUMF3[k], where the expression for calculating the third summation parameter SUMF3[k] is specifically:

[0075]

[0076] In the formula, M3data[i] is a preset third parameter, and m is the remainder obtained by dividing i by 66;

[0077] Calculate the third compensation sub-criterion BiF3, BiF3 = MaxSumF3 / SUMF1, and determine whether the third compensation sub-criterion BiF3 is greater than 0.03. If so, let the third compensation parameter BuChangF3 = 1; if not, let the third compensation parameter BuChangF3 = 0;

[0078] S56. Take k = 1 to 12, search for the maximum value MaxSumF4 in the fourth summation parameter SUMF4[k], where the expression for calculating the fourth summation parameter SUMF4[k] is specifically:

[0079]

[0080] In the formula, M4data[i] is the preset fourth parameter, and m is the remainder obtained by dividing i by 50;

[0081] Calculate the fourth compensation sub-criterion BiF4, BiF4 = MaxSumF4 / SUMF1. Determine whether the fourth compensation sub-criterion BiF4 is greater than 0.03. If it is, set the fourth compensation parameter BuChangF4 = 1. If not, set the fourth compensation parameter BuChangF4 = 0.

[0082] S57. Take k = 1 to 10, and search for the maximum value MaxSumF5 in the fifth summation parameter SUMF5[k]. The specific expression for calculating the fifth summation parameter SUMF5[k] is as follows:

[0083]

[0084] In the formula, M5data[i] is the preset fifth parameter, and m is the remainder obtained by dividing i by 40;

[0085] Calculate the fifth compensation sub-criterion BiF5, BiF5 = MaxSumF5 / SUMF1. Determine whether the fifth compensation sub-criterion BiF5 is greater than 0.03. If it is, set the fifth compensation parameter BuChangF5 = 1. If not, set the fifth compensation parameter BuChangF5 = 0.

[0086] S58. Calculate the first compensation parameter BuChang using the following formula;

[0087] BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5

[0088] Determine whether the first compensation parameter BuChang is greater than 1. If it is, set the compensation criterion BZ = 1; otherwise, set the compensation criterion BZ = 0.

[0089] Further: In step S6, the method for performing the compensation action through the compensation action subroutine is specifically as follows:

[0090] S61. Determine whether the second compensation parameter BuChangF2 is equal to 1. If not, set the second compensation action parameter bcDataF2[i] = 0, where i ranges from 0 to 399.

[0091] If so, the second compensation action parameters bcDataF2[2*i], bcDataF2[2*i+1], bcDataF2

[199] and bcDataF2[i+200] are calculated using the following formula;

[0092] bcDataF2[2*i]=-1*BiF2*M2data[i], where i takes values ​​from 0 to 99;

[0093] bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i ranges from 0 to 98;

[0094] bcDataF2

[199] =(bcDataF2[0]+bcDataF2

[198] ) / 2;

[0095] bcDataF2[i+200]=bcDataF2[i], where i ranges from 0 to 199;

[0096] S62. Determine whether the third compensation parameter BuChangF3 is equal to 1. If not, set the third compensation action parameter bcDataF3[i] = 0, where i ranges from 0 to 399.

[0097] If so, the third compensation action parameters bcDataF3[2*i], bcDataF3[2*i+1], bcDataF3

[131] , bcDataF3

[132] , bcDataF3[i+133], bcDataF3

[266] and bcDataF3[i+267] are calculated by the following formula;

[0098] bcDataF3[2*i]=-1*BiF3*M3data[i], where i takes values ​​from 0 to 65;

[0099] bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2, where i ranges from 0 to 64;

[0100] bcDataF3

[131] =(bcDataF3[0]+bcDataF3

[130] ) / 2;

[0101] bcDataF3

[132] =bcDataF3

[131] ;

[0102] bcDataF3[i+133]=bcDataF3[i], where i ranges from 0 to 132;

[0103] bcDataF3

[266] =bcDataF3

[265] ;

[0104] bcDataF3[i+267]=bcDataF3[i], where i ranges from 0 to 132;

[0105] S63. Determine whether the fourth compensation parameter BuChangF4 is equal to 1. If not, set the fourth compensation action parameter bcDataF4[i] = 0, where i ranges from 0 to 399.

[0106] If so, the fourth compensation action parameters bcDataF4[2*i], bcDataF4[2*i+1], bcDataF4

[99] , bcDataF4[i+100] and bcDataF4[i+200] are calculated by the following formula;

[0107] bcDataF4[2*i]=-1*BiF4*M4data[i], where i ranges from 0 to 49;

[0108] bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2, where i ranges from 0 to 48;

[0109] bcDataF4

[99] =(bcDataF4[0]+bcDataF4

[98] ) / 2;

[0110] bcDataF4[i+100]=bcDataF4[i], where i ranges from 0 to 99;

[0111] bcDataF4[i+200]=bcDataF4[i], where i ranges from 0 to 199;

[0112] S64. Determine whether the fifth compensation parameter BuChangF5 is equal to 1. If not, set the fifth compensation action parameter bcDataF5[i] = 0, where i ranges from 0 to 399.

[0113] If so, the fifth compensation action parameters bcDataF5[2*i], bcDataF5[2*i+1], bcDataF5

[79] , bcDataF5[i+80], bcDataF5[i+160] and bcDataF5[i+320] are calculated by the following formula;

[0114] bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39;

[0115] bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2, where i ranges from 0 to 38;

[0116] bcDataF5

[79] =(bcDataF5[0]+bcDataF5

[78] ) / 2;

[0117] bcDataF5[i+80]=bcDataF5[i], where i ranges from 0 to 79;

[0118] bcDataF5[i+160]=bcDataF6[i], where i ranges from 0 to 159;

[0119] bcDataF5[i+320]=bcDataF6[i], where i ranges from 0 to 79;

[0120] S65. Calculate the first compensation action parameter BuChangV using the following formula, and perform the compensation action based on the first compensation action parameter BuChangV.

[0121] BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], where i ranges from 0 to 399.

[0122] The beneficial effects of this invention are as follows: This invention connects a microprocessor to a voltage sensor, a current sensor, a mechanical circuit breaker, a GPS module, a wireless communication module, a thyristor drive circuit, and a power quality regulation module. The microprocessor receives the sensing signals from the voltage and current sensors, the clock signal from the GPS module, and the control information from the wireless communication module; based on the sensing signals from the voltage and current sensors, the clock signal from the GPS module, and the control information from the wireless communication module, it calculates the operating status of the distribution area and controls the mechanical circuit breaker, thyristor drive circuit, and power quality regulation module based on the calculation and analysis results, thus solving the problem that traditional circuit breakers can no longer meet the needs of the increasing number of photovoltaic, charging pile, and other new energy sources in the distribution area. Attached Figure Description

[0123] Figure 1 This is a schematic diagram of an arc-free AC circuit breaker for distribution areas with synchronous compensation capability.

[0124] Figure 2 This is a schematic diagram of a power quality regulation module.

[0125] Figure 3 This is a schematic diagram of a three-phase inverter.

[0126] Figure 4 This is a schematic diagram of a single-phase inverter.

[0127] Figure 5 This is a schematic diagram of the driving circuit for a voltage sensor and a current sensor.

[0128] Figure 6 This is a schematic diagram of a thyristor drive circuit.

[0129] Figure 7 This is a schematic diagram of the first optical transceiver A.

[0130] Figure 8 This is a schematic diagram of the first optical transceiver B.

[0131] Figure 9 This is the schematic diagram of the first trigger circuit.

[0132] Figure 10 This is a schematic diagram of a thyristor.

[0133] Figure 11 This is the schematic diagram of the drive circuit for the IGBT module.

[0134] Figure 12 This is a schematic diagram of the second optical transceiver A.

[0135] Figure 13 This is a schematic diagram of the second optical transceiver B.

[0136] Figure 14 This is the schematic diagram of the second trigger circuit.

[0137] Figure 15 This is a flowchart of the control method.

[0138] Wherein: 1. Voltage sensor; 101. Upper arm diode; 102. Lower arm diode; 103-1. First IGBT module; 103-2. Second IGBT module; 103-3. Third IGBT module; 103-4. Fourth IGBT module; 104-1. First IGBT driver module; 104-2. Second IGBT driver module; 104-3. Third IGBT driver module; 104-4. Fourth IGBT driver module; 105-1. Connection port Q1; 105-2. Connection port Q2; 105-3. Connection port Q3; 105-4. Connection port Q4; 106. Connection terminal 1; 107. Connection terminal 2; 108. Connection terminal 3; 109. Connection terminal 4; 133. 1. Optical transceiver A; 134. First optical fiber; 135. First optical transceiver B; 136. First trigger circuit; 143. Second optical transceiver A; 144. Second optical fiber; 145. Second optical transceiver B; 146. Second trigger circuit; 2. Current sensor; 21. Grid-side inductor; 22. Load-side inductor; 23. Inverter inductor; 24. Filter inductor; 25. Inverter; 26. Filter capacitor; 3. Mechanical circuit breaker; 4. Power quality regulation module; 5. GPS module; 51. Energy storage capacitor A; 52. Energy storage capacitor B; 53. Neutral line inverter; 54. Phase A inverter; 55. Phase B inverter; 56. Phase C inverter; 6. Wireless communication module; 7. Thyristor drive circuit; 8. Thyristor; 9. Microprocessor. Detailed Implementation

[0139] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0140] like Figure 1 As shown, in one embodiment of the present invention, a transformer area arc-free AC circuit breaker with synchronous compensation capability includes a voltage sensor 1, a current sensor 2, a mechanical circuit breaker 3, a power quality adjustment module 4, a GPS module 5, a wireless communication module 6, a thyristor drive circuit 7, a thyristor 8, and a microprocessor 9.

[0141] Among them, the microprocessor 9 is connected to the voltage sensor 1, the current sensor 2, the mechanical circuit breaker 3, the power quality regulation module 4, the GPS module 5, the wireless communication module 6 and the thyristor drive circuit 7, and the thyristor drive circuit 7 is connected to the thyristor 8.

[0142] Voltage sensor 1 is used to collect the three-phase voltage values ​​output by the transformer in the distribution area. Current sensor 2 is used to collect the three-phase current values ​​output by the transformer in the distribution area. GPS module 5 is used to provide clock signals to microprocessor 9. Wireless communication module 6 is used to provide control information to microprocessor 9. Microprocessor 9 is used to calculate the operating status of the distribution area based on the three-phase voltage and current values ​​output by the transformer in the distribution area, clock signals and control information. Based on the calculation results, it controls mechanical circuit breaker 3, thyristor drive circuit 7 and power quality adjustment module 4. Thyristor 8 is used to control the current.

[0143] In this embodiment, Figure 1 The diagram only shows the structure of one phase. In the three-phase structure, there is only one microprocessor 9, one wireless communication module 6, and one GPS module 5. The mechanical circuit breaker 3 is a three-phase circuit breaker. Other components, such as voltage sensor 1, current sensor 2, power quality regulation module 4, thyristor 8, and thyristor drive circuit 7, are required for each phase, with three for each of the three phases. The connection method between each phase is the same.

[0144] The output of the transformer in the distribution area consists of three-phase conductors that pass through voltage sensor 1 and current sensor 2 and are connected to the input terminal of mechanical circuit breaker 3. The output terminal of mechanical circuit breaker 3 is connected to the input terminal of power quality conditioning module 4, and the output terminal of power quality conditioning module 4 is connected to the load in the distribution area to supply power to the load.

[0145] like Figure 2As shown, the power quality regulation module 4 includes power quality regulation sub-modules set on the three phases. The power quality regulation sub-modules set on each phase have the same structure, including grid-side inductor 21, load-side inductor 22, inverter inductor 23, filter inductor 24, inverter 25 and filter capacitor 26.

[0146] One end of the grid-side inductor 21 is connected to the mechanical circuit breaker 3, and the other end of the grid-side inductor 21 is connected to one end of the load-side inductor 22, one end of the inverter inductor 23 and one end of the filter inductor 24 respectively. The other end of the inverter inductor 23 is connected to the inverter 25, the other end of the filter inductor 24 is grounded through the filter capacitor 26, and the other end of the load-side inductor 22 is connected to the load of the distribution area.

[0147] like Figure 3 As shown, the power quality regulation module 4 is also equipped with a three-phase inverter, including energy storage capacitor A51, energy storage capacitor B52, neutral line inverter 53, A-phase inverter 54, B-phase inverter 55 and C-phase inverter 56.

[0148] One end of the energy storage capacitor A51 is connected to the No. 2 connection terminal of the neutral line inverter 53, the No. 2 connection terminal of the A-phase inverter 54, the No. 2 connection terminal of the B-phase inverter 55, and the No. 2 connection terminal of the C-phase inverter 56, respectively. The other end of the energy storage capacitor A51 is connected to one end of the energy storage capacitor B52, the No. 1 connection terminal of the neutral line inverter 53, the No. 1 connection terminal of the A-phase inverter 54, the No. 1 connection terminal of the B-phase inverter 55, and the No. 1 connection terminal of the C-phase inverter 56, respectively.

[0149] The other end of the energy storage capacitor B52 is connected to terminal 3 of the neutral line inverter 53, terminal 3 of the A-phase inverter 54, terminal 3 of the B-phase inverter 55, and terminal 3 of the C-phase inverter 56, respectively. Terminal 3 of the neutral line inverter 53 is connected to the neutral line. Terminal 3 of the A-phase inverter 54 is connected to the inverter inductor 23 on the A-phase. Terminal 3 of the B-phase inverter 55 is connected to the inverter inductor 23 on the B-phase. Terminal 3 of the C-phase inverter 56 is connected to the inverter inductor 23 on the C-phase.

[0150] like Figure 4As shown, the neutral inverter 53, A-phase inverter 54, B-phase inverter 55, and C-phase inverter 56 have the same structure, each including an upper arm diode 101, a lower arm diode 102, a first IGBT module 103-1, a second IGBT module 103-2, a third IGBT module 103-3, a fourth IGBT module 103-4, a first IGBT driver module 104-1, a second IGBT driver module 104-2, a third IGBT driver module 104-3, a fourth IGBT driver module 104-4, connection ports Q1105-1, Q2105-2, Q3105-3, Q4105-4, connection terminal 106, connection terminal 2, connection terminal 108, and connection terminal 4 109.

[0151] The gate of the first IGBT module 103-1 is connected to the connection port Q1105-1 through the first IGBT driving module 104-1, the collector of the first IGBT module 103-1 is connected to the second connection terminal 107, and the emitter of the first IGBT module 103-1 is connected to the collector of the second IGBT module 103-2 and the negative terminal of the upper arm diode 101, respectively.

[0152] The gate of the second IGBT module 103-2 is connected to the connection port Q2105-2 through the second IGBT drive module 104-2, and the emitter of the second IGBT module 103-2 is connected to the collector of the third IGBT module 103-3 and the fourth connection terminal 109, respectively.

[0153] The gate of the third IGBT module 103-3 is connected to the connection port Q3105-3 through the third IGBT driver module 104-3. The emitter of the third IGBT module 103-3 is connected to the positive terminal of the lower arm diode 102 and the collector of the fourth IGBT module 103-4, respectively. The negative terminal of the lower arm diode 102 is connected to the positive terminal of the upper arm diode 101 and the No. 1 connection terminal 106, respectively.

[0154] The gate of the fourth IGBT module 103-4 is connected to the connection port Q4105-4 through the fourth IGBT driver module 104-4, and the emitter of the fourth IGBT module 103-4 is connected to the connection terminal 108.

[0155] In this embodiment, the microprocessor 9 is a TMS320F28027.

[0156] The driving circuits for voltage sensor 1 and current sensor 2 are as follows: Figure 5 As shown.

[0157] Thyristor drive circuit 7 Figure 6As shown, it includes a first optical transceiver A133, a first optical fiber 134, a first optical transceiver B135, and a first trigger circuit 136 connected in sequence.

[0158] The optical transceiver module consists of a first optical transceiver A, a first optical transceiver B, and two first optical fibers. One first optical fiber connects the optical signal transmitting end of the first optical transceiver A to the optical signal receiving end of the first optical transceiver B, and the other first optical fiber connects the optical signal receiving end of the first optical transceiver A to the optical signal transmitting end of the first optical transceiver B. The first optical transceiver A... Figure 7 As shown.

[0159] In the circuit described above, SWITCH2 is connected to the microprocessor output pin, and SWITCH3 is connected to the microprocessor input pin; U3 is an integrated circuit manufactured by TEXAS INSTRUMENT, model number SN75451, used to provide drive current to U1; U1 is the first optical fiber connected to the transmitting port, and U2 is the first optical fiber connected to the receiving port.

[0160] U1 is used to receive microprocessor control signals and send microprocessor control signals to the first optical fiber. The sent signals are transmitted to U2 of the first optical transceiver B through the first optical fiber. U2 is used to receive the first optical fiber signal, which comes from U1 of the first optical transceiver B. U2 also sends the received first optical fiber signal to the microprocessor.

[0161] The schematic diagram of the first optical transceiver B is as follows: Figure 8 As shown, U2 is connected to the first optical fiber receiving port, using an HFBR2414 first optical fiber receiving port manufactured by AVAGO TECHNOLOGIES. The received signal comes from U1 of the first optical transceiver A. U2 converts the received optical signal into an electrical signal, the network name of which is REDATA. REDATA is used to connect to the first trigger circuit, causing the first trigger circuit to generate a switch trigger signal. At the same time, REDATA is connected to the optical transmitting circuit composed of U3 and U1, used to feed the signal back to the microprocessor. U3 and U1 constitute the optical transmitting circuit, used to convert the REDATA electrical signal into an optical signal. The optical signal emitted by U1 is sent to U2 of the first optical transceiver A through the first optical fiber and the REDATA signal is sent to the microprocessor. U3 is an integrated circuit manufactured by TEXAS INSTRUMENT, model SN75451. U1 is connected to the first optical fiber transmitting port, using an HFBR1414 first optical fiber transmitting port manufactured by AVAGO TECHNOLOGIES.

[0162] like Figure 9As shown, the first trigger circuit amplifies the power of REDATA to trigger the thyristor in the switching circuit. The first trigger circuit mainly consists of an integrated circuit, a transformer, and a rectifier circuit. U1 is an integrated circuit L292 manufactured by STMicroelectronics Group of Companies. When U1 receives REDATA at a low level, it generates a high-power square wave. T1 is a three-winding transformer with one primary winding and two secondary windings. The primary winding is connected to the high-power square wave output by U1. Both secondary windings are connected to a rectifier circuit consisting of a full-bridge rectifier. The positive terminal of the rectifier circuit is connected to terminals G1 and G2, and the negative terminal is connected to terminals K1 and K2. The rectifier circuit consists of a full-bridge rectifier composed of four diodes, with capacitors and resistors added to form a filter circuit. The other peripheral circuits of U1 are designed according to the L292 datasheet.

[0163] like Figure 10 As shown, the switching circuit consists of thyristors Q1 and Q2 connected in reverse parallel, and in parallel with a mechanical circuit breaker, as well as a resistor and a series circuit of a resistor and a capacitor. The anode of Q1 is short-circuited to the cathode of Q2, and the connection terminal is called CON2; the anode of Q1 is short-circuited to the cathode of Q2, and the connection terminal is called CON2; the cathode of Q1 is short-circuited to the anode of Q2, and the connection terminal is called CON1; CON1 and CON2 are connected to the mechanical circuit breaker; the gate of Q1 is short-circuited to the first trigger circuit G1; the gate of Q2 is short-circuited to the first trigger circuit G2; in this embodiment, thyristors Q1 and Q2 are selected from ABB's 5STP42U6500 thyristors.

[0164] like Figure 11 As shown, the driving circuit of the IGBT module includes a second optical transceiver A143, a second optical fiber 144, a second optical transceiver B145, and a second trigger circuit 146 connected in sequence.

[0165] The optical transceiver module consists of a second optical transceiver A, a second optical transceiver B, and a second set of four optical fibers. Two second optical fibers are used, with one end connected to the two optical signal transmitting ends of the second optical transceiver A and the other end connected to the two optical signal receiving ends of the second optical transceiver B. The other two second optical fibers are used, with one end connected to the two optical signal receiving ends of the second optical transceiver A and the other end connected to the two optical signal transmitting ends of the second optical transceiver B.

[0166] Second optical transceiver A Figure 12As shown, in the circuit above, SWITCH2 and SWITCH3 are connected to the two output pins of the microprocessor, and SWITCH4 and SWITCH5 are connected to the two input pins of the microprocessor; U5 is an integrated circuit manufactured by TEXAS INSTRUMENT, model number SN75451, used to provide drive current to U1 and U3; U1 and U3 are fiber optic connections to the transmitting port, and U2 and U4 are fiber optic connections to the receiving port.

[0167] U1 and U3 are used to receive microprocessor control signals and send microprocessor control signals to the optical fiber. The sent signals are transmitted to U2 and U4 of optical transceiver B through the optical fiber. U2 and U4 are used to receive optical fiber signals, which come from U1 and U3 of optical transceiver B. They also send the received optical fiber signals to the microprocessor.

[0168] like Figure 13 As shown, U2 and U4 are fiber optic receiving ports, using the HFBR2414 fiber optic receiving port manufactured by AVAGO TECHNOLOGIES. The received signal comes from U1 and U3 of the second optical transceiver A. U2 and U4 convert the received optical signal into an electrical signal, with the electrical signal network names REDATA1 and REDATA2. REDATA1 and REDATA2 are used to connect to the second trigger circuit, causing the second trigger circuit to generate an insulated gate bipolar transistor drive signal. U3 and U1 are fiber optic transmitting ports, used to convert the electrical signals OUTPUT1 and OUTPUT2 of the second trigger circuit into optical signals and send the OUTPUT1 and OUTPUT2 signals to the microprocessor. U3 and U1 use the HFBR1414 fiber optic transmitting port manufactured by AVAGO TECHNOLOGIES.

[0169] like Figure 14 As shown, the second trigger circuit is used to provide a drive signal to the insulated gate bipolar transistor (IGBT). The second trigger circuit is mainly composed of two IGBT driver chips. In this embodiment, the driver chip is the M57962L manufactured by MITSUBISHI ELECTRIC, Japan. The peripheral circuit of the M57962L is designed according to the M57962L datasheet. The power supply of the M57962L is provided by a DC / DC circuit according to its datasheet. A resistor is used to connect pin 5 and the gate driver, and the two gates are named BB1 and BB2 respectively. A diode is used to connect pin 1 and the collector driver, and pin 1 is connected to the positive terminal of the diode. The two collector drivers are named CC1 and CC2 respectively.

[0170] The common point of the second trigger circuit is connected to the transmitter, and the two transmitters are named EE1 and EE2 respectively; pin 14 is connected to the receiver and connected to the optical receiver output of the second optical transceiver B; that is, REDATA1 is short-circuited to INPUT1 and REDATA2 is short-circuited to INPUT2; a diode is connected between pin 13 and pin 14, and the positive terminal of the diode is connected to pin 14; pin 13 is connected to the common point; pins 8 are named OUTPUT1 and OUTPUT2 and connected to the optical transmitter input of the second optical transceiver B; OUTPUT1 and OUTPUT2 are short-circuited to TXDATA1 and TXDATA2 of the second optical transceiver B respectively.

[0171] The IGBT module selected is a power module containing two insulated-gate bipolar transistors, model number: FF1800R17IP5.

[0172] A control method for arc-free AC circuit breakers with synchronous compensation capability in distribution areas includes the following steps:

[0173] S1. Initialization is performed through an initialization subroutine;

[0174] S2. Calculate the tripping criteria using the tripping criteria calculation subroutine;

[0175] S3. Determine if the tripping criterion is equal to 1. If yes, proceed to S4; otherwise, proceed to S5.

[0176] S4. Perform the tripping action through the tripping action subroutine, then proceed to S5;

[0177] S5. Calculate the compensation criterion through the compensation criterion calculation subroutine;

[0178] S6. In response to the compensation criterion being equal to 1, perform the compensation action through the compensation action subroutine.

[0179] S1 includes the following steps:

[0180] S11. Set the low-frequency interrupt clock to 100 milliseconds, set the high-frequency interrupt clock to 100 microseconds, set the compensation clock to 50 microseconds, set the wireless communication module reading interface, and set the GPS module reading interface.

[0181] S12. Set low-frequency interrupt conditions and set the low-frequency interrupt subroutine to be called when an interrupt occurs; set high-frequency interrupt conditions and set the high-frequency interrupt subroutine to be called when an interrupt occurs; set compensation interrupt conditions and set the compensation interrupt subroutine to be called when an interrupt occurs.

[0182] S13. Set variables, including:

[0183] MA represents the current time in seconds, ranging from 0 to 59; HA represents the current time in milliseconds, ranging from 0 to 999; UA represents the current time in microseconds, ranging from 0 to 999; A0 represents the zero-degree moment of phase A voltage, in milliseconds; CH represents the high-frequency interrupt counter, ranging from 0 to 999; XY represents the trip phase threshold; ZY represents the trip impedance threshold; BY represents the compensation threshold; TZ represents the trip marker; and CVA represents the sensor readout counter, ranging from 0 to 59. ~999, CZQ represents the period counter, with a value range of 0~199, SUMV represents voltage summation, SUMI represents current summation, ZSUM represents impedance, VIN

[1000] represents the current sensor reading value, FV

[1000] represents the voltage floating-point value, IIN

[1000] represents the voltage sensor reading value, FI

[1000] represents the current floating-point value, PT represents the time update data position, FTZ represents the trip calculation variable, and FBZ represents the compensation calculation variable;

[0184] S14. Initialize variables. The variables to be initialized are:

[0185] MA=0, HA=0, UA=0, A0=0, CH=0, PT=0, FTZ=0, FBZ=0, TZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0, VIN

[1000] initialized to all zeros, IIN

[1000] initialized to all zeros;

[0186] In S12, the method for calling the low-frequency interrupt subroutine is as follows:

[0187] SA1: Read the data from wireless communication module 6, parse the read data according to the wireless communication protocol, and update the variables A0, XY, ZY, and BY.

[0188] The wireless communication protocol is byte-coded as follows: 55, AA, A0 high 8 bits, A0 low 8 bits, XY high 8 bits, XY low 8 bits, ZY high 8 bits, ZY low 8 bits, BY high 8 bits, BY low 8 bits, parity bit, 33, CC.

[0189] In this context, 55 and AA represent the start of the communication packet, 33 and CC represent the end of the communication packet, and the check bits are XORed bitwise from A0 high 8 bits, A0 low 8 bits, XY high 8 bits, XY low 8 bits, ZY high 8 bits, ZY low 8 bits, BY high 8 bits, and BY low 8 bits.

[0190] SA2: Read data from GPS module 5, parse the read data according to the GPS communication protocol, and update the MA, HA, and UA variables;

[0191] The GPS communication protocol is byte-based, in the following order: 55, AA, MA, HA high 8 bits, HA low 8 bits, check bit, 33, CC;

[0192] Among them, 55 and AA indicate the start of the communication packet, and 33 and CC indicate the end of the communication packet; the parity bits are the high eight bits of MA and HA and the low eight bits of HA, which are XORed bit by bit.

[0193] SA3. Assign the value of CVA to PT;

[0194] In S12, the method for calling the high-frequency interrupt subroutine is as follows:

[0195] SB1. Assign the stored value of the memory corresponding to voltage sensor 1 to VIN[CVA], assign the stored value of the memory corresponding to current sensor 2 to IIN[CVA], and increment CVA by 1;

[0196] SB2, In response to CVA equaling 1000, set CVA = 0 and FBZ = 1;

[0197] The specific method for calling the compensation interrupt subroutine is as follows:

[0198] Set the compensation action judgment parameter CBuchang = 0, and determine whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang].

[0199] If so, the compensation action is as follows: control the IGBT module (103-2) to turn on, and control the IGBT module (103-3) to turn off;

[0200] If not, the compensation action is: control IGBT module (103-2) to turn off, and control IGBT module (103-3) to turn on.

[0201] S2 includes the following steps:

[0202] S21. Let CZQ equal the remainder of CVA divided by 200.

[0203] S22. In response to CZQ being less than 50, set FTZ = 1;

[0204] S23. Determine if CZQ is greater than 197. If yes, and FTZ equals 1, proceed to step S24; otherwise, proceed to step S3.

[0205] S24. Set FTZ = 0;

[0206] S25. For i = 0 to 199, calculate:

[0207] FV[i] = (VIN[CVA - 197 + i] – 32768) / 32768;

[0208] FI[i] = (IIN[CVA - 197 + i] – 32768) / 32768;

[0209] S26. Calculate ZSUM, specifically:

[0210] ZSUM = SUMV / SUMI

[0211] Where,

[0212] S27. Determine whether ZSUM is less than ZY. If so, set the tripping criterion TZ = 1; if not, set the tripping criterion TZ = 0.

[0213] The said S4 includes the following sub - steps:

[0214] S41. Control the thyristor 8 to conduct;

[0215] S42. Control the mechanical circuit breaker 3 to open;

[0216] S43. Control the thyristor 3 to open.

[0217] The said S5 includes the following sub - steps:

[0218] S51. Take 300 sample points before the current IIN sampling data through INDATA

[300] . The sampling method is specifically:

[0219] Determine whether CAV is greater than or equal to 300. If so, set the INDATA data to IIN[CAV - 300] to IIN[CAV]; if not, set the data of INDATA

[300] to the concatenation of two segments of data, IIN[1000 - CAV] to IIN

[1000] and IIN[0] to IIN[CAV];

[0220] S52. Within the range of i = 0 to 100, find the first i that simultaneously satisfies INDATA[i]*INDATA[i + 4] < 0 and INDATA[i] < INDATA[i + 4], and set j = i;

[0221] S53. Calculate the first summation parameter SUMF1, specifically:

[0222]

[0223] In the formula, M1data[i] is a preset first parameter;

[0224] S54. Take k = 1 to 25, and search for the maximum value MaxSumF2 in the second summation parameter SUMF2[k]. The specific expression for calculating the second summation parameter SUMF2[k] is as follows:

[0225]

[0226] In the formula, M2data[i] is the preset second parameter;

[0227] Calculate the second compensation sub-criterion BiF2, BiF2 = MaxSumF2 / SUMF1, and determine whether the second compensation sub-criterion BiF2 is greater than 0.03. If it is, set the second compensation parameter BuChangF2 = 1; otherwise, set the second compensation parameter BuChangF2 = 0.

[0228] S55. Take k = 1 to 15, and search for the maximum value MaxSumF3 in the third summation parameter SUMF3[k]. The specific expression for calculating the third summation parameter SUMF3[k] is as follows:

[0229]

[0230] In the formula, M3data[i] is the preset third parameter, and m is the remainder obtained by dividing i by 66;

[0231] Calculate the third compensation sub-criterion BiF3, BiF3 = MaxSumF3 / SUMF1. Determine whether the third compensation sub-criterion BiF3 is greater than 0.03. If it is, set the third compensation parameter BuChangF3 = 1. If not, set the third compensation parameter BuChangF3 = 0.

[0232] S56. Take k = 1 to 12, and search for the maximum value MaxSumF4 in the fourth summation parameter SUMF4[k]. The specific expression for calculating the fourth summation parameter SUMF4[k] is as follows:

[0233]

[0234] In the formula, M4data[i] is the preset fourth parameter, and m is the remainder obtained by dividing i by 50;

[0235] Calculate the fourth compensation sub-criterion BiF4, BiF4 = MaxSumF4 / SUMF1. Determine whether the fourth compensation sub-criterion BiF4 is greater than 0.03. If it is, set the fourth compensation parameter BuChangF4 = 1. If not, set the fourth compensation parameter BuChangF4 = 0.

[0236] S57. Take k = 1 to 10, and search for the maximum value MaxSumF5 in the fifth summation parameter SUMF5[k]. The specific expression for calculating the fifth summation parameter SUMF5[k] is as follows:

[0237]

[0238] In the formula, M5data[i] is the preset fifth parameter, and m is the remainder obtained by dividing i by 40;

[0239] Calculate the fifth compensation sub-criterion BiF5, BiF5 = MaxSumF5 / SUMF1. Determine whether the fifth compensation sub-criterion BiF5 is greater than 0.03. If it is, set the fifth compensation parameter BuChangF5 = 1. If not, set the fifth compensation parameter BuChangF5 = 0.

[0240] S58. Calculate the first compensation parameter BuChang using the following formula;

[0241] BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5

[0242] Determine whether the first compensation parameter BuChang is greater than 1. If it is, set the compensation criterion BZ = 1; otherwise, set the compensation criterion BZ = 0.

[0243] In S5, the first to fifth parameters are adaptively set according to the actual circuit breaker control requirements.

[0244] In step S6, the method for performing the compensation action through the compensation action subroutine is as follows:

[0245] S61. Determine whether the second compensation parameter BuChangF2 is equal to 1. If not, set the second compensation action parameter bcDataF2[i] = 0, where i ranges from 0 to 399.

[0246] If so, the second compensation action parameters bcDataF2[2*i], bcDataF2[2*i+1], bcDataF2

[199] and bcDataF2[i+200] are calculated using the following formula;

[0247] bcDataF2[2*i]=-1*BiF2*M2data[i], where i takes values ​​from 0 to 99;

[0248] bcDataF2[2*i+1]=(bcDataF2[2*i]+bcDataF2[2*i+2]) / 2, where i ranges from 0 to 98;

[0249] bcDataF2

[199] =(bcDataF2[0]+bcDataF2

[198] ) / 2;

[0250] bcDataF2[i+200]=bcDataF2[i], where i ranges from 0 to 199;

[0251] S62. Determine whether the third compensation parameter BuChangF3 is equal to 1. If not, set the third compensation action parameter bcDataF3[i] = 0, where i ranges from 0 to 399.

[0252] If so, the third compensation action parameters bcDataF3[2*i], bcDataF3[2*i+1], bcDataF3

[131] , bcDataF3

[132] , bcDataF3[i+133], bcDataF3

[266] and bcDataF3[i+267] are calculated by the following formula;

[0253] bcDataF3[2*i]=-1*BiF3*M3data[i], where i takes values ​​from 0 to 65;

[0254] bcDataF3[2*i+1]=(bcDataF3[2*i]+bcDataF3[2*i+2]) / 2, where i ranges from 0 to 64;

[0255] bcDataF3

[131] =(bcDataF3[0]+bcDataF3

[130] ) / 2;

[0256] bcDataF3

[132] =bcDataF3

[131] ;

[0257] bcDataF3[i+133]=bcDataF3[i], where i ranges from 0 to 132;

[0258] bcDataF3

[266] =bcDataF3

[265] ;

[0259] bcDataF3[i+267]=bcDataF3[i], where i ranges from 0 to 132;

[0260] S63. Determine whether the fourth compensation parameter BuChangF4 is equal to 1. If not, set the fourth compensation action parameter bcDataF4[i] = 0, where i ranges from 0 to 399.

[0261] If so, the fourth compensation action parameters bcDataF4[2*i], bcDataF4[2*i+1], bcDataF4

[99] , bcDataF4[i+100] and bcDataF4[i+200] are calculated by the following formula;

[0262] bcDataF4[2*i]=-1*BiF4*M4data[i], where i ranges from 0 to 49;

[0263] bcDataF4[2*i+1]=(bcDataF4[2*i]+bcDataF4[2*i+2]) / 2, where i ranges from 0 to 48;

[0264] bcDataF4

[99] =(bcDataF4[0]+bcDataF4

[98] ) / 2;

[0265] bcDataF4[i+100]=bcDataF4[i], where i ranges from 0 to 99;

[0266] bcDataF4[i+200]=bcDataF4[i], where i ranges from 0 to 199;

[0267] S64. Determine whether the fifth compensation parameter BuChangF5 is equal to 1. If not, set the fifth compensation action parameter bcDataF5[i] = 0, where i ranges from 0 to 399.

[0268] If so, the fifth compensation action parameters bcDataF5[2*i], bcDataF5[2*i+1], bcDataF5

[79] , bcDataF5[i+80], bcDataF5[i+160] and bcDataF5[i+320] are calculated by the following formula;

[0269] bcDataF5[2*i]=-1*BiF5*M5data[i], where i ranges from 0 to 39;

[0270] bcDataF5[2*i+1]=(bcDataF5[2*i]+bcDataF5[2*i+2]) / 2, where i ranges from 0 to 38;

[0271] bcDataF5

[79] =(bcDataF5[0]+bcDataF5

[78] ) / 2;

[0272] bcDataF5[i+80]=bcDataF5[i], where i ranges from 0 to 79;

[0273] bcDataF5[i+160]=bcDataF6[i], where i ranges from 0 to 159;

[0274] bcDataF5[i+320]=bcDataF6[i], where i ranges from 0 to 79;

[0275] S65. Calculate the first compensation action parameter BuChangV using the following formula, and perform the compensation action based on the first compensation action parameter BuChangV.

[0276] BuChangV=bcDataF2[i]+bcDataF3[i]+bcDataF4[i]+bcDataF5[i], where i ranges from 0 to 399.

[0277] In step S6, the comparison variable BiJiao is adaptively set according to the actual circuit breaker control requirements. In this embodiment, the expression of the preset comparison variable BiJiao is as follows:

[0278] BiJiao

[10] ={-1,-0.6,-0.2,0.2,0.6,1,0.6,0.2,-0.2,-0.6}

[0279] In the formula, i ranges from 0 to 399, m is the remainder when i is divided by 10, and BiJiaoV[i] = BiJiao[m].

[0280] In the description of this invention, it should be understood that the terms "center," "thickness," "upper," "lower," "horizontal," "top," "bottom," "inner," "outer," and "radial," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying the relative importance or the number of technical features implicitly specified. Therefore, a feature defined by "first," "second," and "third" may explicitly or implicitly include one or more of that feature.

Claims

1. A transformer substation arc-free AC circuit breaker with synchronous compensation capability, characterized in that, It includes a voltage sensor (1), a current sensor (2), a mechanical circuit breaker (3), a power quality regulation module (4), a GPS module (5), a wireless communication module (6), a thyristor drive circuit (7), a thyristor (8), and a microprocessor (9). Among them, the microprocessor (9) is connected to the voltage sensor (1), the current sensor (2), the mechanical circuit breaker (3), the power quality regulation module (4), the GPS module (5), the wireless communication module (6) and the thyristor drive circuit (7), and the thyristor drive circuit (7) is connected to the thyristor (8); Voltage sensor (1) is used to collect the three-phase voltage values ​​output by the transformer in the distribution area. Current sensor (2) is used to collect the three-phase current values ​​output by the transformer in the distribution area. GPS module (5) is used to provide clock signals to microprocessor (9). Wireless communication module (6) is used to provide control information to microprocessor (9). Microprocessor (9) is used to calculate the operating status of the distribution area based on the three-phase voltage and current values, clock signals and control information output by the transformer in the distribution area. Based on the calculation results, it controls mechanical circuit breaker (3), thyristor drive circuit (7) and power quality adjustment module (4). Thyristor (8) is used to control current. The power quality regulation module (4) includes power quality regulation sub-modules set on the three phases. The power quality regulation sub-modules set on each phase have the same structure, including grid-side inductor (21), load-side inductor (22), inverter inductor (23), filter inductor (24), inverter (25) and filter capacitor (26). One end of the grid-side inductor (21) is connected to the mechanical circuit breaker (3), and the other end of the grid-side inductor (21) is connected to one end of the load-side inductor (22), one end of the inverter inductor (23) and one end of the filter inductor (24), respectively. The other end of the inverter inductor (23) is connected to the inverter (25), and the other end of the filter inductor (24) is grounded through the filter capacitor (26). The other end of the load-side inductor (22) is connected to the load of the distribution area.

2. The arc-free AC circuit breaker with synchronous compensation capability for distribution areas according to claim 1, characterized in that, The power quality regulation module (4) is also equipped with a three-phase inverter, including energy storage capacitor A (51), energy storage capacitor B (52), neutral line inverter (53), A-phase inverter (54), B-phase inverter (55) and C-phase inverter (56). One end of the energy storage capacitor A (51) is connected to the No. 2 connection terminal of the neutral line inverter (53), the No. 2 connection terminal of the A-phase inverter (54), the No. 2 connection terminal of the B-phase inverter (55), and the No. 2 connection terminal of the C-phase inverter (56), respectively. The other end of the energy storage capacitor A (51) is connected to one end of the energy storage capacitor B (52), the No. 1 connection terminal of the neutral line inverter (53), the No. 1 connection terminal of the A-phase inverter (54), the No. 1 connection terminal of the B-phase inverter (55), and the No. 1 connection terminal of the C-phase inverter (56), respectively. The other end of the energy storage capacitor B (52) is connected to the No. 3 connection terminal of the neutral line inverter (53), the No. 3 connection terminal of the A-phase inverter (54), the No. 3 connection terminal of the B-phase inverter (55), and the No. 3 connection terminal of the C-phase inverter (56), respectively. The No. 4 connection terminal of the neutral line inverter (53) is connected to the neutral line. The No. 4 connection terminal of the A-phase inverter (54) is connected to the inverter inductor (23) on the A-phase. The No. 4 connection terminal of the B-phase inverter (55) is connected to the inverter inductor (23) on the B-phase. The No. 4 connection terminal of the C-phase inverter (56) is connected to the inverter inductor (23) on the C-phase.

3. The arc-free AC circuit breaker with synchronous compensation capability for distribution areas according to claim 2, characterized in that, The neutral line inverter (53), A-phase inverter (54), B-phase inverter (55) and C-phase inverter (56) have the same structure, each including an upper arm diode (101), a lower arm diode (102), a first IGBT module (103-1), a second IGBT module (103-2), a third IGBT module (103-3), a fourth IGBT module (103-4), a first IGBT drive module (104-1), a second IGBT drive module (104-2), a third IGBT drive module (104-3), a fourth IGBT drive module (104-4), connection ports Q1 (105-1), Q2 (105-2), Q3 (105-3), Q4 (105-4), connection terminal 1 (106), connection terminal 2 (107), connection terminal 3 (108), and connection terminal 4 (109). The gate of the first IGBT module (103-1) is connected to the connection port Q1 (105-1) through the first IGBT driving module (104-1), the collector of the first IGBT module (103-1) is connected to the second connection terminal (107), and the emitter of the first IGBT module (103-1) is connected to the collector of the second IGBT module (103-2) and the negative terminal of the upper arm diode (101), respectively. The gate of the second IGBT module (103-2) is connected to the connection port Q2 (105-2) through the second IGBT driver module (104-2), and the emitter of the second IGBT module (103-2) is connected to the collector of the third IGBT module (103-3) and the No. 4 connection terminal (109) respectively. The gate of the third IGBT module (103-3) is connected to the connection port Q3 (105-3) through the third IGBT driver module (104-3). The emitter of the third IGBT module (103-3) is connected to the positive terminal of the lower arm diode (102) and the collector of the fourth IGBT module (103-4) respectively. The negative terminal of the lower arm diode (102) is connected to the positive terminal of the upper arm diode (101) and the No. 1 connection terminal (106) respectively. The gate of the fourth IGBT module (103-4) is connected to the connection port Q4 (105-4) through the fourth IGBT driver module (104-4), and the emitter of the fourth IGBT module (103-4) is connected to the connection terminal 3 (108).

4. A control method for a transformer substation arc-free AC circuit breaker with synchronous compensation capability, applied to the transformer substation arc-free AC circuit breaker with synchronous compensation capability as described in any one of claims 1 to 3, characterized in that, Includes the following steps: S1. Initialization is performed through an initialization subroutine, specifically as follows: S11. Set the low-frequency interrupt clock to 100 milliseconds, set the high-frequency interrupt clock to 100 microseconds, set the compensation clock to 50 microseconds, set the wireless communication module (6) reading interface, and set the GPS module (5) reading interface. S12. Set low-frequency interrupt conditions and set the low-frequency interrupt subroutine to be called when an interrupt occurs; set high-frequency interrupt conditions and set the high-frequency interrupt subroutine to be called when an interrupt occurs; set compensation interrupt conditions and set the compensation interrupt subroutine to be called when an interrupt occurs. The method for calling the low-frequency interrupt subroutine is as follows: SA1, Read the data from the wireless communication module (6), parse the read data according to the wireless communication protocol, and update the variables A0, XY, ZY and BY; The wireless communication protocol is byte-coded as follows: 55, AA, A0 high 8 bits, A0 low 8 bits, XY high 8 bits, XY low 8 bits, ZY high 8 bits, ZY low 8 bits, BY high 8 bits, BY low 8 bits, parity bit, 33, CC. In this context, 55 and AA represent the start of the communication packet, 33 and CC represent the end of the communication packet, and the check bits are XORed bitwise from A0 high 8 bits, A0 low 8 bits, XY high 8 bits, XY low 8 bits, ZY high 8 bits, ZY low 8 bits, BY high 8 bits, and BY low 8 bits. SA2, Read data from GPS module (5), parse the read data according to the GPS communication protocol, and update the MA, HA and UA variables; The GPS communication protocol is byte-coded as follows: 55, AA, MA, HA high octets, HA low octets, check bit, 33, CC; Among them, 55 and AA indicate the start of the communication packet, and 33 and CC indicate the end of the communication packet; the parity bits are the high eight bits of MA and HA and the low eight bits of HA, which are XORed bit by bit. SA3. Assign the value of CVA to PT; The method for calling the high-frequency interrupt subroutine is as follows: SB1. Assign the stored value of the memory corresponding to the voltage sensor (1) to VIN[CVA], assign the stored value of the memory corresponding to the current sensor (2) to IIN[CVA], and increment CVA by 1; SB2, In response to CVA equaling 1000, set CVA=0 and FBZ=1; The specific method for calling the compensation interrupt subroutine is as follows: Set the compensation action judgment parameter CBuchang=0, and determine whether BuChangV[CBuchang] is greater than BiJiaoV[CBuchang]. If so, the compensation action is as follows: control the second IGBT module (103-2) to turn on, and control the third IGBT module (103-3) to turn off; If not, the compensation action is as follows: control the second IGBT module (103-2) to turn off and control the third IGBT module (103-3) to turn on; S13, Set variables; S14. Initialize variables; S15. Set the first parameter M1data, the second parameter M2data, the third parameter M3data, the fourth parameter M4data, the fifth parameter M5data, and the comparison variable BiJiao; S2. Calculate the tripping criteria using the tripping criteria calculation subroutine; S3. Determine if the tripping criterion is equal to 1. If yes, proceed to S4; otherwise, proceed to S5. S4. Perform the tripping action through the tripping action subroutine, then proceed to S5; S5. Calculate the compensation criterion through the compensation criterion calculation subroutine; S6. In response to the compensation criterion being equal to 1, perform the compensation action through the compensation action subroutine.

5. The control method according to claim 4, characterized in that, S13 specifically includes: MA represents the current time in seconds, ranging from 0 to 59; HA represents the current time in milliseconds, ranging from 0 to 999; UA represents the current time in microseconds, ranging from 0 to 999; A0 represents the zero-degree moment of phase A voltage, in milliseconds; CH represents the high-frequency interrupt counter, ranging from 0 to 999; XY represents the trip phase threshold; ZY represents the trip impedance threshold; BY represents the compensation threshold; TZ represents the trip marker; and CVA represents the sensor readout counter, ranging from 0 to 59. ~999, CZQ represents the period counter, with a value range of 0~199, SUMV represents voltage summation, SUMI represents current summation, ZSUM represents impedance, VIN[1000] represents the current sensor reading value, FV[1000] represents the voltage floating-point value, IIN[1000] represents the voltage sensor reading value, FI[1000] represents the current floating-point value, PT represents the time update data position, FTZ represents the trip calculation variable, and FBZ represents the compensation calculation variable; The S14 initialization variables are specifically as follows: MA=0, HA=0, UA=0, A0=0, CH=0, PT=0, FTZ=0, FBZ=0, TZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0, VIN[1000] is initialized to all zeros, IIN[1000] is initialized to all zeros.

6. The control method according to claim 5, characterized in that, S2 includes the following steps: S21. Let CZQ equal the remainder of CVA divided by 200. S22. In response to CZQ being less than 50, set FTZ=1; S23. Determine if CZQ is greater than 197. If yes, and FTZ equals 1, proceed to step S24; otherwise, proceed to step S3. S24. Set FTZ=0; S25. For i = 0 ~ 199, calculate: FV[i] =(VIN[CVA-197+i] – 32768) / 32768; FI[i] =(IIN[CVA-197+i] – 32768) / 32768; S26. Calculate ZSUM, specifically: ZSUM = SUMV / SUMI in, , ; S27. Determine whether ZSUM is less than ZY. If yes, set the trip criterion TZ=1. If no, set the trip criterion TZ=0.

7. The control method according to claim 6, characterized in that, S4 includes the following sub-steps: S41, control the thyristor (8) to conduct; S42, Control the mechanical circuit breaker (3) to disconnect; S43, control thyristor (8) to disconnect.

8. The control method according to claim 7, characterized in that, S5 includes the following steps: S51. Obtain the 300 sample points preceding the current IIN sampling data through INDATA[300]. The specific sampling method is as follows: Determine if CAV is greater than or equal to 300; if yes, then set INDATA data to IIN[CAV-300]~IIN[CAV]; if no, then set INDATA[300] data to be the concatenation of IIN[1000-CAV]~IIN[1000] and IIN[0]~IIN[CAV]; S52. Within the range of i = 0 to 100, find the first i that simultaneously satisfies INDATA[i] INDATA[i + 4] is less than zero, and INDATA[i] < INDATA[i + 4], and let j = i; S53. Calculate the first summation parameter SUMF1, specifically as follows: In the formula, This is the preset first parameter; S54. Take k = 1~25, and search for the maximum value MaxSumF2 in the second summation parameter SUMF2[k]. The specific expression for calculating the second summation parameter SUMF2[k] is as follows: In the formula, This is the preset second parameter; Calculate the second compensation sub-criterion BiF2, BiF2 = MaxSumF2 / SUMF1. Determine whether the second compensation sub-criterion BiF2 is greater than 0.

03. If it is, set the second compensation parameter BuChangF2 = 1. If not, set the second compensation parameter BuChangF2 = 0. S55. Take k = 1~15, and search for the maximum value MaxSumF3 in the third summation parameter SUMF3[k]. The specific expression for calculating the third summation parameter SUMF3[k] is as follows: In the formula, The third parameter is a preset parameter, and m is the remainder when i is divided by 66. Calculate the third compensation sub-criterion BiF3, BiF3 = MaxSumF3 / SUMF1. Determine whether the third compensation sub-criterion BiF3 is greater than 0.

03. If it is, set the third compensation parameter BuChangF3 = 1. If not, set the third compensation parameter BuChangF3 = 0. S56. Take k = 1~12, and search for the maximum value MaxSumF4 in the fourth summation parameter SUMF4[k]. The specific expression for calculating the fourth summation parameter SUMF4[k] is as follows: In the formula, The fourth parameter is preset, and m is the remainder obtained by dividing i by 50; Calculate the fourth compensation sub-criterion BiF4, BiF4 = MaxSumF4 / SUMF1. Determine whether the fourth compensation sub-criterion BiF4 is greater than 0.

03. If it is, set the fourth compensation parameter BuChangF4 = 1. If not, set the fourth compensation parameter BuChangF4 = 0. S57. Taking k = 1~10, search for the maximum value MaxSumF5 in the fifth summation parameter SUMF5[k]. The specific expression for calculating the fifth summation parameter SUMF5[k] is as follows: In the formula, The fifth parameter is preset, and m is the remainder obtained by dividing i by 40; Calculate the fifth compensation sub-criterion BiF5, BiF5 = MaxSumF5 / SUMF1, and determine whether the fifth compensation sub-criterion BiF5 is greater than 0.

03. If it is, set the fifth compensation parameter BuChangF5=1; otherwise, set the fifth compensation parameter BuChangF5=0. S58. Calculate the first compensation parameter BuChang using the following formula; BuChang=BuChangF2+BuChangF3+BuChangF4+BuChangF5 Determine whether the first compensation parameter BuChang is greater than 1. If it is, set the compensation criterion BZ=1; otherwise, set the compensation criterion BZ=0.

9. The control method according to claim 8, characterized in that, In step S6, the method for performing the compensation action through the compensation action subroutine is as follows: S61. Determine whether the second compensation parameter BuChangF2 is equal to 1. If not, set the second compensation action parameter bcDataF2[i]=0, where i takes values ​​from 0 to 399. If so, the second compensation action parameter bcDataF2[2] is calculated using the following formula. i]、bcDataF2[2 i+1], bcDataF2[199] and bcDataF2[i+200]; bcDataF2[2 i]= -1 BiF2 M2data[i], where i ranges from 0 to 99; bcDataF2[2 i+1]=(bcDataF2[2 i]+ bcDataF2[2 i+2]) / 2, where i takes values ​​from 0 to 98; bcDataF2[199]=( bcDataF2[0] + bcDataF2[198]) / 2; bcDataF2[i+200]= bcDataF2[i], where i ranges from 0 to 199; S62. Determine whether the third compensation parameter BuChangF3 is equal to 1. If not, set the third compensation action parameter bcDataF3[i]=0, where i takes the range of 0~399. If so, the third compensation action parameter bcDataF3[2] is calculated using the following formula. i]、bcDataF3[2 i+1], bcDataF3[131], bcDataF3[132], bcDataF3[i+133], bcDataF3[266] and bcDataF3[i+267]; bcDataF3[2 i]= -1 BiF3 M3data[i], where i ranges from 0 to 65; bcDataF3[2 i + 1] = (bcDataF3[2 i] + bcDataF3[2 i + 2]) / 2, where i ranges from 0 to 64; bcDataF3[131]=( bcDataF3[0] + bcDataF3[130]) / 2; bcDataF3[132]= bcDataF3[131]; bcDataF3[i+133]= bcDataF3[i], where i ranges from 0 to 132; bcDataF3[266]= bcDataF3[265]; bcDataF3[i+267]= bcDataF3[i], where i ranges from 0 to 132; S63. Determine whether the fourth compensation parameter BuChangF4 is equal to 1. If not, set the fourth compensation action parameter bcDataF4[i]=0, where i takes values ​​from 0 to 399. If so, the fourth compensation action parameter bcDataF4[2] is calculated using the following formula. i]、bcDataF4[2 i+1], bcDataF4[99], bcDataF4[i+100] and bcDataF4[i+200]; bcDataF4[2 i]= -1 BiF4 M4data[i], where i ranges from 0 to 49; bcDataF4[2 i + 1] = (bcDataF4[2 i] + bcDataF4[2 i + 2]) / 2, where i takes values from 0 to 48; bcDataF4[99]=( bcDataF4[0] + bcDataF4[98]) / 2; bcDataF4[i+100]= bcDataF4[i], where i ranges from 0 to 99; bcDataF4[i+200]= bcDataF4[i], where i ranges from 0 to 199; S64. Determine whether the fifth compensation parameter BuChangF5 is equal to 1. If not, set the fifth compensation action parameter bcDataF5[i]=0, where i takes the range of 0 to 399. If so, the fifth compensation action parameter bcDataF5[2] is calculated using the following formula. i]、bcDataF5[2 i+1], bcDataF5[79], bcDataF5[i+80], bcDataF5[i+160] and bcDataF5[i+320]; bcDataF5[2 i]= -1 BiF5 M5data[i], i in the formula 0~39; bcDataF5[2 i + 1] = (bcDataF5[2 i] + bcDataF5[2 i + 2]) / 2, where i takes values from 0 to 38; bcDataF5[79]=( bcDataF5[0] + bcDataF5[78]) / 2; bcDataF5[i+80]= bcDataF5[i], where i ranges from 0 to 79; bcDataF5[i+160]= bcDataF6[i], where i ranges from 0 to 159; bcDataF5[i+320]= bcDataF6[i], where i ranges from 0 to 79; S65. Calculate the first compensation action parameter BuChangV using the following formula, and perform the compensation action based on the first compensation action parameter BuChangV. BuChangV = bcDataF2[i] + bcDataF3[i]+ bcDataF4[i]+bcDataF5[i], where i ranges from 0 to 399.

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