Quasi-resonant switching power supply valley bottom locking and valley bottom switching circuit and method

Abstract

The invention discloses a quasi-resonant switching power supply valley bottom locking and valley bottom switching circuit and method, and mainly solves the problems that valley bottom locking is discontinuous and timing time is difficult to determine in the prior art. The control chip comprises a valley bottom locking and switching module, a valley bottom detection module connected with the valley bottom locking and switching module, a VCO clock signal generation module, a trigger, a peak current limiting module connected with a reset end R pin of the trigger, and a driving module connected with an output end Q of the trigger. According to the invention, a continuous valley bottom switching function enables a system control loop to work continuously and reliably, and the problem of large output voltage ripple caused by large frequency change is avoided. The rapid valley bottom switching following can enable the switching frequency to rapidly follow the change of the load power, ensures that the power output of the switching power supply is equal to the load power, and avoids the problem of large fluctuation of the output voltage caused by large or small power output due to slow frequency following.

Description

Technical Field

[0001] The present invention belongs to the technical field of switching power supplies, and in particular, relates to a valley locking and valley switching circuit and method for a quasi-resonant switching power supply. Background Art

[0002] As the power of the switching power supply increases, the switching loss increases. In order to reduce the switching loss of the switch tube, the quasi-resonant switching technology is generally used to turn on the switch tube when the voltage at the drain end of the switch tube oscillates to the bottom, so as to reduce the turn-on loss of the switch tube and improve the efficiency of the switching power supply. However, since the switch tube is turned on at the bottom of the oscillation, the switching frequency jumps when it is turned on at different bottoms, and the switching frequency cannot change continuously. The output power of the switching power supply P0=1 / 2*Lp*Ip 2 *f*η, where Lp is the primary inductance value, Ip is the primary inductance peak current, f is the switching frequency, and η is the conversion efficiency. It can be seen that the output power is affected by the switching frequency. When the valley value of the switch changes, the frequency will jump significantly, resulting in a large change in the output power in a short period of time. The switching power supply loop control will adjust the primary inductance peak current Ip, which will move the oscillation valley of the switch tube drain, thereby affecting the valley value of the switch again and affecting the switching frequency. In this way, the valley value of the switch will switch frequently, that is, the switching frequency will jump frequently. Figure 1 The waveform of the drain end of the switch tube N1 of the switching power supply is shown. It can be known that the switching frequency of the quasi-resonant switching power supply is determined by the opening time, demagnetization time and the number of valleys of the oscillation waveform. When it is opened one valley ahead of time, the switching frequency will suddenly increase, resulting in an increase in output power and output voltage. Then the switching power supply loop control will reduce the FB voltage, thereby reducing the primary inductor peak current Ip, reducing output power and output voltage. This will shorten the opening time and demagnetization time, and the valley of the drain oscillation of the switch tube will move forward, which in turn will cause the next switch to be opened one valley later, and the switching frequency will suddenly decrease again. This will be repeated, and the frequency will change frequently.

[0003] To solve this problem, the prior art has proposed a variety of valley locking technologies, and the core principles can basically be divided into two categories. One is to judge valley locking and valley switching by outputting feedback voltage signal FB, and the other is to judge valley locking and valley switching by switching cycle and timing. The first method is relatively simple and widely used. The valley locking value is directly determined by voltage detection. The voltage value corresponds to the valley locking value one by one, and the valley locking function is direct and clear. However, the disadvantage is that the range of FB feedback voltage is limited, resulting in limited interval division of valley locking, which is only applicable to limited valley locking, and 6 valley locking schemes are generally adopted. If there are more than 6 valleys, the valley locking and valley opening functions cannot be realized, such as the seventh valley locking switch control cannot be realized. This will result in no valley locking function after 6 valleys, discontinuous switching frequency, and increase the difficulty of loop control adjustment. As shown in patents CN105071662B, CN112701924B, CN115065254B and CN112332647B, patents CN114696626B and CN105262333B are also essentially voltage-determined valley locks. It's just that patent CN114696626B generates a load-related voltage signal CCsg through the drive signal and the CS peak current. This voltage signal is actually similar to the FB voltage and can reflect the size of the output load. Patent CN105262333B converts the feedback voltage FB into a working cycle time period to control the valley lock. The second method raises the problem of how to set the timing time. The oscillation period of the resonance changes with the system, and the timing time setting needs to be able to adapt to the changes in the oscillation period. As shown in patents CN111490681A and CN114900025B. Among them, patent CN111490681A introduces the hysteresis time Tdv. It can be seen that this time is not easy to determine and needs to be gradually adjusted. Patent CN114900025B does not specify what the resonant period is, so it is not clear how the time delay is generated and how long it takes. The oscillation period of the oscillation waveform of the valley detection is jointly affected by the transformer inductance, the parasitic capacitance at the drain end of the switch tube, and the parasitic capacitance at the output end of the secondary transformer. Different systems have different oscillation periods, which makes it difficult for the chip time delay setting to follow the time change. Patent CN114900025B cannot clearly know how to reduce the valley lock. However, it can be known that the time delay is difficult to set accurately, and the patent adopts a variety of changes. Compared with patent CN113992028B, which uses dual-frequency clamping signals and valley change signals to obtain the valley lock function, its valley lock interval only has the rising edge difference of the dual-frequency clamping, and the range is small. It is difficult to achieve a more ideal valley lock function, which will cause the switching frequency to switch frequently. Summary of the invention

[0004] The object of the present invention is to provide a valley locking and valley switching circuit and method for a quasi-resonant switching power supply, mainly to solve the problems of discontinuous valley locking and difficulty in determining the timing time in the prior art.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows: A valley locking and valley switching circuit for a quasi-resonant switching power supply comprises a rectifier bridge, a transformer TF1, a capacitor C1, a capacitor C2, a voltage-dividing resistor R1, a voltage-dividing resistor R2, a switch tube N1, a detection resistor Rcs, an absorption circuit and a control chip; two ends of the capacitor C1 are connected to two output ends of the rectifier bridge, an opposite-name end of a primary winding Lp of the transformer TF1 is connected to one end of the capacitor C1, an opposite-name end of an auxiliary winding Laux of the transformer TF1 is connected to the other end of the capacitor C1, one end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2 connected in series is connected to the same-name end of the auxiliary winding Laux of the transformer TF1, an INV pin of the control chip is connected to a common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, a drv pin of the control chip is connected to a gate of the switch tube N1, one end of the detection resistor Rcs is connected to a source of the switch tube N1 and a CS pin of the control chip, and the other end of the detection resistor Rcs is connected to a source of the switch tube N1 and a CS pin of the control chip. The end is connected to the FB pin of the control chip through the capacitor C2, the other end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2 connected in series is connected to the common end of the capacitor C2 and the detection resistor Rcs, and the absorption circuit is connected between the same-name end and the opposite-name end of the primary winding Lp of the transformer TF1; the control chip includes a valley locking and switching module, a valley detection module connected to the valley locking and switching module, a VCO clock signal generating module and a trigger, a peak current limiting module connected to the reset end R pin of the trigger, and a driving module connected to the output end Q of the trigger; wherein, the valley detection module leads out the INV pin connected to the common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, the peak current limiting module leads out the CS pin connected to the source of the switch tube N1, the VCO clock signal generating module leads out the FB pin connected to the capacitor C2, and the driving module leads out the drv pin connected to the gate of the switch tube N1.

[0006] Furthermore, in the present invention, the valley locking and switching module includes a comparator, a valley pulse counter connected to the comparator, a valley counting register connected to the valley pulse counter, a subtractor connected to the valley counting register, a valley locking value module and a valley minus 1 judgment module connected to the subtractor, a valley plus 1 judgment module connected between the output end of the comparator and the valley locking value module, a first logic AND gate having an input end connected to the output end of the comparator, and a second logic AND gate connected to the output end of the first logic AND gate.

[0007] Based on the above circuit, the present invention also provides a valley locking and valley switching method for a quasi-resonant switching power supply, comprising the following steps: S1, uses a rectifier bridge to rectify the AC input voltage into DC, and stores it on capacitor C1 to obtain the VIN DC input voltage, which serves as the main input power supply of the switching power supply; S2, the main input power passes through transformer TF1 and then through resistors R1 and R2 to obtain the INV detection signal to provide signal detection to the control chip; S3, the control chip drives the switch tube N1 to perform switching action, cooperates with the transformer TF1, outputs power to the output winding end of the transformer TF1 cycle by cycle, detects the peak current of the primary winding of the transformer TF1 through the detection resistor Rcs, and when the peak current is reached, the control chip turns off the switch tube N1; S4, the valley detection module of the control chip detects the INV detection signal output by the transformer auxiliary winding and generates a valley pulse valley; the VCO clock signal generation module receives the FB voltage signal and generates a clock signal clk and a clock signal clkpre whose frequency changes with the voltage signal; S5, the rising edge of the clock signal clk becomes high just at the valley number corresponding to the valley lock value, so that the system is in a stable equilibrium state, and the switch tube N1 is turned on at the rising edge of the clock signal clk; S6, when the load becomes larger, the frequencies of the clock signal clk and the clock signal clkpre become larger, and then the rising edges of the clock signal clk and the clock signal clkpre move forward, and the rising edge of the clock signal clk maintains the valley opening corresponding to the valley lock value within n valleys before the valley lock value, where n is a natural number, and when the rising edge of the clock signal clk is greater than n valleys before the valley lock value, the valley switching speed is determined according to the valley difference between the rising edge of the clock signal clk and the valley lock value, so as to realize a stable valley lock function and a fast valley switching function; when the load becomes smaller, the clock signal clk The frequency of the clock signal clkpre becomes smaller, and then the rising edges of the clock signal clk and the clock signal clkpre move back. When the rising edge of the clock signal clkpre is within the valley number corresponding to the valley lock value, the valley lock value remains unchanged for a certain period of time, that is, the valley lock state is maintained; in this way, the valley lock interval of the valley lock function is realized by the dual clock signals; when the valley lock value deviates from the clock signal clk and the clock signal clkpre to the preset value, that is, when the valley number corresponding to the valley lock value is arrived, the rising edge of the clock signal clkpre has not arrived yet, the valley lock value will be increased to realize the valley lock switching.

[0008] Compared with the prior art, the present invention has the following beneficial effects: The present invention can realize the valley locking function, avoiding frequent switching when the valley cannot be locked during the switching process. At the same time, the method proposed by the present invention can realize the continuous and adjustable valley locking, and can quickly follow the load changes, so that the loop control is stable and reliable. In addition, the valley locking and valley switching are not affected by the oscillation waveform period of the system, and have wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a waveform diagram of the quasi-resonance valley opening in the prior art.

[0010] Figure 2 It is a system block diagram of the present invention.

[0011] Figure 3 It is a schematic diagram of valley bottom locking of the present invention.

[0012] Figure 4 VCO clock signal generation in an embodiment of the present invention - relationship diagram between FB and clk frequency.

[0013] Figure 5 A diagram showing the relationship between the dual clock signals of the VCO in an embodiment of the present invention.

[0014] Figure 6 Block diagram of valley locking and switching module in the present invention.

[0015] Figure 7 A flow chart of valley locking and valley switching in an embodiment of the present invention.

[0016] Figure 8 Valley lock plus 1 in the embodiment of the present invention Figure 1 .

[0017] Fig. 9 Valley lock plus 1 in the embodiment of the present invention Figure 2 .

[0018] Fig.10 Valley lock minus 1 in the embodiment of the present invention Figure 1 .

[0019] Fig.11 Valley lock minus 1 in the embodiment of the present invention Figure 2 .

[0020] Fig.12 Valley lock minus 1 in the embodiment of the present invention Figure 3 . DETAILED DESCRIPTION

[0021] The present invention is further described below in conjunction with the accompanying drawings and embodiments. The embodiments of the present invention include but are not limited to the following embodiments.

[0022] The invention discloses a valley locking and valley switching circuit for a quasi-resonant switching power supply, comprising a rectifier bridge, a transformer TF1, a capacitor C1, a capacitor C2, a voltage-dividing resistor R1, a voltage-dividing resistor R2, a switch tube N1, a detection resistor Rcs, an absorption circuit and a control chip; two ends of the capacitor C1 are connected to two output ends of the rectifier bridge, an opposite-name end of a primary winding Lp of the transformer TF1 is connected to one end of the capacitor C1, an opposite-name end of an auxiliary winding Laux of the transformer TF1 is connected to the other end of the capacitor C1, one end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2 connected in series is connected to the same-name end of the auxiliary winding Laux of the transformer TF1, an INV pin of the control chip is connected to a common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, a drv pin of the control chip is connected to the gate of the switch tube N1, one end of the detection resistor Rcs is connected to the source of the switch tube N1 and the CS pin of the control chip, and the detection resistor Rcs is connected to the gate of the switch tube N1. The other end of s is connected to the FB pin of the control chip through the capacitor C2, the other end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2 connected in series is connected to the common end of the capacitor C2 and the detection resistor Rcs, and the absorption circuit is connected between the same-name end and the opposite-name end of the primary winding Lp of the transformer TF1; the control chip includes a valley locking and switching module, a valley detection module connected to the valley locking and switching module, a VCO clock signal generating module and a trigger, a peak current limiting module connected to the reset end R pin of the trigger, and a driving module connected to the output end Q of the trigger; wherein, the valley detection module leads out the INV pin connected to the common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, the peak current limiting module leads out the CS pin connected to the source of the switch tube N1, the VCO clock signal generating module leads out the FB pin connected to the capacitor C2, and the driving module leads out the drv pin connected to the gate of the switch tube N1.

[0023] Among them, the valley locking and switching module includes a comparator, a valley pulse counter connected to the comparator, a valley counting register connected to the valley pulse counter, a subtractor connected to the valley counting register, a valley locking value module and a valley minus 1 judgment module connected to the subtractor, a valley plus 1 judgment module connected between the output end of the comparator and the valley locking value module, a first logic AND gate having an input end connected to the output end of the comparator, and a second logic AND gate connected to the output end of the first logic AND gate.

[0024] like Figure 2As shown, in this embodiment, diodes D1, D2, D3 and D4 form a rectifier bridge, which rectifies the AC input voltage into DC, and stores it on capacitor C1 to obtain a VIN DC input voltage as the main input power of the switching power supply. Transformer TF1 usually has three windings, namely the primary winding Lp, the output winding Ls and the auxiliary winding Laux. The VAUX end of the auxiliary winding is in phase with the Drain end of the primary winding, so the VAUX end voltage forms a proportional relationship with the voltage wave of the drain of the switch tube Drain. The auxiliary winding Laux output VAUX is usually used to power the chip and obtain the INV detection signal after voltage division by resistors R1 and R2 to provide signal detection to the control chip. The absorption circuit is used to absorb the peak voltage of the drain end Drain generated by the leakage inductance of the transformer.

[0025] The control chip drives the switch tube N1 to perform switching action, and cooperates with the transformer TF1 to output power to the output winding end cycle by cycle. The detection resistor Rcs is used to detect the peak current of the primary winding of the transformer TF1. When the peak current is reached, the control chip turns off the switch tube N1. The FB pin of the control chip is used as an error signal output by comparing the output voltage feedback from the optocoupler with the reference voltage. The voltage of FB reflects the level of the output voltage. Since the output voltage is related to the load, the FB voltage also indirectly reflects the size of the output load. If the output load increases, the output voltage decreases, and the FB voltage will also increase accordingly. Capacitor C2 is the loop compensation capacitor of FB. The valley detection module of the control chip detects the INV signal output by the transformer auxiliary winding and generates a valley pulse valley.

[0026] like Figure 3 As shown, the valley pulse valley generates a pulse signal for each valley of the auxiliary winding Laux oscillation waveform. The VCO clock signal generation module receives the FB voltage signal to generate dual clock signals clk and clkpre whose frequencies vary with its voltage signal. When the frequency is appropriate, the rising edge of the clock signal clk becomes high just before the valley number corresponding to the valley lock value, as shown in FIG. Figure 3 The clock signal clk becomes high just before the third valley, so the system is in a stable equilibrium state. When the load increases, the frequency will increase, and then the rising edge of the clock signal will move forward. The rising edge of the clock signal clk will maintain the third valley open within the two valleys before the valley lock value, realizing the valley lock function. Figure 3 , the clock signal clk will be valley locked when it goes high after the first valley, and will be opened at the third valley. When the load becomes smaller, the frequency will become smaller, and then the rising edge of the clock signal will move back. When the rising edge of the clock clkpre is within the valley number corresponding to the valley lock value, the valley lock value remains unchanged for a certain period of time, that is, the valley lock state is maintained. In this way, the valley lock interval of the valley lock function is realized through dual clock signals to avoid frequent valley switching.

[0027] like Figure 4 The figure shows the frequency relationship between FB and the clock signal clk. The frequency of the clock signal clk increases with the increase of the FB voltage. However, the frequency of the clock signal clk is limited by the maximum switching frequency Fclk_max and the minimum switching frequency Fclk_min, which is used to limit the operating frequency range of the switching power supply. Figure 5 As shown, the frequencies of the two clock signals clk and clkpre are the same, and the rising edge of the clock signal clkpre arrives earlier than the rising edge of the clock signal clk.

[0028] In this embodiment, the working principle of the control chip is as follows: the valley lock and switching module receives the valley pulse signal valley and the clock signals clk and clkpre, generates a switch opening control signal to the set terminal S of the trigger, and outputs a high-level modulated pulse pwm to the drive module to output a drv signal to drive the external switch tube N1 to open. The peak current limiting module receives the FB voltage signal, and after an internal step-down operation, it is used to limit the peak voltage at the CS terminal, that is, it limits the peak current of the detection resistor Rcs and the primary side of the transformer, and realizes the peak current limiting function. When the CS voltage reaches the voltage division value of FB, it outputs a pulse signal to the reset terminal R of the trigger to reset the trigger, and the pulse signal pwm becomes low. After passing through the drive module, the drv signal becomes low, and the external switch tube N1 is turned off. When the output load is large, the FB voltage is high, and the corresponding CS peak current is large, and vice versa. At the same switching frequency, the peak value of CS also has a maximum and minimum value limit.

[0029] Figure 6The valley lock and valley switching module of the present invention is shown. The valley pulse counting module is reset when the PWM high level of each pulse signal occurs, and then counts each valley pulse. The valley pulse count value is latched at the rising edge of the clock signal clk, and at the same time, the valley pulse counting continues. The valley lock value module compares with the valley pulse count in real time. When the valley pulse count value reaches the valley lock value, the comparator outputs a high level, and at the same time, the valley pulse counting stops. After the comparator outputs a high level, it indicates that the valley opening condition is reached. The valley opening control pulse valleyon is output through an AND logic operation with the valley pulse. When the clock signal clkpre is at a high level, the switch opening control signal pwmon is output, which acts on the set end S of the subsequent flip-flop to achieve switch opening control. At the same time, the high-level signal output by the comparator, the clock signal clk, and clkpre are jointly used to determine whether the valley lock value is incremented by 1 as the valley lock. When the comparator outputs a high level and both the clock signals clk and clkpre are still at a low level, the valley lock value is immediately incremented by 1, and when the clock signal clkpre becomes high level and the valley pulse is satisfied at the same time, the switch opening control signal is output. When the comparator outputs a high level, the clock signal clkpre is at a high level but the clock signal clk is still at a low level, the switch opening control signal is output, and the valley lock value is incremented by 1 only after the condition is continuously satisfied for the set time T1. When the comparator outputs a high level and both the clock signals clk and clkpre are at a high level, the switch opening control signal is immediately output, and the valley lock value is not incremented. At the same time, after the valley count register latches the valley count value at the rising edge of clk, the valley lock value minus the valley count latch value is sent to the valley decrement by 1 judgment module. When the valley difference < n, the valley lock value remains unchanged. When n <= valley difference < m, if this condition is continuously satisfied within the T2 time, the valley lock value is decremented by 1. When m <= valley difference < k, if this condition is satisfied in consecutive switching cycles within the T3 time, the valley lock value is decremented by 1. When the valley difference >= k, the valley lock value is immediately decremented by 1. Where n, m, and k are positive integers, and n < m < k. At the same time, when the valley difference is greater than 0, it indicates that the clock signal clkpre has become high before the valley count reaches the valley lock value, so the switch opening control signal is immediately output when the valley count reaches the valley lock value.

[0030] Figure 7The following is the flowchart of valley locking and valley switching of the present invention. Start by setting the valley locking value, including the initial setting of the valley locking value and the adjustment of adding 1 and subtracting 1 during the working process. Then reset the valley count when each switching cycle is turned on, perform real-time counting on each valley pulse, and determine whether the count reaches the valley locking value. If it reaches, stop the counting. Then determine whether the rising edges of the clock signals clk and clkpre both arrive. If not satisfied, it means that the switching frequency needs to be decreased and the valley locking value needs to be increased. There are two cases. If the rising edge of the clock signal clkpre does not arrive, the valley locking value is immediately incremented by 1. If the rising edge of the clock signal clkpre arrives but the rising edge of the clock signal clk does not arrive, continuous determination is required. If this condition is continuously satisfied within the time T1, the valley locking value is incremented by 1. And when the clock signal clkpre arrives, the switch-on signal pwmon is output. The time T1 can be set to infinity, that is, no operation of incrementing the valley locking value is performed under this condition.

[0031] Meanwhile, during the valley counting, the counted value is latched at the rising edge of the clock signal clk to obtain the valley count latch value. Then subtract the valley count latch value from the valley locking value to obtain the valley difference. Judge the valley difference. When the valley difference is greater than or equal to n, immediately output the switch-on signal pwmon, and at the same time indicate that the valley locking value is too large and needs to be decreased. Then, according to the deviation degree, set the adjustment rate. When n <= valley difference < m, if this condition is continuously satisfied within the time T2, the valley locking value is decremented by 1. When m <= valley difference < k, if this condition is satisfied in consecutive switching cycles within the time T3, the valley locking value is decremented by 1. When the valley difference >= k, the valley locking value is immediately decremented by 1. Where n, m, and k are positive integers, and n < m < k. The times T2 and T3 can also be clock count values, where T2 > T3, and T3 can also be set to 1 clock count value, that is, equal to one switching cycle to decrement the valley locking value, which is the same as the processing when the valley difference >= k. At the same time, when the valley difference is greater than 0, it means that the clock signal clkpre has become high before the valley count reaches the valley locking value, so the switch-on control signal is immediately output when the valley count reaches the valley locking value.

[0032] Figure 8-Figure 12 The following is the illustration of the valley locking and switching embodiments of the present invention. Figure 8 The following is the schematic of incrementing the valley locking of the present invention Figure 1 . At the beginning, the valley locking value is 3, indicating that the switch will stably turn on at the 3rd valley during normal operation. At this time, if the load becomes slightly smaller, the FB voltage becomes lower, the corresponding clock frequency becomes smaller, and the clock period becomes larger. Then the rising edges of both the clock clk and clkpre are delayed. At the same time, the peak current decreases, the corresponding switch-on time and demagnetization time both decrease, and the vibration waveform moves forward, relatively reflecting the delay of the rising edges of the clock signals clk and clkpre. There appears Figure 8When the valley pulse count reaches 3, clkpre has become a high level, but the clock signal clk has not become a high level. At this time, the control chip can still lock the third valley to control the switch tube to open, maintaining the switching frequency unchanged. When the above continues for T1 time, it means that the switching power supply system is stable and the valley lock value is small, then the valley lock value is increased by 1. The subsequent switching cycle controls the switch tube to open at the fourth valley. At this time, the rising edge of the clock signal clk just corresponds to the fourth valley pulse, and the system is in a balanced state. The T1 time can be set to infinity, that is, the valley lock value is not increased by 1 under this condition.

[0033] Fig. 9 The valley lock plus 1 indicates the present invention. Figure 2 . At the beginning, the valley lock value is 2. At the second valley, the clock signal clkpre is already at a high level, so the switch is turned on at the second valley in the first switching cycle. However, as the load decreases rapidly, the FB voltage decreases rapidly, and the switching frequency decreases significantly. In the second switching cycle, when the valley count reaches the valley lock value 2, the clock signal clkpre is still at a low level, and the switch is not turned on. After the second valley, the rising edge of the clock signal clkpre arrives. After the valley count reaches the valley lock value, the valley lock value is immediately increased by 1, and the valley lock value becomes 3. At the third valley, the clock signal clkpre is already at a high level, and the switch is controlled to turn on. The subsequent switch switches to turn on the switch at valley 3.

[0034] Fig.10 This is a valley lock minus 1 diagram of the present invention. Figure 1 . Another situation is that the output load becomes larger, resulting in a higher FB voltage, a higher switching frequency, and the clock signals clk and clkpre become high and flat before the valley count reaches the valley lock value. The valley count value is reset to zero each time the switch is turned on, and then the valley pulses are counted in real time. During the counting process, the count value is stored at the rising edge of the clock signal clk. As shown in the figure, the valley count storage value is 1. The valley lock value is 4, and the valley difference is 3. When the valley difference is 3 for T2 time, the valley lock value is reduced by 1, and the valley lock value becomes 3. The subsequent switching cycle controls the switch to open at the third valley.

[0035] Fig.11 This is a valley lock minus 1 diagram of the present invention. Figure 2 If the load changes greatly, the switching frequency will also change greatly, resulting in a large valley difference. Fig.11 As shown in the figure, the initial valley lock value is 4, and the clock rises to a high level before the first valley, so the valley difference is 4. After T3 time, the valley lock value is reduced by 1. Fig.10 In this case, T3 is less than T2, and the valley lock value switches faster.

[0036] Fig.12 This is a valley lock minus 1 diagram of the present invention. Figure 3 When the load switches from light load to heavy load, the original valley lock value will be larger, but the clock frequency will increase significantly, resulting in a larger valley difference between the clock rising edge and the valley lock. At this time, the valley lock value needs to be adjusted quickly. Fig.12 As shown in the figure, the original valley lock value is 5, but due to the increase in frequency, the valley count value at the rising edge of clk is 0, so the valley count register value is 0, and the valley difference value is 5. At this time, the valley lock value is immediately reduced by 1, from 5 to 4. The next switching cycle will be turned on at the 4th valley. At this time, the valley count register value may be 1, and the valley difference value is 3, which satisfies Fig.10 As shown, after T2 time, the valley lock value is reduced by 1.

[0037] The present invention realizes a stable valley locking function and a fast and continuous valley switching following function. The stable valley locking function can avoid the noise problem caused by frequent switching of valley opening. The continuous valley switching function enables the system control loop to work continuously and reliably, avoiding the problem of large output voltage ripple caused by large frequency changes. Fast valley switching following allows the switching frequency to quickly follow the changes in load power, ensuring that the power output of the switching power supply is equal to the load power, and avoiding the problem of large output voltage fluctuations caused by large or small power output due to slow frequency following.

[0038] The above embodiment is only one of the preferred implementation modes of the present invention and should not be used to limit the protection scope of the present invention. Any changes or modifications that are made to the main design concept and spirit of the present invention and have no substantive significance, and the technical problems they solve are still consistent with the present invention, should be included in the protection scope of the present invention.

Claims

1. A valley locking and valley switching circuit for a quasi-resonant switching power supply, comprising a rectifier bridge, a transformer TF1, a capacitor C1, a capacitor C2, a voltage-dividing resistor R1, a voltage-dividing resistor R2, a switch tube N1, a detection resistor Rcs, an absorption circuit and a control chip; the two ends of the capacitor C1 are connected to the two output ends of the rectifier bridge, the opposite-name end of the primary winding Lp of the transformer TF1 is connected to one end of the capacitor C1, the opposite-name end of the auxiliary winding Laux of the transformer TF1 is connected to the other end of the capacitor C1, and the voltage-dividing resistor R1 and the voltage-dividing resistor R2 are connected in series at one end to the auxiliary winding Laux of the transformer TF1 The same-name end of the control chip is connected, the INV pin of the control chip is connected to the common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, the drv pin of the control chip is connected to the gate of the switch tube N1, one end of the detection resistor Rcs is connected to the source of the switch tube N1 and the CS pin of the control chip, the other end of the detection resistor Rcs is connected to the FB pin of the control chip via the capacitor C2, the other end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2 connected in series is connected to the common end of the capacitor C2 and the detection resistor Rcs, and the absorption circuit is connected between the same-name end and the opposite-name end of the primary winding Lp of the transformer TF1; it is characterized in that, The control chip includes a valley locking and switching module, a valley detection module connected to the valley locking and switching module, a VCO clock signal generating module and a trigger, a peak current limiting module connected to the reset end R pin of the trigger, and a driving module connected to the output end Q of the trigger; wherein, the valley detection module leads out an INV pin connected to the common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, the peak current limiting module leads out a CS pin connected to the source of the switch tube N1, the VCO clock signal generating module leads out an FB pin connected to the capacitor C2, and the driving module leads out a drv pin connected to the gate of the switch tube N1.

2. A valley locking and valley switching circuit for a quasi-resonant switching power supply according to claim 1, characterized in that: The valley locking and switching module includes a comparator, a valley pulse counter connected to the comparator, a valley counting register connected to the valley pulse counter, a subtractor connected to the valley counting register, a valley locking value module and a valley minus 1 judgment module connected to the subtractor, a valley plus 1 judgment module connected between the output end of the comparator and the valley locking value module, a first logic AND gate having an input end connected to the output end of the comparator, and a second logic AND gate connected to the output end of the first logic AND gate.

3. A valley locking and valley switching method for a quasi-resonant switching power supply, characterized in that: A valley locking and valley switching circuit for a quasi-resonant switching power supply as claimed in claim 2 is adopted, comprising the following steps: S1, uses a rectifier bridge to rectify the AC input voltage into DC, and stores it on capacitor C1 to obtain the VIN DC input voltage, which serves as the main input power supply of the switching power supply; S2, the main input power passes through transformer TF1 and then through resistors R1 and R2 to obtain the INV detection signal to provide signal detection to the control chip; S3, the control chip drives the switch tube N1 to perform switching action, cooperates with the transformer TF1, outputs power to the output winding end of the transformer TF1 cycle by cycle, detects the peak current of the primary winding of the transformer TF1 through the detection resistor Rcs, and when the peak current is reached, the control chip turns off the switch tube N1; S4, the valley detection module of the control chip detects the INV detection signal output by the transformer auxiliary winding and generates a valley pulse valley; the VCO clock signal generation module receives the FB voltage signal and generates a clock signal clk and a clock signal clkpre whose frequency changes with the voltage signal; S5, the rising edge of the clock signal clk becomes high just at the valley number corresponding to the valley lock value, so that the system is in a stable equilibrium state, and the switch tube N1 is turned on at the rising edge of the clock signal clk; S6, when the load becomes larger, the frequencies of the clock signal clk and the clock signal clkpre become larger, and then the rising edges of the clock signal clk and the clock signal clkpre move forward, and the rising edge of the clock signal clk maintains the valley opening corresponding to the valley lock value within n valleys before the valley lock value, where n is a natural number, and when the rising edge of the clock signal clk is greater than n valleys before the valley lock value, the valley switching speed is determined according to the valley difference between the rising edge of the clock signal clk and the valley lock value, so as to realize a stable valley lock function and a fast valley switching function; when the load becomes smaller, the clock signal clk The frequencies of lk and clock signal clkpre become smaller, and then the rising edges of clock signal clk and clock signal clkpre move back. When the rising edge of clock signal clkpre is within the valley number corresponding to the valley lock value, the valley lock value remains unchanged for a certain period of time, that is, the valley lock state is maintained. In this way, the valley lock interval of the valley lock function is realized by dual clock signals. When the valley lock value deviates from the clock signals clk and clkpre to the preset value, that is, when the valley number corresponding to the valley lock value is arrived, the rising edge of clock signal clkpre has not arrived yet, the valley lock value will be increased to realize valley lock switching.

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