Cipher coprocessor architecture giving consideration to security and flexibility and working method

Abstract

The invention belongs to the technical field of data security, and more particularly relates to a password coprocessor architecture giving consideration to security and flexibility and a working method. The architecture comprises a clock gating unit, a coprocessor, a bus and control register, a read-only memory (ROM) and a static random access memory (RAM), the coprocessor is used for instruction operation and data transmission; the clock gating unit is used for controlling the clock signal transmission of the coprocessor; the bus and control register is used for controlling the working mode and state of the coprocessor, and an instruction register REG is used as an instruction space in a user programming mode; the ROM is used for storing an algorithm security mode instruction; and the static random access memory RAM is used as a data storage space, part of the space is used as a privacy space, and the operation intermediate quantity is temporarily stored in an algorithm security mode. According to the invention, the problem of poor algorithm flexibility of the password coprocessor on the premise of ensuring safety and high efficiency is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of data security, and more specifically, relates to a cryptographic coprocessor architecture and a working method that take into account both security and flexibility. Background Art

[0002] With the in-depth development of the Internet of Things, the number of IoT smart terminal devices has exploded, which has brought more complex security issues such as device authentication, data protection and wireless communication. Therefore, it is very important for cryptographic coprocessors to provide chip-level cryptographic technology application solutions to ensure the security and privacy of data transmission, but the existing cryptographic coprocessors have poor balance between security and flexibility.

[0003] Chinese patent document CN220874549U discloses a data encryption and decryption processing module, including a SOC chip and a key memory, wherein the SOC chip and the key memory are electrically connected to each other for power supply and data communication through a PCB board, the key memory is used to store quantum keys, the SOC chip is integrated with an encryption and decryption coprocessor and a temporary storage unit, the temporary storage unit is used to cache data to be encrypted, and the encryption and decryption coprocessor is used to substitute the data to be encrypted and the quantum key into the national secret algorithm to realize data encryption and decryption.

[0004] At present, most cryptographic coprocessors on the market have internally integrated operator units related to commonly used cryptographic algorithms, relying on instructions to use and schedule various types of operators to compile the entire cryptographic algorithm. For the above-mentioned cryptographic coprocessors that rely on instructions to run, instruction memory is required to store the algorithm. The main instruction memories used are RAM and ROM. The RAM storage component is readable, writable and volatile, which means that it supports users to write data and can modify existing data, but the internal data will be lost after power failure. The ROM storage component is readable and non-volatile, and does not support users to change data, but the data will not be lost after power failure.

[0005] The design of cryptographic coprocessors has attracted much attention in recent years. The choice of instruction storage components for cryptographic coprocessors on the market also varies according to the application scenario. A cryptographic coprocessor that chooses RAM as the instruction storage component means that the security and efficiency of the cryptographic coprocessor are not easy to guarantee, while a cryptographic coprocessor that chooses ROM as the instruction storage component means that the flexibility of the cryptographic coprocessor is not easy to guarantee. How to increase algorithm flexibility while ensuring security and efficiency has become one of the important factors restricting the widespread development of cryptographic coprocessors. However, there is little research and innovation on the above major constraints, and further research is needed. Summary of the invention

[0006] The present invention aims to overcome at least one defect of the above-mentioned prior art and provide a cryptographic coprocessor architecture that takes into account both security and flexibility, so as to solve the problem of how to increase the algorithm flexibility of the cryptographic coprocessor while ensuring security and efficiency.

[0007] The invention also provides a working method of a cryptographic coprocessor architecture that takes both security and flexibility into consideration.

[0008] The present invention also provides a computer-readable storage medium for implementing the above method.

[0009] The detailed technical scheme of the present invention is as follows: A cryptographic coprocessor architecture that takes into account both security and flexibility, the architecture comprising: a clock gating unit, a coprocessor, a bus and a control register, a read-only memory ROM and a static random access memory RAM; The coprocessor is used for instruction execution and data transmission; The clock gating unit is used to control the clock signal transmission of the coprocessor and turn off the clock of the coprocessor when the coprocessor is not working; The bus and control register are used to control the working mode and state of the coprocessor, and are stored in the instruction register REG as an instruction space in the user programming mode; the working modes include the algorithm security mode and the user programming mode, and the instruction register REG is used to store the user programming mode instructions; The read-only memory ROM is used to store algorithm security mode instructions, has a built-in security algorithm, and cannot be accessed by customers; The static random access memory RAM is used for data storage space, and part of the space is used as a privacy space to temporarily store intermediate calculation quantities in the algorithm security mode; different storage spaces are divided in the static random access memory RAM, and different access permissions are set according to the working mode.

[0010] Further, the coprocessor includes an instruction fetch unit, an arbitration unit, a decoding unit, a transmitting unit and a plurality of functional units; The instruction fetch unit is used for fetching instructions after the coprocessor is started, and selects different instruction spaces for fetching instructions according to the working mode; An arbitration unit, used to select valid instructions from different instruction spaces according to the working mode, and transmit the valid instructions to the decoding unit; A decoding unit is used to decode valid instructions, decompose them into different functional instructions and split the information; A transmitting unit, used to send the decoded instructions to different functional units for execution; Functional unit, the functional unit N of the coprocessor is used to execute specific instruction functions and perform actions.

[0011] Further, the arbitration unit includes a working mode register MODE_REG and an arbiter, and the working mode register MODE_REG is used to configure the working mode of the coprocessor; The arbiter is used to arbitrate between user programming mode instructions and algorithm security mode instructions, and select one of the two.

[0012] The present invention also includes a working method based on a cryptographic coprocessor architecture that takes into account both security and flexibility, and configures the coprocessor to have two working modes, namely, an algorithm security mode and a user programming mode, as follows: When the user configures the coprocessor's working mode to algorithm security mode, it includes: S1, configure the coprocessor's working mode to algorithm security mode through the bus and control register; S2, write the data to be calculated DATA into the fixed position of the static random access memory RAM; S3, start the coprocessor operation, and the coprocessor runs the instructions in the read-only memory ROM; S4, the coprocessor starts the operation. If the operation is completed, the operation result is read from the fixed position of the static random access memory RAM; otherwise, continue to wait for the coprocessor to complete the operation.

[0013] When the user configures the coprocessor's operating mode to user programming mode, it includes: S01, configuring the coprocessor's working mode to be a user programming mode through the bus and control register; S02, write the data to be calculated DATA into the user-specified location of the static random access memory RAM; S03, write the user programming instruction User_INST into the instruction register REG; S04, start the coprocessor operation, and the coprocessor runs the instruction in the instruction register REG; S05, the coprocessor starts to calculate. If the coprocessor completes the calculation, the process proceeds to step S06; otherwise, the process continues to wait for the coprocessor to complete the calculation. S06, judging whether the user algorithm, i.e., the custom algorithm, is completed, if completed, proceeding to step S07; otherwise, returning to step S03 to loop; S07, reading the operation result from the user-specified location of the static random access memory RAM.

[0014] Furthermore, the instruction arbitration of the coprocessor includes: The instruction register REG stores user instructions, which are user programming instructions User_INST instructions and end instructions END instructions. The memory ROM stores security algorithm instructions. Under the selection of the working mode register MODE_REG, the user programming mode instructions and the algorithm security mode instructions are output in a selected manner through arbitration by the arbitration unit ARBITER. The output valid instruction INST will be transmitted to the decoding unit through the pipe timing beat; The decoding unit decodes the valid instructions, decomposes them into different functional instructions and splits the information; The transmitting unit sends the decoded instructions to multiple functional units to execute specific instruction functions.

[0015] In another aspect of the present invention, a machine-readable storage medium is provided, which stores executable instructions. When the instructions are executed, the machine executes a cryptographic coprocessor architecture working method that takes into account both security and flexibility as described above.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention provides a cryptographic coprocessor architecture and a working method that take into account both security and flexibility. The proposed cryptographic coprocessor architecture can provide two working modes. Users can select the working mode according to their needs, so that the system takes into account both security and flexibility.

[0017] (2) The present invention provides a cryptographic coprocessor architecture and working method that takes into account both security and flexibility. The proposed algorithm security mode allows the cryptographic coprocessor to run the algorithm in the read-only memory ROM, and at the same time calculates the intermediate data in the privacy space, which ensures security while running more efficiently. Users do not need to learn or write algorithm instructions, and it is easy to use. The proposed user programming mode allows the cryptographic coprocessor to run the instructions in REG. Users can customize the algorithm, write instructions to REG cyclically and start the cryptographic coprocessor to implement the customized algorithm, which greatly increases the flexibility of the cryptographic coprocessor without increasing the occupancy of on-chip resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the cryptographic coprocessor architecture design of the present invention.

[0019] Figure 2 This is a schematic diagram of an arbitration circuit in Embodiment 1 of the present invention.

[0020] Figure 3 This is a schematic diagram of the static random access memory RAM space permissions in Example 1 of the present invention.

[0021] Figure 4It is a schematic diagram of the algorithm security mode workflow in Example 1 of the present invention.

[0022] Figure 5 It is a schematic diagram of the user programming mode workflow in Example 1 of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0025] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0026] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0027] Example 1 Ginseng Figure 1 , this embodiment provides a cryptographic coprocessor architecture that takes into account both security and flexibility, the architecture comprising: a clock gating unit, a coprocessor, a bus and a control register, a read-only memory ROM and a static random access memory RAM; The coprocessor is used for instruction execution and data transmission; The clock gating unit is used to control the clock signal transmission of the coprocessor and turn off the clock of the coprocessor when the coprocessor is not working; The bus and control register are used to control the working mode and state of the coprocessor, and the instruction register REG is used as an instruction space in the user programming mode. The working modes include the algorithm security mode and the user programming mode. The instruction register REG is used to store the user programming mode instructions; An instruction register REG is added to the bus register. Without increasing on-chip resources, only the register can be used to provide users with instruction space for executing custom algorithms. If the user executes a fixed algorithm, ROM will be used as the instruction space. At the same time, an arbitration unit is added to the coprocessor as a core component to distinguish the effective instruction space in different working modes. It receives REG instructions and ROM instructions at the same time, arbitrates between the two, and outputs valid instructions.

[0028] The read-only memory ROM is used to store algorithm security mode instructions, has a built-in security algorithm, and cannot be accessed by customers; The static random access memory RAM is used for data storage, and part of the space is used as a privacy space to temporarily store intermediate calculation quantities in the algorithm security mode; Specifically, different storage spaces are divided in the static random access memory RAM, and different access permissions are set according to the working mode. The static random access memory RAM space permissions are as follows: Figure 3 As shown: In the algorithm security mode, the coprocessor can access the entire space of the static random access memory RAM, and cooperate with the instructions in the ROM to load and store input data and output data in the non-privacy space, i.e., the normal space, and load and store the privacy data, i.e., the intermediate calculation data, in the privacy space; In user programming mode, the coprocessor can only access the non-privacy space of the static random access memory RAM, namely the normal space. The user loads and stores the input data, output data and intermediate calculation data of the custom algorithm in this space, limiting the user's access rights to the privacy space to protect the privacy data in the secure mode from being leaked.

[0029] Preferably, the coprocessor comprises an instruction fetch unit, an arbitration unit, a decoding unit, a transmitting unit and a plurality of functional units, namely, functional unit 1 to functional unit N; The instruction fetch unit is used for fetching instructions after the coprocessor is started, and selects different instruction spaces for fetching instructions according to the working mode; An arbitration unit, used to select valid instructions from different instruction spaces according to the working mode, and transmit the valid instructions to the decoding unit; A decoding unit is used to decode valid instructions, decompose them into different functional instructions and split the information; A transmitting unit, used to send the decoded instructions to different functional units for execution; Functional unit, the functional unit N of the coprocessor is used to execute specific instruction functions and perform actions.

[0030] Further, the arbitration unit includes a working mode register MODE_REG and an arbiter, and the working mode register MODE_REG is used to configure the working mode of the coprocessor; The arbiter is used to arbitrate between user programming mode instructions and algorithm security mode instructions, and select one of the two.

[0031] Example 2 This embodiment also provides a working method based on the above-mentioned cryptographic coprocessor architecture that takes into account both security and flexibility. The two matching working modes are an algorithm security mode and a user programming mode, as follows: When the user configures the coprocessor to work in safe mode, the instructions in the ROM will be output to the next stage through the arbitration circuit. When the pipeline encounters the end instruction, the pipeline will stop and the coprocessor will be turned off. At this time, the coprocessor will run a safe and efficient fixed algorithm, which is easy to use.

[0032] The workflow when configured in algorithm security mode is as follows: Figure 4 As shown, the steps are: S1, configure the coprocessor's working mode to algorithm security mode through the bus and control register; S2. Write the data to be calculated DATA to a fixed position of the static random access memory RAM; that is, in the algorithm security mode, the coprocessor can access the entire space of the static random access memory RAM, and load and store the input data and output data in the non-privacy space, i.e., the normal space, in conjunction with the instructions in the ROM, and load and store the privacy data, i.e., the intermediate calculation data, in the privacy space; S3, start the coprocessor operation, and the coprocessor runs the instructions in the read-only memory ROM; S4, the coprocessor starts the operation. If the operation is completed, the operation result is read from the fixed position of the static random access memory RAM; otherwise, continue to wait for the coprocessor to complete the operation; When the user configures the coprocessor's working mode to user mode, the instruction in register REG will be output to the next stage through the arbitration circuit. In order not to increase the control logic, the pipeline control end circuit is reused, and the hard-coded hardware connection is used as the next end instruction to automatically stop the pipeline and shut down the coprocessor. At this time, the coprocessor will run the user-defined algorithm to improve the flexibility of the coprocessor.

[0033] The workflow for configuration in user programming mode is as follows: Figure 5 As shown, the steps are: S01, configuring the coprocessor's working mode to be a user programming mode through the bus and control register; S02, write the data to be calculated to the user-specified location of the static random access memory RAM; that is, in the user programming mode, the coprocessor only accesses the non-privacy space of the static random access memory RAM, that is, the normal space, and the user loads and stores the input data, output data and intermediate calculation data of the custom algorithm in this space; S03, write the user programming instruction User_INST into the instruction register REG; S04, start the coprocessor operation, and the coprocessor runs the instruction in the instruction register REG; S05, the coprocessor starts to calculate. If the coprocessor completes the calculation, the process proceeds to step S06; otherwise, the process continues to wait for the coprocessor to complete the calculation. S06, judging whether the user algorithm, i.e., the custom algorithm, is completed, if completed, proceeding to step S07; otherwise, returning to step S03 to loop; S07, reading the operation result from the user-specified location of the static random access memory RAM.

[0034] The user algorithm includes a plurality of user programming instructions.

[0035] Further, the instruction arbitration of the coprocessor is implemented by an instruction arbitration circuit; Instruction arbitration circuit Figure 2 As shown, it includes instruction register REG, user programming instruction User_INST, end instruction END, read-only memory ROM, arbitration unit ARBITER, working mode register MODE_REG, effective instruction INST and pipe instant beat; The instruction arbitration of the coprocessor includes: The instruction register REG stores user instructions, which are user programming instructions User_INST instructions and end instructions END instructions. The memory ROM stores security algorithm instructions. Under the selection of the working mode register MODE_REG, the user programming mode instructions and the algorithm security mode instructions are output in a selected manner through arbitration by the arbitration unit ARBITER. The output valid instruction INST will be transmitted to the decoding unit through the pipe timing beat; The decoding unit decodes the valid instructions, decomposes them into different functional instructions and splits the information; The transmitting unit sends the decoded instruction to the functional unit 1, the functional unit 2, ..., the functional unit N-1 and the functional unit N to execute the specific instruction function.

[0036] In summary, the new coprocessor architecture proposed in the present invention optimizes the instruction space and data space, and proposes two working modes. The present invention proposes two types of instruction space, namely ROM as a security algorithm instruction space and REG as a user-programmed algorithm instruction space. When the algorithm is run using ROM, the algorithm content cannot be accessed from the outside, thereby achieving safe operation of the algorithm. At the same time, the algorithm in the ROM is written and designed by the manufacturer according to the coprocessor architecture, and the operation is more efficient; when the algorithm is run using register REG, the user can cyclically fill in instructions and run to implement a custom algorithm, which does not increase the on-chip resource usage and has high flexibility.

[0037] The present invention proposes two types of permission division for data space, namely, a normal space for storing common data and a privacy space for storing privacy data. When running in algorithm security mode, the coprocessor can access the entire space. When running in user programming mode, the coprocessor can only access the normal space, thereby protecting privacy data from leakage at the hardware level and further improving the security of the cryptographic coprocessor.

[0038] This architecture combines multi-type instruction storage space technology, permission-based data storage space technology and working mode, which can solve the current problem of the coprocessor's inability to balance security and flexibility when working, and further improve the coprocessor's adaptability in different application scenarios.

[0039] Example 3 This embodiment also provides a computer-readable storage medium storing executable instructions, which, when executed, enable the machine to execute a working method of a cryptographic coprocessor architecture that takes into account both security and flexibility as described above.

[0040] Specifically, a system or device equipped with a readable storage medium can be provided, on which software program codes that implement the functions of any of the above-mentioned embodiments are stored, and a computer or processor of the system or device can read and execute instructions stored in the readable storage medium.

[0041] In this case, the program code itself read from the machine-readable medium can realize the function of any one of the above embodiments, and thus the machine-readable code and the machine-readable storage medium storing the machine-readable code constitute part of this specification.

[0042] Examples of readable storage media include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program code may be downloaded from a server computer or a cloud via a communication network.

[0043] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0044] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0045] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0046] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0047] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solution of the present invention, and are not intended to limit the specific implementation methods of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the claims of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A cryptographic coprocessor architecture that takes into account both security and flexibility, characterized in that: The architecture includes a coprocessor, a clock gating unit, a bus and control registers, a read-only memory ROM and a static random access memory RAM; The coprocessor is used for instruction execution and data transmission; The clock gating unit is used to control the clock signal transmission of the coprocessor and turn off the clock of the coprocessor when the coprocessor is not working; The bus and control register are used to control the coprocessor working mode and state, and are stored in the instruction register REG as an instruction space in the user programming mode; wherein the working mode includes the algorithm security mode and the user programming mode; The read-only memory ROM is used to store algorithm security mode instructions, has a built-in security algorithm, and cannot be accessed by customers; The static random access memory RAM is used for data storage space, and part of the space is used as a privacy space to temporarily store intermediate calculation quantities in the algorithm security mode.

2. A cryptographic coprocessor architecture that takes into account both security and flexibility according to claim 1, characterized in that: The coprocessor includes an instruction fetch unit, an arbitration unit, a decoding unit, a transmitting unit and a plurality of functional units; The instruction fetch unit is used for fetching instructions after the coprocessor is started, and selects different instruction spaces for fetching instructions according to the working mode; An arbitration unit, used to select valid instructions from different instruction spaces according to the working mode, and transmit the valid instructions to the decoding unit; A decoding unit is used to decode valid instructions, decompose them into different functional instructions and split the information; A transmitting unit, used to send the decoded instructions to different functional units for execution; Functional unit, used to execute specific instruction functions and perform actions.

3. A cryptographic coprocessor architecture that takes into account both security and flexibility according to claim 2, characterized in that: The arbitration unit includes a working mode register MODE_REG and an arbiter, wherein the working mode register MODE_REG is used to configure the working mode of the coprocessor; The arbiter is used to arbitrate between user programming mode instructions and algorithm security mode instructions, and select one of the two.

4. A method for operating a cryptographic coprocessor architecture that takes into account both security and flexibility, characterized in that: The two working modes of the configuration coprocessor are algorithm security mode and user programming mode; When the user configures the coprocessor's working mode to algorithm security mode, it includes: S1, configure the coprocessor's working mode to algorithm security mode through the bus and control register; S2, write the data to be calculated DATA into the fixed position of the static random access memory RAM; S3, start the coprocessor operation, and the coprocessor runs the instructions in the read-only memory ROM; S4, the coprocessor starts the operation. If the operation is completed, the operation result is read from the fixed position of the static random access memory RAM; otherwise, continue to wait for the coprocessor to complete the operation; When the user configures the coprocessor's operating mode to user programming mode, it includes: S01, configuring the coprocessor's working mode to be a user programming mode through the bus and control register; S02, write the data to be calculated DATA into the user-specified location of the static random access memory RAM; S03, write the user programming instruction User_INST into the instruction register REG; S04, start the coprocessor operation, and the coprocessor runs the instruction in the instruction register REG; S05, the coprocessor starts to calculate. If the coprocessor completes the calculation, the process proceeds to step S06; otherwise, the process continues to wait for the coprocessor to complete the calculation. S06, judging whether the user algorithm, i.e., the custom algorithm, is completed. If it is completed, i.e., the custom algorithm is finished, then proceeding to step S07; otherwise, returning to step S03 to loop back and forth; S07, reading the operation result from the user-specified location of the static random access memory RAM.

5. The method for operating a cryptographic coprocessor architecture that takes into account both security and flexibility according to claim 4, characterized in that: The instruction arbitration of the coprocessor includes: The instruction register REG stores user instructions, which are user programming instructions User_INST instructions and end instructions END instructions. The memory ROM stores security algorithm instructions. Under the selection of the working mode register MODE_REG, the user programming mode instructions and the algorithm security mode instructions are output in a selected manner through arbitration by the arbitration unit ARBITER. The output valid instruction INST will be transmitted to the decoding unit through the pipe timing beat; The decoding unit decodes the valid instructions, decomposes them into different functional instructions and splits the information; The transmitting unit sends the decoded instructions to multiple functional units to execute specific instruction functions.

6. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 4 to 5 are implemented.

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