CPU-GPU (Central Processing Unit-Graphic Processing Unit) data processing and transmission optimization system and method for zero-knowledge proof

Abstract

The invention discloses a CPU-GPU (central processing unit-graphics processing unit) data processing and transmission optimization system for zero-knowledge proof, which is used for executing multi-scalar multiplication based on elliptic curve cryptography so as to realize the generation of zero-knowledge proof, and comprises a CPU and a GPU, a data transmission channel is arranged between the CPU and the GPU, and the data transmission channel is communicated with the GPU. The CPU is used for acquiring and storing a point set and a scalar set related to the multi-scalar multiplication and communicating with the GPU by utilizing a set parallel data transmission mechanism, and the GPU executes the multi-scalar multiplication calculation based on the point set and the scalar set and returns a calculation result to the CPU. Through the synergistic effect of a plurality of technical points, the speed and efficiency of zero-knowledge proof generation are remarkably improved, and the resource use efficiency is optimized.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more specifically, to a CPU-GPU data processing and transmission optimization system and method for zero-knowledge proof. Background Art

[0002] Zero-Knowledge Proof (ZKP) is a cryptographic protocol based on the consent of two or more parties. Its purpose is to enable the prover (Prover) to convince the verifier of the authenticity of a statement without revealing any useful information to the verifier. The key to this protocol is to ensure the trust of the verifier while protecting the information privacy of the prover. The core value of zero-knowledge proof is that it can prove the authenticity of a statement without leaking any specific information. However, the implementation of this technology faces huge computing challenges, mainly due to the computationally intensive nature of its algorithm. The traditional central processing unit (CPU) architecture seems to be unable to cope with such high-concurrency and high-computational-density tasks, especially when dealing with large-scale data sets and complex calculations. Limited by its single-threaded performance and memory access latency, the CPU often finds it difficult to achieve satisfactory efficiency.

[0003] To overcome this limitation, heterogeneous computing architectures, especially field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and graphics processing units (GPUs), have become the key to achieving efficient computing of zero-knowledge proofs due to their unique parallel processing capabilities and customized computing advantages. FPGAs can greatly improve the speed of complex mathematical operations in ZKP through parallel processing and pipeline optimization, thereby shortening the time for proof generation and verification, which is particularly important for application scenarios with high real-time requirements. In addition, the programmability and flexibility of FPGAs allow customized designs for specific ZKP algorithms, achieving more efficient computing paths, reducing unnecessary data movement and storage, thereby improving overall performance and making large-scale deployment possible. ASICs are integrated circuits customized for a certain type of application. For zero-knowledge proofs, ASICs can be designed to specifically perform certain key mathematical operations, such as modular multiplication and elliptic curve point addition, thereby providing higher-performance customized computing, lower power consumption, smaller physical size, and long-term economic benefits. Especially in stable large-scale applications, the fixed circuit design of ASICs ensures computing efficiency and data processing security. For example, PipeZK uses ASIC chips to implement a pipelined architecture, which achieves efficient zero-knowledge proof generation by setting up special circuits to accelerate the two computationally intensive stages of fast number theory transformation and multi-scalar multiplication. GPUs have a large number of simple computing units that are specifically used for parallel computing and can perform a large number of similar computing tasks at the same time, which is very effective for matrix operations, vector operations, and parallelized large number operations commonly used in zero-knowledge proofs. GPUs have a good programming environment and provide developers with more friendly development tools and libraries, allowing developers to program in high-level languages ​​close to C++, which significantly reduces the learning curve for zero-knowledge proof algorithm development and allows developers from more backgrounds to participate. In addition, the GPU market is relatively mature, with rich driver support and development tools.

[0004] However, the existing heterogeneous computing architecture for generating zero-knowledge proofs has the following defects:

[0005] 1) The design and implementation of FPGAs usually require deep knowledge of hardware description languages ​​(such as Verilog or VHDL) and a deep understanding of the principles of hardware logic design. This leads to high technical barriers and learning costs. For developers with a software background, mastering FPGA development skills often takes a long time and effort. In addition, circuit designs on FPGAs are usually highly customized and optimized for specific algorithms or applications. This specificity means that porting designs between different application scenarios will be difficult, and the hardware configuration needs to be re-evaluated and adjusted, which increases the development cycle and cost of the project.

[0006] 2) Although the application of ASIC chips to the generation and verification of zero-knowledge proofs can significantly improve the operating efficiency of specific algorithms and reduce energy consumption, there are also some limitations. For example, poor flexibility: once the design of an ASIC chip is completed, its circuit layout and functions are fixed, which means that it cannot easily adapt to new ZKP algorithms or parameter changes; high development costs: designing and manufacturing ASIC chips requires high upfront investment, including design fees, mask costs, and testing and production costs, which is not economical for smaller-scale applications or experimental ZKP solutions; long update cycle: ASIC has a long design and manufacturing cycle. If there is a major breakthrough or algorithm improvement in the ZKP field, ASIC cannot follow up in time, resulting in obsolescence.

[0007] 3) Although GPUs have high-bandwidth video memory, ZKP calculations may involve a large amount of data transfer, especially when data needs to be frequently exchanged between the CPU and GPU, which will add additional latency and overhead. The transmission of data between the host (CPU) and the device (GPU) needs to go through the PCIe bus, which is a bottleneck. For ZKP calculations, if the algorithm requires a large amount of data exchange, this communication delay will significantly affect performance. Frequent data transfer will aggravate this problem, especially when ZKP involves complex interactive protocols. In addition, not only is there a delay in communication between the GPU and the outside world, but data sharing and synchronization between different threads within the GPU will also cause delays. If the ZKP algorithm is not designed properly, it will lead to unnecessary memory access patterns or excessive synchronization operations, which will also increase computing latency.

[0008] In existing zero-knowledge proof generation libraries, such as the Bellman algorithm library, their architecture is often limited by the data transmission from the CPU to the GPU, resulting in performance bottlenecks. Figure 1 As shown in Figure 1, during the multi-scalar multiplication calculation process, a large number of point sets and scalar sets are usually transferred between heterogeneous architectures. However, since the GPU needs to wait for the CPU to complete the data transfer before starting the calculation, the GPU is idle while waiting for the data transfer to complete, thus affecting the overall computing efficiency.

[0009] In summary, the promotion and application of zero-knowledge proof technology still faces problems such as high computing requirements, lengthy generation cycles and high operating costs, which greatly hinder its widespread application in architectures such as blockchain. Especially in environments such as financial markets that have strict requirements for immediate response, the generation and verification delays of zero-knowledge proofs will directly threaten the confidentiality and robustness of transactions, thereby triggering a series of negative effects, such as transaction delays, reduced trust and potential economic losses. It is worth noting that frequent data exchanges between the host and the graphics processing unit (GPU) often cause idle computing resources and form a bottleneck for performance improvement. Therefore, optimizing the communication mechanism between the CPU and GPU and improving the memory access strategy have become key strategies to improve the performance of zero-knowledge proofs, with the aim of significantly reducing the proof construction time. Summary of the invention

[0010] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a CPU-GPU data processing and transmission optimization system and method for zero-knowledge proof.

[0011] According to a first aspect of the present invention, there is provided a CPU-GPU data processing and transmission optimization system for zero-knowledge proof, which is used to perform multi-scalar multiplication operations based on elliptic curve cryptography to achieve the generation of zero-knowledge proofs. The system comprises a CPU and a GPU, wherein a data transmission channel is provided between the CPU and the GPU, the CPU is used to obtain and store point sets and scalar sets involved in the multi-scalar multiplication operations, and communicate with the GPU using a set parallelized data transmission mechanism, the GPU performs multi-scalar multiplication calculations based on the point sets and the scalar sets, and transmits the calculation results back to the CPU.

[0012] According to a second aspect of the present invention, a method for optimizing CPU-GPU data processing and transmission for zero-knowledge proof is provided. The method comprises the following steps:

[0013] The point set and the scalar set involved in the multi-scalar multiplication operation are stored in the CPU, where the multi-scalar multiplication operation is a multi-scalar multiplication operation based on elliptic curve cryptography and is used to realize the generation of zero-knowledge proof;

[0014] Data is transferred between the CPU and the GPU using a set parallel data transmission mechanism, so as to control the GPU to perform multi-scalar multiplication calculation based on the point set and the scalar set, and to return the calculation result to the CPU.

[0015] Compared with the prior art, the advantage of the present invention is that it proposes an innovative parallel data transmission mechanism for the CPU-GPU heterogeneous architecture. The core of the parallel mechanism is to redesign the data flow, allowing the GPU to immediately process part of the transmitted data while the CPU is preparing the data, without waiting for all the data to be fully transmitted at one time. This design improves the throughput of zero-knowledge proof generation, reduces the idle cycle of the GPU, and shortens the proof generation time through more efficient task scheduling, thereby effectively improving system performance and reducing computing costs without increasing hardware overhead. The present invention solves the problems of communication delay between the CPU and the GPU, as well as data sharing and synchronization delay.

[0016] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0018] Figure 1 It is a Bellman execution diagram of the prior art;

[0019] Figure 2 is a schematic diagram of a CPU-GPU heterogeneous architecture for zero-knowledge proof according to an embodiment of the present invention;

[0020] Figure 3 is a schematic diagram of an update process of a shared pre-calculated table according to an embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of elliptic curve calculation according to an embodiment of the present invention;

[0022] Figure 5 is a schematic diagram of CPU-GPU transmission performance comparison for zero-knowledge proof according to an embodiment of the present invention;

[0023] Figure 6 Schematic diagram of zero copy technology according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0025] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0026] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0027] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0028] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0029] In the calculation process of zero-knowledge proof, efficient data transmission between CPU and GPU is crucial. Improving data transmission efficiency can significantly shorten the delay of data exchange between CPU and GPU, reduce the waiting time during the transmission process, thereby speeding up the generation and verification of zero-knowledge proof, and can provide users with a smoother and more efficient service experience under the premise of ensuring high security and privacy, meeting the growing needs of big data processing and complex computing.

[0030] The CPU-GPU data processing and transmission optimization system for zero-knowledge proof provided by the present invention is a CPU-GPU heterogeneous architecture, see Figure 2 As shown. The CPU (central processing unit) is the main computing unit of a computer, including, for example, a controller, an ALU (arithmetic logic unit), a cache, and memory. The CPU is responsible for controlling and coordinating the operation of the system, including but not limited to running the operating system, managing memory, and I / O devices. In the context of ZKP, the CPU is usually responsible for processing non-parallel logic processes, such as initialization, data preparation, result aggregation, etc., as well as performing necessary data pre-processing and post-processing before and after GPU (graphics processing unit) calculations. The GPU was originally designed for graphics rendering, but due to its powerful parallel computing capabilities, it has now been widely used in scientific computing, machine learning, and cryptography. The GPU consists of multiple stream processors (SMs), each of which uses a single instruction multi-threaded parallel processing mode and supports thousands of synchronous threads co-resident in the GPU main memory. This makes the GPU highly parallel and particularly suitable for processing large-scale computing tasks without data dependencies, such as the computing operations required in zero-knowledge proofs. In the scenario of zero-knowledge proofs, the GPU is mainly used to perform a large number of parallel mathematical operations, such as matrix multiplication, modular operations, polynomial operations, etc., which are the most time-consuming parts of the zero-knowledge proof generation and verification process.

[0031] In general, the system architecture of the present invention focuses on optimizing the communication architecture and memory architecture in design. These two parts are crucial to improving the efficient data transmission between the CPU and GPU for zero-knowledge proof (ZKP). For the communication structure, a high-speed data transmission channel, such as PCIe (Peripheral Component Interconnect Express), is required between the CPU and the GPU. The optimized system will use more efficient transmission protocols and hardware to achieve intelligent scheduling and optimization of data flow, ensure that data flows efficiently between the CPU and the GPU, reduce unnecessary data copying and waiting time, and ensure that data transmission will not become a bottleneck for the performance of the entire system. For the memory architecture, the system usually contains two types of memory, namely CPU memory and GPU memory. In order to improve efficiency, data needs to be intelligently managed and scheduled between these memory spaces so as to minimize data copying and transmission during the calculation process.

[0032] Aiming at the performance bottleneck in the zero-knowledge proof generation process, the present invention proposes an innovative high-performance computing framework that focuses on optimizing data transmission and preprocessing mechanisms. The framework aims to significantly improve the execution efficiency of the zero-knowledge proof algorithm while ensuring the rational use of resources and enhancing the overall performance and security of the system. In the following, the embodiments of the optimized preprocessing mechanism and data transmission mechanism will be specifically introduced.

[0033] First, optimize the preprocessing mechanism

[0034] 1. Shared pre-calculated tables

[0035] A precomputation table is a data structure used to precompute and store the results of specific functions or operations that will be frequently used in subsequent computations. By creating such a table before the computation begins or in the early stages of a computationally intensive task, a portion of the computationally intensive workload can be shifted to the preprocessing stage. This approach can significantly reduce the cost of online or real-time computing and improve computing efficiency.

[0036] Shared precomputed tables are an optimization technique used to reduce computation time and storage requirements in the context of multi-scalar multiplication (MSM) in elliptic curve cryptography (ECC). Shared precomputed tables are an efficient way to speed up subsequent multi-scalar multiplication computations by computing and storing multiples of points on the elliptic curve in advance. This approach is particularly useful when dealing with multiple related points, as it allows these points to share the same optimization table, reducing redundant computation and storage burden.

[0037] The basic idea of ​​sharing precomputed tables is: suppose there is a set of points {P1, P2, ..., P n}, and these points are all in the same subgroup on the elliptic curve. This means that for any point P i and P j , there exists some integer k such that P i = k·P j or P j = k·P i If we can find a base point G, which is the generator of all points, that is, all P i =k i G, then we can precompute only the multiples of the base point G, and these multiples can be used to speed up any point P i Scalar multiplication of .

[0038] In one embodiment, the steps of implementing multi-scalar multiplication using a shared pre-calculation table include:

[0039] S1, choose the base point: find a suitable base point G that can generate all P i subgroup of .

[0040] Typically, G is a generator of large prime order on an elliptic curve.

[0041] S2, build a pre-calculation table: pre-calculate the multiple sequence of G.

[0042] For example, the sequence of multiples of precomputed G is G, 2G, 3G, ..., lG, where l is the maximum length of the precomputed table, usually 2. w , where w is the window size in the split window phase of the Pippenger (bucket) algorithm.

[0043] S3, optimized scalar multiplication.

[0044] For example, for each point P i =k i G, scalar multiplication can be accelerated by looking up the appropriate value in a precomputed table. Specifically, if k i In binary, it can be decomposed into k i =b0+b1·2 w +b2·2 2w +..., where b j is a w-bit binary number, then we can use the point G in the precomputed table, 2 w G, 2 2w G..., and obtain P by point addition and doubling i .

[0045] The storage core of the pre-calculated table mainly lies in the carefully selected set of multiples of the base point G, and the storage of the scalar relationship between the points in each point set and G. These multiples constitute the basic components for quickly constructing arbitrary scalar multiplication results. By pre-calculating a series of multiple points of the base point G and storing them, subsequent large-scale scalar multiplication operations can be significantly accelerated, because many common multiplications can be decomposed into simple combinations of pre-calculated points, reducing the need for real-time calculations. In addition, in order to reduce the storage overhead of the pre-calculated table, coordinate compression technology can be adopted, that is, only the x coordinate of the point is stored, and the y coordinate can be calculated when needed according to the elliptic curve equation, realizing the efficient use of storage space.

[0046] In order to cope with different situations and performance requirements, in one embodiment, the set pre-calculation table will also be updated regularly, including but not limited to adding deeper pre-calculation points to adapt to the Pippenger algorithm with a larger window size, or updating the algorithm to improve efficiency.

[0047] Figure 3 It is the updating process of the pre-calculation table. At the beginning of the calculation, a certain amount of storage space is reserved in the pre-calculation table to store the pre-calculated point sets. These point sets are usually carefully selected according to the expected calculation requirements so as to cover most cases as much as possible in the subsequent calculation process. When a point set that needs to be solved is encountered during the calculation, first try to find out whether there is a corresponding calculated result in the pre-calculation table. If it exists, the result can be obtained directly from the table without the need to perform complex calculations again, thus saving a lot of computing time and resources; if it does not exist, the point set is recalculated and the calculation result is returned to the GPU. As the calculation progresses, the content of the pre-calculation table will also change. When a new calculation result is generated, it is necessary to decide whether to add it to the pre-calculation table. If there is still enough remaining space in the pre-calculation table, the newly generated point set result will be directly inserted into the table for subsequent query use. Through this design, the future calculation burden can be further reduced and the calculation efficiency can be improved. However, when the space in the pre-calculation table is insufficient, a set effective strategy is adopted to manage the content in the table. Considering that the calculation of point sets has obvious temporal locality, that is, the point sets that have been recently visited are likely to be visited again in the future, in one embodiment, the Least Recently Used (LRU) strategy is used to update the content of the pre-calculated table. The LRU algorithm is a replacement algorithm, and its basic idea is to give priority to eliminating those items that have not been used for the longest time, so as to keep the content stored in the table as the most representative and most frequently used point sets. In this way, the value of the pre-calculated table can be maximized, so that it is always in the optimal state to meet the current calculation needs.

[0048] At the same time, as the pre-calculated table is updated, the point set relationship database designed by the pre-calculated table will also be checked and updated synchronously to ensure that all point sets that rely on the pre-calculated table can be correctly mapped to the latest point set to maintain the accuracy and efficiency of the calculation. Finally, in the selection of data structure, in order to efficiently manage the points and their scalar relationships in the pre-calculated table, a hash table is used to store the scalar value of the base point, ensuring an average search time of O(1), that is, regardless of the size of the data set, the time required to find the scalar value of a point is constant. Through this strategy, the pre-calculated table can not only significantly improve the computational efficiency of multi-scalar multiplication in elliptic curve cryptography, but also effectively manage storage resources to ensure the security and reliability of the system.

[0049] 2. Signed Window Method

[0050] Combination Figure 4 As shown, in elliptic curve cryptography, the negation of a point shows a significant computational efficiency advantage over point addition or doubling, mainly due to its simplified mathematical operation requirements. Specifically, in elliptic curve cryptography, the negative point -P of a point P usually refers to the point on the elliptic curve that is symmetric with P about the x-axis. In most mathematical representations of elliptic curves, calculating the negative point of a point is a very simple operation because it only involves changing the sign of the y coordinate. There is no need to perform complex modular operations, multiplication inverse element calculations, or square root solutions. Therefore, in one embodiment, the computational complexity of multi-scalar multiplication is reduced in an easy way according to the elliptic curve to take the sign, thereby improving the efficiency of generating zero-knowledge proofs.

[0051] In contrast, point addition or doubling not only involves the calculation of polynomials, but also often requires solving the inverse of multiplication, which is a time-consuming task in a finite field. Therefore, the present invention introduces it into the calculation of multiple scalar multiplication and point multiplication. In view of the efficient characteristics of the negation operation, it can significantly reduce the consumption of computing resources and improve the overall computing speed, providing an important performance optimization method for the application of elliptic curve cryptography. In the traditional Pippenger unsigned window method, the window value range is [0, 2 c-1 ], resulting in each window possibly needing to process up to 2 c After the introduction of the signed window, the window value range becomes [-2 c-1 , 2 c-1 -1]. This not only reduces the absolute range of the window values, but also allows the use of negative representations of points, i.e., the inversion of points, to replace some dot multiplication operations, thereby reducing the number of window values ​​that need to be processed separately.

[0052] In one embodiment, the step of converting the scalar k into a signed sliding window encoding includes:

[0053] Step S21, determine the window size

[0054] For example, choose a window size c. The window size determines how many bits are in each window.

[0055] Step S2, expressing the scalar k in binary form to obtain a binary string.

[0056] For example, if k=23, its binary form is 10111.

[0057] Step S3, performing window division on the binary string.

[0058] The binary string is divided into several windows according to the length of c bits. For example, for c=3, 10111 will be divided into 010 and 111. It should be understood that in order to form a complete window, it is necessary to fill the leading 0 in some cases.

[0059] Step S4, converting the window value into a decimal number.

[0060] For example, 010 converts to 2 and 111 converts to 7.

[0061] Step S5, signed conversion

[0062] For each window value v, if v>2 c-1 -1, then subtract 2 from v c , making it a signed number. For example, if c = 3, the window value should be in the range [-4, 3]. If the window value is 5 or greater, it is converted to an equivalent negative number. For example, 5 will be converted to -3 because 5-8 = -3.

[0063] Step S6, adjusting the subsequent window

[0064] If the value of the current window changes from a positive number to a negative number (i.e. minus 2 c ), then we need to increase the value of the next window by 1 to maintain the equivalence of scalar multiplication.

[0065] In elliptic curve arithmetic, point addition and point doubling are the most basic and expensive operations. The signed window method reduces the absolute size of the window value by allowing the use of negative points, thereby more frequently utilizing the inverted form of the point in the multi-scalar multiplication (MSM) process to improve computational efficiency. This efficient feature significantly reduces the number of complex point operations, reduces computing resource consumption, improves computational efficiency, and ensures that the efficiency and correctness of the computation can be maintained even when a smaller window size is used.

[0066] Second, optimize the data transmission mechanism

[0067] 1. Asynchronous data transmission mechanism

[0068] The core value of asynchronous data transmission is that it breaks the inherent boundary between data transmission and computing tasks, making it possible for the two to proceed in parallel. Specifically, when data is being copied from the CPU to the GPU, the GPU will not stagnate, but will continue to process the existing data set and perform computing tasks. This mechanism not only significantly shortens the idle period of the GPU, but also greatly improves the utilization efficiency of hardware resources by overlapping data transmission and computing.

[0069] In order to achieve this optimization in the data transmission part of zero-knowledge proof generation, in one embodiment, a point set-based batch transmission strategy is proposed. The key to this strategy lies in sophisticated performance evaluation and data management. First, a large data set is divided into several small batches, and the size of each batch is evaluated based on the performance of the GPU to ensure that the GPU has enough workload after receiving the data while avoiding waiting time during data transmission. The purpose of this strategy is to keep the GPU active at all times, fully utilize its computing power, and avoid performance waste caused by data transmission.

[0070] In addition, in the data processing process, after each batch of data is calculated, the GPU will immediately send the results back to the CPU, instead of waiting until all data is processed before summarizing. This instant feedback mechanism enables the CPU to perform subtask regulation and integration in a timely manner, prepare for the next step of calculation in advance, and further accelerate the entire calculation process. In addition, in order to meet the storage requirements of large-scale data sets and reduce storage costs, this strategy also emphasizes the effective management of memory. Once a data set or some of its elements are no longer involved in the calculation, the occupied memory space is immediately released to ensure efficient use of resources.

[0071] In summary, by implementing an asynchronous data transmission strategy, combining point set batch processing and instant feedback mechanisms, and a dynamic memory management strategy, the efficiency of CPU and GPU collaboration can be significantly improved. This overlapping computation and data transmission method not only reduces GPU waiting time, but also optimizes memory usage, providing powerful technical support for processing large-scale data sets, especially in computationally intensive tasks such as zero-knowledge proof (ZKP) generation and verification, showing great potential and advantages. Compared with the original zero-knowledge generation system, Figure 1 For comparison, Figure 5 It shows that the CPU has improved by 4 time blocks and the GPU has improved by 2 time blocks. As the amount of data increases, the optimization method proposed in the present invention will have more obvious advantages in improving the work efficiency of the CPU and GPU.

[0072] 2. Zero copy technology

[0073] Zero-copy technology refers to a series of methods and strategies that aim to minimize or completely eliminate data copying operations when data is transmitted between different software layers or hardware components. By reducing the number of data copies, zero-copy technology can significantly improve system performance, reduce latency, and reduce CPU and memory bandwidth consumption, thereby improving the overall efficiency of the system. In the process of performing multi-scalar multiplication calculations in zero-knowledge proofs, efficient transmission of data between the CPU and GPU is a key factor in improving overall system performance. Traditionally, data transfer from CPU memory to GPU device memory requires explicit copy operations, which not only increases the burden on the CPU, but also causes significant latency and bandwidth consumption on large-scale data sets. In order to solve these problems, the present invention also introduces zero-copy technology on the premise of realizing a multi-batch asynchronous transmission mechanism.

[0074] Zero-copy technology is an asynchronous memory mapping method that maps fixed (non-pageable) host memory directly to GPU memory and implicitly transfers it to the GPU. This technology allows GPU threads to directly access host memory. When a GPU thread reads a variable mapped with the host, it will submit a PCIe read transaction, and the host will return the data through the PCIe bus. The core principle of zero-copy technology is to reduce or eliminate the number of times data is copied between different memory areas, especially during data transfer between the CPU and the GPU. In the traditional data transfer process, data usually needs to be copied from the host memory to the kernel buffer, and then from the kernel buffer to the GPU's device memory. This series of copy operations consumes a lot of CPU cycles and memory bandwidth. In contrast, zero-copy technology allows data to be transferred directly from host memory to GPU device memory without the intermediate copy step, thereby significantly reducing CPU intervention and data transfer latency.

[0075] In traditional CUDA programming, data must be explicitly copied from host memory to GPU device memory using APIs such as cudaMemcpy. This process not only adds additional latency, but also takes up CPU resources. In contrast, Figure 6As shown, the present invention implements the CUDA unified virtual address space (Unified VirtualAddressing, UVA) function in the CUDA environment to achieve a similar zero-copy effect. After the UVA function is implemented, the CPU and GPU share a unified virtual address space. This means that both the CPU and the GPU can use the same virtual address to access data without knowing which physical memory area (CPU memory or GPU memory) the data is actually stored in. UVA allows the GPU to directly access the host memory without explicitly copying the data to the GPU device memory. This simplifies data management and speeds up data transmission.

[0076] In summary, the present invention significantly improves the speed and efficiency of ZKP generation through the synergy of multiple technical points, while optimizing resource utilization, providing strong support for zero-knowledge proof technology in high-performance computing environments. Compared with the prior art, the advantages of the present invention are mainly reflected in the following aspects:

[0077] 1) The present invention introduces an innovative preprocessing mechanism, which builds an efficient computing framework by using the CPU to pre-execute key computing tasks, greatly shortens the time of ZKP generation, and is particularly outstanding when processing large-scale data sets. For example, by designing a shared pre-calculation table, effective use of computing resources is achieved, and by caching intermediate data of complex operations, repeated calculations are avoided. When processing large-scale data sets or high-complexity algorithms, computing time and energy consumption are reduced, especially in multi-scalar multiplication calculations. For another example, in view of the low cost of elliptic curve negation, a signed window technology is designed for multi-scalar multiplication operations. By extending the operands by signs, the number of point multiplications in actual operations is reduced, and the complexity of large number multiplication in elliptic curve cryptography is reduced. This signed sliding window technology reduces the number of point multiplications required for large number multiplication in elliptic curve cryptography by performing sign extension and optimizing operand processing, and directly accelerates the generation process of zero-knowledge proofs.

[0078] 2) The present invention provides a set of optimization solutions for the proof generation speed of the zero-knowledge proof system. It does not need to reconstruct the original proof generation logic, but focuses on optimizing the communication efficiency between heterogeneous computing platforms. By improving the data transmission mechanism between the CPU and the GPU, the generation delay is effectively reduced, and the system performance is greatly improved. For example, the transmission method between the systems is improved, and a faster and resource-saving data exchange process is achieved when processing and transmitting data through zero-copy transmission technology. This zero-copy transmission technology realizes the optimization in the data processing and transmission process, which not only greatly reduces the processing burden of the CPU, reduces the consumption of memory bandwidth, but also greatly shortens the delay of data transmission, thereby realizing the acceleration of data processing and the significant improvement of the overall system performance. For example, by improving the data transmission method between heterogeneous architectures and implementing a batch transmission strategy, the point set and scalar set are delivered to the GPU in a progressive manner, avoiding the idle waiting period of the GPU, ensuring the continuous use of GPU resources, and thus significantly improving the resource utilization and overall efficiency in the zero-knowledge proof generation process. This design not only significantly improves the utilization of the GPU, but also greatly optimizes the overall computing efficiency. Especially when processing large-scale data sets, this progressive delivery mechanism greatly reduces waiting time and promotes continuous and maximum utilization of resources, thus achieving a leap in system performance. This phased, decoupled data delivery strategy enables the CPU and GPU to work together instead of waiting alternately, thereby ensuring the continuous utilization of GPU resources.

[0079] 3) The present invention has been subjected to multiple simulation tests, and the experiments have proven that it can meet the expected design indicators. For example, by utilizing the parallel computing capability of the CPU, a series of key computing tasks are pre-executed, and a pre-calculation table is constructed, which enables the direct reference of these pre-calculated results when actually generating zero-knowledge proofs, avoiding repeated calculations and greatly reducing the time required to generate proofs.

[0080] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0081] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0082] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0083] The computer program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, Python, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present invention.

[0084] Various aspects of the present invention are described herein with reference to the flow charts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flow chart and / or block diagram and the combination of each box in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0085] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0086] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0087] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a part of a module, a program segment or an instruction, and a part of the module, a program segment or an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that it is equivalent to implement it by hardware, implement it by software, and implement it by combining software and hardware.

[0088] Embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present invention is defined by the appended claims.

Claims

1. A CPU-GPU data processing and transmission optimization system for zero-knowledge proof, used to perform multi-scalar multiplication operations based on elliptic curve cryptography to achieve the generation of zero-knowledge proof, the system includes a CPU and a GPU, wherein a data transmission channel is provided between the CPU and the GPU, the CPU is used to obtain and store point sets and scalar sets involved in the multi-scalar multiplication operations, and communicate with the GPU using a set parallelized data transmission mechanism, the GPU performs multi-scalar multiplication calculations based on the point sets and the scalar sets, and transmits the calculation results back to the CPU.

2. The system according to claim 1, characterized in that The GPU performs multi-scalar multiplication operations using a shared pre-computed table, which is used to store a series of multiple points of a base point G and store a scalar relationship between each point in the point set and the base point G, where the base point G is a generator for all points in the point set.

3. The system according to claim 1, characterized in that GPU implements multi-scalar multiplication based on the bucket algorithm, in which the scalar k is converted into a signed sliding window in the following way: Determine a window size c, which is used to limit the number of bits in each window; Represent the scalar k in binary form to form a binary string; Dividing the binary string into a plurality of windows according to the length of c bits to obtain a plurality of window values; Convert each window value into a decimal number to obtain a decimal window value; For each decimal window value v, if v>2 c-1 -1, then subtract 2 from v c , making it a signed number; If the value of the current window changes from positive to negative, the value of the next window is increased by 1 to maintain the equivalence of scalar multiplication.

4. The system according to claim 2, characterized in that The shared pre-computed table is set to be updated regularly according to the following steps: At the beginning of the calculation, a set amount of storage space is reserved in the shared pre-calculation table for storing the pre-calculated point set; When the calculation is running, for the point set to be solved, the shared pre-calculation table is searched to see whether there is a corresponding calculated result. If so, the result is obtained from the table. If not, the point set is recalculated and the calculation result is returned to the GPU. When a new point set result is generated, if the shared pre-calculated table still has enough remaining space, the newly generated point set result is inserted into the table. When the shared pre-calculated table has insufficient space, the storage content in the table is updated using the set update strategy.

5. The system according to claim 4, characterized in that The update strategy adopts the least recently used strategy to preferentially eliminate items that have not been used for the longest time.

6. The system according to claim 1, characterized in that The parallel data transmission mechanism is a batch transmission strategy based on point sets, including: The point set stored in the CPU is divided into several batches according to the performance of the GPU and transferred to the GPU in batches; After the GPU obtains the calculation results of each batch, it immediately returns the calculation results of the batch to the CPU and releases the memory space occupied by the elements that are no longer involved in the calculation.

7. The system according to claim 1, characterized in that When executing multi-scalar multiplication operations, the CPU and GPU share a unified virtual address space to achieve data transmission between the CPU and GPU through zero-copy technology.

8. The system according to claim 1, characterized in that In the shared pre-calculated table, a hash table is used to store the scalar value of the base point G, and for the points in the point set, only the x coordinate of the point is stored.

9. A CPU-GPU data processing and transmission optimization method for zero-knowledge proof, comprising the following steps: The point set and the scalar set involved in the multi-scalar multiplication operation are stored in the CPU, where the multi-scalar multiplication operation is a multi-scalar multiplication operation based on elliptic curve cryptography and is used to realize the generation of zero-knowledge proof; Data is transferred between the CPU and the GPU using a set parallel data transmission mechanism, so as to control the GPU to perform multi-scalar multiplication calculation based on the point set and the scalar set, and to return the calculation result to the CPU.

10. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the steps of the method according to claim 9 are implemented.

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