Optical module control system, server and server networking system

Abstract

The embodiment of the present application provides an optical module control system, a server and a server networking system, wherein the system includes: a switch, a management controller and a processor, the management controller includes a debugging interface, the switch is connected to the debugging interface, and the processor is connected to the switch; wherein the management controller is used to control the processor to connect to the detection link corresponding to the data port of the optical module connected to the processor in response to the identified switching request, and the switching request is triggered when the data port of the optical module connected to the processor changes. Through this application, the problem of low efficiency of the detection link of the data port on the optical module connected to the switching processor is solved, thereby achieving the effect of improving the efficiency of the detection link of the data port on the optical module connected to the switching processor.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of optical modules, and more specifically, to an optical module control system, a server, and a server networking system. Background Art

[0002] The data port of the optical module on the switch connected to the processor (e.g., OAM module) in the server may change. In the related art, when the data port on the optical module connected to the OAM changes, it is necessary to manually switch the low-speed link (or detection link) of the port on the optical module connected to the OAM, resulting in low efficiency.

[0003] With respect to the problem of low efficiency of the detection link of the data port on the optical module to which the switching processor is connected in the related art, no effective solution has been proposed. Summary of the invention

[0004] The embodiments of the present application provide an optical module control system, a server, and a server networking system to at least solve the problem of low efficiency of the detection link of the data port on the optical module to which the switching processor is connected in the related art.

[0005] According to one embodiment of the present application, an optical module control system is provided, comprising: a switch, a management controller and a processor, the management controller comprising a debugging interface, the switch being connected to the debugging interface, and the processor being connected to the switch; wherein the management controller is used to control the processor to connect to a detection link corresponding to a data port of an optical module to which the processor is connected in response to an identified switching request, and the switching request is triggered when a change occurs in the data port of the optical module to which the processor is connected.

[0006] In an exemplary embodiment, the switch includes a first switch and a second switch, the processor includes a first processor and a second processor, the first switch and the second switch are both connected to the debugging interface, the first processor and the second processor are both connected to the management controller, the first switch includes a first port, a second port and a third port, the second switch includes a fourth port, a fifth port and a sixth port, the second port is connected to the fifth port, the optical module includes: a first data port and its corresponding first detection link, a second data port and its corresponding second detection link, a third data port and its corresponding third detection link, and a fourth data port and its corresponding fourth detection link, the first port is used to connect the first detection link, the third port is used to connect the second detection link, the fourth port is used to connect the third detection link and the fourth detection link, the first port is used to connect the first processor, and the sixth port is used to connect the second processor.

[0007] In an exemplary embodiment, when the first switch includes a first gating device and the second switch includes a second gating device, the management controller is used to send a first control signal to the first gating device and the second gating device, wherein the first control signal is used to control the first processor to be connected to the detection link corresponding to the data port connected to the first processor, and to control the second processor to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow use of the detection link corresponding to the data port connected to the second processor.

[0008] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the management controller sends the first control signal of a low level to the first gating device and the second gating device; when the first processor is connected to the first data port, and the second processor is connected to the second data port, the management controller sends the first control signal of a high level to the first gating device and the second gating device.

[0009] In an exemplary embodiment, when the management controller sends the first control signal of a low level to the first gating device and the second gating device, the first port is connected to the third port, and the fourth port is connected to the sixth port; when the management controller sends the first control signal of a high level to the first gating device and the second gating device, the second port is connected to the third port, and the fifth port is connected to the sixth port.

[0010] In an exemplary embodiment, when the first port is connected to the third port and the fourth port is connected to the sixth port, the first processor is connected to the first detection link and the second detection link, and the second processor is connected to the third detection link and the fourth detection link; when the second port is connected to the third port and the fifth port is connected to the sixth port, the first processor is connected to the first detection link, and the second processor is connected to the second detection link.

[0011] In an exemplary embodiment, the optical module also includes a first detection unit corresponding to the first data port, a second detection unit corresponding to the second data port, a third detection unit corresponding to the third data port, and a fourth detection unit corresponding to the fourth data port, wherein the first detection link exists between the first detection unit and the first data port, the second detection link exists between the second detection unit and the second data port, the third detection link exists between the third detection unit and the third data port, and the fourth detection link exists between the fourth detection unit and the fourth data port; the first port is used to connect the first detection unit, the third port is used to connect the second detection unit, and the fourth port is used to connect the third detection unit and the fourth detection unit.

[0012] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first port is connected to the first processor, the first port is connected to the first detection unit, and the first port is connected to the third port, the third port is connected to the second detection unit, the sixth port is connected to the second processor, the sixth port is connected to the fourth port, and the fourth port is connected to the third detection unit and the fourth detection unit.

[0013] In an exemplary embodiment, when the first processor is connected to the first data port and the second processor is connected to the second data port, the first port is connected to the first processor, the first port is connected to the first detection unit, the second port is connected to the third port, the third port is connected to the second detection unit, the fifth port is connected to the second port, the fifth port is connected to the sixth port, and the sixth port is connected to the second processor.

[0014] In an exemplary embodiment, the first bus address of the first detection unit is the same as the third bus address of the third detection unit, the second bus address of the second detection unit is the same as the fourth bus address of the fourth detection unit, and the first bus address is different from the second bus address.

[0015] In an exemplary embodiment, the optical module control system also includes a first connector and a second connector, the first connection end of the first connector is used to connect the first detection link, the second connection end of the first connector is used to connect the second detection link, the third connection end of the first connector is also used to connect the first processor, the first connection end of the second connector is used to connect the second processor, and the second connection end of the second connector is used to connect the third detection link and the fourth detection link; wherein, the management controller is used to control the first processor to connect to the detection link corresponding to the data port connected to the first processor, and control the second processor to connect to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor.

[0016] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first connection end of the first connector is connected to the first detection link, the second connection end of the first connector is connected to the second detection link, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection link and the fourth detection link; when the first processor is connected to the first data port, and the second processor is connected to the third data port, the first connection end of the first connector is connected to the first detection link, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection link.

[0017] In an exemplary embodiment, the optical module also includes a first detection unit corresponding to the first data port, a second detection unit corresponding to the second data port, a third detection unit corresponding to the third data port, and a fourth detection unit corresponding to the fourth data port, wherein the first detection link exists between the first detection unit and the first data port, the second detection link exists between the second detection unit and the second data port, the third detection link exists between the third detection unit and the third data port, and the fourth detection link exists between the fourth detection unit and the fourth data port; wherein the first connection end of the first connector is used to connect the first detection unit, the second connection end of the first connector is used to connect the second detection unit, and the second connection end of the second connector is used to connect the third detection unit and the fourth detection unit.

[0018] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first connection end of the first connector is connected to the first detection unit, the second connection end of the first connector is connected to the second detection unit, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection unit and the fourth detection unit.

[0019] In an exemplary embodiment, when the first processor is connected to the first data port and the second processor is connected to the third data port, the first connection end of the first connector is connected to the first detection unit, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection unit.

[0020] In an exemplary embodiment, the optical module control system also includes a third gating device and a fourth gating device, the third gating device includes a seventh port, an eighth port and a ninth port, the fourth gating device includes a tenth port, an eleventh port and a twelfth port, the seventh port is used to connect to the first processor, the eighth port is connected to the management controller, the ninth port is connected to the first port, the tenth port is used to connect to the second processor, the eleventh port is connected to the management controller, and the twelfth port is connected to the sixth port; the management controller is used to control the detection link connection corresponding to the data port connected to the first object and the first processor, and control the detection link connection corresponding to the data port connected to the second object and the second processor, wherein the first object includes the first processor or the management controller, and the second object includes the second processor or the management controller.

[0021] In an exemplary embodiment, the management controller is used to send a second control signal to the third gating device and the fourth gating device, wherein the second control signal is used to control the first processor to be connected to the detection link corresponding to the data port connected to the first processor, and to control the second processor to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor. The second control signal is also used to control the management controller to be connected to the detection link corresponding to the data port connected to the first processor, and to control the management controller to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to not allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to not allow the use of the detection link corresponding to the data port connected to the second processor.

[0022] In an exemplary embodiment, when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor, and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor, the management controller sends a low-level second control signal to the third gating device and the fourth gating device; when the first processor is set to not allow the use of the detection link corresponding to the data port connected to the first processor, and the second processor is set to not allow the use of the detection link corresponding to the data port connected to the second processor, the management controller sends a high-level second control signal to the third gating device and the fourth gating device.

[0023] In an exemplary embodiment, when the management controller sends the second control signal of a low level to the third gating device and the fourth gating device, the seventh port is connected to the ninth port, and the tenth port is connected to the twelfth port; when the management controller sends the second control signal of a high level to the third gating device and the fourth gating device, the eighth port is connected to the ninth port, and the eleventh port is connected to the twelfth port.

[0024] In an exemplary embodiment, in the case where the first switch includes a first gating device, the second switch includes a second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, or in the case where the first switch includes a first gating device, the second switch includes a second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the management controller sends a signal to the first gating device. The management controller sends a low-level first control signal to the first gating device and the second gating device; when the first switch includes a first gating device, the second switch includes a second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port, or when the first switch includes a first gating device, the second switch includes a second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port, the management controller sends a high-level first control signal to the first gating device and the second gating device.

[0025] In an exemplary embodiment, the optical module control system further includes a first connector and a second connector, the ninth port is connected to the third connection end of the first connector, and the twelfth port is connected to the first connection end of the second connector.

[0026] According to another embodiment of the present application, a server is further provided, comprising the optical module control system as described in any one of the above embodiments.

[0027] According to another embodiment of the present application, a server networking system is also provided, including a plurality of the servers, wherein the servers are connected to each other via switches, and the servers are used to perform data exchange via the switches.

[0028] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0029] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0030] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0031] Through the present application, when the data port of the optical module connected to the processor changes, a switching request will be triggered, and the management controller will control the processor to connect to the detection link corresponding to the data port of the optical module connected to the processor according to the switching request. In this way, the problem of confusion or failure of the use right of the detection link of the data port that may be caused in different application scenarios when the data port on the optical module connected to the processor changes is avoided, and the connection of the detection link corresponding to the data port of the optical module connected to the processor after the processor is automatically switched is realized according to the requirements of different application scenarios, and the ownership of the detection link of the data port is automatically changed. Therefore, the problem of low efficiency of the detection link of the data port on the optical module connected to the switching processor can be solved, and the effect of improving the efficiency of the detection link of the data port on the optical module connected to the switching processor is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of an optional connection status of an optical module system according to an embodiment of the present application Figure 1 ;

[0033] Figure 2 Schematic diagram of an optional connection status of an optical module control system according to an embodiment of the present application Figure 2 ;

[0034] Figure 3 This is a schematic diagram of an optional OAM Scale-out application scenario according to an embodiment of the present application. Figure 1 ;

[0035] Figure 4 This is a schematic diagram of an optional OAM Scale-out application scenario according to an embodiment of the present application. Figure 2 ;

[0036] Figure 5 is a schematic diagram of an optional optical module control system according to an embodiment of the present application Figure 1 ;

[0037] Figure 6is a schematic diagram of an optional optical module control system according to an embodiment of the present application Figure 2 ;

[0038] Figure 7 This is a schematic diagram of an optional OAM Scale-out application scenario according to an embodiment of the present application. Figure 3 ;

[0039] Figure 8 is a schematic diagram of an optional optical module control system according to an embodiment of the present application Figure 3 ;

[0040] Fig. 9 is a logical schematic diagram of an optional OAM control optical module according to an embodiment of the present application;

[0041] Fig.10 is a logic diagram of an optional BMC controlling an optical module according to an embodiment of the present application;

[0042] Fig.11 This is a schematic diagram of an optional server transmitting data through a switch according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0045] First, the terms involved in the embodiments of the present application are explained as follows:

[0046] OAM: OCP (Open Compute Project) Accelerator Module, a card-type GPU (Graphics Processing Unit) module based on the OCP standard.

[0047] UBB: Universal Baseboard, a carrier board used to carry OAM modules. A single UBB can carry, but is not limited to, 8 OAM modules. The high-speed interconnect bus on the UBB board enables full interconnection between OAM acceleration cards.

[0048] QSFP56: Quad Small Form-factor Pluggable 56Gbps, a four-channel small pluggable 56Gbps (Gigabits per second) optical module. A single optical module can include but is not limited to 4 pairs of high-speed signals and can be used in 200G optical ports.

[0049] QSFP112: Quad Small Form-factor Pluggable 112Gbps, a four-channel small pluggable 112Gbps optical module. A single optical module can include but is not limited to 4 pairs of high-speed signals and can be used in 400G optical ports.

[0050] In this embodiment, an optical module control system is provided, including: a switch, a management controller and a processor, the management controller including a debugging interface, the switch connected to the debugging interface, and the processor connected to the switch; wherein the management controller is used to control the processor to connect to a detection link corresponding to a data port of an optical module to which the processor is connected in response to an identified switching request, and the switching request is triggered when a change occurs in the data port of the optical module to which the processor is connected.

[0051] Optionally, in this embodiment, Figure 1 is a schematic diagram of an optional connection status of an optical module system according to an embodiment of the present application Figure 1 ,like Figure 1 As shown, the optical module control system may include but is not limited to: a switch 101, a management controller 102 and a processor 103, the management controller 102 may include but is not limited to a debugging interface 102-1, the switch 101 is connected to the debugging interface 102-1, and the processor 103 is connected to the switch 101.

[0052] Optionally, in this embodiment, the switch may be, but is not limited to, used to switch the detection link of the data port connected to the processor when there is a change in the data port of the optical module connected to the processor. As an optional example, the switch may be, but is not limited to, including a MUX (Multiplexer) or other switches, and this application does not impose any restrictions on this.

[0053] Optionally, in this embodiment, the management controller may, but is not limited to, determine that a switching request is identified when a change occurs in a data port on an optical module connected to the processor, or the management controller may, but is not limited to, receive a switching request when a change occurs in a data port on an optical module connected to the processor. For example, the management controller may, but is not limited to, include a BMC (Baseboard Management Controller) or other controllers, and this application does not limit this.

[0054] Optionally, in this embodiment, the management controller may, but is not limited to, directly send commands to the switch through the debug interface to switch the detection link of the data port to which the processor is connected, thereby changing the processor's ownership of the low-speed management link (or detection link) of the data port of the optical module.

[0055] Optionally, in this embodiment, the optical module may be but is not limited to being deployed on a data transmission device (e.g., a switch), for example, the optical module may be but is not limited to including a QSFP56 optical module or a QSFP112 optical module, and the processor may be but is not limited to realizing data transmission through the optical module, for example, the processor may be but is not limited to including a GPU (Graphics Processing Unit) integrated in the OAM, an FPGA (Field Programmable Gate Array) or a CPU (Central Processing Unit), etc.

[0056] For example, if the processor includes OAM, OAM needs to be used with Ethernet switches to build a large interconnect topology. Ethernet switches can include but are not limited to multiple interface types such as 200G and 400G. The same OAM may need to adapt to switches with two interface types. In this case, there will be a need to detect the automatic switching of the link.

[0057] Optionally, in this embodiment, there may be, but is not limited to, a data link (or high-speed link) and a detection link (or low-speed link) between the processor and the data port on the connected optical module, wherein the processor transmits actual business data of the processor to the connected data port via the data link.

[0058] Optionally, in this embodiment, the detection link can be used but is not limited to monitoring the operating status of the data port to which the processor is connected. For example, the detection link can be used but is not limited to detecting the operating parameters of the data port, and detecting the operating status of the data port based on the detected operating parameters of the data port, wherein the operating parameters can include but are not limited to whether the data port is in place, the temperature of the data port, the rate at which the data port transmits data, etc. The operating status can be used but is not limited to indicating the operating status of the data port, for example, whether the operation of the data port is abnormal.

[0059] Optionally, in this embodiment, the change in the data port of the optical module to which the processor is connected may include but is not limited to: the optical module to which the processor is connected has changed, for example, the processor switches from being connected to the data port on optical module 1 to being connected to the data port on optical module 2, or, the optical module to which the processor is connected has not changed, but the data port on the connected optical module has changed, for example, the processor switches from being connected to data port 1 on optical module 1 to being connected to data port 2 on optical module 1.

[0060] Through the above system, when the data port of the optical module connected to the processor changes, a switching request will be triggered, and the management controller will control the processor to connect to the detection link corresponding to the data port of the optical module connected to the processor according to the switching request. In this way, the problem of confusion or failure of the use right of the detection link of the data port that may be caused when the data port on the optical module connected to the processor changes in different application scenarios is avoided, and the connection of the detection link corresponding to the data port of the optical module connected to the processor after the processor is automatically switched is realized according to the requirements of different application scenarios, and the ownership of the detection link of the data port is automatically changed. Therefore, the problem of low efficiency of the detection link of the data port on the optical module connected to the switching processor can be solved, and the effect of improving the efficiency of the detection link of the data port on the optical module connected to the switching processor is achieved.

[0061] In an exemplary embodiment, the switch includes a first switch and a second switch, the processor includes a first processor and a second processor, the first switch and the second switch are both connected to the debugging interface, the first processor and the second processor are both connected to the management controller, the first switch includes a first port, a second port and a third port, the second switch includes a fourth port, a fifth port and a sixth port, the second port is connected to the fifth port, the optical module includes: a first data port and its corresponding first detection link, a second data port and its corresponding second detection link, a third data port and its corresponding third detection link, and a fourth data port and its corresponding fourth detection link, the first port is used to connect the first detection link, the third port is used to connect the second detection link, the fourth port is used to connect the third detection link and the fourth detection link, the first port is used to connect the first processor, and the sixth port is used to connect the second processor.

[0062] Optionally, in this embodiment, when the switch includes a first switch and a second switch, and the processor includes a first processor and a second processor, the management controller may, but is not limited to, send commands to the first switch and the second switch through the debugging interface to adjust the usage rights of the detection links of the data ports corresponding to the first processor and the second processor.

[0063] Optionally, in this embodiment, Figure 2 Schematic diagram of an optional connection status of an optical module control system according to an embodiment of the present application Figure 2 ,like Figure 2As shown, it can be but not limited to taking the first switch including MUX0, the second switch including MUX1, the first processor including OAM0, the second processor including OAM1, the management controller including BMC, and the data port of the optical module including QSFP112 port as an example, MUX0 and MUX1 are both connected to the BMC debugging interface, MUX0 includes port A (equivalent to the first port), port B (equivalent to the second port) and port C (equivalent to the third port), MUX1 includes port A (equivalent to the fourth port), port B (equivalent to the fifth port) and port C (equivalent to the sixth port), port B in MUX0 is connected to port B in MUX1, and the optical module includes: QSFP-112 PORT0 (equivalent to the first data port) and its corresponding first detection link (equivalent to the link connecting MUX0 and QSFP-112 PORT0), QSFP-112 PORT1 (equivalent to the second data port) and its corresponding second detection link (equivalent to the link connecting MUX0 and QSFP-112 PORT1), QSFP-112 PORT2 (equivalent to the third data port) and its corresponding third detection link (equivalent to the link connecting MUX1 and QSFP-112 PORT2) and QSFP-112 PORT3 (equivalent to the fourth data port) and its corresponding fourth detection link (equivalent to the link connecting MUX1 and QSFP-112 PORT3), port A in MUX0 is used to connect the first detection link, port C in MUX0 is used to connect the second detection link, port A in MUX1 is used to connect the third detection link and the fourth detection link, port A in MUX0 is used to connect OAM0, and port C in MUX0 is used to connect OAM1.

[0064] In an exemplary embodiment, when the first switch includes a first gating device and the second switch includes a second gating device, the management controller is used to send a first control signal to the first gating device and the second gating device, wherein the first control signal is used to control the first processor to be connected to the detection link corresponding to the data port connected to the first processor, and to control the second processor to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow use of the detection link corresponding to the data port connected to the second processor.

[0065] Optionally, in this embodiment, the processor may, but is not limited to, have the function of using the detection link of the data port on the connected optical module, for example, the processor is configured to allow the operating status of the data port to be detected through the detection link of the connected data port, or the processor may, but is not limited to, not have the function of using the detection link of the data port on the connected optical module, for example, the processor is configured to not allow the operating status of the data port to be detected through the detection link of the connected data port.

[0066] Through the embodiments of the present application, a first control signal is sent to a first selection device and a second selection device by a management controller, thereby solving the problem of manually switching the use rights of the first processor and the second processor over the detection link, and automatically switching the detection link connected to the processor when a data port on an optical module connected to the processor changes, thereby improving the efficiency of switching the detection link of the optical module.

[0067] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the management controller sends the first control signal of a low level to the first gating device and the second gating device; when the first processor is connected to the first data port, and the second processor is connected to the second data port, the management controller sends the first control signal of a high level to the first gating device and the second gating device.

[0068] Optionally, in this embodiment, the low level and the high level can be but are not limited to being used to indicate logic levels. For example, the low level can be but are not limited to being used to indicate that the voltage is less than a first voltage threshold, and the high level can be but are not limited to being used to indicate that the voltage is greater than or equal to a second voltage threshold. The first voltage threshold and the second voltage threshold can be but are not limited to being the same or different. The low level and the high level can be but are not limited to being represented by corresponding identifiers. For example, the high level can be represented by identifier 1, and the low level can be represented by identifier 0.

[0069] Optionally, in this embodiment, Figure 3 This is a schematic diagram of an optional OAM Scale-out application scenario according to an embodiment of the present application. Figure 1 ,like Figure 3As shown, it can be but not limited to take the first processor including OAM0 and the second processor including OAM1 as an example, OAM0 and OAM1 respectively have x8 (8) 56Gbps Serdes channels (Lane 0 to Lane 7) for high-speed data transmission, and these Serdes channels are connected to the data port of the external device (for example, switch) through the PHY Retimer (Physical Layer Retimer) chip. Since QSFP112 is backward compatible with QSFP56, Figure 3 The QSFP112 connector is used, and the PHY Retimer is also compatible with 56G and 112G transmission rates. When the Serdes (Serializer / Deserializer) on the OAM0 and OAM1 sides is 56G and the Serdes on the switch side is 56G, the 8 56Gbps Serdes channels from a single OAM, through the retiming function of the PHY Retimer, just match the two QSFP112 optical modules, each module processes 4*56Gbps signals, thereby establishing a high-speed data link with the switch side. Specifically, the 4 pairs of 56Gbps signals from Lane 0 to Lane 3 in OAM0 are transmitted to QSFP-112 PORT0, and the 4 pairs of 56Gbps signals from Lane 4 to Lane 7 in OAM0 are transmitted to QSFP-112 PORT1; the 4 pairs of 56Gbps signals from Lane 0 to Lane 3 in OAM1 are transmitted to QSFP-112 PORT2, and the 4 pairs of 56Gbps signals from Lane 4 to Lane 7 in OAM1 are transmitted to QSFP-112 PORT3. In this application scenario, OAM0 is connected to QSFP-112 PORT0 (equivalent to the first data port) and QSFP-112 PORT1 (equivalent to the second data port), and OAM1 is connected to QSFP-112 PORT2 (equivalent to the third data port) and QSFP-112 PORT3 (equivalent to the fourth data port).

[0070] Optionally, in this embodiment, Figure 4 This is a schematic diagram of an optional OAM Scale-out application scenario according to an embodiment of the present application. Figure 2 ,like Figure 4As shown, it can be but not limited to taking the first processor including OAM0 and the second processor including OAM1 as an example, OAM0 and OAM1 are respectively equipped with x8 (8) 56Gbps Serdes channels (Lane 0 to Lane 7) for high-speed data transmission, and these Serdes channels are connected to the data port of the external device (for example, the switch) through the PHY Retimer chip. When the Serdes on the OAM0 and OAM1 sides are 56G and the Serdes on the switch side is 112G, the x8 56G Serdes from a single OAM matches 1 QSFP112 optical module, and each module processes 4*112Gbps signals, thereby establishing a high-speed data link with the switch side. Specifically, the 8 pairs of 56Gbps signals in Lane 0 to Lane 7 in OAM0 are correspondingly transmitted to QSFP-112 PORT0, and the 8 pairs of 56Gbps signals in Lane 0 to Lane 7 in OAM1 are correspondingly transmitted to QSFP-112 PORT1. At this time, QSFP-112PORT2 (equivalent to the third data port) and QSFP-112 PORT3 (equivalent to the fourth data port) are in idle state. In this application scenario, OAM0 is connected to QSFP-112 PORT0 (equivalent to the first data port), and OAM1 is connected to QSFP-112PORT1 (equivalent to the second data port).

[0071] Optionally, in this embodiment, Table 1 is compatible Figure 3 and Figure 4 The switch logic control relationship table of the application scenario can be but not limited to taking the first gating device including MUX0, the second gating device including MUX1, the first processor including OAM0, the second processor including OAM1, and the management controller including BMC as an example. As shown in Table 1, when QSFP_CTRL_SEL (equivalent to the first control signal) is at a low level, the A port (equivalent to the first port) in MUX0 is connected to the C port (equivalent to the third port), and the C port (equivalent to the sixth port) in MUX1 is connected to the A port (equivalent to the fourth port). In this case, OAM0 is connected to QSFP-112 PORT0 (equivalent to the first data port) and QSFP-112 PORT1 (equivalent to the second data port), and OAM1 is connected to QSFP-112 PORT2 (equivalent to the third data port) and QSFP-112 PORT3 (equivalent to the fourth data port) is connected; when QSFP_CTRL_SEL is high, port B in MUX0 (equivalent to the second port) is connected to port C, and port B in MUX1 (equivalent to the fifth port) is connected to port A. In this case, OAM0 is connected to QSFP-112 PORT0, and OAM1 is connected to QSFP-112 PORT1.

[0072] Table 1

[0073]

[0074] In an exemplary embodiment, when the management controller sends the first control signal of a low level to the first gating device and the second gating device, the first port is connected to the third port, and the fourth port is connected to the sixth port; when the management controller sends the first control signal of a high level to the first gating device and the second gating device, the second port is connected to the third port, and the fifth port is connected to the sixth port.

[0075] Optionally, in this embodiment, it is possible but not limited to that when the management controller switches from sending a low-level first control signal to the first gating device and the second gating device to sending a high-level first control signal to the first gating device and the second gating device, the first port of the first gating device is connected to the third port, and the fourth port of the second gating device is connected to the sixth port, and the second port of the first gating device is connected to the third port, and the fifth port of the second gating device is connected to the sixth port; it is possible but not limited to that when the management controller switches from sending a high-level first control signal to the first gating device and the second gating device to sending a low-level first control signal to the first gating device and the second gating device, the second port of the first gating device is connected to the third port, and the fifth port of the second gating device is connected to the sixth port, and the first port of the first gating device is connected to the third port, and the fourth port of the second gating device is connected to the sixth port.

[0076] In an exemplary embodiment, when the first port is connected to the third port and the fourth port is connected to the sixth port, the first processor is connected to the first detection link and the second detection link, and the second processor is connected to the third detection link and the fourth detection link; when the second port is connected to the third port and the fifth port is connected to the sixth port, the first processor is connected to the first detection link, and the second processor is connected to the second detection link.

[0077] Optionally, in this embodiment, the detection link of the data port on the optical module can be, but is not limited to, set to allow connection with a processor of the data link of the data port. It can be understood that a processor that does not use the data link of the data port cannot connect to the data link corresponding to the data port.

[0078] In an exemplary embodiment, the optical module also includes a first detection unit corresponding to the first data port, a second detection unit corresponding to the second data port, a third detection unit corresponding to the third data port, and a fourth detection unit corresponding to the fourth data port, wherein the first detection link exists between the first detection unit and the first data port, the second detection link exists between the second detection unit and the second data port, the third detection link exists between the third detection unit and the third data port, and the fourth detection link exists between the fourth detection unit and the fourth data port; the first port is used to connect the first detection unit, the third port is used to connect the second detection unit, and the fourth port is used to connect the third detection unit and the fourth detection unit.

[0079] Optionally, in this embodiment, the data port on the optical module may have, but is not limited to, a one-to-one corresponding detection unit, and the processor may detect, but is not limited to, the operating state of the data port to which the processor is connected through the detection unit to achieve management and configuration of the connected data port. The detection unit may be, but is not limited to, connected to the corresponding data port on the optical module, and there may be, but is not limited to, a group of detection links between each detection unit and the corresponding data port. For example, taking the detection unit as an example, which may include, but is not limited to, IO EXP 0, the corresponding data port may include, but is not limited to, QSFP-112 PORT 0. In this case, the detection link between IO EXP 0 and QSFP-112 PORT 0 may include, but is not limited to, QSFP0_RESET_N link, QSFP0_INT_N link, QSFP0_MODSEL_N link, QSFP0_MODPRSNT_N link, QSFP0_LPMODE link, QSFP0_RED_LED link, QSFP0_GREEN_LED link, and QSFP0_9511_READY link.

[0080] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first port is connected to the first processor, the first port is connected to the first detection unit, and the first port is connected to the third port, the third port is connected to the second detection unit, the sixth port is connected to the second processor, the sixth port is connected to the fourth port, and the fourth port is connected to the third detection unit and the fourth detection unit.

[0081] In an exemplary embodiment, when the first processor is connected to the first data port and the second processor is connected to the second data port, the first port is connected to the first processor, the first port is connected to the first detection unit, the second port is connected to the third port, the third port is connected to the second detection unit, the fifth port is connected to the second port, the fifth port is connected to the sixth port, and the sixth port is connected to the second processor.

[0082] Through the embodiment of the present application, the processor adjusts the control right of the detection link of the optical module by controlling the gating state of the gating device, thereby improving the flexibility and response speed of the optical module control system. In the scenario where the control strategy needs to be switched quickly, this design can quickly adjust the control path of the optical module to ensure the stability of signal transmission.

[0083] In an exemplary embodiment, the first bus address of the first detection unit is the same as the third bus address of the third detection unit, the second bus address of the second detection unit is the same as the fourth bus address of the fourth detection unit, and the first bus address is different from the second bus address.

[0084] Optionally, in this embodiment, the bus address may include but is not limited to an address that complies with the bus protocol, and different detection units may include but are not limited to having a corresponding bus address. As an optional example, the bus protocol may include but is not limited to I2C (Inter-Integrated Circuit, two-wire serial bus) protocol, PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) protocol, etc.

[0085] For example, taking the example that the bus protocol includes the I2C protocol, the first detection unit includes IO EXP 0, the second detection unit includes IO EXP 1, the third detection unit includes IO EXP 2, and the fourth detection unit includes IO EXP 3, the bus address of the detection unit IOEXP 0 may be but is not limited to 0100_000X, the bus address of the detection unit IO EXP 1 may be but is not limited to 0100_001X, the bus address of the detection unit IO EXP 2 may be but is not limited to 0100_000X, and the bus address of the detection unit IO EXP3 may be but is not limited to 0100_001X.

[0086] Through the embodiment of the present application, the I2C addresses (equivalent to the bus address) of IO EXP 0 (equivalent to the first detection unit) and IO EXP 1 (equivalent to the second detection unit) should be different, avoiding Figure 2 The I2C address conflict problem in the application scenario is improved, and the stability and accuracy of signal transmission are improved; the I2C addresses of IO EXP 0 and IO EXP 2 (equivalent to the third detection unit) should be the same, and the I2C addresses of IO EXP 1 and IO EXP 3 (equivalent to the fourth detection unit) should be the same, which means that different processors can reuse the same part of the management code to facilitate firmware development in various scenarios, thereby improving the consistency and universality of the firmware code of the management end (for example, OAM or BMC).

[0087] In order to better understand the application scenarios and working principles of the optical module control system in the embodiment of the present application, the application scenarios and working principles of the optical module control system in the embodiment of the present application are explained and illustrated in combination with optional embodiments below, which can be applicable to but not limited to the embodiments of the present application.

[0088] Figure 5 is a schematic diagram of an optional optical module control system according to an embodiment of the present application Figure 1 ,like Figure 5 As shown, suitable for Figure 3 Optical module control system in application scenarios, Figure 6 is a schematic diagram of an optional optical module control system according to an embodiment of the present application Figure 2 ,like Figure 6 As shown, suitable for Figure 4 The optical module control system in the application scenario may be, but is not limited to, the first gating device includes MUX0, the second gating device includes MUX1, the first processor includes OAM0, the second processor includes OAM1, the management controller includes BMC, the data port of the optical module includes QSFP112 data port, the first detection unit includes IOEXP 0, the second detection unit includes IO EXP 1, the third detection unit includes IO EXP 2, and the fourth detection unit includes IOEXP 3 as an example.

[0089] like Figure 5 and Figure 6 As shown in the figure, the PHY Card is connected to the UBB board through the relevant high-speed / low-speed connector. For the control of QSFP, the main interaction signals between the two boards are as follows: MUX_A_I2C, MUX_B_I2C, QSFP_CTRL_SEL. MUX_A_I2C and MUX_B_I2C are the I2C signals of OAM0 and OAM1 after switching with BMC.

[0090] The QSFP_CTRL_SEL signal (equivalent to the first control signal) is a control signal issued by the BMC to control the selection of MUX0 and MUX1 in the PHY card. The BMC debug interface directly issues commands to change the state of the QSFP_CTRL_SEL signal, thereby changing the ownership of the low-speed management link (equivalent to the detection link) of the QSFP module by OAM.

[0091] In the design of PHY card, it can be divided into two units based on functional emphasis: one is the logic switching unit composed of MUX0 and MUX1; the other is the function execution unit composed of IO_EXP (equivalent to the detection unit), I2C isolation unit, QSFP-112, LED, etc. (there are four groups of execution units, each corresponding to the function control of a QSFP112).

[0092] The logic switching unit composed of MUX0 and MUX1 is the core unit of the embodiment of the present application, and its combination realizes Figure 3 and Figure 4 The logic of the application scenario is compatible. During the design, MUX0 is placed in a 2-to-1 forward direction, and MUX1 is placed in a 1-to-2 reverse direction. The B port of MUX0 needs to be interconnected with the B port of MUX1.

[0093] It should be noted that the MUX in the embodiment of the present application refers to the function rather than limiting the specific selection. Currently, there are many types of MUXs in the market, such as Figure 5 and Figure 6 The two-to-one type MUX shown in the figure can also realize the function of a gating device like a four-to-two multi-channel model, and this application does not impose any limitation on this.

[0094] The function execution unit is composed of IO_EXP, I2C isolation unit, QSFP-112, LED (Light Emitting Diode), etc. Each IO_EXP needs to be interconnected with QSFP for signal, and finally realizes QSFP identification and information reading, reset, hot plug control, link status indication and other functions. In the design, IO EXP 0 and QSFP-112PORT0 are mounted before the A port of MUX0, IO EXP 1 and QSFP-112 PORT1 are mounted after the C port of MUX0, and IO EXP 2, IO EXP 3, QSFP-112 PORT2, QSFP-112 PORT3 are mounted after the A port of MUX1 to avoid the address conflict of each I2C device after MUX switching.

[0095] exist Figure 5In the case where the BMC sends a low-level first control signal to MUX0 and MUX1, port A in MUX0 is connected to OAM0, port A in MUX0 is connected to IO EXP 0, port A in MUX0 is connected to port C in MUX0, port C in MUX0 is connected to IO EXP 1, port C in MUX1 is connected to OAM1, port C in MUX1 is connected to port A in MUX1, and port A in MUX1 is connected to IO EXP 2 and IO EXP 3, and port B in MUX0 is connected to port B in MUX1, OAM0 is connected to IO EXP 0 through MUX0, IO EXP 0 is connected to QSFP-112 PORT0 through the first detection link (equivalent to the link connecting IO EXP0 and QSFP-112 PORT0); OAM0 is connected to IO EXP 1 through MUX0, and IOEXP 1 is connected to IO EXP 2 and IO EXP 3 through the second detection link (equivalent to the link connecting IO EXP 1 and QSFP-112 PORT1 link) and QSFP-112PORT1; OAM1 is connected to IO EXP 2 through MUX1, and IO EXP 2 is connected to QSFP-112 PORT2 through the third detection link (equivalent to the link connecting IOEXP 2 and QSFP-112 PORT2); OAM1 is connected to IO EXP 3 through MUX1, and IO EXP 3 is connected to QSFP-112PORT3 through the fourth detection link (equivalent to the link connecting IO EXP 3 and QSFP-112 PORT3), which is suitable for Figure 3 The application scenario is that OAM0 is connected to QSFP-112 PORT0 and QSFP-112 PORT1, and OAM1 is connected to QSFP-112 PORT2 and QSFP-112 PORT3.

[0096] exist Figure 6In the case where the BMC sends a high-level first control signal to MUX0 and MUX1, port A in MUX0 is connected to OAM0, port A in MUX0 is connected to IO EXP 0, port B in MUX0 is connected to port C in MUX0, port C in MUX0 is connected to IO EXP 1, port B in MUX1 is connected to port B in MUX0, port B in MUX1 is connected to port C in MUX1, and port C in MUX1 is connected to OAM1. OAM0 is connected to IO EXP 0 through MUX0, and IO EXP 0 is connected to QSFP-112 PORT0 through the first detection link (equivalent to the link connecting IO EXP 0 and QSFP-112 PORT0); OAM1 is connected to IO EXP 1 through MUX1, and IO EXP 1 is connected to QSFP-112 PORT1 through the second detection link (equivalent to the link connecting IO EXP 1 and QSFP-112 PORT1). Adapted to Figure 4 The application scenario is that OAM0 is connected to QSFP-112 PORT0, and OAM1 is connected to QSFP-112 PORT1.

[0097] In an exemplary embodiment, the optical module control system also includes a first connector and a second connector, the first connection end of the first connector is used to connect the first detection link, the second connection end of the first connector is used to connect the second detection link, the third connection end of the first connector is also used to connect the first processor, the first connection end of the second connector is used to connect the second processor, and the second connection end of the second connector is used to connect the third detection link and the fourth detection link; wherein, the management controller is used to control the first processor to connect to the detection link corresponding to the data port connected to the first processor, and control the second processor to connect to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor.

[0098] Optionally, in this embodiment, the connector may be, but is not limited to, a detection link for connecting the processor and a data port on an optical module to which the processor is connected. As an optional example, the connector may be, but is not limited to, include a bypass resistor.

[0099] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first connection end of the first connector is connected to the first detection link, the second connection end of the first connector is connected to the second detection link, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second processor is connected to the third detection link and the fourth detection link; when the first processor is connected to the first data port, and the second processor is connected to the third data port, the first connection end of the first connector is connected to the first detection link, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection link.

[0100] Optionally, in this embodiment, the data port to which the first processor and the second processor are connected may change. Figure 7 This is a schematic diagram of an optional OAM Scale-out application scenario according to an embodiment of the present application. Figure 3 ,like Figure 7 As shown, it can be but not limited to taking the first processor including OAM0 and the second processor including OAM1 as an example, OAM0 and OAM1 are respectively equipped with x8 (8) 56Gbps Serdes channels (Lane 0 to Lane 7) for high-speed data transmission, and these Serdes channels are connected to the data port of the external device (for example, the switch) through the PHY Retimer chip. When the Serdes on the OAM0 and OAM1 sides are 56G and the Serdes on the switch side is 112G, the x8 56G Serdes channel from a single OAM module matches 1 QSFP112 optical module, and each module processes 4*112Gbps signals, thereby establishing a high-speed data link with the switch side. Specifically, the 8 pairs of 56Gbps signals in Lane 0 to Lane 7 of OAM0 are correspondingly transmitted to QSFP-112 PORT0, and the 8 pairs of 56Gbps signals in Lane 0 to Lane 7 of OAM1 are correspondingly transmitted to QSFP-112 PORT2. At this time, QSFP-112 PORT1 (equivalent to the second data port) and QSFP-112 PORT3 (equivalent to the fourth data port) are in idle state. In this application scenario, OAM0 is connected to QSFP-112 PORT0 (equivalent to the first data port), and OAM1 is connected to QSFP-112 PORT2 (equivalent to the third data port).

[0101] In an exemplary embodiment, the optical module also includes a first detection unit corresponding to the first data port, a second detection unit corresponding to the second data port, a third detection unit corresponding to the third data port, and a fourth detection unit corresponding to the fourth data port, wherein the first detection link exists between the first detection unit and the first data port, the second detection link exists between the second detection unit and the second data port, the third detection link exists between the third detection unit and the third data port, and the fourth detection link exists between the fourth detection unit and the fourth data port; wherein the first connection end of the first connector is used to connect the first detection unit, the second connection end of the first connector is used to connect the second detection unit, and the second connection end of the second connector is used to connect the third detection unit and the fourth detection unit.

[0102] Optionally, in this embodiment, the data port on the optical module may have, but is not limited to, a one-to-one corresponding detection unit, and the processor may detect, but is not limited to, the operating state of the data port to which the processor is connected through the detection unit to achieve management and configuration of the connected data port. The detection unit may be, but is not limited to, connected to the corresponding data port on the optical module, and there may be, but is not limited to, a group of detection links between each detection unit and the corresponding data port. For example, taking the detection unit as an example, which may include, but is not limited to, IO EXP 1, the corresponding data port may include, but is not limited to, QSFP-112PORT 1. In this case, the detection link between IO EXP 1 and QSFP-112 PORT 1 may include, but is not limited to, QSFP1_RESET_N link, QSFP1_INT_N link, QSFP1_MODSEL_N link, QSFP1_MODPRSNT_N link, QSFP1_LPMODE link, QSFP1_RED_LED link, QSFP1_GREEN_LED link, and QSFP1_9511_READY link.

[0103] In an exemplary embodiment, when the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first connection end of the first connector is connected to the first detection unit, the second connection end of the first connector is connected to the second detection unit, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection unit and the fourth detection unit.

[0104] Optionally, in this embodiment, Figure 8 is a schematic diagram of an optional optical module control system according to an embodiment of the present application Figure 3 ,like Figure 8 As shown, it can be but not limited to taking the first connector including the bypass resistor R1, the second connector including the bypass resistor R2, the first processor including OAM0, the second processor including OAM1, the management controller including BMC, and the data port of the optical module including the QSFP112 data port as an example.

[0105] The first connection end of the bypass resistor R1 is connected to IO EXP 0 (equivalent to the first detection unit), and IO EXP 0 is connected to QSFP-112 PORT 0 through the first detection link (equivalent to the link connecting IO EXP 0 and QSFP-112 PORT0); the second connection end of the bypass resistor R1 is connected to IO EXP 1 (equivalent to the second detection unit), and IO EXP 1 is connected to QSFP-112 PORT 1 through the second detection link (equivalent to the link connecting IO EXP 1 and QSFP-112 PORT1); the third connection end of the bypass resistor R1 is connected to OAM0; the first connection end of the bypass resistor R2 is connected to OAM1, and the second connection end of the bypass resistor R2 is connected to IO EXP 2 (equivalent to the third detection unit) and IO EXP 3 (equivalent to the fourth detection unit), IO EXP 2 is connected to QSFP-112 PORT 2 through the third detection link (equivalent to the link connecting IO EXP 2 and QSFP-112 PORT2), and IO EXP 3 is connected to QSFP-112 PORT 3 through the fourth detection link (equivalent to the link connecting IO EXP 3 and QSFP-112PORT3).

[0106] like Figure 8 The optical module system shown is compatible with Figure 3 and Figure 7 The application scenario shown is similar to Figure 5 and Figure 6 The difference of the optical module system shown is the use of bypass resistors R1 and R2. In this optical module system, the logic switching unit composed of MUX0 and MUX1 needs to be processed without being installed, and bypass resistors R1 and R2 need to be installed. When R1 is installed and MUX0 is not installed, IO EXP 0, QSFP-112 PORT0 and IO EXP 1, QSFP-112 PORT1 are now mounted to OAM0, and IO EXP 2, QSFP-112 PORT2, IO EXP 3, QSFP-112 PORT3 are mounted to OAM1.

[0107] At this time, for Figure 3 In the application scenario shown, that is, when OAM0 is connected to QSFP-112 PORT0 and QSFP-112 PORT1, and OAM1 is connected to QSFP-112 PORT2 and QSFP-112 PORT3, OAM0 can directly control IO EXP 0 and IOEXP 1, and OAM1 can directly control IO EXP 2 and IO EXP 3.

[0108] In an exemplary embodiment, when the first processor is connected to the first data port and the second processor is connected to the third data port, the first connection end of the first connector is connected to the first detection unit, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection unit.

[0109] Optionally, in this embodiment, if Figure 8 As shown, it can be but not limited to taking the first connector including the bypass resistor R1, the second connector including the bypass resistor R2, the first processor including OAM0, the second processor including OAM1, the management controller including the BMC, and the data port of the optical module including the QSFP112 data port as an example.

[0110] A first connection end of the bypass resistor R1 is connected to IO EXP 0 (equivalent to the first detection unit), a third connection end of the bypass resistor R1 is connected to OAM0, IO EXP 0 is connected to QSFP-112 PORT 0 through a first detection link (equivalent to a link connecting IO EXP 0 and QSFP-112 PORT0); a first connection end of the bypass resistor R2 is connected to OAM1, a second connection end of the bypass resistor R2 is connected to IO EXP 2 (equivalent to the third detection unit), IO EXP 2 is connected to QSFP-112 PORT 2 through a third detection link (equivalent to a link connecting IO EXP 2 and QSFP-112 PORT2).

[0111] for Figure 7In the application scenario shown, when OAM0 is connected to QSFP-112 PORT0 and OAM1 is connected to QSFP-112PORT2, OAM0 only controls IO EXP 0 and OAM1 only controls IO EXP 2. At this time, QSFP-112PORT1 and QSFP-112 PORT3 are unconnected, and whether they are unconnected or not does not affect the structure of the optical module control system. Since the I2C addresses of IO EXP 0 and IO EXP 2 are the same, and the I2C addresses of IO EXP 1 and IO EXP 3 are the same, different OAMs can reuse this part of the management code, which greatly simplifies the code complexity.

[0112] In an exemplary embodiment, the optical module control system also includes a third gating device and a fourth gating device, the third gating device includes a seventh port, an eighth port and a ninth port, the fourth gating device includes a tenth port, an eleventh port and a twelfth port, the seventh port is used to connect to the first processor, the eighth port is connected to the management controller, the ninth port is connected to the first port, the tenth port is used to connect to the second processor, the eleventh port is connected to the management controller, and the twelfth port is connected to the sixth port; the management controller is used to control the detection link connection corresponding to the data port connected to the first object and the first processor, and control the detection link connection corresponding to the data port connected to the second object and the second processor, wherein the first object includes the first processor or the management controller, and the second object includes the second processor or the management controller.

[0113] Optionally, in this embodiment, the first object may include but is not limited to a first processor or a management controller. When the first processor is set to allow the use of the detection link of the data port on the optical module to which the first processor is connected, the first object is the first processor. When the first processor is set not to allow the use of the detection link of the data port on the optical module to which it is connected, the first object is the management controller. The second object may include but is not limited to a second processor or a management controller. When the second processor is set to allow the use of the detection link of the data port on the connected optical module, the second object is the second processor. When the second processor is set not to allow the use of the detection link of the data port on the connected optical module, the second object is the management controller.

[0114] In an exemplary embodiment, the management controller is used to send a second control signal to the third gating device and the fourth gating device, wherein the second control signal is used to control the first processor to be connected to the detection link corresponding to the data port connected to the first processor, and to control the second processor to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor. The second control signal is also used to control the management controller to be connected to the detection link corresponding to the data port connected to the first processor, and to control the management controller to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to not allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to not allow the use of the detection link corresponding to the data port connected to the second processor.

[0115] Optionally, in this embodiment, in the initialization configuration, the processor can be, but is not limited to, set by default to allow the use of the detection link corresponding to the data port connected to the processor. Before the machine is assembled, the switching setting is directly completed by means of a hardware switch based on the detection result of whether the processor allows the use of the detection link corresponding to the data port connected to the processor. For example, when it is detected that the processor does not allow the use of the detection link corresponding to the data port connected to the processor, the connection between the processor and the detection link corresponding to the data port connected to the processor is switched to the connection between the management controller and the detection link corresponding to the data port connected to the processor.

[0116] Optionally, in this embodiment, it can be but not limited to the example that the third gating device includes MUX_A, the fourth gating device includes MUX_B, the first processor includes OAM0, the second processor includes OAM1, and the management controller includes BMC. MUX_A and MUX_B are designed on the UBB board to meet the requirements that some OAMs that do not support direct control of optical modules and low-speed links (equivalent to detection links) will be managed by BMC. The OAM / BMC_CTRL_SEL signal (equivalent to the second control signal) is used to control MUX_A and MUX_B, which is issued by BMC or dial code development control. It can be seen that compared with QSFP_CTRL_SEL (equivalent to the first control signal), it adds a dial switch control option because whether OAM supports controlling QSFP can be determined before the machine is assembled, so the switching setting can be directly completed by hardware switch at the factory. Similarly, you can also choose to bypass MUX by using bypass resistors. In theory, reducing MUX can further improve the quality of I2C signals.

[0117] In an exemplary embodiment, when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor, and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor, the management controller sends a low-level second control signal to the third gating device and the fourth gating device; when the first processor is set to not allow the use of the detection link corresponding to the data port connected to the first processor, and the second processor is set to not allow the use of the detection link corresponding to the data port connected to the second processor, the management controller sends a high-level second control signal to the third gating device and the fourth gating device.

[0118] Optionally, in this embodiment, the processor may be, but is not limited to, set to allow the use of the detection link corresponding to the data port connected to the processor, or not to allow the use of the detection link corresponding to the data port connected to the processor. For example, when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor, and the second processor is set to not allow the use of the detection link corresponding to the data port connected to the second processor, the management controller sends a low-level second control signal to the third gating device, and the management controller sends a high-level second control signal to the fourth gating device; when the first processor is set to not allow the use of the detection link corresponding to the data port connected to the first processor, and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor, the management controller sends a high-level second control signal to the third gating device; the management controller sends a low-level second control signal to the fourth gating device.

[0119] In an exemplary embodiment, when the management controller sends the second control signal of a low level to the third gating device and the fourth gating device, the seventh port is connected to the ninth port, and the tenth port is connected to the twelfth port; when the management controller sends the second control signal of a high level to the third gating device and the fourth gating device, the eighth port is connected to the ninth port, and the eleventh port is connected to the twelfth port.

[0120] Optionally, in this embodiment, when the management controller sends a low-level second control signal to the third gating device and sends a high-level second control signal to the fourth gating device, the seventh port is connected to the ninth port, and the eleventh port is connected to the twelfth port.

[0121] In order to better understand the control process of the optical module in the embodiment of the present application, the control process of the optical module in the embodiment of the present application is explained and illustrated in combination with optional embodiments below, which can be but not limited to taking the third gating device including MUX_A, the fourth gating device including MUX_B, the first processor including OAM0, the second processor including OAM1, and the management controller including BMC as an example, combined with Fig. 9 and Fig.10 The explanation is provided and can be applied to, but not limited to, the embodiments of the present application.

[0122] Fig. 9 is a logical schematic diagram of an optional OAM control optical module according to an embodiment of the present application, such as Fig. 9As shown, when the BMC sends a low-level second control signal (equivalent to the OAM / BMC_CTRL_SEL signal) to MUX_A and MUX_B, the A port in MUX_A (equivalent to the seventh port) is connected to the C port in MUX_A (equivalent to the ninth port), and the A port in MUX_B (equivalent to the tenth port) is connected to the C port in MUX_B (equivalent to the twelfth port).

[0123] Fig.10 is a logical schematic diagram of an optional BMC controlling an optical module according to an embodiment of the present application, such as Fig.10 As shown, when the BMC sends a high-level OAM / BMC_CTRL_SEL signal to MUX_A and MUX_B, the B port in MUX_A (equivalent to the eighth port) is connected to the C port in MUX_A (equivalent to the ninth port), and the B port in MUX_B (equivalent to the eleventh port) is connected to the C port in MUX_A (equivalent to the twelfth port).

[0124] Optionally, in this embodiment, Table 2 is a logical control relationship table compatible with OAM and BMC control schemes. As shown in Table 2, when the BMC sends a low-level OAM / BMC_CTRL_SEL signal (equivalent to the second control signal) to MUX_A and MUX_B, the A port in MUX_A is connected to the C port in MUX_A, and the A port in MUX_B is connected to the C port in MUX_B, indicating that OAM controls the QSFP at this time. In this case, OAM is set to allow the use of the detection link of the data port on the connected optical module to detect the operating status of the connected data port; when the BMC sends a low-level OAM / BMC_CTRL_SEL signal (equivalent to the second control signal) to MUX_A and MUX_B, the A port in MUX_A is connected to the C port in MUX_A, and the A port in MUX_B is connected to the C port in MUX_B, indicating that OAM controls the QSFP at this time. In this case, OAM is set to allow the use of the detection link of the data port on the connected optical module to detect the operating status of the connected data port; When MUX_B sends a high-level OAM / BMC_CTRL_SEL signal, the B port in MUX_A is connected to the C port in MUX_A, and the B port in MUX_B is connected to the C port in MUX_A, indicating that the BMC controls the QSFP at this time. In this case, OAM may not have the function of allowing the use of the detection link of the data port on the connected optical module to detect the operating status of the connected data port. In this case, it is possible but not limited to enabling the BMC to detect the operating status of the data port on the optical module connected to OAM by managing the data port on the optical module connected to OAM.

[0125] Table 2

[0126]

[0127] In an exemplary embodiment, in the case where the first switch includes a first gating device, the second switch includes a second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, or in the case where the first switch includes a first gating device, the second switch includes a second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the management controller sends a signal to the first gating device. The management controller sends a low-level first control signal to the first gating device and the second gating device; when the first switch includes the first gating device, the second switch includes the second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port, or when the first switch includes the first gating device, the second switch includes the second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port, the management controller sends a high-level first control signal to the first gating device and the second gating device.

[0128] Optionally, in this embodiment, when the first switch includes a first gating device, the second switch includes a second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port, or when the first switch includes a first gating device, the second switch includes a second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port, the management controller sends a high-level first control signal to the first gating device and the second gating device; when the first switch includes In the case where the first gating device and the second switch include the second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, or in the case where the first switch includes the first gating device and the second switch includes the second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the management controller sends a low-level first control signal to the first gating device and the second gating device.

[0129] In an exemplary embodiment, the optical module control system further includes a first connector and a second connector, the ninth port is connected to the third connection end of the first connector, and the twelfth port is connected to the first connection end of the second connector.

[0130] Optionally, in this embodiment, the optical module control system also includes an isolation unit corresponding one-to-one to the data port of the optical module, the isolation unit is connected to the data port one-to-one, the processor is connected to the isolation unit, the isolation unit is connected to the data port, the data link between the processor and the data port includes the isolation unit, and the isolation unit is used to isolate interference between data links between different processors and the corresponding data ports.

[0131] Through the embodiments of the present application, a set of optical module control solutions compatible with multiple OAM scale-out solutions is constructed, which solves the problem of ownership change of low-speed control links (equivalent to detection links) caused by high-speed link switching to optical modules in different application scenarios; the overall hardware control solution topology including UBB boards and PHY (Physical Layer) cards and switching logic for different scenarios are designed, as well as a logic switching unit composed of MUX0 (equivalent to the first gating device) and MUX1 (equivalent to the second gating device), a function execution unit composed of IO_EXP, I2C isolation unit, QSFP-112 (equivalent to optical module), LED, etc., and supplemented by bypass resistors R1 (equivalent to the first connector) and R2. The same hardware design scheme is used with the smallest BOM (Bill of Materials, which records the information of all electronic components on the PCB) change, and is compatible Figure 3 , Figure 4 , Figure 7 The OAM system can meet all application requirements on the same PCB (Printed Circuit Board) with minimal changes in software and hardware. In terms of hardware architecture design and logic design, it provides a complete solution with full feasibility and application prospects, which greatly saves design costs and improves the adaptability of the OAM system.

[0132] This embodiment further provides a server, including the optical module control system as described in any one of the above embodiments.

[0133] Optionally, in this embodiment, an optical module control system may include but is not limited to multiple groups of processors. For example, a group of processors may include but is not limited to two processor sets, each processor set may include but is not limited to multiple processors. For example, taking a group of processors including OAM0 and OAM1 as an example, OAM0 may include but is not limited to multiple GPUs, and OAM2 may include but is not limited to multiple GPUs.

[0134] In this embodiment, a server networking system is also provided, including a plurality of the servers, wherein the servers are connected to each other via switches, and the servers are used to perform data exchange via the switches.

[0135] Optionally, in this embodiment, each of the multiple servers can be connected to a corresponding switch, but is not limited to being connected. For example, each server can be connected to the same switch, but is not limited to being connected to a different switch. Each of the multiple servers can transmit data through the switch, but is not limited to being connected to the same switch.

[0136] Fig.11 is a schematic diagram of an optional server transmitting data through a switch according to an embodiment of the present application, such as Fig.11 As shown, it can be but not limited to Figure 3 The example of the server transmitting data through the switch in the application scenario is used for explanation and description. It can be but not limited to the example that the first processor includes OAM0, the second processor includes OAM1, and each server is connected to the same switch. OAM0 can be but not limited to being connected to QSFP-112 PORT0 (equivalent to the first data port) and QSFP-112 PORT1 (equivalent to the second data port), and then connected to the switch; OAM1 can be but not limited to being connected to QSFP-112 PORT2 (equivalent to the third data port) and QSFP-112 PORT3 (equivalent to the fourth data port), and then connected to the switch. There can be but not limited to a data link and a detection link between OAM and the data port on the connected optical module.

[0137] The explanation and description can be made by taking, but not limited to, the data link between OAM and the data port on the connected optical module as an example. OAM0 and OAM1 each have x8 (8) 56Gbps Serdes channels (Lane 0 to Lane 7) for high-speed data transmission, and these Serdes channels are connected to the data port of the optical module through the PHY Retimer chip. When the Serdes on the OAM0 and OAM1 sides is 56G and the Serdes on the switch side is 56G, the 4 pairs of 56Gbps signals from Lane 0 to Lane 3 in OAM0 are correspondingly transmitted to QSFP-112 PORT0, and the 4 pairs of 56Gbps signals from Lane 4 to Lane 7 in OAM0 are correspondingly transmitted to QSFP-112 PORT1; the 4 pairs of 56Gbps signals from Lane 0 to Lane 3 in OAM1 are correspondingly transmitted to QSFP-112 PORT2, and the 4 pairs of 56Gbps signals from Lane 4 to Lane 7 in OAM1 are correspondingly transmitted to QSFP-112 PORT3. QSFP-112 PORT0 to QSFP-112 PORT3 respectively transmit the received signals (or data) to the switch, and the switch then transmits the received signals.

[0138] In this way, each server can, but is not limited to, transmit data to each other through a switch. The data can, but is not limited to, be used for training AI (Artificial Intelligence) models. In this way, during the training process of the AI ​​model, when the processor switches to connect different data ports for data transmission, the time required to switch the detection link of the data port is reduced, thereby improving the training efficiency of the AI ​​model.

[0139] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0140] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0141] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0142] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0143] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0144] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0145] An embodiment of the present application also provides a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0146] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0147] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0148] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. An optical module control system, characterized in that: include: A switch, a management controller and a processor, wherein the management controller includes a debugging interface, the switch is connected to the debugging interface, and the processor is connected to the switch; The management controller is used to control the processor to connect to the detection link corresponding to the data port of the optical module connected to the processor in response to the identified switching request, and the switching request is triggered when the data port of the optical module connected to the processor changes; Among them, the switch includes a first switch and a second switch, the processor includes a first processor and a second processor, the first switch and the second switch are both connected to the debugging interface, the first processor and the second processor are both connected to the management controller, the first switch includes a first port, a second port and a third port, the second switch includes a fourth port, a fifth port and a sixth port, the second port is connected to the fifth port, the optical module includes: a first data port and its corresponding first detection link, a second data port and its corresponding second detection link, a third data port and its corresponding third detection link, and a fourth data port and its corresponding fourth detection link, the first port is used to connect the first detection link, the third port is used to connect the second detection link, the fourth port is used to connect the third detection link and the fourth detection link, the first port is used to connect the first processor, and the sixth port is used to connect the second processor.

2. The optical module control system according to claim 1, characterized in that: When the first switch includes a first gating device and the second switch includes a second gating device, the management controller is used to send a first control signal to the first gating device and the second gating device, wherein the first control signal is used to control the first processor to be connected to the detection link corresponding to the data port connected to the first processor, and to control the second processor to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow use of the detection link corresponding to the data port connected to the second processor.

3. The optical module control system according to claim 2, characterized in that: When the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the management controller sends the first control signal of a low level to the first gating device and the second gating device; When the first processor is connected to the first data port and the second processor is connected to the second data port, the management controller sends the first control signal of a high level to the first gating device and the second gating device.

4. The optical module control system according to claim 3, characterized in that: In the case where the management controller sends the first control signal of a low level to the first gating device and the second gating device, the first port is connected to the third port, and the fourth port is connected to the sixth port; In a case where the management controller sends the first control signal of a high level to the first gating device and the second gating device, the second port is connected to the third port, and the fifth port is connected to the sixth port.

5. The optical module control system according to claim 4, characterized in that: In a case where the first port is connected to the third port, and the fourth port is connected to the sixth port, the first processor is connected to the first detection link and the second detection link, and the second processor is connected to the third detection link and the fourth detection link; When the second port is connected to the third port, and the fifth port is connected to the sixth port, the first processor is connected to the first detection link, and the second processor is connected to the second detection link.

6. The optical module control system according to claim 1, characterized in that: The optical module also includes a first detection unit corresponding to the first data port, a second detection unit corresponding to the second data port, a third detection unit corresponding to the third data port, and a fourth detection unit corresponding to the fourth data port, wherein the first detection link exists between the first detection unit and the first data port, the second detection link exists between the second detection unit and the second data port, the third detection link exists between the third detection unit and the third data port, and the fourth detection link exists between the fourth detection unit and the fourth data port; The first port is used to connect the first detection unit, the third port is used to connect the second detection unit, and the fourth port is used to connect the third detection unit and the fourth detection unit.

7. The optical module control system according to claim 6, characterized in that: When the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first port is connected to the first processor, the first port is connected to the first detection unit, and the first port is connected to the third port, the third port is connected to the second detection unit, the sixth port is connected to the second processor, the sixth port is connected to the fourth port, and the fourth port is connected to the third detection unit and the fourth detection unit.

8. The optical module control system according to claim 6, characterized in that: When the first processor is connected to the first data port and the second processor is connected to the second data port, the first port is connected to the first processor, the first port is connected to the first detection unit, the second port is connected to the third port, the third port is connected to the second detection unit, the fifth port is connected to the second port, the fifth port is connected to the sixth port, and the sixth port is connected to the second processor.

9. The optical module control system according to claim 6, characterized in that: The first bus address of the first detection unit is the same as the third bus address of the third detection unit, the second bus address of the second detection unit is the same as the fourth bus address of the fourth detection unit, and the first bus address is different from the second bus address.

10. The optical module control system according to claim 1, characterized in that: The optical module control system also includes a first connector and a second connector, the first connection end of the first connector is used to connect the first detection link, the second connection end of the first connector is used to connect the second detection link, the third connection end of the first connector is also used to connect the first processor, the first connection end of the second connector is used to connect the second processor, and the second connection end of the second connector is used to connect the third detection link and the fourth detection link; The management controller is used to control the first processor to be connected to the detection link corresponding to the data port connected to the first processor, and to control the second processor to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor.

11. The optical module control system according to claim 10, characterized in that: In a case where the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first connection end of the first connector is connected to the first detection link, the second connection end of the first connector is connected to the second detection link, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection link and the fourth detection link; When the first processor is connected to the first data port and the second processor is connected to the third data port, the first connection end of the first connector is connected to the first detection link, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection link.

12. The optical module control system according to claim 11, characterized in that: The optical module also includes a first detection unit corresponding to the first data port, a second detection unit corresponding to the second data port, a third detection unit corresponding to the third data port, and a fourth detection unit corresponding to the fourth data port, wherein the first detection link exists between the first detection unit and the first data port, the second detection link exists between the second detection unit and the second data port, the third detection link exists between the third detection unit and the third data port, and the fourth detection link exists between the fourth detection unit and the fourth data port; The first connection end of the first connector is used to connect the first detection unit, the second connection end of the first connector is used to connect the second detection unit, and the second connection end of the second connector is used to connect the third detection unit and the fourth detection unit.

13. The optical module control system according to claim 12, characterized in that: When the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the first connection end of the first connector is connected to the first detection unit, the second connection end of the first connector is connected to the second detection unit, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection unit and the fourth detection unit.

14. The optical module control system according to claim 12, characterized in that: When the first processor is connected to the first data port and the second processor is connected to the third data port, the first connection end of the first connector is connected to the first detection unit, the third connection end of the first connector is connected to the first processor, the first connection end of the second connector is connected to the second processor, and the second connection end of the second connector is connected to the third detection unit.

15. The optical module control system according to claim 1, characterized in that: The optical module control system further includes a third gating device and a fourth gating device, the third gating device includes a seventh port, an eighth port and a ninth port, the fourth gating device includes a tenth port, an eleventh port and a twelfth port, the seventh port is used to connect to the first processor, the eighth port is connected to the management controller, the ninth port is connected to the first port, the tenth port is used to connect to the second processor, the eleventh port is connected to the management controller, and the twelfth port is connected to the sixth port; The management controller is used to control the detection link connection corresponding to the data port connected to the first object and the first processor, and to control the detection link connection corresponding to the data port connected to the second object and the second processor, wherein the first object includes the first processor or the management controller, and the second object includes the second processor or the management controller.

16. The optical module control system according to claim 15, characterized in that: The management controller is used to send a second control signal to the third gating device and the fourth gating device, wherein the second control signal is used to control the first processor to be connected to the detection link corresponding to the data port connected to the first processor, and to control the second processor to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to allow the use of the detection link corresponding to the data port connected to the second processor. The second control signal is also used to control the management controller to be connected to the detection link corresponding to the data port connected to the first processor, and to control the management controller to be connected to the detection link corresponding to the data port connected to the second processor when the first processor is set to not allow the use of the detection link corresponding to the data port connected to the first processor and the second processor is set to not allow the use of the detection link corresponding to the data port connected to the second processor.

17. The optical module control system according to claim 16, characterized in that: When the first processor is configured to allow the use of a detection link corresponding to a data port connected to the first processor, and the second processor is configured to allow the use of a detection link corresponding to a data port connected to the second processor, the management controller sends a low-level second control signal to the third gating device and the fourth gating device; When the first processor is set to not allow the use of the detection link corresponding to the data port connected to the first processor, and the second processor is set to not allow the use of the detection link corresponding to the data port connected to the second processor, the management controller sends a high-level second control signal to the third gating device and the fourth gating device.

18. The optical module control system according to claim 17, characterized in that: In the case where the management controller sends the second control signal of a low level to the third gating device and the fourth gating device, the seventh port is connected to the ninth port, and the tenth port is connected to the twelfth port; In a case where the management controller sends the second control signal of a high level to the third gating device and the fourth gating device, the eighth port is connected to the ninth port, and the eleventh port is connected to the twelfth port.

19. The optical module control system according to claim 18, characterized in that: In the case where the first switch includes a first gating device, the second switch includes a second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port; or, in the case where the first switch includes a first gating device, the second switch includes a second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, the first processor is connected to the first data port and the second data port, and the second processor is connected to the third data port and the fourth data port, the management controller sends a low-level first control signal to the first gating device and the second gating device; In the case where the first switch includes a first gating device, the second switch includes a second gating device, the seventh port is connected to the ninth port, the tenth port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port; or, in the case where the first switch includes a first gating device, the second switch includes a second gating device, the eighth port is connected to the ninth port, the eleventh port is connected to the twelfth port, and the first processor is connected to the first data port, and the second processor is connected to the second data port, the management controller sends a high-level first control signal to the first gating device and the second gating device.

20. The optical module control system according to claim 18, characterized in that: The optical module control system further includes a first connector and a second connector, the ninth port is connected to the third connection end of the first connector, and the twelfth port is connected to the first connection end of the second connector.

21. A server, characterized in that: The optical module control system comprises the optical module control system as claimed in any one of claims 1 to 20.

22. A server networking system, characterized in that: It comprises a plurality of servers as claimed in claim 21, wherein the servers are connected via switches, and the servers are used for data exchange via the switches.

Images