Optical Interconnection System, Optical Communication Control Method, Device, Equipment, Medium and Product

Abstract

The present invention discloses an optical interconnection system, an optical communication control method, device, equipment, medium and product, relating to the field of communication technologies. The optical interconnection system includes a first optical communication device and a second optical communication device. The first optical communication device includes a first chip, a first optical module and a first control module which are interconnected. The second optical communication device includes a second chip, a second optical module and a second control module which are interconnected. The first control module is configured to detect that the first optical module is in place through a first control signal, and detect the state of the driver chip inside the first optical module through a second control signal, so as to determine whether the driver inside the first optical module is working properly. If so, the first control module controls the port corresponding to the first chip to exit the electrical idle state through a third control signal, and controls the first chip to start link training. After the link training is completed, the first chip establishes communication with the second chip. The present invention avoids the optical interconnection system from operating in a speed reduction state.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and more particularly, to an optical interconnection system, an optical communication control method, device, equipment, medium and product. Background Art

[0002] Optical interconnection technology has the characteristic of low loss and can support long-distance transmission of PCIe (Peripheral Component Interconnect Express) signals. When a device is connected, the PCIe link will start link training until a specific rate. However, after the optical module is inserted, it will perform a power-on operation, and it takes a certain amount of time for chips such as internal drivers to enter the normal working state, and the time for different drivers inside the optical module to enter the normal working state from power-on is also inconsistent. Before the optical module enters the normal working state, it may cause abnormalities in the electro-optic conversion process of high-speed signals, resulting in error codes. And the PCIe link training starts from low speed to high speed and adjusts the link rate according to the link state, that is, if the PCIe chip determines in the link that the current link cannot support the highest rate supported by the chip, it will lower the link rate. Therefore, for a PCIe optical interconnection system, it is very easy to cause the PCIe link to complete link training and lower the link rate before the chips inside the optical module reach the normal working state, that is, it fails to enter the highest rate state supported by the link, resulting in the system running in a speed-reduced state.

[0003] Therefore, how to avoid the optical interconnection system from running in a speed-reduced state is a technical problem that those skilled in the art need to solve. Summary of the Invention

[0004] The purpose of the present invention is to provide an optical interconnection system, an optical communication control method, device, equipment, medium and product, which avoid the optical interconnection system from running in a speed-reduced state.

[0005] To achieve the above purpose, the present invention provides an optical interconnection system, including a first optical communication device and a second optical communication device. The first optical communication device includes a first chip, a first optical module and a first control module connected to each other. The second optical communication device includes a second chip, a second optical module and a second control module connected to each other. The first optical communication device and the second optical communication device are connected through the first optical module and the second optical module, and the first optical module and the second optical module communicate through optical signals;

[0006] The first control module is used to, when the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, detect that the first optical module is in place through the first control signal, detect the state of the driver chip inside the first optical module through the second control signal, and determine whether the driver inside the first optical module is working properly according to the state of the driver chip inside the first optical module; if so, control the port corresponding to the first chip to exit the electrical idle state and control the first chip to start link training through the third control signal, and after the link training is completed, establish communication between the first chip and the second chip.

[0007] Among them, when both the first optical module and the second optical module are in place, after the first optical module is removed, the port corresponding to the first chip enters the electrical idle state;

[0008] The first control module is also used to: detect that the first optical module is not in place through the first control signal, and control the first chip to stop the receive - end detection through the third control signal.

[0009] Among them, the first control module is also used to: when the first optical module is in place and the port corresponding to the first chip enters the electrical idle state, detect whether there is an input optical signal at the receive - end of the first optical module through the second control signal; if there is, restore the power supply of the driver inside the first optical module through the second control signal; detect the state of the driver inside the first optical module through the second control signal, and determine whether the driver inside the first optical module is working properly according to the state of the driver inside the first optical module; if so, control the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal, and after the link training is completed, establish communication between the first chip and the second chip.

[0010] Among them, when both the first optical module and the second optical module are in place, after the second optical module is removed, the port corresponding to the first chip enters the electrical idle state;

[0011] The first control module is also used to: after detecting that the first chip enters the electrical idle state through the third control signal, detect that the first optical module is in place through the first control signal, and turn off the power supply of the driver inside the first optical module and keep the power supply of the receive - end of the first optical module through the second control signal.

[0012] Among them, the first control module is further configured to: when neither the first optical module nor the second optical module is in place, after the first optical module is inserted, detect that the first optical module is in place through the first control signal; detect the status of the driver chip inside the first optical module through the second control signal, and determine whether the driver inside the first optical module is working properly according to the status of the driver chip inside the first optical module; if so, detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is, control the first chip to exit the electrical idle state and start link training through the third control signal, and after the link training is completed, establish communication between the first chip and the second chip.

[0013] Among them, the first control module is connected to the in-place pin of the first optical module through the first control signal, the first control module is connected to the integrated circuit pin of the first optical module through the second control signal, the first control module is connected to the integrated circuit pin and / or the serial communication pin of the first chip through the third control signal, and the serial communication pin includes a serial data bus pin and / or a universal asynchronous receiver / transmitter serial communication pin.

[0014] Among them, the first control module is integrated inside the first chip, or the first control module is a chip independent of the first chip;

[0015] If the first control module is a chip independent of the first chip, the first control module includes a complex programmable logic device and / or a field programmable gate array.

[0016] To achieve the above object, the present invention provides an optical communication control method, which is applied to a first optical communication device. The method includes:

[0017] When the first optical module is not in place and the second optical module is in place, when the first optical module is inserted, the first control module in the first optical communication device detects that the first optical module is in place through the first control signal; among them, the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in a second optical communication device connected to the first optical communication device;

[0018] The first control module detects the status of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module is working properly according to the status of the driver chip inside the first optical module;

[0019] If so, the first control module controls the port corresponding to the first chip in the first optical communication device to exit the electrical idle state and controls the first chip in the first optical communication device to start link training through the third control signal. After the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device.

[0020] Among them, it further includes:

[0021] During the link training process of the first chip, improve the communication rate between the first chip and the second chip.

[0022] Among them, it also includes:

[0023] When both the first optical module and the second optical module are in place, after the first optical module is unplugged, the port corresponding to the first chip enters the electrical idle state. The first control module detects that the first optical module is not in place through the first control signal, and controls the first chip to stop the receiver detection through the third control signal.

[0024] Among them, if the first optical module is unplugged and then inserted, after the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device, including:

[0025] After the link training is completed, the first chip in the first optical communication device communicates with the first optical module through an electrical signal, the first optical module communicates with the second optical module through an optical signal, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module was unplugged.

[0026] Among them, it also includes:

[0027] When the first optical module is in place and the port corresponding to the first chip enters the electrical idle state, the first control module detects whether there is an input optical signal at the receiver of the first optical module through the second control signal;

[0028] If there is, the first control module restores the power supply of the internal driver of the first optical module through the second control signal;

[0029] The first control module detects the state of the internal driver of the first optical module through the second control signal, and judges whether the internal driver of the first optical module is working properly according to the state of the internal driver of the first optical module;

[0030] If so, the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. After the link training is completed, the first chip and the second chip establish communication.

[0031] Among them, it also includes:

[0032] When both the first optical module and the second optical module are in place, after the second optical module is unplugged, the port corresponding to the first chip enters the electrical idle state;

[0033] After the first control module detects that the first chip enters the electrical idle state through the third control signal, it detects that the first optical module is present through the first control signal, and turns off the power supply of the internal driver of the first optical module and maintains the power supply of the receiving end of the first optical module through the second control signal.

[0034] Wherein, if the second optical module is inserted after being pulled out, after the link training is completed, the first chip establishes communication with the second chip, including:

[0035] After the link training is completed, the first chip communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the second optical module is pulled out.

[0036] Wherein, it further includes:

[0037] When neither the first optical module nor the second optical module is present, after the first optical module is inserted, the first control module detects that the first optical module is present through the first control signal;

[0038] The first control module detects the status of the internal driver chip of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working properly according to the status of the internal driver chip of the first optical module;

[0039] If so, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal;

[0040] If there is, the first control module controls the first chip to exit the electrical idle state and start link training through the third control signal. After the link training is completed, the first chip establishes communication with the second chip.

[0041] Wherein, if both the first optical module and the second optical module are inserted after being pulled out, after the link training is completed, the first chip establishes communication with the second chip, including:

[0042] After the link training is completed, the first chip communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are pulled out.

[0043] To achieve the above object, the present invention provides an optical communication control device, which is applied to a first optical communication device. The device includes:

[0044] The first detection unit is used to detect that the first optical module is in place through the first control signal when the first optical module is pulled out and then inserted under the condition that the first optical module is not in place and the second optical module is in place; wherein, the first optical module is the optical module in the first optical communication device, and the second optical module is the optical module in the second optical communication device connected to the first optical communication device.

[0045] The first judgment unit is used to detect the state of the driver chip inside the first optical module through the second control signal and judge whether the driver inside the first optical module is working properly according to the state of the driver chip inside the first optical module; if so, start the working process of the first control unit.

[0046] The first control unit is used to control the port corresponding to the first chip in the first optical communication device to exit the electrical idle state through the third control signal and control the first chip in the first optical communication device to start link training. After the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device.

[0047] To achieve the above object, the present invention provides an electronic device, including:

[0048] A memory for storing a computer program;

[0049] A processor for implementing the steps executed by the above optical communication control method when executing the computer program.

[0050] To achieve the above object, the present invention provides a non-volatile storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps executed by the above optical communication control method.

[0051] To achieve the above object, the present invention provides a computer program product, including a computer program, and the computer program, when executed by a processor, implements the steps executed by the above optical communication control method.

[0052] As can be seen from the above solution, an optical interconnection system provided by the present invention includes a first optical communication device and a second optical communication device. The first optical communication device includes a first chip, a first optical module, and a first control module that are interconnected. The second optical communication device includes a second chip, a second optical module, and a second control module that are interconnected. The first optical communication device and the second optical communication device are connected through the first optical module and the second optical module, and optical signals are used for communication between the first optical module and the second optical module. The first control module is configured to, when the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, detect that the first optical module is in place through a first control signal, detect the state of the driver chip inside the first optical module through a second control signal, and determine whether the driver inside the first optical module is working properly according to the state of the driver chip inside the first optical module. If so, control the port corresponding to the first chip to exit the electrical idle state through a third control signal, and control the first chip to start link training. After the link training is completed, communication is established between the first chip and the second chip.

[0053] The beneficial effects of the present invention are as follows: In the optical interconnection system provided by the present invention, when the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, the first control module in the first optical communication device controls the first chip to start link training after detecting that the first optical module is in place and the driver inside the first optical module is working properly, avoiding the first chip starting link training when the first optical module fails to enter the normal working state and resulting in failure to enter the highest rate state supported by the link, enabling the communication rate between the first chip and the second chip to reach the maximum rate through training, and avoiding the optical interconnection system operating in a speed-reduced state. The present invention also discloses an optical communication control method, device, an electronic device, a non-volatile storage medium, and a computer program product, which can also achieve the above technical effects.

[0054] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following specific embodiments to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0056] Figure 1Structural diagram of an optical interconnection system shown according to an exemplary embodiment;

[0057] Figure 2 Flowchart of a first optical communication control method shown according to an exemplary embodiment;

[0058] Figure 3 Flowchart of a second optical communication control method shown according to an exemplary embodiment;

[0059] Figure 4 Flowchart of a third optical communication control method shown according to an exemplary embodiment;

[0060] Figure 5 Structural diagram of an optical communication control device shown according to an exemplary embodiment;

[0061] Figure 6 Structural diagram of an electronic device shown according to an exemplary embodiment. Detailed implementation manners

[0062] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Additionally, in the embodiments of the present invention, "first", "second", etc. are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence.

[0063] This embodiment discloses an optical interconnection system. Refer to Figure 1 , which shows an architecture diagram of an optical interconnection system provided by an embodiment of the present invention. As shown in Figure 1 , the optical interconnection system includes a first optical communication device 10 and a second optical communication device 20. The first optical communication device 10 includes a first chip 101, a first optical module 102, and a first control module 103 that are connected to each other. The second optical communication device 20 includes a second chip 201, a second optical module 202, and a second control module 203 that are connected to each other. The first optical communication device 10 and the second optical communication device 20 are connected through the first optical module 102 and the second optical module 202, and the first optical module 102 and the second optical module 202 communicate through optical signals.

[0064] In a specific implementation, the first control module 103 controls the first chip 101 and the first optical module 102 respectively through electrical signals. Data is transmitted between the first chip 101 and the first optical module 102 through electrical signals. The second control module 203 controls the second chip 201 and the second optical module 202 respectively through electrical signals. Data is transmitted between the second chip 201 and the second optical module 202 through electrical signals.

[0065] The first optical communication device 10 and the second optical communication device 20 can be devices compliant with the PCIe protocol. Correspondingly, the first chip 101 and the second chip 201 can be chips compliant with the PCIe protocol. Data is transmitted between the first chip 101 and the first optical module 102 through electrical signals compliant with the PCIe protocol. Data is transmitted between the second chip 201 and the second optical module 202 through electrical signals compliant with the PCIe protocol.

[0066] The first control module 103 controls the first optical module 102 through a first control signal and a second control signal, and the first control signal and the second control signal are electrical signals. The first control signal is used to detect the presence status of the first optical module 102, whether it is present or not. As a feasible implementation, the first control module is connected to the presence pin of the first optical module through the first control signal. In a specific implementation, the first control module 103 is connected to the presence pin of the first optical module 102 through the first control signal. The first control module 103 detects the presence pin of the first optical module 102 through the first control signal, and determines the presence status of the first optical module 102 according to the level status of the presence pin. If the presence pin is at a high level, it is determined that the first optical module 102 is present. If the presence pin is at a low level, it is determined that the first optical module 102 is not present. The second control signal is used to detect the status of the driver chip inside the first optical module 102, and determine whether the driver inside the first optical module 102 is working properly according to the status of the driver chip inside the first optical module 102. The driver chip inside the first optical module 102 can specifically be a Microcontroller Unit (MCU). As a feasible implementation, the first control module is connected to the integrated circuit pin of the first optical module through the second control signal. In a specific implementation, the first control module 103 is connected to the Inter-Integrated Circuit (I2C) pin of the first optical module 102 through the second control signal. The first control module 103 accesses the integrated circuit pin of the first optical module 102 through the second control signal to obtain the status of the driver chip inside the first optical module 102.

[0067] The first control module 103 controls the first chip 101 through a third control signal, including controlling the first chip 101 to stop receiving end detection, exit the electrical idle state, start link training, etc. As a feasible implementation manner, the first control module is connected to the integrated circuit pins and / or serial communication pins of the first chip through the third control signal. In a specific implementation, the first control module 103 is connected to the integrated circuit (I2C) pins or other serial communication pins of the first chip 101, and the serial communication pins may include serial data bus (SDB) pins, universal asynchronous receiver / transmitter (UART) serial communication pins, etc.

[0068] As a feasible implementation manner, the first control module is integrated inside the first chip. In a specific implementation, the first control module 103 may be integrated inside the first chip 101 as a functional module. As another feasible implementation manner, the first control module is a chip independent of the first chip. In a specific implementation, the first control module 103 may also be independent of the first chip 101. If the first control module 103 is a chip independent of the first chip 101, the first control module may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), etc.

[0069] The second control module 203 controls the second optical module 202 through a first control signal and a second control signal, and the first control signal and the second control signal are electrical signals. The first control signal is used to detect the presence state of the second optical module 202, either present or not present. As a feasible implementation manner, the second control module is connected to the presence pin of the second optical module through the first control signal. In a specific implementation, the second control module 203 is connected to the presence pin of the second optical module 202 through the first control signal, and the second control module 203 detects the presence pin of the second optical module 202 through the first control signal, and determines the presence state of the second optical module 202 according to the level state of the presence pin. If the presence pin is at a high level, it is determined that the second optical module 202 is present. If the presence pin is at a low level, it is determined that the second optical module 202 is not present. The second control signal is used to detect the state of the driver chip inside the second optical module 202, and determine whether the driver inside the second optical module 202 is working properly according to the state of the driver chip inside the second optical module 202. The driver chip inside the second optical module 202 may specifically be a micro control unit. As a feasible implementation manner, the second control module is connected to the I2C pin of the second optical module through the second control signal. In a specific implementation, the second control module 203 is connected to the I2C pin of the second optical module 202 through the second control signal, and the second control module 203 accesses the I2C pin of the second optical module 202 through the second control signal to obtain the state of the driver chip inside the second optical module 202.

[0070] The second control module 203 controls the second chip 201 through a third control signal, including controlling the second chip 201 to stop receiving end detection, exit the electrical idle state, start link training, etc. As a feasible implementation manner, the second control module is connected to the I2C pin and / or serial communication pin of the second chip through the third control signal. In a specific implementation, the second control module 203 is connected to the I2C pin or other serial communication pins of the second chip 201 through the third control signal, and the serial communication pins may include SDB pins, UART serial communication pins, etc.

[0071] As a feasible implementation manner, the second control module is integrated inside the second chip. In a specific implementation, the second control module 203 may be integrated inside the second chip 201 as a functional module. As another feasible implementation manner, the second control module is a chip independent of the second chip. In a specific implementation, the second control module 203 may also be independent of the second chip 201. If the second control module 203 is a chip independent of the second chip 201, the second control module may be a CPLD, FPGA, etc.

[0072] As a feasible implementation, when both the first optical module and the second optical module are in place, after the first optical module is unplugged, the port corresponding to the first chip enters an electrical idle state; the first control module is further configured to: detect that the first optical module is not in place through the first control signal, and control the first chip to stop the receiver detection through the third control signal.

[0073] From the perspective of the first optical communication device, when both optical modules at both ends are in place, after the local optical module (i.e., the first optical module) is unplugged, the port in the first chip connected to the first optical module enters an electrical idle state. After the first control module detects that the first optical module is not in place through the first control signal, it controls the first chip to stop the receiver detection through the third control signal, which helps to reduce the power consumption of the first chip.

[0074] As a feasible implementation, the first control module is configured to, when the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, detect that the first optical module is in place through the first control signal, detect the status of the driver chip inside the first optical module through the second control signal, and determine whether the driver inside the first optical module is working properly based on the status of the driver chip inside the first optical module; if so, control the port corresponding to the first chip to exit the electrical idle state through the third control signal, control the first chip to start link training, and after the link training is completed, establish communication between the first chip and the second chip.

[0075] In a specific implementation, from the perspective of the first optical communication device, when the opposite optical module (i.e., the second optical module) is in place, after the local optical module (i.e., the first optical module) is inserted, the first control module detects that the first optical module is in place through the first control signal, and detects the status of the driver chip inside the first optical module through the second control signal, including the input status and output status of the driver chip inside, etc. Determine whether the driver inside the first optical module is working properly based on the status of the driver chip inside the first optical module. If the driver inside the first optical module is working properly, control the first chip to start link training through the third control signal, otherwise re-detect the status of the driver chip inside the first optical module until the driver inside the first optical module is working properly.

[0076] During the link training process of the first chip, gradually increase the communication rate between the first chip and the second chip until the communication rate between the first chip and the second chip reaches the maximum rate. After the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module communicates with the second optical module through optical signals. If the first optical module is unplugged and then inserted, that is, hot-plugged, after the link training is completed, the communication rate between the first chip and the second chip resumes to the rate before the first optical module was unplugged.

[0077] As a feasible implementation, when the second optical module is pulled out with both the first optical module and the second optical module in place, the port corresponding to the first chip enters an electrical idle state; the first control module is further configured to: after detecting that the first chip enters the electrical idle state through the third control signal, detect that the first optical module is in place through the first control signal, and turn off the power supply of the internal driver of the first optical module and maintain the power supply of the receiving end of the first optical module through the second control signal.

[0078] In a specific implementation, when the second optical module is pulled out with the first optical module in place, the optical signal communication between the first optical module and the second optical module is interrupted, and the electrical signal communication between the first chip and the first optical module is interrupted. The port in the first chip connected to the first optical module enters an electrical idle state. After the first control module detects that the first chip enters the electrical idle state through the third control signal and detects that the first optical module is in place through the first control signal, it turns off the power supply of the internal driver of the first optical module and maintains the power supply of the receiving end of the first optical module through the second control signal. Turning off the power supply of the internal driver of the first optical module helps reduce the power consumption of the first optical communication device, and maintaining the power supply of the receiving end of the first optical module is to be able to detect whether the second optical module is inserted again.

[0079] As a feasible implementation, the first control module is further configured to: when the first optical module is in place and the port corresponding to the first chip enters the electrical idle state, detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if so, restore the power supply of the internal driver of the first optical module through the second control signal; detect the state of the internal driver of the first optical module through the second control signal, and determine whether the internal driver of the first optical module is working properly according to the state of the internal driver of the first optical module; if so, control the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal, and after the link training is completed, establish communication between the first chip and the second chip.

[0080] In a specific implementation, when the first optical module is in place and the port corresponding to the first chip enters the electrical idle state, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal. If not, it indicates that the second optical module is not inserted, and the current state is maintained. If there is, it indicates that the second optical module is inserted again. The first control module restores the power supply of the internal driver of the first optical module through the second control signal, detects the status of the internal driver chip of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working properly according to the status of the internal driver chip of the first optical module. If the internal driver of the first optical module is working properly, the port corresponding to the first chip is controlled to exit the electrical idle state and start link training through the third control signal. Otherwise, the status of the internal driver chip of the first optical module is detected again until the internal driver of the first optical module is working properly.

[0081] During the link training of the first chip, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the maximum rate. After the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module communicates with the second optical module through optical signals. If the first optical module is inserted after being unplugged, that is, hot-plugged, after the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the second optical module was unplugged.

[0082] As a feasible implementation manner, the first control module is further configured to: when neither the first optical module nor the second optical module is in place, after the first optical module is inserted, detect that the first optical module is in place through the first control signal; detect the status of the internal driver chip of the first optical module through the second control signal, and determine whether the internal driver of the first optical module is working properly according to the status of the internal driver chip of the first optical module; if so, detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is, control the first chip to exit the electrical idle state and start link training through the third control signal, and after the link training is completed, establish communication between the first chip and the second chip.

[0083] In a specific implementation, when neither the first optical module nor the second optical module is in place, the first optical module is inserted first. After the first control module detects that the first optical module is in place through the first control signal, the first control module detects the status of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module is working properly based on the status of the driver chip inside the first optical module. If the driver inside the first optical module is working properly, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal. If the driver inside the first optical module is not working properly, the status of the driver chip inside the first optical module is detected again until the driver inside the first optical module is working properly. If there is no input optical signal at the receiving end of the first optical module, it means that the second optical module is not inserted, and the current state is maintained. If there is an input optical signal at the receiving end of the first optical module, it means that the second optical module is inserted again, and the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal.

[0084] It should be noted that after the second optical module is inserted again, after the second control module in the second optical communication device detects that the second optical module is in place through the first control signal, the second control module detects the status of the driver chip inside the second optical module through the second control signal, and determines whether the driver inside the second optical module is working properly based on the status of the driver chip inside the second optical module; if so, the second control module controls the port corresponding to the second chip to exit the electrical idle state through the third control signal, and the second optical module can send an optical signal to the first optical module, that is, there is an input optical signal at the receiving end of the first optical module.

[0085] During the link training process, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the highest rate. After the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module and the second optical module communicate with each other through optical signals. If the first optical module and the second optical module are inserted after being pulled out, that is, hot-plugged, after the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are pulled out.

[0086] The optical interconnection system provided by the embodiment of the present invention confirms that the local optical module has entered the normal working state according to the in-place state of the optical module and the internal chip state, and determines that the remote optical module has entered the normal working state according to the receiving end state of the optical module, so as to control the local chip to start link training, thereby avoiding the chip starting link training when the optical module link fails to enter the normal working state and resulting in failure to enter the highest rate state supported by the link, thereby avoiding the optical interconnection system running in the speed reduction state.

[0087] An embodiment of the present invention discloses an optical communication control method, which avoids the optical interconnection system from operating in a speed-reducing state.

[0088] See Figure 2 , the flowchart of the first optical communication control method shown according to an exemplary embodiment is as Figure 2 shown, including:

[0089] S101: When both the first optical module and the second optical module are in place, after the first optical module is unplugged, the port corresponding to the first chip enters an electrical idle state. The first control module detects that the first optical module is not in place through the first control signal, and controls the first chip to stop the receiver detection through the third control signal;

[0090] This embodiment introduces the control process of hot plugging of the first optical module when the second optical module is in place from the perspective of the first optical communication device in the above optical interconnection system, that is, the control process of hot plugging of the local optical module. The execution subject of this embodiment is the first control module in the first optical communication device.

[0091] In this step, when the second optical module is in place and the first optical module is unplugged, the port in the first chip connected to the first optical module enters an electrical idle state. After the first control module detects that the first optical module is not in place through the first control signal, it controls the first chip to stop the receiver detection through the third control signal, which helps to reduce the power consumption of the first chip.

[0092] S102: When the first optical module is inserted, the first control module detects that the first optical module is in place through the first control signal;

[0093] In this step, when the first optical module is inserted again, after the first control module detects that the first optical module is in place through the first control signal, it enters S103.

[0094] S103: The first control module detects the state of the internal driver chip of the first optical module through the second control signal, and judges whether the internal driver of the first optical module is working properly according to the state of the internal driver chip of the first optical module; if so, it enters S104; if not, it re-enters S103;

[0095] In this step, the first control module detects the state of the internal driver chip of the first optical module through the second control signal, and judges whether the internal driver of the first optical module is working properly according to the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working properly, it enters S104, otherwise it re-enters S103 to re-detect the state of the internal driver chip of the first optical module until the internal driver of the first optical module is working properly.

[0096] S104: The first control module controls the ports corresponding to the first chip to exit the electrical idle state through the third control signal, controls the first chip to start link training, and after the link training is completed, the first chip establishes communication with the second chip.

[0097] In this step, if the internal driver of the first optical module is already working properly, the first control module controls the ports of the first chip connected to the first optical module to exit the electrical idle state through the third control signal, and controls the first chip to start link training.

[0098] As a feasible implementation, this embodiment further includes: during the link training process of the first chip, increasing the communication rate between the first chip and the second chip. In a specific implementation, during the link training process of the first chip, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the highest rate.

[0099] After the link training is completed, the first chip communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module was unplugged.

[0100] As a feasible implementation, if the first optical module is unplugged and then inserted, after the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module was unplugged. In a specific implementation, if the first optical module is unplugged and then inserted, that is, hot-plugged, after the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the first optical module was unplugged.

[0101] The communication control method provided by the embodiment of the present invention, when the first optical module is unplugged, controls the first chip to stop the receiver detection through the third control signal, which is beneficial to reducing the power consumption of the first chip. When the first optical module is inserted again, after detecting that the first optical module is in place and the internal driver of the first optical module is working properly, controls the first chip to start link training, avoiding the first chip starting link training when the first optical module fails to enter the normal working state and resulting in not entering the highest rate state supported by the link, enabling the communication rate between the first chip and the second chip to be restored to the rate before the first optical module was unplugged, and avoiding the optical interconnection system running in a speed-reduced state after the optical module is hot-plugged.

[0102] The embodiment of the present invention discloses an optical communication control method. Refer to Figure 3 , according to the flowchart of the second optical communication control method shown in an exemplary embodiment, asFigure 3 As shown in, it includes:

[0103] S201: When both the first optical module and the second optical module are in place, after the second optical module is pulled out, the port corresponding to the first chip enters an electrical idle state.

[0104] In this embodiment, from the perspective of the first optical communication device in the above optical interconnection system, the control process of the first optical communication device when the second optical module is hot-plugged with the first optical module in place is introduced, that is, the control process of the hot-plugging of the opposite optical module. The execution subject of this embodiment is the first control module in the first optical communication device.

[0105] In this step, when the second optical module is pulled out with the first optical module in place, the optical signal communication between the first optical module and the second optical module is interrupted, and the electrical signal communication between the first chip and the first optical module is interrupted. The port in the first chip connected to the first optical module enters an electrical idle state.

[0106] S202: After the first control module detects that the first chip enters an electrical idle state through the third control signal, detects that the first optical module is in place through the first control signal, and turns off the power supply of the internal driver of the first optical module and keeps the power supply of the receiving end of the first optical module through the second control signal.

[0107] In this step, after the first control module detects that the first chip enters an electrical idle state through the third control signal and detects that the first optical module is in place through the first control signal, it turns off the power supply of the internal driver of the first optical module and keeps the power supply of the receiving end of the first optical module through the second control signal. Turning off the power supply of the internal driver of the first optical module helps reduce the power consumption of the first optical communication device, and keeping the power supply of the receiving end of the first optical module is to be able to detect whether the second optical module is inserted again.

[0108] S203: The first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is, enter S204; if not, re-enter S203.

[0109] In this step, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal. If not, it means that the second optical module is not inserted, and the S203 state is maintained. If there is, it means that the second optical module is inserted again, and enter S204.

[0110] S204: The first control module restores the power supply of the internal driver of the first optical module through the second control signal.

[0111] In this step, after the second optical module is inserted again, the first control module restores the power supply of the internal driver of the first optical module through the second control signal.

[0112] S205: The first control module detects the status of the driver inside the first optical module through the second control signal, and determines whether the driver inside the first optical module is working properly based on the status of the driver inside the first optical module; if so, proceed to S206; if not, re-enter S205;

[0113] In this step, the first control module detects the status of the driver chip inside the first optical module through the second control signal, determines whether the driver inside the first optical module is working properly based on the status of the driver chip inside the first optical module. If the driver inside the first optical module is working properly, proceed to S206; otherwise, return to S305 to re-detect the status of the driver chip inside the first optical module until the driver inside the first optical module is working properly.

[0114] S206: The first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip and the second chip establish communication.

[0115] In this step, if the driver inside the first optical module is already working properly, the first control module controls the first chip to start link training through the third control signal. During the link training of the first chip, gradually increase the communication rate between the first chip and the second chip until the communication rate between the first chip and the second chip reaches the maximum rate.

[0116] When the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, and the first optical module communicates with the second optical module through optical signals.

[0117] As a feasible implementation, if the second optical module is pulled out and then inserted, when the link training is completed, the first chip communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip and the second chip is restored to the rate before the second optical module was pulled out. In a specific implementation, if the first optical module is pulled out and then inserted, that is, hot-plugged, when the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the second optical module was pulled out.

[0118] The communication control method provided by the embodiment of the present invention, when the second optical module is pulled out and then inserted again, after detecting that the first optical module is in place, the internal driver of the first optical module is working properly, and there is an input optical signal at the receiving end of the first optical module, controls the first chip to start link training, avoiding the first chip starting link training when the first optical module and the second optical module fail to enter the working state normally, resulting in failure to enter the highest rate state supported by the link, so that the communication rate between the first chip and the second chip is restored to the rate before the second optical module is pulled out, avoiding the optical interconnection system running in a speed-reduced state after hot plugging of the optical module.

[0119] The embodiment of the present invention discloses an optical communication control method. Refer to Figure 4 , according to the flowchart of the third optical communication control method shown in an exemplary embodiment, as Figure 4 shown, includes:

[0120] S301: In the case where neither the first optical module nor the second optical module is in place, when the first optical module is inserted, the first control module detects that the first optical module is in place through the first control signal;

[0121] This embodiment introduces the control process of hot plugging both the first optical module and the second optical module from the perspective of the first optical communication device in the above optical interconnection system. The execution subject of this embodiment is the first control module in the first optical communication device.

[0122] In this step, after both the first optical module and the second optical module are pulled out, neither the first optical module nor the second optical module is in place. The port in the first chip connected to the first optical module enters the electrical idle state, and the port in the second chip connected to the second optical module enters the electrical idle state. At this time, the first optical module is inserted first. After the first control module detects that the first optical module is in place through the first control signal, it enters S302.

[0123] S302: The first control module detects the state of the internal driver chip of the first optical module through the second control signal, and judges whether the internal driver of the first optical module is working properly according to the state of the internal driver chip of the first optical module; if so, it enters S303; if not, it re-enters S302;

[0124] In this step, the first control module detects the state of the internal driver chip of the first optical module through the second control signal, and judges whether the internal driver of the first optical module is working properly according to the state of the internal driver chip of the first optical module. If the internal driver of the first optical module is working properly, it enters S303, otherwise it re-enters S302 to re-detect the state of the internal driver chip of the first optical module until the internal driver of the first optical module is working properly.

[0125] S303: The first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if so, proceed to S304; if not, re-enter S303;

[0126] In this step, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal. If not, it indicates that the second optical module is not inserted, and the S303 state is maintained. If there is an input optical signal, it indicates that the second optical module is inserted again, and proceed to S304.

[0127] It should be noted that after the second optical module is inserted again, after the second control module in the second optical communication device detects that the second optical module is in place through the first control signal, the second control module detects the state of the driver chip inside the second optical module through the second control signal, and determines whether the driver inside the second optical module is working properly based on the state of the driver chip inside the second optical module; if so, the second control module controls the port corresponding to the second chip to exit the electrical idle state through the third control signal, and the second optical module can send an optical signal to the first optical module, that is, there is an input optical signal at the receiving end of the first optical module.

[0128] S304: The first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip and the second chip establish communication.

[0129] In this step, if there is an input optical signal at the receiving end of the first optical module, the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. During the link training process, the communication rate between the first chip and the second chip is gradually increased until the communication rate between the first chip and the second chip reaches the highest rate. When the link training is completed, the first chip in the first optical communication device communicates with the first optical module through an electrical signal, and the first optical module and the second optical module communicate with each other through an optical signal.

[0130] As a feasible implementation manner, if both the first optical module and the second optical module are inserted after being pulled out, when the link training is completed, the first chip communicates with the first optical module through an electrical signal, the first optical module and the second optical module communicate with each other through an optical signal, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are pulled out. In a specific implementation, if the first optical module and the second optical module are inserted after being pulled out, that is, hot-swapped, when the link training is completed, the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are pulled out.

[0131] It can be seen that in this embodiment, by detecting the in-place state of the optical module, the state of the internal driver chip, and the state of the receiving end, judging the optical link state according to the in-place state of the optical module and the state of the receiving end, and controlling whether to start link training for the corresponding chip according to the state of the internal driver chip of the optical module, the function of hot plugging the optical modules at both ends of the optical interconnection link can be realized. Confirm that the local optical module has entered the normal working state according to the in-place state of the optical module and the state of the internal chip, and judge that the remote optical module has entered the normal working state according to the state of the receiving end of the optical module, so as to control the local chip to start link training, thus avoiding the chip from starting link training when the optical module link fails to enter the normal working state and resulting in failure to enter the highest rate state supported by the link, and thus avoiding the system from running in the speed reduction state.

[0132] Next, an optical communication control device provided by an embodiment of the present invention will be introduced. It is applied to the first optical communication device in the above optical interconnection system. An optical communication control device described below can be referred to each other with an optical communication control method described above.

[0133] See Figure 5 , a structural diagram of an optical communication control device shown according to an exemplary embodiment, as Figure 5 shown, includes:

[0134] A first detection unit 100, configured to detect that the first optical module is in place through a first control signal when the first optical module is inserted after being pulled out in the case where the first optical module is not in place and the second optical module is in place; wherein, the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in a second optical communication device connected to the first optical communication device;

[0135] A first judgment unit 200, configured to detect the state of the internal driver chip of the first optical module through a second control signal, and judge whether the internal driver of the first optical module is working normally according to the state of the internal driver chip of the first optical module; if so, start the working process of the first control unit;

[0136] A first control unit 300, configured to control a port of a first chip in the first optical communication device to exit the electrical idle state through a third control signal, control the first chip in the first optical communication device to start link training, and after the link training is completed, establish communication between the first chip in the first optical communication device and a second chip in the second optical communication device.

[0137] In the communication control device provided by the embodiment of the present invention, when the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, the first control module in the first optical communication device controls the first chip to start link training after detecting that the first optical module is in place and the internal driver of the first optical module is working properly, avoiding the situation that the first chip starts link training when the first optical module fails to enter the normal working state and thus fails to enter the highest rate state supported by the link, enabling the communication rate between the first chip and the second chip to reach the maximum rate through training, and avoiding the optical interconnection system from operating in a speed-reduced state.

[0138] Based on the above embodiment, as a preferred embodiment, it further includes:

[0139] A training unit, configured to improve the communication rate between the first chip and the second chip during the link training process of the first chip.

[0140] Based on the above embodiment, as a preferred embodiment, it further includes:

[0141] A second control unit, configured to, when the first optical module and the second optical module are both in place, after the first optical module is pulled out, the port corresponding to the first chip enters the electrical idle state, and the first control module detects that the first optical module is not in place through the first control signal, and controls the first chip to stop the receive-end detection through the third control signal.

[0142] Based on the above embodiment, as a preferred embodiment, if the first optical module is pulled out and then inserted, after the link training is completed, the first chip in the first optical communication device communicates with the first optical module through electrical signals, the first optical module and the second optical module communicate with each other through optical signals, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module is pulled out.

[0143] Based on the above embodiment, as a preferred embodiment, it further includes:

[0144] A second detection unit, configured to, when the first optical module is in place and the port corresponding to the first chip enters the electrical idle state, the first control module detects whether there is an input optical signal at the receive end of the first optical module through the second control signal; if so, start the working process of the power supply unit;

[0145] A power supply restoration unit, configured to restore the power supply of the internal driver of the first optical module by the first control module through the second control signal;

[0146] A second judgment unit, configured to detect the status of the driver inside the first optical module through a second control signal, and judge whether the driver inside the first optical module is working properly according to the status of the driver inside the first optical module; if so, start the working process of the third control unit;

[0147] A third control unit, configured to control the port corresponding to the first chip to exit the electrical idle state and start link training through a third control signal. After the link training is completed, the first chip and the second chip resume communication.

[0148] Based on the above embodiments, as a preferred implementation manner, it further includes:

[0149] A power supply unit shutdown, configured to, after detecting that the first chip enters the electrical idle state through the third control signal, detect that the first optical module is in place through the first control signal, and turn off the power supply of the driver inside the first optical module and keep the power supply of the receiving end of the first optical module through the second control signal.

[0150] Based on the above embodiments, as a preferred implementation manner, if the second optical module is pulled out and then inserted, after the link training is completed, the first chip and the first optical module communicate through electrical signals, the first optical module and the second optical module communicate through optical signals, and the communication rate between the first chip and the second chip resumes to the rate before the second optical module is pulled out.

[0151] Based on the above embodiments, as a preferred implementation manner, it further includes:

[0152] A third detection unit, configured to, when neither the first optical module nor the second optical module is in place, detect that the first optical module is in place through the first control signal after the first optical module is inserted;

[0153] A third judgment unit, configured to detect the status of the driver chip inside the first optical module through the second control signal, and judge whether the driver inside the first optical module is working properly according to the status of the driver chip inside the first optical module; if so, start the working process of the fourth detection unit;

[0154] A fourth detection unit, configured to detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if so, start the working process of the fourth control unit;

[0155] A fourth control unit, configured to control the first chip to exit the electrical idle state and start link training through the third control signal. After the link training is completed, the first chip and the second chip resume communication.

[0156] Based on the above embodiments, as a preferred embodiment, if both the first optical module and the second optical module are inserted after being pulled out, after the link training is completed, the first chip communicates with the first optical module through electrical signals, the first optical module communicates with the second optical module through optical signals, and the communication rate between the first chip and the second chip resumes to the rate before the first optical module and the second optical module are pulled out.

[0157] Regarding the device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0158] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiments of the present invention, the embodiments of the present invention further provide an electronic device. Figure 6 The structure diagram of an electronic device shown according to an exemplary embodiment is as Figure 6 shown. The electronic device includes:

[0159] Communication interface 1, capable of interacting with other devices such as network devices for information.

[0160] Processor 2, connected to the communication interface 1 to achieve information interaction with other devices, and is used to execute the optical communication control method provided by the above one or more technical solutions when running a computer program. The computer program is stored on the memory 3.

[0161] Of course, in actual applications, the various components in the electronic device are coupled together through the bus system 4. It can be understood that the bus system 4 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in Figure 6 all the buses are labeled as the bus system 4.

[0162] The memory 3 in the embodiments of the present invention is used to store various types of data to support the operation of the electronic device. Examples of these data include: any computer program for operating on the electronic device.

[0163] It can be understood that the memory 3 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), an erasable programmable read-only memory (EPROM, Erasable Programmable Read-Only Memory), an electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), a ferromagnetic random access memory (FRAM, ferromagnetic random access memory), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM, Compact Disc Read-Only Memory); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM, Random Access Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as a static random access memory (SRAM, Static Random Access Memory), a synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory), a dynamic random access memory (DRAM, Dynamic Random Access Memory), a synchronous dynamic random access memory (SDRAM, Synchronous Dynamic Random Access Memory), a double data rate synchronous dynamic random access memory (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory), an enhanced synchronous dynamic random access memory (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), a sync link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and a direct rambus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 3 described in the embodiments of the present invention is intended to include, but not limited to, these and any other suitable types of memories.

[0164] The method disclosed in the above embodiments of the present invention can be applied to the processor 2 or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 2 or by instructions in the form of software. The above-mentioned processor 2 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 2 can implement or execute each method, step, and logic block diagram disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the method disclosed in the embodiments of the present invention can be directly embodied as being executed and completed by the hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, and this storage medium is located in the memory 3. The processor 2 reads the program in the memory 3 and combines its hardware to complete the steps of the foregoing method.

[0165] When the processor 2 executes the program, it implements the corresponding processes in each method of the embodiments of the present invention. For the sake of brevity, it will not be elaborated here.

[0166] In an exemplary embodiment, the embodiments of the present invention also provide a non-volatile storage medium storing a computer program that can be executed by the processor 2 to complete the foregoing method steps.

[0167] In an exemplary embodiment, the embodiments of the present invention also provide a computer program product including a computer program that is executed by the processor 2 to complete the foregoing method steps.

[0168] Those of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed by hardware related to computer program instructions. The foregoing computer program can be stored in a non-volatile storage medium. When the computer program is executed, it executes the steps including the above method embodiments. Or, if the above integrated unit is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a non-volatile storage medium. Based on such an understanding, the technical solution of the embodiments of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a non-volatile storage medium and includes several instructions for causing an electronic device (which may be a personal computer, a server, a network device, etc.) to execute all or part of the methods of the various embodiments of the present invention.

[0169] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention.

Claims

1. An optical interconnection system, characterized in that, It includes a first optical communication device and a second optical communication device. The first optical communication device includes a first chip, a first optical module, and a first control module that are interconnected. The second optical communication device includes a second chip, a second optical module, and a second control module that are interconnected. The first optical communication device is connected to the second optical communication device through the first optical module and the second optical module, and optical signal communication is carried out between the first optical module and the second optical module. The first control module is used, when the first optical module is not in place and the second optical module is in place, after the first optical module is inserted, to detect that the first optical module is in place through a first control signal, to detect the state of the driver chip inside the first optical module through a second control signal, and to judge whether the driver inside the first optical module is working properly according to the state of the driver chip inside the first optical module, and to judge whether the second optical module has entered the normal working state according to the receiving end state of the first optical module. If both are the case, then control the port corresponding to the first chip to exit the electrical idle state through a third control signal, control the first chip to start link training. During the link training process of the first chip, gradually increase the communication rate between the first chip and the second chip until the communication rate between the first chip and the second chip reaches the maximum rate. When the link training is completed, the first chip and the second chip establish communication.

2. The optical interconnection system according to claim 1, characterized in that, When the first optical module and the second optical module are both in place, when the first optical module is pulled out, the port corresponding to the first chip enters the electrical idle state. The first control module is further used to: detect that the first optical module is not in place through a first control signal, and control the first chip to stop the receiving end detection through a third control signal.

3. The optical interconnection system according to claim 1, wherein The first control module is further used to: when the first optical module is in place and the port corresponding to the first chip enters the electrical idle state, detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal. If there is, then restore the power supply of the driver inside the first optical module through the second control signal; detect the state of the driver inside the first optical module through the second control signal, and judge whether the driver inside the first optical module is working properly according to the state of the driver inside the first optical module. If it is, then control the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. When the link training is completed, the first chip and the second chip establish communication.

4. The optical interconnection system according to claim 3, wherein When the first optical module and the second optical module are both in place, when the second optical module is pulled out, the port corresponding to the first chip enters the electrical idle state. The first control module is further used to: after detecting that the first chip has entered the electrical idle state through the third control signal, detect that the first optical module is in place through the first control signal, and turn off the power supply of the driver inside the first optical module and keep the power supply of the receiving end of the first optical module through the second control signal.

5. The optical interconnection system according to claim 1, wherein The first control module is further configured to: when neither the first optical module nor the second optical module is in place, after the first optical module is inserted, detect that the first optical module is in place through the first control signal; detect the status of the driver chip inside the first optical module through the second control signal, and determine whether the driver inside the first optical module is working properly according to the status of the driver chip inside the first optical module; if so, detect whether there is an input optical signal at the receiving end of the first optical module through the second control signal; if there is, control the first chip to exit the electrical idle state and start link training through the third control signal, and after the link training is completed, establish communication between the first chip and the second chip.

6. The optical interconnection system according to claim 1, wherein The first control module is connected to the in-place pin of the first optical module through the first control signal, the first control module is connected to the integrated circuit pin of the first optical module through the second control signal, the first control module is connected to the integrated circuit pin and / or the serial communication pin of the first chip through the third control signal, and the serial communication pin includes a serial data bus pin and / or a universal asynchronous receiver / transmitter serial communication pin.

7. The optical interconnection system according to claim 1, wherein The first control module is integrated inside the first chip, or the first control module is a chip independent of the first chip; If the first control module is a chip independent of the first chip, the first control module includes a complex programmable logic device and / or a field programmable gate array.

8. A method for optical communication control, characterized in that, Applied to a first optical communication device, the method includes: When the first optical module is not in place and the second optical module is in place, when the first optical module is inserted, the first control module in the first optical communication device detects that the first optical module is in place through the first control signal; wherein, the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in a second optical communication device connected to the first optical communication device; The first control module detects the status of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module is working properly according to the status of the driver chip inside the first optical module, and determines whether the second optical module enters the normal working state according to the receiving end status of the first optical module; If both are the case, the first control module controls the port corresponding to the first chip in the first optical communication device to exit the electrical idle state through the third control signal, controls the first chip in the first optical communication device to start link training, and during the link training process of the first chip, increases the communication rate between the first chip and the second chip in the second optical communication device until the communication rate between the first chip and the second chip reaches the highest rate, and after the link training is completed, establish communication between the first chip and the second chip.

9. The optical communication control method according to claim 8, characterized in that Further included: When the first optical module and the second optical module are both in place, after the first optical module is pulled out, the port corresponding to the first chip enters an electrical idle state. The first control module detects that the first optical module is not in place through the first control signal, and controls the first chip to stop the receive-end detection through the third control signal.

10. The optical communication control method according to claim 9, characterized in that, If the first optical module is pulled out and then inserted, after the link training is completed, the first chip in the first optical communication device establishes communication with the second chip in the second optical communication device, including: After the link training is completed, the first chip in the first optical communication device communicates with the first optical module through an electrical signal, the first optical module communicates with the second optical module through an optical signal, and the communication rate between the first chip in the first optical communication device and the second chip in the second optical communication device is restored to the rate before the first optical module was pulled out.

11. The optical communication control method according to claim 8, wherein, It further includes: When the first optical module is in place and the port corresponding to the first chip enters an electrical idle state, the first control module detects whether there is an input optical signal at the receive end of the first optical module through the second control signal; If there is, the first control module restores the power supply of the internal driver of the first optical module through the second control signal; The first control module detects the state of the internal driver of the first optical module through the second control signal, and determines whether the internal driver of the first optical module is working properly according to the state of the internal driver of the first optical module; If so, the first control module controls the port corresponding to the first chip to exit the electrical idle state and start link training through the third control signal. After the link training is completed, the first chip establishes communication with the second chip.

12. The optical communication control method according to claim 11, wherein, It further includes: When the first optical module and the second optical module are both in place, after the second optical module is pulled out, the port corresponding to the first chip enters an electrical idle state; After the first control module detects that the first chip enters the electrical idle state through the third control signal, it detects that the first optical module is in place through the first control signal, and turns off the power supply of the internal driver of the first optical module and keeps the power supply of the receive end of the first optical module through the second control signal.

13. The optical communication control method according to claim 12, wherein If the second optical module is pulled out and then inserted, after the link training is completed, the first chip establishes communication with the second chip, including: After the link training is completed, the first chip communicates with the first optical module through an electrical signal, the first optical module communicates with the second optical module through an optical signal, and the communication rate between the first chip and the second chip is restored to the rate before the second optical module was pulled out.

14. The optical communication control method according to claim 8, wherein It further includes: When the first optical module and the second optical module are both not in place, after the first optical module is inserted, the first control module detects that the first optical module is in place through the first control signal; The first control module detects the status of the driver chip inside the first optical module through the second control signal, and determines whether the driver inside the first optical module is working properly according to the status of the driver chip inside the first optical module; If so, the first control module detects whether there is an input optical signal at the receiving end of the first optical module through the second control signal; If there is, the first control module controls the first chip to exit the electrical idle state and start link training through the third control signal. After the link training is completed, the first chip establishes communication with the second chip.

15. The optical communication control method according to claim 14, wherein If both the first optical module and the second optical module are inserted after being pulled out, after the link training is completed, the first chip establishes communication with the second chip, including: After the link training is completed, the first chip communicates with the first optical module through an electrical signal, the first optical module communicates with the second optical module through an optical signal, and the communication rate between the first chip and the second chip is restored to the rate before the first optical module and the second optical module are pulled out.

16. An optical communication control device, characterized in that, Applied to a first optical communication device, the device includes: A first detection unit, configured to, when the first optical module is not in place and the second optical module is in place, detect that the first optical module is in place through a first control signal when the first optical module is inserted after being pulled out; wherein, the first optical module is an optical module in the first optical communication device, and the second optical module is an optical module in a second optical communication device connected to the first optical communication device; A first judgment unit, configured to detect the status of the driver chip inside the first optical module through a second control signal, and determine whether the driver inside the first optical module is working properly according to the status of the driver chip inside the first optical module and determine whether the second optical module enters the normal working state according to the receiving end status of the first optical module; if both are, start the working process of the first control unit; A first control unit, configured to control the port corresponding to the first chip in the first optical communication device to exit the electrical idle state through a third control signal, control the first chip in the first optical communication device to start link training, and increase the communication rate between the first chip and the second chip in the second optical communication device during the link training process of the first chip until the communication rate between the first chip and the second chip reaches the highest rate. After the link training is completed, the first chip establishes communication with the second chip.

17. An electronic device, characterized in that, Including: A memory, configured to store a computer program; A processor, configured to implement the steps executed by the optical communication control method according to any one of claims 8 to 15 when executing the computer program.

18. A non-volatile storage medium, characterized in that, A computer program is stored on the non-volatile storage medium, and when the computer program is executed, the steps executed by the optical communication control method according to any one of claims 8 to 15 are implemented.

19. A computer program product, characterized in that, Including a computer program, and when the computer program is executed, the steps executed by the optical communication control method according to any one of claims 8 to 15 are implemented.

Images