Base station fronthaul interface encapsulation processor and message encapsulation method

Abstract

The present invention provides a base station front-haul interface encapsulation processor and a message encapsulation method, belonging to the field of communication technology, wherein the processor comprises: a data integration module, an operation module, a register group module composed of a plurality of registers, a block transfer module and a cache; the data integration module compresses the data width and size of the message data to be sent according to the pre-configured data integration control word; the operation module generates a block transfer control word and a header based on the control information processing result of the message data to be sent under the drive of the encapsulation instruction sequence, and the block transfer module moves the compressed message data from the cache to the register group module based on the block transfer control word to send the compressed message data until the sending of one message data is completed. The present invention configures the control word for realizing block transfer in the processor through the operation module, constructs a new architecture for ASIP and accelerator to collaboratively encapsulate message data, and realizes a high-speed and high-throughput processor under the front-haul interface message data encapsulation.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a base station fronthaul interface encapsulation processor and a message encapsulation method. Background Art

[0002] The fronthaul interface is the data transmission bridge between the air interface and the base station processing unit. The performance of the fronthaul interface processor in encapsulating message data will affect the execution effect of the upper-layer application software.

[0003] Currently, network processors that support the eCPRI protocol, O-RAN protocol, and similar protocols generally have the disadvantages of high cost, slow processing speed, and can only support relatively small data throughput when encapsulating message data.

[0004] Therefore, it is necessary to provide a low-cost, high-speed, and high-throughput base station fronthaul interface encapsulation processor. Summary of the invention

[0005] The present invention provides a base station fronthaul interface encapsulation processor and a message encapsulation method, which are used to solve the defects of the network processor in the prior art, such as high cost, slow processing speed and only supporting relatively small data throughput, and realize a low-cost, high-speed and large-throughput base station fronthaul interface encapsulation processor.

[0006] The present invention provides a base station fronthaul interface encapsulation processor, comprising: a data integration module, a calculation module, a register group module composed of a plurality of registers, a block moving module and a cache;

[0007] The data integration module is used to compress the data bit width and size of the message data to be sent according to the pre-configured data integration control word after responding to the packet sending request signal of the uplink transmission, and write the compressed message data into the cache;

[0008] The operation module is used to process the control information of the message data to be sent under the drive of the encapsulation instruction sequence, and generate a block movement control word and a header of the message data to be sent based on the control information processing result; the encapsulation instruction sequence is composed of a plurality of special processing instructions in the special processing instruction set;

[0009] The register group module is used to temporarily store the calculation results of the operation module and send the header after responding to the timing sending signal;

[0010] The block moving module is used to move the compressed message data from the cache to the register group module based on the block moving control word until the sending of one message data is completed.

[0011] According to a base station fronthaul interface encapsulation processor provided by the present invention, the register group module is mapped with a data input interface and a data output interface, the data input interface and the data output interface are externally connected to a sending link, and the register group module and the sending link complete data writing based on a hardware handshake method.

[0012] According to a base station fronthaul interface encapsulation processor provided by the present invention, the data integration control word includes a first initial cache address control word, a first data length control word, a register number control word, a compression bit width control word and a compression method control word;

[0013] The step of compressing the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and writing the compressed message data into the cache comprises:

[0014] Extracting the message data to be sent from the target register corresponding to the register number control word in the register group module, compressing the data bit width and size of the message data to be sent according to the compression bit width corresponding to the compression bit width control word and the compression method corresponding to the compression method control word, and removing redundant bits so that the message data to be sent are closely arranged, thereby obtaining the compressed message data;

[0015] The compressed message data is sequentially written into the cache using the cache address corresponding to the first initial cache address control word as the storage space of the initial cache address until the data length of the message data to be sent extracted from the target register is equal to the data length corresponding to the first data length control word.

[0016] According to a base station fronthaul interface encapsulation processor provided by the present invention, the block move control word includes a second initial cache address control word, a second data length control word, a register initial number control word and a register quantity control word;

[0017] The step of moving the compressed message data from the cache to the register group module based on the block move control word includes:

[0018] sequentially moving the compressed message data from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, and cyclically writing the compressed message data into the target register until the length of the message data being moved is equal to the data length corresponding to the second data length control word;

[0019] The target register is a register determined from the register group module based on the register initial number control word and the register quantity control word; the first register in the target register is the initial register corresponding to the register initial number control word.

[0020] According to a base station fronthaul interface encapsulation processor provided by the present invention, the block move control word further includes a low byte number control word and a high byte number control word;

[0021] The method of sequentially moving the compressed message data from the storage space in the cache using the cache address corresponding to the second initial cache address control word as the initial cache address, and cyclically writing the compressed message data into the target register includes:

[0022] Based on the low byte number control word, determining a first byte number;

[0023] Determining a second byte number based on the high byte number control word;

[0024] sequentially moving the compressed message data from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, using the low byte data of the first byte number in the message data of the previous address to be moved as the high-order data, and using the high byte data of the second byte number in the message data of the next address to be moved as the low-order data;

[0025] Sequentially splicing the high-order data and the low-order data to obtain spliced ​​message data;

[0026] The spliced ​​message data is cyclically written into the target register.

[0027] According to a base station fronthaul interface encapsulation processor provided by the present invention, each dedicated processing instruction in the dedicated processing instruction set is configured with a calculation method of the dedicated processing instruction, a bit starting position of two operands, a bit length and a target position;

[0028] The operation module comprises: a first masker, a second masker, a first shifter, a second shifter and an operator;

[0029] The first masker is used to perform a mask operation on one of the operands using a first mask to obtain a first mask result; the first mask is determined based on a bit starting position and a bit length of the one operand;

[0030] The second masker is used to perform a mask operation on another operand using a second mask to obtain a second mask result; the second mask is determined based on a bit starting position and a bit length of the other operand;

[0031] The first shifter is used to shift the first mask result based on the target position of the first operand to obtain a first shift result;

[0032] The second shifter is used to shift the second mask result based on the target position of the other operand to obtain a second shift result;

[0033] The operator is used to operate the first shift result and the second shift result based on the calculation method to obtain the operation result and complete the execution of the special processing instruction.

[0034] According to a base station fronthaul interface encapsulation processor provided by the present invention, the dedicated processing instruction set includes data change instructions, bit operation instructions and bit arbitration instructions.

[0035] A base station fronthaul interface encapsulation processor according to the present invention also includes a slow channel processing module;

[0036] The slow channel processing module is used for not performing accelerated encapsulation processing on the message data to be sent when the message data to be sent is management package message data.

[0037] A base station fronthaul interface encapsulation processor according to the present invention also includes: a program control module, an instruction storage module, a decoder module and a check module; the check module includes a checksum generation module and a cyclic redundancy check sequence generation module;

[0038] The program control module is used to manage program counts and arbitrate program count change requests sent by various modules of the base station fronthaul interface encapsulation processor;

[0039] The instruction storage module is used to store the encapsulated instruction sequence;

[0040] The decoder module is used to decode the encapsulation instruction in the encapsulation instruction sequence and distribute the decoding results to the various modules of the base station front transmission interface encapsulation processor to drive the various modules to work;

[0041] The checksum generation module is used to complete the generation calculation of the checksum of the message data to be sent;

[0042] The cyclic redundancy check sequence generation module is used to complete the generation calculation of the cyclic redundancy check sequence of the message data to be sent.

[0043] The present invention also provides a message encapsulation method based on any of the above-mentioned base station fronthaul interface encapsulation processors, comprising:

[0044] After responding to the packet request signal of the uplink transmission, the control data integration module compresses the data width and size of the message data to be sent according to the pre-configured data integration control word, and writes the compressed message data into the cache; the register group module includes a plurality of registers;

[0045] The control operation module processes the control information of the message data to be sent under the drive of the encapsulation instruction sequence, and generates a block movement control word and a header of the message data to be sent based on the control information processing result; the encapsulation instruction sequence is composed of a number of special processing instructions in the special processing instruction set;

[0046] The control register group module temporarily stores the calculation result of the operation module, and sends the header after responding to the timing sending signal;

[0047] The control block transfer module transfers the compressed message data from the cache to the register group module based on the block transfer control word until the sending of one message data is completed.

[0048] The base station fronthaul interface encapsulation processor and message encapsulation method provided by the present invention processes message data under the drive of an encapsulation instruction sequence obtained by flexible programming based on a dedicated processing instruction set by a computing module, and generates a control word for realizing a block moving function, that is, a control word for realizing a block moving function in an ASIP configuration processor is constructed in the processor, a new architecture for collaboratively encapsulating message data by an ASIP and an accelerator is constructed, the cost is low, the rate of special functions such as a block moving function in a message data parsing process can be increased, thereby improving the processing speed of message data encapsulation and meeting the real-time requirements of message processing at the same time, and realizing a base station fronthaul interface message data encapsulation processor and a message encapsulation method. The invention relates to a high-speed, high-throughput processor in the data encapsulation scenario; by using a dedicated processing instruction set when pre-programming the encapsulation instruction sequence, the number of encapsulation instructions that operators need to program when encapsulating message data can be reduced, thereby reducing instruction overhead and increasing the message data encapsulation speed; by sending message data through the register group module, the timing of message data encapsulation can be optimized and the programming difficulty of the encapsulation instruction sequence can be simplified; by writing the compressed message data to be sent into the cache through the data integration module, and using the register group module to send the message data only after waiting for the timing sending signal, the network jitter of data processing can be overcome and the timing requirements of the 5G fronthaul interface and the wireless system can be met. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 This is one of the structural schematic diagrams of the base station fronthaul interface encapsulation processor provided by the present invention.

[0051] Figure 2It is a schematic diagram of the process of encapsulating message data provided by the present invention.

[0052] Figure 3 This is an example diagram of splicing message data to be sent provided by the present invention.

[0053] Figure 4 This is an example diagram of aligning message data to be sent provided by the present invention.

[0054] Figure 5 It is a structural schematic diagram of the operation module provided by the present invention.

[0055] Figure 6 This is the second structural schematic diagram of the base station fronthaul interface encapsulation processor provided by the present invention.

[0056] Figure 7 It is a flow chart of a message encapsulation method based on a base station fronthaul interface encapsulation processor provided by the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] It should be noted that, in the description of the present invention, the term "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0059] The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0060] Combine the following Figure 1-Figure 7The present invention describes a base station fronthaul interface encapsulation processor and a message encapsulation method.

[0061] Application Specific Instruction Set Processor (ASIP), also known as a dedicated processor, is a programmable platform that is customized for a specific operation or a certain type of algorithm. It has both software programming capabilities and is oriented to accelerated processing in a specific field. It can use the same chip on multiple related applications, different versions of applications, and even future applications. It has the advantages of sharing the chip design cost on a large number of chips, having enough functions and flexibility to deal with chip modifications during product development, and extending the product life cycle. ASIP is often programmed for specific fields and has strong specialization. It has a significant performance improvement over general-purpose processors.

[0062] Corresponding to ASIP, Application Specific Integrated Circuit (ASIC) is specially used to implement a certain type of customized circuit algorithm. In comparison, ASIC has higher performance but poorer flexibility, while ASIP has slightly lower performance than ASIC but has greater flexibility.

[0063] In the design and implementation of LTE (Long Time Evolution) and 5G NR (New Radio), the baseband processing unit (Building Baseband Unit, BBU) and the remote radio unit (Remote Radio Unit, RRU) are usually split and connected using optical fiber. The interface between the RRU and BBU is called the fronthaul interface.

[0064] Common fronthaul interfaces include Common Public Radio Interface (CPRI) and enhanced CPRI (eCPRI). The CPRI protocol is block-based data transmission, and its application scenarios are relatively simple. In addition, there are a large number of custom fields, which makes the CPRI protocol poorly adaptable. Compared with the CPRI protocol, the eCPRI protocol is used in the implementation of 5G. The eCPRI protocol is carried on the Ethernet, MAC layer or TCP / IP layer to integrate the eCPRI protocol into the TCP / IP protocol family. Compared with the proprietary CPRI protocol, the universality of the eCPRI protocol allows the RRU to no longer be attached to the BBU, thus acting as an independent network element. The network management center can directly manage the RRU, and no longer needs to rely on the BBU to manage the RRU. The protocol between the BBU and the RRU can be standardized, which provides an architectural guarantee for the interconnection and interoperability of BBU and RRU from different manufacturers, and greatly improves the universality.

[0065] The Open Radio Access Network (O-RAN) protocol is a specific implementation of the eCPRI protocol. The eCPRI protocol is only a transport layer protocol and does not define application layer protocol specifications such as IQ data format and real-time control plane data format above the service access point. The O-RAN protocol defines in detail the specific usage details when used as the fronthaul interface of NR, making the fronthaul interface implemented using the O-RAN protocol have good adaptability.

[0066] The eCPRI protocol and O-RAN protocol have the following characteristics when applied: First, both the eCPRI protocol and the O-RAN protocol are relatively new, and there are not many hardware devices that can support the eCPRI protocol and the O-RAN protocol (such as those based on FAGA implementation), but both have the defects of high cost, slow processing speed and can only support relatively small data throughput; second, the eCPRI protocol and the O-RAN protocol are in the process of continuous evolution. If ASIC is used, the form risk is high and it is difficult to cope with subsequent protocol upgrades; third, the eCPRI protocol and the O-RAN protocol work on the fronthaul interface, which is the transmission bridge between the air interface and the base station processing unit data, requiring high real-time and high accuracy that traditional network processors cannot achieve; finally, due to the characteristics of the fronthaul interface service, in order to reduce the complexity of hardware design, improve the data transmission efficiency of the fronthaul interface, and reduce the system bandwidth, the message data of the fronthaul interface will be compressed before transmission, resulting in changes in the data bit width and size of the message data, and the boundary of the message data is no longer aligned with the transmission bit width, which requires that when encapsulating the message data, the network processor needs to have the ability to load non-aligned data.

[0067] In view of the characteristics of the eCPRI protocol and the O-RAN protocol in their applications, the processor that supports the eCPRI protocol and the O-RAN protocol needs to achieve at least one of the following requirements: (1) high speed and large throughput. Taking the fronthaul interface of the 5G NR 4-transmit 4-receive small base station as an example, the processor needs to achieve at least an average throughput of 10 Gbps and support the processing capability of 60 Gbps burst throughput; (2) support source message data compression and transmission; (3) support message data reordering.

[0068] In view of this, the base station fronthaul interface encapsulation processor provided by the present invention is a network processor (NP) based on ASIP, which can support the message encapsulation work of the eCPRI protocol, O-RAN protocol and similar protocols when working on the base station fronthaul interface, and can process data packets and data frames in the network in real time at line speed, and can be widely used in scenarios where message data needs to be encapsulated in the fields of mobile communications, broadband communications, industrial control, etc.

[0069] Figure 1 This is one of the structural diagrams of the base station fronthaul interface encapsulation processor provided by the present invention, such as Figure 1 As shown, the base station fronthaul interface encapsulation processor includes but is not limited to a data integration module 101, a calculation module 102, a register group module 103 composed of multiple registers, a block transfer module 104 and a cache 105. The solid arrows represent the data flow direction of the message data, and the dotted arrows represent the data flow direction of the control word.

[0070] The data integration module 101 is used to compress the data bit width and size of the message data to be sent according to the pre-configured data integration control word after responding to the packet sending request signal of the uplink transmission, and write the compressed message data into the cache 105.

[0071] The operation module 102 is used to process the control information of the message data to be sent under the drive of the encapsulation instruction sequence, and generate a block movement control word and a header of the message data to be sent based on the control information processing result.

[0072] The register group module 103 is used to temporarily store the calculation results of the operation module and send a header after responding to the timing sending signal.

[0073] The block transfer module 104 is used to transfer the compressed message data from the cache 105 to the register group module 103 based on the block transfer control word until the transmission of one message data is completed.

[0074] The encapsulated instruction sequence is composed of a number of special processing instructions in a special processing instruction set.

[0075] When processing the message data encapsulation task, it is necessary to pre-program the various protocols used by the message data, and then obtain an encapsulation instruction sequence consisting of several encapsulation instructions to drive each module of the base station fronthaul interface encapsulation processor to process the message data. When processing message data based on the base station fronthaul interface encapsulation processor, the encapsulation instruction sequence will be composed of several special processing instructions in a pre-set special processing instruction set.

[0076] The number of special processing instructions involved in the encapsulation instruction sequence and the number of times of repeated use are determined according to the specific message data encapsulation task, and the present invention does not impose any limitation on this.

[0077] The data integration control word is a control word that controls the data integration module to carry the message data to be sent.

[0078] The block transfer control word is a control word that controls the block transfer module to transfer the message data to be sent.

[0079] Timing packet signals are used for precise timing of wireless communication systems.

[0080] Specifically, Figure 2 It is a schematic diagram of the process of encapsulating message data provided by the present invention, such as Figure 2 As shown, after the base station fronthaul interface encapsulation processor starts working, it polls and receives the packet request signal transmitted by the uplink every time there is new data to be sent. After responding to the packet request signal, the data integration module 101 starts to compress the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and writes the compressed message data into the cache 105.

[0081] Driven by the encapsulation instruction sequence, the operation module 102 extracts the control information of the message data to be sent for processing, and generates a block movement control word and a header of the message data to be sent according to the control information processing result. The register group module 103 temporarily stores the calculation results such as the block movement control word and the header of the message data to be sent generated by the operation module 102.

[0082] Waiting for the timing sending signal, after receiving the timing sending signal, the operation module 102 sends the header of the message data to be sent through the register group module 103; the block moving module 104 moves the compressed message data from the cache 105 to the register group module 103 based on the block moving control word, and sends the compressed message data through the register group module 103 until the sending of a message data (such as an eCPRI message or an O-RAN message) is finally completed, thereby completing the encapsulation of the currently processed message data.

[0083] Furthermore, after completing the encapsulation of the currently processed message data, the base station fronthaul interface encapsulation processor continues to poll and receive the packet request signal of the uplink transmission, and after receiving the next packet request signal and responding, the data integration module 101 compresses the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and starts the step of writing the compressed message data into the cache 105 to encapsulate the next message data.

[0084] The base station fronthaul interface encapsulation processor provided by the present invention processes message data under the drive of the encapsulation instruction sequence obtained by flexible programming based on the dedicated processing instruction set by the operation module, and generates a control word for realizing the block moving function, that is, the control word for realizing the block moving function in the ASIP configuration processor is constructed in the processor. A new architecture for ASIP and ASIC to cooperate in encapsulating message data is constructed, which has low cost and can improve the rate of special functions such as the block moving function in the message data parsing process, thereby improving the processing speed of message data encapsulation and meeting the real-time requirements of message processing at the same time, and realizing a base station fronthaul interface message data encapsulation. A high-speed, high-throughput processor for scenarios; by using a dedicated processing instruction set when pre-programming the encapsulation instruction sequence, the number of encapsulation instructions that operators need to program when encapsulating message data can be reduced, reducing instruction overhead and increasing the message data encapsulation speed; by sending message data through the register group module, the timing of message data encapsulation can be optimized and the programming difficulty of the encapsulation instruction sequence can be simplified; by writing the compressed message data to be sent into the cache through the data integration module, and using the register group module to send the message data after waiting for the timing sending signal, the network jitter of data processing can be overcome and the timing requirements of the 5G fronthaul interface and wireless system can be met.

[0085] Based on the above embodiment, as an optional embodiment, the register group module is mapped with a data input interface and a data output interface, the data input interface and the data output interface are externally connected to a sending link, and the register group module and the sending link complete data writing based on a hardware handshake method.

[0086] Optionally, the register group module and the sending link complete data writing based on a handshake method of a hardware Semaphone.

[0087] Specifically, after responding to the timing transmission signal, the header of the message data to be transmitted and the compressed message data can be directly sent out as a complete assembled packet message through the data input interface and data output interface mapped by the register group module. At the same time, other modules of the base station fronthaul interface encapsulation processor can also directly read data from the register group module when needed.

[0088] The base station fronthaul interface encapsulation processor provided by the present invention maps the data interface and the control interface to a general register group and uses hardware handshake to complete data writing, thereby improving the speed of message data reading and sending, optimizing the timing of message data encapsulation and simplifying the programming difficulty of the encapsulation instruction sequence.

[0089] Based on the above embodiment, as an optional embodiment, the data integration control word includes a first initial cache address control word, a first data length control word, a register number control word, a compression bit width control word and a compression method control word;

[0090] The step of compressing the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and writing the compressed message data into the cache comprises:

[0091] Extracting the message data to be sent from the target register corresponding to the register number control word in the register group module, compressing the data bit width and size of the message data to be sent according to the compression bit width corresponding to the compression bit width control word and the compression method corresponding to the compression method control word, and removing redundant bits so that the message data to be sent are closely arranged, thereby obtaining the compressed message data;

[0092] The compressed message data is sequentially written into the cache using the cache address corresponding to the first initial cache address control word as the storage space of the initial cache address until the data length of the message data to be sent extracted from the target register is equal to the data length corresponding to the first data length control word.

[0093] The compression methods include but are not limited to μ-law, a-law, BFP (block floating point), block scaling and other methods; the compression bit width is 7-15 bits.

[0094] Specifically, the preconfigured data integration control words for compressing and integrating message data include a first initial cache address control word rd, a first data length control word rs2, a register number control word rs1, a compression bit width control word compwidth, and a compression method control word compmethod.

[0095] After configuring the data integration module based on the pre-configured data integration control word, the data integration module extracts the message data to be sent from the target register corresponding to the register number control word rs1 in the register group module. At this time, the message data to be sent has been pre-stored in the register group module through the uplink after responding to the packet request signal of the uplink transmission. Then the data integration module compresses the data bit width and size of the message data to be sent according to the compression bit width corresponding to the compression bit width control word compwidth and the compression method corresponding to the compression method control word compmethod, removes the redundant bits after compression, and arranges the data tightly to obtain the compressed message data.

[0096] The compressed message data is then written into the cache in sequence, with the storage address corresponding to the first initial cache address control word rd as the storage space of the initial cache address, until the message data length extracted from the target register is equal to the data length corresponding to the first data length control word rs2.

[0097] Optionally, the process of compressing the original data width of the message data according to the compression bit width corresponding to the compression bit width control word compwidth, and the process of compressing the original data size of the message data according to the compression method corresponding to the compression method control word compmethod are collectively referred to as compression, which can be implemented by a compression submodule based on ASIC logic; the process of removing redundant bits after compression and arranging the data tightly is also called encoding, which can be implemented by an encoding submodule based on ASIC logic. That is, the data integration module includes two compression submodules and encoding submodules based on ASIC logic that work in series to realize the data integration function.

[0098] The above process can be expressed in code form as the data integration module configuration instruction "Comb rd, rs1, rs2, compwidth, compmethod", where "Comb" means data integration during message data encapsulation, and "rd", "rs1", "rs2", "compwidth" and "compmethod" are all pre-configured data recovery control words.

[0099] The base station fronthaul interface encapsulation processor provided by the present invention adopts a configurable ASIC to fixedly integrate the data bit width and size compression method and encoding method of the message data to be sent. When encapsulating the message, the data integration module is configured using a pre-configured data integration control word. The data integration module can be started to accelerate the processing of the message data to be sent at the application layer. After the data integration module is started, it will work in parallel with the processor without affecting the normal execution of other modules of the processor, thereby improving the rate of message data encapsulation.

[0100] Based on the above embodiment, as an optional embodiment, the block move control word includes a second initial cache address control word, a second data length control word, a register initial number control word and a register quantity control word;

[0101] The moving the compressed message data from the cache to the register group module based on the block move control word includes:

[0102] sequentially moving the compressed message data from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, and cyclically writing the compressed message data into the target register until the length of the message data being moved is equal to the data length corresponding to the second data length control word;

[0103] The target register is a register determined from the register group module based on the register initial number control word and the register quantity control word; the first register in the target register is the initial register corresponding to the register initial number control word.

[0104] Specifically, the operation module processes the control information of the message data to be sent under the drive of the encapsulation instruction sequence to generate block movement control words including the second initial cache address control word rs1, the second data length control word rs2, the register initial number control word rd and the register quantity control word range.

[0105] When the block transfer module transfers the message data to be sent based on the transfer control word, it first determines the target register for transferring the message data from the register group module according to the register initial number control word rd and the register quantity control word range. Among them, the first register in the target register is the initial register, that is, the register corresponding to the register initial number control word rd.

[0106] The number of target registers may be one or more, which is determined by the block transfer control word specifically calculated by the operation module in a specific message data encapsulation task.

[0107] The block moving module moves the compressed message data from the cache in sequence from the storage space with the cache address corresponding to the second initial cache address control word rs1 as the initial cache address, and writes the compressed message data to the target register in a loop until the length of the message data being moved is equal to the data length corresponding to the second data length control word rs2.

[0108] The above process can be expressed in code form as a block loading instruction "Blkl rd,rs1,rs2,range", where "Blkl" represents block movement during message data encapsulation, and "rd", "rs1", "rs2" and "range" are all block movement control words generated after the operation module processes the control information.

[0109] Taking "Blkl x1,x4,x5,3" as an example, the block moving module starts to move the compressed message data from the storage address x4 in the cache, and moves a total of x5 data. Assume x5=7, and writes them cyclically into the three registers x1, x2 and x3 starting from register x1. That is, the storage addresses of the 7 data cached in the cache are "x4, x4+1, x4+2, x4+3, x4+4, x4+5, x4+6" in sequence, and the block moving module moves these 7 data and writes them into the "x1, x2, x3, x1, x2, x3, x1" registers in sequence.

[0110] Taking the O-RAN protocol as an example, the O-RAN protocol first defines the data format of the application layer data on the U (user) plane, followed by the compressed and tightly arranged IQ data (also known as IQ payload), which occupies the main body of the message. When encapsulating the message, these compressed IQ data need to be extracted from the cache. Due to the flexibility of the message, the starting address of the IQ payload in the message data has various possibilities, and because the payload in the message is large, using software loops to move it will result in excessive time overhead.

[0111] The base station fronthaul interface encapsulation processor provided by the present invention adopts a read-write double loop method, cyclically reads compressed message data from a cache, cyclically writes the read compressed message data into a target register, and the target register sends out a header and the compressed message data as a complete assembly package message, and fixes this message data load block transport method based on a block transport module. Each time the message data load is transported, the block transport module can be started as a new task as long as the block transport control word determined by the operation module is used to configure the block transport module, thereby realizing rapid transport of message data with the help of hardware, and does not affect the execution logic of other parts of the base station fronthaul interface encapsulation processor, thereby improving the performance of the base station fronthaul interface encapsulation processor in encapsulating message data.

[0112] Based on the above embodiment, as an optional embodiment, the block move control word further includes a low byte number control word and a high byte number control word;

[0113] The method of sequentially moving the compressed message data from the storage space in the cache using the cache address corresponding to the second initial cache address control word as the initial cache address, and cyclically writing the compressed message data into the target register includes:

[0114] Based on the low byte number control word, determining a first byte number;

[0115] Determining a second byte number based on the high byte number control word;

[0116] sequentially moving the compressed message data from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, using the low byte data of the first byte number in the message data of the previous address to be moved as the high-order data, and using the high byte data of the second byte number in the message data of the next address to be moved as the low-order data;

[0117] Sequentially splicing the high-order data and the low-order data to obtain spliced ​​message data;

[0118] The spliced ​​message data is cyclically written into the target register.

[0119] Specifically, in order to solve the problem that the message data to be sent cannot be aligned after being temporarily stored in the cache due to compression and encoding by the data integration module, the operation module processes the control information of the message data to be sent under the drive of the encapsulation instruction sequence to generate a block movement control word, which also includes a low byte number control word lowbyte and a high byte number control word highbyte.

[0120] When the block moving module moves the message data to be sent based on the block moving control word, it first determines the first byte number according to the low byte number control word lowbyte, and determines the second byte number according to the high byte number control word highbyte. Then, the message data is read from the cache starting from the initial cache address corresponding to the second initial cache address control word rs1.

[0121] Figure 3 is an example diagram of splicing the message data to be sent provided by the present invention, such as Figure 3 As shown, starting from the first message data read, for the two message data "a+b" and "c+d" read adjacently from the cache, the low byte data "b" of the first byte number in the message data to be sent in the previous cache address to be transported is used as the high-order data, and the high byte data "c" of the second byte number in the message data to be sent in the next cache address to be transported is used as the low-order data, and a high-order data and a low-order data are spliced ​​in turn to obtain the spliced ​​message data "b+c".

[0122] The spliced ​​message data is cyclically written into the target registers in the register group module starting from the register corresponding to the register initial number control word rd until the length of the message data to be sent is equal to the difference between the data lengths corresponding to the second data length control word rs2. In this process, the splicing of rs2 spliced ​​message data is completed.

[0123] The above process can be expressed in code form as the non-aligned block load instruction "Blklna rd,rs1(lowbyte,highbyte),rs2", where "Blklna" represents the non-aligned block load in the message data encapsulation process, and "rd", "rs1", "rs2", "lowbyte" and "highbyte" are all block movement control words generated after the operation module processes the control information.

[0124] Figure 4 is an example diagram of aligning message data to be sent provided by the present invention, such as Figure 4 As shown, the block moving module continuously reads the message data from the initial cache address rs1 of the cache, takes the low byte data "d0_low" of the first byte number in the message data of the previous address rs1 to be moved as the high-order data, and takes the high byte data "d0_hi" of the second byte number in the message data of the next address rs1+1 to be moved as the low-order data, and obtains the spliced ​​message data "d0_low+d0_hi". By analogy, the spliced ​​spliced ​​message data "d0_low+d0_hi" and "d1_low+d1_hi" will be written into the target register for transmission.

[0125] During the message data encapsulation process, the message data to be sent is compressed and encoded by the data integration module, resulting in boundary misalignment, that is, the boundary of the payload in the message data is not 64-bit aligned. In the case where network message data is stored in big-endian and general registers are in little-endian machines, using the DMA of a traditional general-purpose processor to perform data movement operations cannot support the alignment of message data with misaligned big-endian storage boundaries.

[0126] The base station fronthaul interface encapsulation processor provided by the present invention adopts an aligned loading method of non-aligned message data with fixed boundaries based on a block shifting module. Each time the payload of the message data is loaded, a low-byte control word and a high-byte control word are generated by a calculation module. The block shifting module is configured by all control words, and data can be spliced ​​front and back with the help of hardware to be written into the target register in an aligned manner, thereby supporting automatic alignment of message data boundaries when the big-endian storage boundaries are not aligned.

[0127] Based on the above embodiment, as an optional embodiment, each special processing instruction in the special processing instruction set is configured with a calculation method of the special processing instruction, a bit starting position of two operands, a bit length and a target position.

[0128] The calculation method includes but is not limited to any one of the methods such as the change method, the operation method and the arbitration method. The change method includes but is not limited to data replacement, insertion, etc.; the operation method includes but is not limited to bit domain data addition, subtraction, multiplication, and, or, XOR, etc.; the arbitration method includes but is not limited to bit domain precise branching with comparison conditions of equal, not equal, greater than, less than or equal to, etc.

[0129] Correspondingly, the types of the special processing instructions in the special processing instruction set include data change instructions, bit operation instructions or bit arbitration instructions.

[0130] Taking the special processing instruction as a bit operation instruction as an example, each bit operation instruction includes an operation method (i.e., a calculation method), a first operand rs1, a second operand rs2 and a target address rd; the first operand rs1 includes a first bit starting position d, a first bit length e and a first bit number f; the second operand rs2 includes a second bit starting position g, a second bit length h and a second bit number i.

[0131] Accordingly, when executing the bit operation instruction, the operation module will fixedly obtain the first bit data of the first bit length e from the first bit starting position d in the register corresponding to the first operand rs1, and shift the first bit data left by the first bit position f, and the first bit data after the left shift is number 1; at the same time, fixedly obtain the second bit data of the second bit length h from the second bit starting position g in the register corresponding to the second operand rs2, and shift the second bit data left by the second bit position i, and the first bit data after the left shift is number 2. The operation module further operates on number 1 and number 2 according to the operation method, and stores the operation result in the second target address rd, thereby completing the operation of the message data.

[0132] Taking addition as an example, the above process is presented in code form, which can be expressed as a bit-domain precise addition instruction "Bpadd rd,rs1[d,e,f],rs2[g,h,i]", where "Bpadd" means precise addition of the bit-domains of two data.

[0133] For example, when the bit-domain precise addition instruction is "Bpadd n2,n0[8,12,0],n1[4,4,12]", the operation module intercepts bits [19:8] from the n0 register, shifts left by 0 bits, and obtains the number 1; intercepts bits [7:4] from the n1 register, shifts left by 12 bits, and obtains the number 2; and adds the numbers 1 and 2 to complete the bit-domain precise addition of the message data.

[0134] Figure 5 is a schematic diagram of the structure of the operation module provided by the present invention, such as Figure 5 As shown, the operation module includes a first masker 511 , a second masker 512 , a first shifter 521 , a second shifter 522 and an operator 530 .

[0135] The first masker 511 is used to perform a mask operation on one of the operands using a first mask to obtain a first mask result; the first mask is determined based on the bit starting position and bit length of the one operand.

[0136] The second masker 512 is used to perform a mask operation on another operand using a second mask to obtain a second mask result; the second mask is determined based on the bit starting position and bit length of the other operand.

[0137] The first shifter 521 is used to shift the first mask result based on the target position of the first operand to obtain a first shift result.

[0138] The second shifter 522 is used to shift the second mask result based on the target position of the other operand to obtain a second shift result.

[0139] The operator 530 is used to perform an operation on the first shift result and the second shift result based on the calculation method to obtain an operation result and complete the execution of the dedicated processing instruction.

[0140] Specifically, taking the special processing instruction as a bit operation instruction as an example, the first masker 511 in the operation module first determines the first mask based on the first bit starting position and the first bit length, and then uses the first mask to perform a mask operation on the first bit data to obtain a first mask result; the second masker 512 first determines the second mask based on the second bit starting position and the second bit length, and then uses the second mask to perform a mask operation on the second bit data to obtain a second mask result.

[0141] The first shifter 521 then performs a left shift operation on the first mask result according to the first bit number to obtain a first shift result; the second shifter 522 then performs a left shift operation on the second mask result according to the second bit number to obtain a second shift result.

[0142] The operator 530 operates on the first shift result and the second shift result according to the operation method in the currently executed instruction (such as addition, subtraction, multiplication, AND, OR, XOR, etc.), and writes the obtained operation result to the second target address, thereby completing the instruction of the currently executed instruction.

[0143] The base station fronthaul interface encapsulation processor provided by the present invention takes into account the commonality of operations performed by the operation module when adding, subtracting, multiplying, ANDing, ORing, and XORing message data in the process of implementing message data encapsulation, fixes the way in which the operation module operates on two bit fields, thereby accelerating the operation speed and allowing the operation module to simultaneously complete accurate data interception and operation; and the processing of these execution instructions by the operation module has been fixed by setting two maskers, two shifters, and an operator in the operation module. When facing high-throughput message data processing, it can greatly reduce programming costs and time, while reducing the instruction overhead and clock overhead of the processor, thereby greatly improving the processing speed of the message data.

[0144] Based on the above embodiment, as an optional embodiment, a slow channel processing module is further included;

[0145] The slow channel processing module is used for not performing accelerated encapsulation processing on the message data to be sent when the message data to be sent is management package message data.

[0146] By programming to distinguish data packets, control packets and management packets, data packets and control packets will be accelerated to group and encapsulate, which can give full play to the performance of the base station fronthaul interface encapsulation processor, reduce the processing pressure of the main processor, and reduce the programming difficulty when the protocol stack processing is very large.

[0147] On the whole, the base station fronthaul interface encapsulation processor provided by the present invention provides a hot-potato, come-and-go stream processing architecture, including a program control module, an instruction storage module, a decoder module, a block movement module, an operation module, a cache, a data integration module, a register group module and a verification module, taking into account both efficiency and flexibility, and the data channel for packet encapsulation implemented includes program-driven bit synchronization, data segment search, data segment extraction, multi-data segment linking, error checking parallel operation, long field error checking background decoding operation, and case accelerated execution circuit, with an ASIP-based accelerated instruction set and architecture with flexible programmable capabilities, which accelerates message data processing with fast processing speed and high efficiency.

[0148] Figure 6 This is the second structural diagram of the base station fronthaul interface encapsulation processor provided by the present invention, such as Figure 6As shown, the base station fronthaul interface encapsulation processor also includes: a program control module 601, an instruction storage module 602, a decoder module 603 and a check module 604; the check module 604 includes a checksum generation module and a cyclic redundancy check sequence generation module.

[0149] The program control module 601 is used to manage program counts and arbitrate program count change requests sent by various modules of the base station fronthaul interface encapsulation processor.

[0150] The instruction storage module 602 is used to store the encapsulated instruction sequence.

[0151] The decoder module 603 is used to decode the encapsulation instruction in the encapsulation instruction sequence and distribute the decoding results to the various modules of the base station fronthaul interface encapsulation processor to drive the various modules to work.

[0152] The checksum generation module is used to complete the generation calculation of the checksum of the message data to be sent.

[0153] The cyclic redundancy check sequence generation module is used to complete the generation calculation of the cyclic redundancy check sequence (Cyclic Redundancy Check, CRC) of the message data to be sent.

[0154] Specifically, the decoder module 603 decodes the encapsulated instructions stored in the instruction storage module 602, and distributes the decoding results to each module to drive each module to work.

[0155] After each module completes the work of encapsulating instruction driving, it sends a program count change request to the program control module 601 for managing program counts, so that the program control module 601 can arbitrate the program count change request.

[0156] When the message data is encapsulated, the check module 604 is responsible for the generation and calculation of the CRC checksum, so it includes a checksum generation module and a cyclic redundancy check sequence generation module. The check module 604 is configured and started under the drive of the instruction, and does not affect the work of the base station front transmission interface encapsulation processor.

[0157] The base station fronthaul interface encapsulation processor provided by the present invention sets a verification module based on ASIC to accelerate the IP layer and the link layer. The verification module is configured, started and works according to instructions without affecting the normal operation of other modules of the processor.

[0158] Figure 7 is a flow chart of a message encapsulation method based on a base station fronthaul interface encapsulation processor provided by the present invention, such as Figure 7As shown, the message encapsulation method includes but is not limited to steps 701 to 704.

[0159] Step 701: After responding to the packet sending request signal of the uplink transmission, the control data integration module compresses the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and writes the compressed message data into the cache.

[0160] The register group module is composed of a plurality of registers and is used to temporarily store the calculation results of the operation module.

[0161] Step 702: The control operation module processes the control information of the message data to be sent under the drive of the encapsulation instruction sequence, and generates a block movement control word and a header of the message data to be sent based on the control information processing result.

[0162] The encapsulated instruction sequence is composed of a plurality of special processing instructions in a special processing instruction set.

[0163] Step 703: the control register group module temporarily stores the calculation result of the operation module, and sends the header after responding to the timing sending signal.

[0164] Step 704: The control block moving module moves the compressed message data from the cache to the register group module based on the block moving control word until the sending of one message data is completed.

[0165] It should be noted that the message encapsulation method provided by the present invention, when specifically executed, can be based on the base station fronthaul interface encapsulation processor described in any of the above embodiments, which will not be described in detail in this embodiment.

[0166] The message encapsulation method based on the base station fronthaul interface encapsulation processor provided by the present invention processes the message data under the drive of the encapsulation instruction sequence obtained by flexible programming based on the dedicated processing instruction set by the operation module, and generates a control word for realizing the block moving function, that is, the control word for realizing the block moving function in the ASIP configuration processor is constructed in the processor. A new architecture for ASIP and ASIC to cooperate in encapsulating message data is constructed, which has low cost and can improve the rate of special functions such as the block moving function in the message data parsing process, thereby improving the processing speed of message data encapsulation and meeting the real-time requirements of message processing at the same time, realizing a base station fronthaul interface message. A high-speed, high-throughput processor in data encapsulation scenarios; by using a dedicated processing instruction set when pre-programming the encapsulation instruction sequence, the number of encapsulation instructions that operators need to program when encapsulating message data can be reduced, reducing instruction overhead and increasing the message data encapsulation speed; by sending message data through the register group module, the timing of message data encapsulation can be optimized and the programming difficulty of the encapsulation instruction sequence can be simplified; by writing the compressed message data to be sent into the cache through the data integration module, and using the register group module to send the message data only after waiting for the timing sending signal, the network jitter of data processing can be overcome and the timing requirements of the 5G fronthaul interface and wireless system can be met.

[0167] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0168] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0169] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A base station fronthaul interface encapsulation processor, characterized in that: include: A data integration module, a calculation module, a register group module consisting of multiple registers, a block movement module and a cache; The data integration module is used to compress the data bit width and size of the message data to be sent according to the pre-configured data integration control word after responding to the packet sending request signal of the uplink transmission, and write the compressed message data into the cache; The operation module is used to process the control information of the message data to be sent under the drive of the encapsulation instruction sequence, and generate a block movement control word and a header of the message data to be sent based on the control information processing result; the encapsulation instruction sequence is composed of a plurality of special processing instructions in the special processing instruction set; The register group module is used to temporarily store the calculation results of the operation module and send the header after responding to the timing sending signal; The block moving module is used to move the compressed message data from the cache to the register group module based on the block moving control word until the sending of one message data is completed.

2. The base station fronthaul interface encapsulation processor according to claim 1, characterized in that: The register group module is mapped with a data input interface and a data output interface, the data input interface and the data output interface are externally connected to a sending link, and the register group module and the sending link complete data writing based on a hardware handshake method.

3. The base station fronthaul interface encapsulation processor according to claim 1, characterized in that: The data integration control word includes a first initial cache address control word, a first data length control word, a register number control word, a compression bit width control word and a compression method control word; The step of compressing the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and writing the compressed message data into the cache comprises: Extracting the message data to be sent from the target register corresponding to the register number control word in the register group module, compressing the data bit width and size of the message data to be sent according to the compression bit width corresponding to the compression bit width control word and the compression method corresponding to the compression method control word, and removing redundant bits so that the message data to be sent are closely arranged, thereby obtaining the compressed message data; The compressed message data is sequentially written into the cache using the cache address corresponding to the first initial cache address control word as the storage space of the initial cache address until the data length of the message data to be sent extracted from the target register is equal to the data length corresponding to the first data length control word.

4. The base station fronthaul interface encapsulation processor according to claim 1, characterized in that: The block move control word includes a second initial cache address control word, a second data length control word, a register initial number control word and a register quantity control word; The moving the compressed message data from the cache to the register group module based on the block move control word includes: sequentially moving the compressed message data from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, and cyclically writing the compressed message data into the target register until the length of the message data being moved is equal to the data length corresponding to the second data length control word; The target register is a register determined from the register group module based on the register initial number control word and the register quantity control word; the first register in the target register is the initial register corresponding to the register initial number control word.

5. The base station fronthaul interface encapsulation processor according to claim 4, characterized in that: The block move control word also includes a low byte number control word and a high byte number control word; The method of sequentially moving the compressed message data from the storage space in the cache using the cache address corresponding to the second initial cache address control word as the initial cache address, and cyclically writing the compressed message data into the target register includes: Based on the low byte number control word, determining a first byte number; Determining a second byte number based on the high byte number control word; sequentially moving the compressed message data from the storage space in the cache with the cache address corresponding to the second initial cache address control word as the initial cache address, using the low byte data of the first byte number in the message data of the previous address to be moved as the high-order data, and using the high byte data of the second byte number in the message data of the next address to be moved as the low-order data; Sequentially splicing the high-order data and the low-order data to obtain spliced ​​message data; The spliced ​​message data is cyclically written into the target register.

6. The base station fronthaul interface encapsulation processor according to claim 1, characterized in that: Each special processing instruction in the special processing instruction set is configured with a calculation method of the special processing instruction, a bit starting position of two operands, a bit length and a bit number; The operation module comprises: a first masker, a second masker, a first shifter, a second shifter and an operator; The first masker is used to perform a mask operation on one of the operands using a first mask to obtain a first mask result; the first mask is determined based on a bit starting position and a bit length of the one operand; The second masker is used to perform a mask operation on another operand using a second mask to obtain a second mask result; the second mask is determined based on a bit starting position and a bit length of the other operand; The first shifter is used to shift the first mask result based on the number of bits of the first operand to obtain a first shift result; The second shifter is used to shift the second mask result based on the number of bits of the other operand to obtain a second shift result; The operator is used to operate the first shift result and the second shift result based on the calculation method to obtain the operation result and complete the execution of the dedicated processing instruction.

7. The base station fronthaul interface encapsulation processor according to claim 6, characterized in that: The types of special processing instructions in the special processing instruction set include data change instructions, bit operation instructions and bit arbitration instructions.

8. The base station fronthaul interface encapsulation processor according to claim 1, characterized in that: Also included is a slow channel processing module; The slow channel processing module is used for not performing accelerated encapsulation processing on the message data to be sent when the message data to be sent is management package message data.

9. The base station fronthaul interface encapsulation processor according to claim 1, characterized in that: Also includes: A program control module, an instruction storage module, a decoder module and a check module; the check module includes a checksum generation module and a cyclic redundancy check sequence generation module; The program control module is used to manage program counts and arbitrate program count change requests sent by various modules of the base station fronthaul interface encapsulation processor; The instruction storage module is used to store the encapsulated instruction sequence; The decoder module is used to decode the encapsulation instruction in the encapsulation instruction sequence and distribute the decoding results to the various modules of the base station front transmission interface encapsulation processor to drive the various modules to work; The checksum generation module is used to complete the generation calculation of the checksum of the message data to be sent; The cyclic redundancy check sequence generation module is used to complete the generation calculation of the cyclic redundancy check sequence of the message data to be sent.

10. A message encapsulation method based on the base station fronthaul interface encapsulation processor according to any one of claims 1 to 9, characterized in that: include: After responding to the packet sending request signal of the uplink transmission, the control data integration module compresses the data bit width and size of the message data to be sent according to the pre-configured data integration control word, and writes the compressed message data into the cache; The register group module includes a plurality of registers; The control operation module processes the control information of the message data to be sent under the drive of the encapsulation instruction sequence, and generates a block movement control word and a header of the message data to be sent based on the control information processing result; the encapsulation instruction sequence is composed of a number of special processing instructions in the special processing instruction set; The control register group module temporarily stores the calculation result of the operation module, and sends the header after responding to the timing sending signal; The control block transfer module transfers the compressed message data from the cache to the register group module based on the block transfer control word until the sending of one message data is completed.

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