Semiconductor device and forming method thereof

Abstract

The semiconductor device includes a non-volatile memory structure. A layout of metallization layers in a semiconductor device coupled with a non-volatile memory structure is configured to achieve low electromigration possibilities in the non-volatile memory structure, particularly at operating temperature parameters associated with automotive and / or industrial applications. The non-volatile memory structure is electrically coupled with the first metallization layer. The first metallization electrically couples the non-volatile memory structure with a second metallization configured as a write bit line metallization for the non-volatile memory structure. The first metallization layer electrically couples the non-volatile memory structure with the third metallization layer over the second metallization layer. The third metallization layer is configured as a read bit line metallization layer for the non-volatile memory structure. The embodiment of the invention also discloses a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Many electronic devices include memory devices configured to store electronic data. The memory device may include one or more volatile memory cells and / or one or more non-volatile memory cells. Volatile memory cells store electronic data only when powered on, while non-volatile memory cells can retain stored electronic data even after power is removed. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor device is provided, including: a memory structure; a first metallization layer coupled to the memory structure; a second metallization layer located above the first metallization layer and coupled to the memory structure through the first metallization layer, wherein the second metallization layer is a write bit line metallization layer of the memory structure; and a third metallization layer located above the second metallization layer and coupled to the memory structure through the first metallization layer, wherein the third metallization layer is a read bit line of the memory structure.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a memory structure; a first metallization layer coupled to the memory structure; a second metallization layer located above the first metallization layer, the second metallization layer comprising: a first metal line configured as a write bit line metallization layer of the memory structure, coupled to the first metallization layer through one or more first interconnect structures; and a connecting pad structure spaced apart from the first metal line, coupled to the first metallization layer through one or more second interconnect structures; and a third metallization layer located above the second metallization layer, the third metallization layer comprising: a second metal line configured as a read bit line metallization layer of the memory structure, wherein the second metal line is coupled to the first metallization layer through the connecting pad structure.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, including: forming a doped region in a substrate of the semiconductor device; forming a first gate structure of a first transistor structure of a memory structure above the doped region; forming a third gate structure of a second transistor structure of the memory structure above the doped region; forming a first source / drain region adjacent to the first gate structure in the doped region; forming a second source / drain region adjacent to the second gate structure in the doped region; forming a first metallization layer above the first source / drain region and the second source / drain region; forming a write bit line metallization layer coupled to the first metallization layer above the first source / drain region; and forming a read bit line metallization layer coupled to the first metallization layer above the second source / drain region and above the write bit line metallization layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2 is a circuit diagram of an example nonvolatile memory cell described herein.

[0009] Figure 3 is a schematic diagram of an example implementation of voltage parameters for nonvolatile memory cell operations described herein.

[0010] Figure 4A and Figure 4B is a schematic diagram of an example memory structure described herein.

[0011] Figure 5A-5D is a schematic diagram of an example semiconductor device described herein.

[0012] Figure 6A-6F is a diagram of an example implementation that forms the memory structure described herein.

[0013] Figure 7A-7E is a schematic diagram of an example implementation that forms the memory structure described herein.

[0014] Figure 8 is a flow chart of an example process associated with forming a semiconductor device including the memory structures described herein. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0017] In contrast to a one-time programmable (OTP) nonvolatile memory cell that can only be programmed once, a multi-time programmable (MTP) memory cell is a type of nonvolatile memory cell that can be programmed and erased multiple times. Examples of MTP memory cells include FLASH memory cells, resistive random access memory (RRAM) cells, ferroelectric random access memory (FeRAM) cells, or phase change random access memory (PC-RAM) cells, etc. MTP memory cells can be integrated with logic complementary metal oxide semiconductor (CMOS) processes (including bipolar CMOS double diffused metal oxide semiconductor (double-diffusedmetal-oxide-semiconductor, DMOS) (bipolar CMOSDMOS, BCD) technology and / or high voltage (HV) CMOS technology). In addition, integrating MTP memory cells with HV technology and / or BCD technology enables nonvolatile memory to be used in applications such as the Internet of Things (IoT), power management, smart cards, microcontroller units (MCUs), display controllers, and / or automotive equipment.

[0018] Some applications of MTP memory cells have more demanding environmental parameters than others. For example, automotive and industrial applications typically require higher operating temperatures for MTP memory cells than other applications, such as consumer applications. Thus, MTP memory cells designed for consumer applications may not be able to withstand the high temperatures found in automotive applications. At high operating temperatures, such as in the range of about 85 degrees Celsius to about 175 degrees Celsius or higher, electromigration may occur in the MTP memory cell. Electromigration may result in short circuits and / or open circuits in the MTP memory cell, which may result in, among other things, a shortened useful life of the MTP memory cell and / or failure of the MTP memory.

[0019] In some implementations described herein, a semiconductor device includes a non-volatile memory structure, such as an MTP memory cell. The layout of the metallization layer of the semiconductor device coupled to the non-volatile memory structure is configured to achieve a low electromigration probability in the non-volatile memory structure, particularly under operating temperature parameters associated with demanding applications such as automotive and / or industrial. The non-volatile memory structure is electrically coupled to a first metallization layer (e.g., an M1 layer). The first metallization layer electrically couples the non-volatile memory structure to a second metallization layer (e.g., an M2 layer), which is configured as a write bit line (BL_W) for the non-volatile memory structure. The first metallization layer electrically couples the non-volatile memory structure to a third metallization layer (e.g., an M3 layer) above the second metallization layer. The third metallization layer is configured as a read bit line (BL_R) for the non-volatile memory structure.

[0020] Including a read bit line in the third metallization layer reduces the likelihood and / or amount of electromigration in the non-volatile memory structure. The metallization layers coupled to the non-volatile memory structure are arranged in order of increasing size such that the top-view width of the second metallization layer is greater than the first metallization layer, and the top-view width of the third metallization layer is greater than the top-view width of the second metallization layer. The larger top-view width of the third metallization layer enables it to better handle the cell read current of the non-volatile memory structure (which is greater than the cell write current of the non-volatile memory structure) compared to the second metallization layer. Specifically, due to greater heat dissipation in the third metallization layer than in the second metallization layer, the larger top-view width of the third metallization layer enables it to withstand electromigration at a larger operating current. Therefore, at high operating temperatures, such as in automotive or industrial applications, the larger top-view width of the third metallization layer provides a lower likelihood of electromigration in the read bit line of the non-volatile memory structure than when the second metallization layer is used as a read bit line. This reduces the likelihood of shorts and / or opens in the nonvolatile memory structure, which can extend the operating life of the nonvolatile memory structure and / or reduce the likelihood of failure of the nonvolatile memory structure at high operating temperatures without expanding the footprint of the nonvolatile memory structure.

[0021] Figure 1 1 is a schematic diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1As shown, environment 100 may include multiple semiconductor processing tools 102-114 and wafer / die transfer tools 116. Multiple semiconductor processing tools 102-114 may include deposition tools 102, exposure tools 104, development tools 106, etching tools 108, planarization tools 110, plating tools 112, ion implantation tools 114, and / or another type of semiconductor processing tool. The tools included in example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a semiconductor manufacturing facility, etc.

[0022] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool; an atomic layer deposition (ALD) tool; a plasma enhanced atomic layer deposition (PEALD) tool or another type of tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the example environment 100 includes multiple different types of deposition tools 102. As used herein, "deposition tool 102" may refer to one or more deposition tools 102, one or more deposition tools 102 of the same type, and / or one or more deposition tools 102 of different types, as well as other examples.

[0023] The exposure tool 104 is a semiconductor processing tool that can expose the photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme ultraviolet (EUV) light source, etc.), an x-ray source, an electron beam (e-beam) source, etc. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include a pattern for forming at least one structure of a semiconductor device, may include a pattern for etching various portions of a semiconductor device, etc. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0024] The developing tool 106 is a semiconductor processing tool that is capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0025] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, etc. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve isotropically or directionally etching the one or more portions using an ionized gas.

[0026] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 can polish or planarize the surface of a semiconductor device by a combination of chemical and mechanical forces (e.g., chemical etching and free grinding polishing). The planarization tool 110 can be used in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device) using abrasive and corrosive chemical slurries. The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and fixed in place by a retaining ring. The dynamic polishing head can rotate with different rotation axes to remove material, flatten any irregular topography of the semiconductor device, and thereby flatten or planarize the semiconductor device.

[0027] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper plating apparatus, an aluminum plating apparatus, a nickel plating apparatus, a tin plating apparatus, a composite material or alloy (e.g., tin-silver, tin-lead, etc.) plating apparatus, and / or a plating apparatus for one or more other types of conductive materials, metals, and / or similar types of materials.

[0028] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or a solid in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed to the substrate so that the ions are implanted below the surface of the substrate.

[0029] The wafer / die transfer tool 116 may be included in a cluster tool or another type of tool including multiple processing chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple processing chambers, transfer substrates and / or semiconductor devices between a processing chamber and a buffer, transfer substrates or semiconductor devices between a processing chamber and an interface tool (such as an equipment front end module (EFEM)), and / or transport substrates and / or semiconductor devices between a processing chamber and a transfer carrier (such as a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transfer tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0030] In some embodiments, one or more of the semiconductor processing tools 102-114 can perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-114 can be used to: form a doped region in a substrate of a semiconductor device; form a first gate structure of a first transistor structure of a memory structure above the doped region; form a second gate structure of a second transistor structure of the memory structure above the doped region; form a first source / drain region adjacent to the first gate structure in the doped region; form a second source / drain region adjacent to the second gate structure in the doped region; form a first metallization layer above the first source / drain region and the second source / drain region; form a write bit line metallization layer coupled to the first metallization layer above the first source / drain region; and / or form a read bit line metallization layer coupled to the first metallization layer above the second source / drain region and above the write bit line metallization layer, as well as other examples. One or more of the semiconductor processing tools 102-114 can perform the operations described herein, for example, in combination with Figure 6A-6F , Figure 7A-7E and / or Figure 8 Other semiconductor processing operations described in, e.g.

[0031] Figure 1 The number and arrangement of devices shown are provided as one or more examples only. In practice, there may be additional devices, fewer devices, different devices, or different Figure 1 The equipment shown is a different arrangement of the equipment. In addition, Figure 1 Two or more of the devices shown in may be implemented in a single device, or Figure 1 A single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (eg, one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices in the example environment 100.

[0032] Figure 2 is a circuit diagram of an example nonvolatile memory cell 200 described herein. The nonvolatile memory cell 200 is an MTP memory cell including a plurality of transistors and a plurality of capacitors. Figure 2 The example in the embodiment includes a 4-transistor 2-capacitor (4T2C) non-volatile memory cell 200, but the non-volatile memory cell 200 may include other numbers of transistors and / or capacitors. Additionally and / or alternatively, the non-volatile memory cell 200 may include another type of MTP memory cell, such as a FLASH memory cell, an RRAM cell, a FeRAM cell, a PC-RAM cell, and / or another non-volatile memory cell.

[0033] like Figure 2 As shown, the nonvolatile memory cell 200 may include a plurality of selection transistors, including a selection transistor 202a and a selection transistor 202b. The selection transistor 202a includes a selection gate 204a, and the selection transistor 202b includes a selection gate 204b. The selection gates 204a and 204b are electrically coupled so that the selection gate voltage (V SG ) can be applied to both select gates 204a and 204b.

[0034] The select source / drain 208a of the select transistor 202a and the select source / drain 208b of the select transistor 202b are also electrically coupled together and coupled to the source line 206. This enables a source line voltage (V SL ) to select the nonvolatile memory cell 200 among other nonvolatile memory cells in a memory cell array including the nonvolatile memory cell 200. "Source / drain" may refer to a source or a drain, depending on the context.

[0035] Another selection source / drain 210a of the selection transistor 202a and another selection source / drain 210b of the selection transistor 202b are electrically coupled to the storage transistor 212a and the storage transistor 212b, respectively. Specifically, the selection source / drain 210a of the selection transistor 202a is electrically coupled to the storage source / drain 214a of the storage transistor 212a, and the selection source / drain 210b of the selection transistor 202b is electrically coupled to the storage source / drain 214b of the storage transistor 212b.

[0036] The storage transistors 212a and 212b can be selectively activated and / or deactivated via the floating gate 216. The floating gate 216 of the nonvolatile memory cell 200 includes a segment for each of the storage transistors 212a and 212b. The storage source / drain 218a of the storage transistor 212a is electrically coupled to the write bit line 220a, and the storage source / drain 218b of the storage transistor 212b is directly electrically coupled to the read bit line 220b. A write bit line voltage (V BL_W ), and a read bit line voltage (V BL_R ).

[0037] Storage transistors 212a and 212b enable data to be stored in nonvolatile memory cell 200. Specifically, storage transistors 212a and 212b control access to erase line capacitor 222 included between floating gate 216 and erase line 224, and access to word line capacitor 226 included between floating gate 216 and word line 228. In some embodiments, a first electrode of erase line capacitor 222 can correspond to a first doped region (e.g., a first capacitor active region and / or a first well region) of a substrate of a semiconductor device, and a second electrode of erase line capacitor 222 can correspond to floating gate 216. In some embodiments, erase line capacitor 222 is configured as a tunneling capacitor. The erase line voltage (V EL ) can be applied to the first electrode of the erase line capacitor 222.

[0038] In some embodiments, a first electrode of word line capacitor 226 may correspond to a second doped region (e.g., a second capacitor active region and / or a second well region) of a substrate of a semiconductor device, and a second electrode of word line capacitor 226 may be defined by floating gate 216. In some embodiments, the word line capacitor is configured as a coupling capacitor. The word line voltage (V WL ) can be applied to the first electrode of the word line capacitor 226.

[0039] As mentioned above, Figure 2 is an example. Other examples might be Figure 2 There is a difference in what is described.

[0040] Figure 3 is a schematic diagram of an example implementation 300 of voltage parameters for operation of the nonvolatile memory cell 200 described herein. For example, the example implementation 300 of voltage parameters includes voltage parameters for an erase operation 302 of the nonvolatile memory cell 200, a program (or write) operation 304 of the nonvolatile memory cell 200, and a read operation 306 of the nonvolatile memory cell 200.

[0041] For the erase operation 302, the select gate voltage (V SG ) are applied to the select gates 204a and 204b of the select transistors 202a and 202b, respectively. A word line voltage (V WL ) can be applied to storage transistors 212a and 212b via word line 228. The erase line voltage (V EL ) can be set to a high voltage (HV) and can be applied to storage transistors 212a and 212b via erase line 224. In some embodiments, HV is included in a range of about 7V to about 10V. In some embodiments, HV is included in a range of about 11V to about 18V. In some embodiments, HV is included in a range of about 7V to about 18V. However, other values ​​and / or ranges of HV are also within the scope of the present disclosure. A write bit line voltage (V) of about 0V can be applied to the storage source / drain 218a of storage transistor 212a via write bit line 220a. BL_W ). The read bit line voltage (V BL_R ) and can be applied to the storage source / drain 218b of the storage transistor 212b via the read bit line 220b. The source line voltage (V SL ) may be applied to the select source / drain 208a and 208b of the select transistors 202a and 202b, respectively. In some embodiments, a bulk substrate voltage (V BULK ) may be applied to a bulk region of a substrate of a semiconductor device including the nonvolatile memory cell 200.

[0042] The above operating voltages enable the erase operation 302 to be performed. The voltage at the erase line capacitor 222 is high enough to cause charge carriers (e.g., electrons) to discharge from the floating gate 216 by tunneling to the first electrode of the erase line capacitor 222. This partially erases the data state of the floating gate 216, leaving the floating gate 216 in a high resistance state.

[0043] For programming operation 304, a select gate voltage (V SG ). Word line voltage (V WL ) can be set to HV and can be applied to storage transistors 212a and 212b via word line 228. The erase line voltage (V EL ) can also be set to HV and can be applied to storage transistors 212a and 212b via erase line 224. A write bit line voltage (V BL_W ) is applied to the storage source / drain 218a of the storage transistor 212a, and a read bit line voltage (V BL_R ) may be applied to the storage source / drain 218b of the storage transistor 212b. A source line voltage (V SL ) may be applied to the select source / drain 208a and 208b of the select transistors 202a and 202b, respectively. In some embodiments, a bulk substrate voltage (V BULK ).

[0044] The above operating voltages enable application of a cell write current to the nonvolatile memory cell 200 in a programming operation 304. The HV applied to the erase line capacitor 222 and the word line capacitor 226, and the 0V applied to the write bit line 220a, results in the reverse operation of the erase operation 302. This results in injection of charge carriers (e.g., electrons) from the storage source / drain 218a of the storage transistor 212a by tunneling into the floating gate 216. This programs the data state of the floating gate 216, causing the floating gate 216 to be in a low resistance state. Additionally and / or alternatively, the floating gate 216 is programmed using a channel hot electrode (CHE) injection.

[0045] For a read operation 306, a select gate voltage (V ) of about 3.0 volts to about 6.0 volts may be applied to the select gates 204a and 204b of the select transistors 202a and 202b, respectively. SG However, other values ​​of the select gate voltage are also within the scope of the present disclosure. A word line voltage (V WL ) can be applied to storage transistors 212a and 212b via word line 228. However, other values ​​of the word line voltage are also within the scope of the present disclosure. An erase line voltage (V ) of approximately 0 V can be applied to storage transistors 212a and 212b via erase line 224. EL ). Write bit line voltage (V BL W) is approximately 0V and can be applied to the storage source / drain 218a of the storage transistor 212a via the write bit line 220a. A read bit line voltage (V BL_R ) can be applied to the storage source / drain 218b of the storage transistor 212b via the read bit line 220b. In some embodiments, the bulk substrate voltage (V BULK ) is approximately 0 V and can be applied to the bulk region of the substrate.

[0046] The above-mentioned operating voltages enable the read operation 306 to be performed. Specifically, in the read operation, a cell read current will be applied to the nonvolatile memory cell 200. This enables the data state of the floating gate 216 to be read at the source line 206 in the read operation 306. For the nonvolatile memory cell 200, the magnitude of the cell read current may be greater than the magnitude of the cell write current.

[0047] As mentioned above, Figure 3 is an example. Other examples may be related to Figure 3 Describe the difference in content.

[0048] Figure 4A and Figure 4B is a schematic diagram of an example memory structure 400 described herein. The memory structure 400 may include a non-volatile memory structure and may be combined with Figure 2 A physical implementation of a non-volatile memory cell 200 is described.

[0049] Figure 4A is a top view of the memory structure 400. Figure 4A As shown, memory structure 400 includes substrate 402 and isolation structure 404 in substrate 402. A plurality of well regions 406-410 are included in substrate 402 within openings of isolation structure 404. Doped regions 406-410 are laterally offset from one another in memory structure 400 by a non-zero distance along the y-direction such that well regions 406-410 are separated from one another.

[0050] The substrate 402 may include a bulk semiconductor substrate (e.g., a bulk silicon (Si) substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate material, and / or may include a first doping type (e.g., p-type). The isolation structure 404 may include a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or another type of isolation structure that electrically isolates the well regions 406-410 from each other. The isolation structure 404 may include one or more dielectric materials, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y, such as Si3N4), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN) and / or another suitable dielectric material.

[0051] Well regions 406-410 may each include a doped region of substrate 402. For example, well region 406 may include a first doping type (e.g., p-type) having a higher doping concentration than substrate 402. As another example, well region 408 may include a second doping type (e.g., n-type). As another example, well region 410 may include a second doping type (e.g., n-type). Examples of p-type dopants include boron (B), gallium (Ga), and / or indium (In), etc. Examples of n-type dopants include arsenic (As) and / or phosphorus (P), etc.

[0052] like Figure 4A As further shown, active regions may be included in well regions 406-410. For example, write bit line active region 412a and read bit line active region 412b may each be included in well region 406. Write bit line active region 412a and read bit line active region 412b may each extend in the y-direction in memory structure 400 and may be adjacent in well region 406 in the x-direction in memory structure 400. As another example, erase line capacitor active region 414 is included in well region 410. As another example, word line capacitor active region 416 is included in well region 408.

[0053] The write bit line active area 412a and the read bit line active area 412b can each include one or more materials doped with a second doping type (e.g., n-type). Therefore, the write bit line active area 412a and the read bit line active area 412b include a doping type opposite to the well area 406. This enables the formation of a depletion region around the write bit line active area 412a and the read bit line active area 412b, thereby facilitating electrical isolation between the write bit line inactive area 412a and the read bit line active area 412b. Examples of materials for the write bit line active area 412a, the read bit line active area 412b, the erase line capacitor active area 414, and the word line capacitor active area 416 include silicon (Si), germanium (Ge), another semiconductor material, one or more conductive metals, and / or another suitable material.

[0054] The select gate structure 418a and the select gate structure 418b may extend in the x-direction in the memory structure 400. The select gate structure 418a is included over the write bit line active area 412a, and the select gate structure 418b is included over the read bit line active area 412b. The select gate structure 418a may correspond to the select gate 204a of the select transistor 202a of the nonvolatile memory cell 200, and the select gate structure 418b may correspond to the select gate 204b of the select transistor 202b of the nonvolatile memory cell 200. The select gate structures 418a and 418b may be formed as a single select gate structure 418, and may include a polysilicon gate structure, a metal gate structure with one or more high dielectric constant (high-k) pads, and / or another type of gate structure. In implementations where the select gate structure 418a and / or the select gate structure 418 includes a metal gate structure, the metal gate structure may include one or more conductive metals, such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), gold (Au) and / or combinations thereof, as well as other examples of conductive materials.

[0055] The sidewall spacers 420 may be included around the select gate structure 418a and / or the select gate structure 418. The sidewall spacers 420 may include one or more dielectric materials, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) and / or another suitable dielectric material.

[0056] The selection source / drain region 422a may be included at a location adjacent to the first side of the selection gate structure 418a, and the selection source / drain region 422b may be included at a location adjacent to the first side of the selection gate structure 418b. "Source / drain region" may refer to a source region, a drain region, or a source and drain region, depending on the context. The selection source / drain region 422a may correspond to the selection source / drain 208a of the selection transistor 202a of the non-volatile memory cell 200, and the selection source / drain region 422b may correspond to the selection source / drain region 208b of the selection transistor 202b of the non-volatile memory cell 200. The selection source / drain region 422a may include a portion of the write bit line active region 412a, and the selection source / drain region 422b may include a portion of the read bit line active region 412b.

[0057] The selection source / drain region 424a may be included at a location adjacent to a second side of the selection gate structure 418a opposite the first side, and the selection source / drain region 424b may be included at a location adjacent to the second side of the selection gate structure 418b. The selection source / drain region 424a may correspond to the selection source / drain 210a of the selection transistor 202a of the nonvolatile memory cell 200, and the selection source / drain region 424b may correspond to the selection source / drain 210b of the selection transistor 202b of the nonvolatile memory cell 200. The selection source / drain region 424a may include a portion of the write bit line active region 412a, and the selection source / drain region 424b may include a portion of the read bit line active region 412b.

[0058] The select gate structure 418a and the select source / drain regions 422a and 424a correspond to the select transistor structure 426a of the memory structure 400. The select transistor structure 426a may correspond to the select transistor 202a of the nonvolatile memory cell 200. The select gate structure 418b and the select source / drain regions 422b and 424b correspond to the select transistor structure 426b of the memory structure 400. The select transistor structure 426b may correspond to the select transistor 202b of the nonvolatile memory cell 200.

[0059] A source / drain contact 428a may be included above the select source / drain region 422a and may be electrically and / or physically coupled to the select source / drain region 422a. The source / drain contact 428a electrically connects the select source / drain region 422a to a select line metallization layer (not shown) corresponding to the source line 206 of the nonvolatile memory cell 200. A source / drain contact 428b may be included above the select source / drain region 422b and may be electrically and / or physically coupled to the select source / drain region 422b. The source / drain contact 428b electrically connects the select source / drain region 422b to a select line metallization layer corresponding to the source line 206 of the nonvolatile memory cell 200. The source / drain contacts 428a and 428b allow the select line voltage (V SL ) can be applied to select source / drain regions 422a and 422b, respectively. Source / drain contacts 428a and 428b can each include a via, a plug, a pad, and / or other types of contact structures. Source / drain contacts 428a and 428b each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0060] Gate contacts 430 may be included above select gate structures 418a and 418b. Gate contacts 430 allow the select gate voltage (V SG ) can be applied to the select gate structures 418a and 418b. The gate contact 430 includes a via, a plug, a pad, and / or another type of contact structure. The gate contact 430 includes one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0061] Floating gate structure 432a and floating gate structure 432b may extend in the x-direction in memory structure 400. Floating gate structure 432a is included over write bit line active area 412a, and floating gate structure 432b is included over read bit line active area 412b. Floating gate structure 432a may correspond to a portion of floating gate 216 of storage transistor 212a of nonvolatile memory cell 200, and floating gate structure 432 may correspond to another portion of floating gate 216 of storage transistor 212b of nonvolatile memory cell 200. Another floating gate structure 432c may be included over erase line capacitor active area 414, and another floating gate structure 432d may be included over word line capacitor active area 416. Floating gate structures 432a-432d may be formed as a single floating gate structure 432, and may include a polysilicon gate structure, a metal gate structure with one or more high-k pads, and / or another type of gate structure. In embodiments where the floating gate structure 432 includes a metal gate structure, the metal gate structure may include one or more conductive metals, such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), gold (Au) and / or combinations thereof, as well as other examples of conductive materials.

[0062] Sidewall spacers 434 may be included around the floating gate structure 432. The sidewall spacers 434 may include one or more dielectric materials, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si X N y , such as Si3N4), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) and / or another suitable dielectric material.

[0063] The storage source / drain region 436a may be included at a position adjacent to the first side of the floating gate structure 432a and adjacent to the selection source / drain region 424a. The storage source / drain region 436b may be included at a position adjacent to the first side of the floating gate structure 432b and adjacent to the selection source / drain region 424b. The storage source / drain region 436a may correspond to the storage source / drain 214a of the storage transistor 212a of the nonvolatile memory cell 200, and the storage source / drain region 436b may correspond to the storage source / drain 214b of the storage transistor 212b. The storage source / drain region 436a may include a portion of the write bit line active region 412a, and the storage source / drain region 436b may include a portion of the read bit line active region 412b.

[0064] The storage source / drain region 438a may be included at a position adjacent to a second side opposite to the first side of the floating gate structure 432a, and the storage source / drain region 438b may be included at a position adjacent to a second side of the floating gate structure 432b opposite to the first side. The storage source / drain region 438a may correspond to the storage source / drain 218a of the storage transistor 212a of the nonvolatile memory cell 200, and the storage source / drain region 438b may correspond to the storage source / drain 218b of the storage transistor 212b. The storage source / drain region 438a may include a portion of the write bit line active region 412a, and the storage source / drain region 438b may include a portion of the read bit line active region 412b.

[0065] Floating gate structure 432a and storage source / drain regions 436a and 438a correspond to storage transistor structure 440a of memory structure 400. Storage transistor structure 440a may correspond to storage transistor 212a of nonvolatile memory cell 200. Floating gate structure 432b and storage source / drain regions 436b and 438b correspond to storage transistor structure 440b of memory structure 400. Storage transistor structure 440b may correspond to storage transistor 212b of nonvolatile memory cell 200.

[0066] A source / drain contact 442a may be included above the storage source / drain region 438a and may be electrically and / or physically coupled to the storage source / drain region 438a. The source / drain contact 442a electrically connects the storage source / drain region 438a to a write bit line metallization layer (not shown) corresponding to the write bit line 220a of the nonvolatile memory cell 200. One or more source / drain contacts 442b may be included above the storage source / drain region 438b and may be electrically and / or physically coupled to the storage source / drain region 438b. The source / drain contact 442b electrically connects the storage source / drain region 438b to a read bit line metallization layer corresponding to the read bit line 220b of the nonvolatile memory cell 200.

[0067] The source / drain contact 442a allows the write bit line voltage (V BL_W ) can be applied to the storage source / drain region 438a. The source / drain contact 442b allows the read bit line voltage (V BL_R ) can be applied to the storage source / drain region 438b. In some embodiments, the number of source / drain contacts 442b is greater than the number of source / drain contacts 442a because the cell read current of the memory structure 400 is greater than the cell write current of the memory structure 400. The greater number of source / drain contacts 442b enables the source / drain contacts 442b to accommodate a larger cell read current.

[0068] Source / drain contacts 442a and 442b may each include a via, a plug, a pad, and / or other types of contact structures. Each of source / drain contacts 442a and 442b includes one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0069] The selection transistor structures 426a and / or 426b and / or the storage transistor structures 440a and / or 440b may each include a metal oxide semiconductor field effect transistor (MOSFET), a high voltage transistor, a bipolar junction transistor (BJT), an n-channel metal oxide semiconductor (nMOS) transistor, a p-channel metal oxide semiconductor (pMOS) transistor, or another suitable transistor. In some embodiments, the selection transistor structures 426a and / or 426b and / or the storage transistor structures 440a and / or 440b may each include a planar transistor structure, a fin field effect transistor (finFET) structure, a nanostructure transistor structure (e.g., a gate-all-around (GAA) transistor, a nanosheet transistor, a nanotube transistor, a nanoribbon transistor), and / or another type of transistor structure.

[0070] The erase line capacitor active area 414 and the floating gate structure 432c correspond to the erase line capacitor structure 444 of the memory structure 400. The erase line capacitor structure 444 corresponds to the erase line capacitor 222 of the non-volatile memory cell 200. One or more contacts 446 may be included above the erase line capacitor active area 414 and may be electrically coupled and / or physically coupled to the erase line capacitor active area 414. The contacts 446 electrically connect the erase line capacitor active area 414 to the erase line metallization layer (not shown) corresponding to the erase line 224 of the non-volatile memory cell 200. The contacts 446 allow the erase line voltage (V EL ) can be applied to the erase line capacitor active area 414. The contacts 446 each include a via, a plug, a pad, and / or another type of contact structure. The contacts 446 each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0071] The word line capacitor active area 416 and the floating gate structure 432d correspond to the word line capacitor structure 448 of the memory structure 400. The word line capacitor structure 448 corresponds to the word line capacitor 226 of the non-volatile memory cell 200. One or more contacts 450 may be included above the word line capacitor active area 416 and may be electrically and / or physically coupled to the word line capacitor active area 416. The contact 450 electrically connects the word line capacitor active area 416 to a word line metallization layer (not shown) corresponding to the word line 228 of the non-volatile memory cell 200. The contact 450 is capable of transmitting a word line voltage (V WL ) is applied to the word line capacitor active area 416. The contacts 450 each include a via, a plug, a pad, and / or another type of contact structure. The contacts 450 each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0072] Figure 4B Shown along Figure 4A 4 is a cross-sectional view of a portion of the memory structure 400 along line AA. The cross-sectional view is a cross-sectional view along the write bit line active area 412a. The cross-sectional view along the read bit line active area 412b may have a similar cross-sectional view.

[0073] like Figure 4BAs shown, the select transistor structure 426a and the storage transistor structure 440a are included in and / or over the well region 406. The select source / drain regions 422a and 424a, the portion of the well region 406 between the select source / drain regions 422a and 424a, the storage source / drain regions 436a and 438a, and the portion of the well region 406 between the storage source / drain regions 436a and 438b correspond to the write bit line active area 412a.

[0074] The extension region 452 may be included in the well region 406 adjacent to one or more of the selection source / drain regions 422a and 424a and / or adjacent to one or more of the storage source / drain regions 436a and 438a. The extension region 452 may include a doped region of the well region 406 doped with the same dopant type as the selection source / drain regions 422a and 424a and / or the storage source / drain regions 436a and 438a. A gate dielectric layer 454 may be included between the well region 406 and the selection gate structure 418a and / or between the well region 406 and the floating gate structure 432a.

[0075] A dielectric layer 456 may be included over the memory structure 400. The dielectric layer 456 may include an interlayer dielectric (ILD) layer and / or another type of dielectric layer. The dielectric layer 456 may provide electrical isolation between structures in the memory structure 400 and / or may provide a substantially planar surface on which subsequent layers (e.g., bonding layers) may be formed. Figure 5A-5D The dielectric layer 456 may include one or more dielectric materials, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) and / or another suitable dielectric material.

[0076] As mentioned above, Figure 4A and Figure 4B This is an example only. Other examples may be related to Figure 4A and Figure 4B The description content is different.

[0077] Figure 5A-5Dis a schematic diagram of an example semiconductor device 500 described herein. The semiconductor device 500 includes an example of a semiconductor device that includes one or more memory structures 400. Examples include a semiconductor memory device, an image sensor device (e.g., a complementary metal oxide semiconductor (CMOS) image sensor (CIS) device), a semiconductor logic device (e.g., a processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP)), an input / output device, an application specific integrated circuit (ASIC), or another type of semiconductor device.

[0078] Figure 5A 4 shows a top view of a semiconductor device 500. Specifically, Figure 5A A layout of multiple metallization layers of semiconductor device 500 is shown. The metallization layers may be included in an interconnect structure of semiconductor device 500. The interconnect structure may be located over memory structure 400 in semiconductor device 500, as well as over substrate 402 and / or dielectric layer 456 of memory structure 400.

[0079] like Figure 5A As shown, the interconnect structure of the semiconductor device 500 includes a first metallization layer 502. The first metallization layer 502 may be the first metallization (e.g., M1 layer) in the interconnect structure above the memory structure 400, and may be included directly above the dielectric layer 456 and contacts (e.g., source / drain contacts 428a and 428b, gate contact 430, source / drain contacts 442a and 442b, contact 446, contact 450) of the memory structure 400. The first metallization layer 502 includes a plurality of metal lines 502a-502d extending along the y-direction in the semiconductor device 500. Figure 5A The number of metal lines 502a-502d of the first metallization layer 502 shown in FIG. 5 is an example, and other numbers of metal lines of the first metallization layer 502 are also within the scope of the present disclosure. The metal lines 502a-502d can each include a trench in the xy plane of the semiconductor device 500, a conductive trace, and / or another type of elongated conductive structure. The metal lines 502a-502d can each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0080] The interconnect structure of the semiconductor device 500 further includes a second metallization layer 504. The second metallization layer 504 may be a second metallization layer (e.g., M2 layer) in the interconnect structure over the memory structure 400, and may be included directly over the first metallization layer 502. The second metallization layer 504 includes a plurality of metal lines 504a-504d extending in the x-direction and spaced apart in the y-direction in the semiconductor device 500. Figure 5A The number of metal lines 504a-504d of the second metallization layer 504 shown in FIG. 5 is an example, and other numbers of metal lines of the second metallization layer 504 are also within the scope of the present disclosure. The metal lines 504a-504d can each include a trench in the xy plane of the semiconductor device 500, a conductive trace, and / or another type of elongated conductive structure. The metal lines 504a-504d can each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0081] The interconnect structure of the semiconductor device 500 further includes a third metallization layer 506. The third metallization layer 506 may be a third metallization layer (e.g., M3 layer) in the interconnect structure over the memory structure 400, and may be included directly over the second metallization layer 504. The third metallization layer 506 includes a plurality of metal lines 506a-506d extending in the x-direction and spaced apart in the y-direction in the semiconductor device 500. Figure 5A The number of metal lines 506a-506d of the third metallization layer 506 shown in FIG. 5 is an example, and other numbers of metal lines of the third metallization layer 506 are also within the scope of the present disclosure. The metal lines 506a-506d can each include a trench in the xy plane of the semiconductor device 500, a conductive trace, and / or another type of elongated conductive structure. The metal lines 506a-506d can each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0082] The semiconductor device 500 also includes a connection pad structure 508. The connection pad structure 508 is part of the second metallization layer 504 (e.g., the connection pad structure 508 is located at a similar vertical height or z-direction height in the semiconductor device 500 as the second metallization layer 504) and is formed during the same process (or multiple processes) as the second metallization layer 504. Therefore, the connection pad structure 508 is formed of a similar material as the second metallization layer 504. The connection pad structure 508 is spaced apart from the metal lines 504a-504d of the second metallization layer 504.

[0083] The metal lines 504a-504d of the second metallization layer 504 at least partially overlap with one or more metal lines 502a-502d of the first metallization layer 502. This enables the first metallization layer 502 and the second metallization layer 504 to be interconnected through the interconnect structure 510. For example, one or more interconnect structures 510a can be located between the metal lines 502a of the first metallization layer 502 and the metal lines 504b of the second metallization layer 504, and can electrically couple the metal lines 502a of the first metallization layer 502 and the metal lines 504b of the second metallization layer 504. The metal lines 502a of the first metallization layer 502 can be electrically coupled to the storage source / drain region 438a of the storage transistor structure 440a through the source / drain contact 442a. This enables the write bit line voltage (V BL_W ) can be applied from the second metallization layer 504 to the storage source / drain region 438a of the storage transistor structure 440a. Thus, the metal line 504b of the second metallization layer 504 is the write bit line metallization layer of the memory structure 400.

[0084] In addition, the connection pad structure 508 of the second metallization layer 504 also at least partially overlaps with one or more metal lines 502a-502d of the first metallization layer 502. This enables the first metallization layer 502 and the connection pad structure 508 to be interconnected via the interconnect structure 510. For example, one or more interconnect structures 510b may be located between the metal line 502b of the first metallization layer 502 and the connection pad structure 508 of the second metallization layer 504, and may electrically couple the metal line 502b of the first metallization layer 502 and the connection pad structure 508 of the second metallization layer 504. The metal line 502b of the first metallization layer 502 may be electrically coupled to the storage source / drain region 438b of the storage transistor structure 440b via the source / drain contact 442b.

[0085] The interconnect structures 510 may each include a via, a plug, a conductive pillar or column, and / or another type of elongated conductive structure extending along the z-direction in the semiconductor device 500. The interconnect structures 510 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0086] The metal lines 506a-506d of the third metallization layer 506 may at least partially overlap the metal lines 504a-504d of the second metallization layer 504. This enables the metal lines 504a-504d of the second metallization layer 504 and the metal lines 506a-506d of the third metallization layer 506 to be interconnected through the interconnection structure 512. The plurality of interconnection structures 512 may be located between the connection pad structures 508 of the second metallization layer 504 and the metal lines 506b of the third metallization layer 506, and may electrically couple the connection pad structures 508 of the second metallization layer 504 and the third metallization layer 506. One or more interconnection structures 512a may be offset from the metal lines 502b of the first metallization layer 502 along the x-direction, and one or more interconnection structures 512b may be adjacent to the one or more interconnection structures 512 and located above the interconnection structure 510b.

[0087] The source / drain contact 442b, the metal line 502b of the first metallization layer 502, the interconnect structure 510b, the connection pad structure 508 and the interconnect structure 512 form a conductive path between the storage source / drain region 438b of the storage transistor structure 440b and the metal line 506b of the third metallization layer 506. This allows the read bit line voltage (V BL_R ) can be applied from the metal line 506b of the third metallization layer 506 to the storage source / drain region 438b of the storage transistor structure 440b through the source / drain contact 442b, the metal line 502b of the first metallization layer 502, the interconnect structure 510b, the connection pad structure 508, and the interconnect structure 512. Therefore, the metal line 506b of the third metallization layer 506 is the read bit line metallization layer of the memory structure 400.

[0088] The interconnect structures 512 may each include a via, a plug, a conductive pillar or column, and / or another type of elongated conductive structure extending along the z-direction in the semiconductor device 500. The interconnect structures 512 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0089] The first metallization layer 502, the second metallization layer 504, and the third metallization layer 506 have different top-view widths. Specifically, the metallization layers in the semiconductor device 500 are arranged with increasing top-view widths in the z-direction. The maximum x-direction top-view width (in Figure 5A The maximum y-direction top-view width of the metal lines 504a-504d of the second metallization layer 504 (indicated as dimension D1 in FIG. 1 ) is smaller than the maximum y-direction top-view width of the metal lines 504a-504d of the second metallization layer 504. The maximum y-direction top-view width of the metal lines 506a-506d of the third metallization layer 506 Figure 5ADimension D3) is greater than the maximum y-direction top-view width of the metal lines 504a-504d of the second metallization layer 504. In addition, the minimum spacing or distance between adjacent metal lines 504a-504d of the second metallization layer 504 (in Figure 5A 4) is less than the maximum spacing or distance between adjacent metal lines 506a-506d on the third metallization layer 506 (in FIG. Figure 5A Dimension D5).

[0090] As previously described, the cell read current of the memory structure 400 is greater than its cell write current. The larger maximum top-view width of the third metallization layer 506 compared to the second metallization layer 504 enables the third metallization layer to better handle the cell read current of the memory structure 400 (which is greater than the cell write current of the memory structure 400). Specifically, since the heat dissipation in the third metallization layer 506 is greater than the heat dissipation in the second metallization layer 504, the maximum top-view width of the third metallization layer 506 is greater, so that the third metallization layer 506 can better withstand electromigration at a higher operating current. Therefore, at high operating temperatures, such as in automotive or industrial applications, the larger top-view width of the third metallization layer 506 provides a smaller possibility of electromigration in the read bit line circuitization layer of the memory structure 400 compared to the case where the second metallization layer 504 is used as a read bit line metallization layer. This reduces the likelihood of shorts and / or opens in the memory structure 400 , which may extend the operating life of the memory structure 400 and / or reduce the likelihood of failure of the memory structure 400 at high operating temperatures without increasing the footprint of the memory structure 400 .

[0091] In addition, the write cell current of the memory structure 400 is smaller than the read cell current in the memory structure 400, so that the metal lines 504a-504d of the second metallization layer 504 have a smaller top-view width and a closer spacing than the metal lines 506a-506d of the third metallization layer 506. This makes the xy dimension of the connection pad structure 508 larger than when the second metallization layer 504 is used as the read bit line metallization layer of the memory structure 400. The larger xy dimension of the connection pad structure 508 enables a greater number of interconnect structures 512 to be included between the connection pad structure 508 and the third metallization layer 506. A greater number of interconnect structures 512 (rather than including fewer interconnect structures 512 in the semiconductor device 500) enables a sufficiently high current flow rate and a sufficiently low current density to be achieved for the cell read current, which can improve the electromigration reliability of the semiconductor device 500.

[0092] In some embodiments, the top-view width (e.g., dimension D2) of the metal lines of the second metallization layer 504 is included in the range of about 0.2 microns to about 0.45 microns to enable a sufficiently high density of metal lines to be included in the second metallization layer 504 while achieving a low probability of electromigration in the write bit line metallization layer of the memory structure 400. A top-view width of the metal lines of the second metallization layer 504 less than about 0.2 microns may result in an amount of electromigration in the write bit line metallization layer of the memory structure 400, which significantly reduces the reliability of the memory structure 400. Due to the minimum spacing between the metal lines 504a-504d of the second metallization layer 504, a top-view width greater than about 0.45 microns may result in an insufficient density of metal lines in the second metallization layer 504. However, other values ​​of the top-view width of the metal lines of the second metallization layer 504 and ranges other than about 0.2 microns to about 0.45 microns are within the scope of the present disclosure. Another example range includes about 0.15 microns to about 0.8 microns.

[0093] In some embodiments, the top-view width (e.g., dimension D3) of the metal lines of the third metallization layer 506 is included in the range of about 0.25 microns to about 0.65 microns to enable a sufficiently high density of metal lines to be included in the third metallization layer 506 while achieving a low probability of electromigration in the read bit line metallization layer of the memory structure 400. The top-view width of the metal lines of the third metallization layer 506 less than about 0.25 microns may result in an amount of electromigration in the read bit line metallization layer of the memory structure 400, which significantly reduces the reliability of the memory structure 400. Due to the minimum spacing between the metal lines 506a-506d of the third metallization layer 506, a top-view width greater than about 0.65 microns may result in insufficient density of metal lines in the third metallization layer 506. However, other values ​​of the top-view width of the metal lines of the third metallization layer 506 and ranges other than about 0.25 microns to about 0.65 microns are within the scope of the present disclosure. Another example range includes about 0.15 microns to about 0.8 microns.

[0094] In some embodiments, the top-view width (e.g., dimension D3) of the metal lines of the third metallization layer 506 is selected based on the expected use or designed use of the semiconductor device 500. For example, the top-view width of the metal lines of the third metallization layer 506 can be selected based on the automotive application and / or industrial application of the semiconductor device 500. In these embodiments, the top-view width of the metal lines of the third metallization layer 506 can be selected based on the operating temperature range of the semiconductor device 500, based on the electromigration reliability requirements of the semiconductor device 500, based on the working life of the semiconductor device 500, based on the temperature distribution based on the use of the semiconductor device 500, and / or based on another parameter. For example, the top-view width of the metal lines of the third metallization layer 506 can be selected based on the maximum silicon temperature of the semiconductor device 500, the three-year life threshold of the semiconductor device 500, the temperature distribution of about 5% to about 15% of the three-year life at an operating temperature of about 175 degrees Celsius, and a read cell current of about 120 microamperes. The top view width of the metal lines of the third metallization layer 506 can be selected to achieve a maximum cell current of the memory structure 400 that is at least twice the read cell current to achieve low electromigration under the above operating parameters. However, other examples of operating parameters are also within the scope of the present disclosure.

[0095] In some embodiments, the top-down distance (or spacing) (e.g., dimension D4) between adjacent metal lines of the second metallization layer 504 is included in the range of about 0.2 microns to about 0.45 microns to enable a sufficiently high density of metal lines to be included in the second metallization layer 504 while achieving sufficient electrical isolation between the metal lines of the second metallization layer 504 to pass acceptance testing. A distance of the second metallization layer 504 less than about 0.2 microns may result in insufficient electrical isolation between the metal lines of the second metallization layer 504, which may cause the semiconductor device 500 to fail acceptance testing and / or fail to operate. A distance of the second metallization layer 504 greater than about 0.45 microns may result in insufficient density of metal lines in the second metallization layer 504. However, other values ​​of the top-down distance (or spacing) between adjacent metal lines in the second metallization layer 504 and ranges other than about 0.2 microns to about 0.45 microns are also within the scope of the present disclosure. Another example range includes about 0.13 microns to about 0.45 microns.

[0096] In some embodiments, the top-down distance (or spacing) (e.g., dimension D5) between adjacent metal lines of the third metallization layer 506 is included in the range of about 0.25 microns to about 0.5 microns to enable a sufficiently high density of metal lines to be included in the third metallization layer 506 while achieving sufficient electrical isolation between the metal lines of the third metallization layer 506 to pass acceptance testing. A distance of the third metallization layer 506 less than about 0.25 microns may result in insufficient electrical isolation between the metal lines of the third metallization layer 506, which may cause the semiconductor device 500 to fail acceptance testing and / or fail to operate. A distance of the third metallization layer 506 greater than about 0.5 microns may result in insufficient density of metal lines in the third metallization layer 506. However, other values ​​of the top-down distance (or spacing) between adjacent metal lines in the third metallization layer 506 and ranges other than about 0.25 microns to about 0.5 microns are also within the scope of the present disclosure. Another example range includes about 0.13 microns to about 0.45 microns.

[0097] In some embodiments, the top-down distance (or spacing) between adjacent metal lines of the second metallization layer 504, between adjacent metal lines of the third metallization layer 506, between adjacent interconnect structures 510, and / or between adjacent interconnect structures 512 is selected based on the expected use or design use of the semiconductor device 500. For example, the top-down distance (or spacing) can be selected based on the automotive application and / or industrial application of the semiconductor device 500. In these embodiments, the top-down distance (or spacing) can be selected based on the operating temperature range of the semiconductor device 500, based on the electrical isolation requirements of the semiconductor device 500, based on the working life of the semiconductor device 500, based on the temperature distribution of the use of the semiconductor device 500, based on the operating voltage of the memory structure 400, and / or based on another parameter. For example, multiple voltage ranges can be specified for automotive applications and / or industrial applications, and a minimum distance or spacing can be associated with each voltage range. The top-down distance (or spacing) can be selected based on the operating voltage of the memory structure 400 in a specific voltage range of the multiple voltage ranges.

[0098] In some embodiments, the top view width (e.g., dimension D6) of the connection pad structure 508 is included in a range of about 0.15 microns to about 0.25 microns to enable a sufficiently high density of interconnect structures 512 to be coupled to the connection pad structure 508 while achieving a low likelihood of electromigration in the write bit line metallization layer of the memory structure 400. A top view width of the connection pad structure 508 less than about 0.25 microns may result in an amount of electromigration in the write bit line metallization layer of the memory structure 400, which significantly reduces the memory structure 400 because not enough interconnect structures 512 can be coupled to the connection pad structure 508. A top view width greater than about 0.5 microns may result in an insufficient density of metal lines in the second metallization layer 504 due to the minimum spacing between the connection pad structure 508 and the metal lines 504a-504d of the second metallization layer 504. However, other values ​​of the top view width of the connection pad structure 508 and ranges other than about 0.25 microns to about 0.5 microns are within the scope of the present disclosure. Another example range includes about 0.15 microns to about 0.8 microns.

[0099] Figure 5B A detailed top view of a metal line 504b of the second metallization layer 504 (eg, a write bit line metallization layer of the memory structure 400) and a metal line 506b of the third metallization layer 506 (eg, a read bit line conductive structure of the memory structure 400) is shown. Figure 5B As shown, metal line 506b at least partially overlaps metal line 504b. Figure 5B As further shown, metal line 504b includes a plurality of segments 514a-514e. In semiconductor device 500, segments 514a, 514b, and 514c extend substantially parallel to each other in the x-direction. Segments 514d and 514e extend substantially parallel to each other in the y-direction and are substantially perpendicular to segments 514a, 514b, and 514c.

[0100] In the top view of the semiconductor device 500, the segments 514a and 514d are located near a first end of the connection pad structure 508. The segments 514b and 514e are adjacent to a second end of the connection pad structure 508, which is opposite to the first end in the top view of the semiconductor device 500. The segment 514c is offset relative to the segments 514a and 514b in the top view of the semiconductor device 500 and is adjacent to one side of the connection pad structure 508.

[0101] The offset of segment 514c relative to segments 514a and 514b enables connection pad structure 508 to be at least partially located under metal line 506b. This enables interconnect structures 512a and 512b to extend between connection pad structure 508 and metal line 506b along the z-direction in semiconductor device 500. Interconnect structure 510a is coupled to segment 514c and can be located under a portion of segment 514c that extends laterally outward from metal line 506b. In other words, interconnect structure 510a can be coupled to a portion of segment 514c that is not located under metal line 506b.

[0102] Segment 514d is a transition segment of metal line 504b, providing a transition between segment 514a and segment 514c. Segment 514e is a transition segment of metal line 504b, providing a transition between segment 514b and segment 514c. Metal line 506b at least partially overlaps segments 514d and 514e.

[0103] Figure 5C and Figure 5D The interconnection details between the metal line 502 b of the first metallization layer 502 , the connection pad structure 508 of the second metallization layer 504 , and the metal line 506 b of the third metallization layer 506 are shown. Figure 5C 5 shows a top view of a portion of a semiconductor device 500. Figure 5D Shown along Figure 5C FIG. 5 is a cross-sectional view of a portion of the semiconductor device 500 taken along line BB in FIG.

[0104] like Figure 5C and Figure 5D As shown, interconnect structure 510b extends along the z direction between metal line 502b and connection pad structure 508 in semiconductor device 500. Interconnect structure 510b is physically coupled and / or electrically coupled to metal line 502b and connection pad structure 508. Interconnect structures 512a and 512b extend along the z direction between connection pad structure 508 and metal line 506b in semiconductor device 500. Interconnect structures 512a and 512b are physically coupled and / or electrically coupled to connection pad structure 508 and metal line 506b. Interconnect structure 512b is directly above interconnect structure 510b. Interconnect structure 512a is offset relative to interconnect structure 510b.

[0105] The connection pad structure 508 (and metal lines 504a-504d) of the second metallization layer 504 may have a z-direction thickness (in Figure 5D The metal line 506b (as well as the metal lines 506a, 506c, and 506d) of the third metallization layer 506 may have a z-direction thickness (in Figure 5DDimension D8 is shown in FIG. 4 ). The z-direction thickness (e.g., dimension D8) of the third metallization layer 506 is greater than the z-direction thickness (e.g., dimension D7) of the second metallization layer 504. The greater thickness of the third metallization layer 506 enables the third metallization layer 506 to accommodate a read cell current of the memory structure 400 that is greater than the write cell current handled by the second metallization layer 504.

[0106] As mentioned above, Figure 5A-5D These are examples only. Other examples may differ Figure 5A-5D Different from what is described in .

[0107] Figure 6A-6F is a diagram of an example implementation 600 of forming the memory structure 400 described herein. In some implementations, the bonding may be performed using one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116. Figure 6A-6F In some embodiments, in combination with one or more semiconductor processing operations described herein. Figure 6A-6F One or more of the processing operations described can be used Figure 1 The invention is performed by another semiconductor processing tool not shown.

[0108] Go to Fig. 6A , a substrate 402 may be provided. The substrate 402 may be provided as a semiconductor wafer, a semiconductor die, and / or another type of semiconductor substrate. In some embodiments, the substrate 402 may be a doped substrate, such as a semiconductor substrate doped with one or more p-type dopants, a semiconductor substrate doped with one or more n-type dopants, and / or another type of doped substrate. In some embodiments, the substrate 402 has a bulk resistivity (or volume resistivity) included in a range of about 1 ohm-cm to about 100 ohm-cm. However, other values ​​of this range are also within the scope of the present disclosure.

[0109] like Figure 6BAs shown, the isolation structure 404 is formed in and / or above the substrate 402. The isolation structure 404 can be formed in a recess in the substrate 402. In some embodiments, the pattern in the photoresist layer is used to etch the substrate 402 to form a recess. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the substrate 402. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the substrate 402 based on the pattern to form a recess in the substrate 402. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etching the substrate 402 based on the pattern.

[0110] like Figure 6C As shown, one or more regions of substrate 402 are doped to form well regions 406, 408, and 410 in the opening of isolation structure 404. In some embodiments, ion implantation tool 114 can be used to perform one or more ion implantation operations to implant ions (e.g., p-type ions, n-type ions) into substrate 402 to form well regions 406, 408, and / or 410. Ion implantation tool 114 can be used to direct an ion beam toward substrate 402 so that ions are implanted below the surface of substrate 402 to dope substrate 402. Additionally and / or alternatively, deposition tool 102 can be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combined operation, or a combination thereof. Figure 1 Well regions 406, 408, and / or 410 are deposited in another type of deposition operation as described and / or another suitable deposition operation.

[0111] like Fig.6D As shown, a selection gate structure 418 is formed over the well region 406, and the selection gate structure 418 includes a selection gate structure 418a of the selection transistor structure 426a and a selection gate structure 418b of the selection transistor structure 426b. In addition, a floating gate structure 432 may be formed, and the floating gate structure 432 includes a floating gate structure 432a of the storage transistor structure 440a over the well region 406, a floating gate structure 432b of the storage transistor structure 440b over the well region 406, a floating gate frame 432c over the well region 410, and a floating gate structure 432d over the well region 408.

[0112] Forming the select gate structure 418 may include depositing material for the select gate structures 418a and 418b, depositing a conformal layer of dielectric material around the select gate structures 418a and 418b, and etching the conformal layer of dielectric material using the etching tool 108 to form sidewall spacers 420 around the select gate structures 418a and 418b. The deposition tool 102 and / or the plating tool 112 may be used using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 The material of the select gate structures 418a and 418b may be deposited using another deposition technique and / or another suitable deposition operation as described herein. In some embodiments, a seed layer is first deposited, and the material of the select gate structures 418a and 418b is deposited on the seed layer. In some embodiments, after depositing the material of the select gate structures 418a and 418b, a planarization tool 110 may be used to planarize the select gate structures 418a and 418b. Deposition tool 102 may be used using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit the material of the sidewall spacer 420 .

[0113] Forming the floating gate structure 432 may include depositing a material of the floating gate structures 432a-432d, depositing a conformal layer of dielectric material around the floating gate structures 431a-432d, and etching the conformal layer of dielectric material using the etching tool 108 to form sidewall spacers 434 around the floating gate structures 432a-432d. The deposition tool 102 and / or the plating tool 112 may be used using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 The material of the floating gate structures 432a-432d is deposited by another deposition technique and / or another suitable deposition operation as described above. In some embodiments, a seed layer is deposited first, and then the material of the floating gate structures 432a-432d is deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the floating gate structures 432a-432d after depositing the material of the floating gate structures 432a-432d. The deposition tool 102 can be used to utilize PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit the material of the sidewall spacers 434 .

[0114] like Fig. 6EAs shown, a write bit line active area 412a (including select source / drain regions 422a and 424a of a select transistor structure 426a and storage source / drain regions 436a and 438a of a storage transistor structure 440a) is formed in the well region 406. The select source / drain regions 422a and 424a may be formed on opposite sides of the select gate structure 418a, and the storage source / drain regions 436a and 438a may be formed on opposite sides of the floating gate structure 432a.

[0115] A read bit line active area 412b, including select source / drain regions 422b and 424b of a select transistor structure 426b and storage source / drain regions 436b and 438b of a storage transistor structure 440b, is also formed in the well region 406. The select source / drain regions 422b and 424b may be formed on opposite sides of the select gate structure 418b, and the storage source / drain regions 436b and 438b may be formed on opposite sides of the floating gate structure 432b.

[0116] The erase line capacitor active region 414 of the erase line capacitor structure 444 may be formed in the well region 410. The word line capacitor active region 416 of the word line capacitor structure 448 may be formed in the well region 408.

[0117] In some embodiments, the deposition tool 102 is used to epitaxially grow a write bit line active area 412a (including selected source / drain regions 422a and 424a and storage source / drain regions 436a and 438a), a read bit line active area 412b (including selected source / drain regions 422b and 424b and storage source / drain regions 436b and 438b), an erase line capacitor active area 414 and / or a word line capacitor active area 416. In some embodiments, the ion implantation tool 114 is used to implant ions in the well region 406 to form a write bit line active region 412a (including selected source / drain regions 422a and 424a and storage source / drain regions 436a and 438a) and / or a read bit line active region 412b (including selected source / drain regions 422b and 424b and storage source / drain regions 436b and 438b), implant ions in the well region 410 to form an erase line capacitor active region 414, and / or implant ions into the well region 408 to form a word line capacitor active region 416. In some embodiments, a recess is formed in the well regions 406, 408 and / or 410, and a write bit line active area 412a (including selected source / drain regions 422a and 424a and storage source / drain regions 436a and 438a), a read bit line active area 412b (including selected source / drain regions 422b and 424b and storage source / drain regions 436b and 438b), an erase line capacitor active area 414 and / or a word line capacitor active area 416 are deposited in the recess using the deposition tool 102 and / or the plating tool 112.

[0118] like Fig. 6F As shown, source / drain contacts 428a and 428b are formed on select source / drain regions 422a and 422b, respectively. Source / drain contacts 442a and 442b are formed on storage source / drain regions 438a and 438b, respectively. Gate contact 430 is formed on select gate structure 418. Contact 446 is formed on erase line capacitor active region 414. Contact 450 is formed on word line capacitor active region 416.

[0119] Source / drain contacts 428a and 428b, source / drain contacts 442a and 442b, contact 446, and contact 450 may be formed in recesses in dielectric layer 456 (not shown) over memory structure 400. Deposition tool 102 may be used using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit dielectric layer 456. In some embodiments, after depositing the material of dielectric layer 456, planarization tool 110 may be used to planarize dielectric layer 456.

[0120] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 456 to form a recess. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the dielectric layer 456. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric layer 456 based on the pattern to form a recess in the dielectric layer 456. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etch the dielectric layer 456 based on the pattern.

[0121] The deposition tool 102 and / or the plating tool 112 may be used to utilize CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1 Another deposition technique and / or another suitable deposition operation described deposits the material of the source / drain contacts 428a and 428b, the source / drain contacts 442a and 442b, the contact 446, and / or the contact 450 in the recesses. In some embodiments, a seed layer is deposited first, and the material of the source / drain contacts 428a and 428b, the source / drain contacts 442a and 442b, the contact 446, and / or the contact 450 is deposited on the seed layer. In some embodiments, after depositing the source / drain contacts 428a and 428b, the source / drain contacts 442a and 442b, the contact 446, and / or the contact 450, the planarization tool 110 may be used to planarize the source / source contacts 428a and 428b, the contacts 442a and 442b, the contact 446, and / or the contact 450.

[0122] As mentioned above, Figure 6A-6F These are examples only. Other examples may differ Figure 6A-6F Different from what is described in .

[0123] Figure 7A-7E is a schematic diagram of an example implementation 700 of forming the semiconductor device 500 described herein. In some implementations, the bonding may be performed using one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116. Figure 7A-7E In some embodiments, in combination with one or more semiconductor processing operations described herein. Figure 7A-7E One or more of the processing operations described can be used Figure 1 In some embodiments, in combination with Figure 6A-6F After the one or more semiconductor processing operations described for forming the memory structure 400 in the semiconductor device 500 are performed in conjunction with Figure 7A-7E One or more processing operations described. For clarity, Figure 7A-7E Portions of memory structure 400 are omitted.

[0124] like Fig. 7A As shown, metal lines 502a-502d of a first metallization layer 502 are formed over a substrate 402 of a semiconductor device 500 and over a memory structure 400. The metal lines 502a-502d may be formed such that the metal lines 502a-502d extend in the semiconductor device 500 along a y-direction.

[0125] The metal lines 502a-502d of the first metallization layer 502 may be formed in recesses in a dielectric layer (not shown) of an interconnect structure above the memory structure 400 in the semiconductor device 500. The deposition tool 102 may be used to utilize PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit the dielectric layer. In some embodiments, after depositing the material of the dielectric layer, a planarization tool 110 may be used to planarize the dielectric layer.

[0126] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer to form a recess. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer based on the pattern to form a recess in the dielectric layer. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technology). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric layer based on the pattern.

[0127] The deposition tool 102 and / or the plating tool 112 may be used to deposit the coating using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1Another deposition technique and / or another suitable deposition operation is described to deposit metal lines 502a-502d of the first metallization layer 502 in the recesses. In some embodiments, a seed layer is deposited first, and the metal lines 502a-502d of the first metallization layer 502 are deposited on the seed layer. In some embodiments, after depositing the metal lines 502a-502d of the first metallization layer 502, a planarization tool 110 may be used to planarize the metal lines of the first metallization layer.

[0128] like Figure 7B As shown, interconnect structure 510 is formed on first metallization layer 502. For example, interconnect structure 510a can be formed on metal line 502a of first metallization layer 502, so that interconnect structure 510b is formed above write bit line active area 412a. As another example, interconnect structure 510b can be formed on metal line 502b of first metallization layer 502, so that interconnect structure 510a is formed above read bit line active area 412b. Interconnect structure 510 can be formed so that interconnect structure 510 extends along the z direction in semiconductor device 500.

[0129] The interconnect structure 510 may be formed in a recess in a dielectric layer (not shown) above the first metallization layer 502 in the interconnect structure of the semiconductor device 500. The deposition tool 102 may be used to deposit the semiconductor device 500 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit the dielectric layer. In some embodiments, after depositing the material of the dielectric layer, a planarization tool 110 may be used to planarize the dielectric layer.

[0130] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer to form a recess. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer based on the pattern to form a recess in the dielectric layer. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technology). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric layer based on the pattern.

[0131] The deposition tool 102 and / or the plating tool 112 may be used to deposit the coating using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1Another deposition technique and / or another suitable deposition operation deposits the interconnect structure 510 in the recess. In some embodiments, a seed layer is deposited first, and the interconnect structure 510 is deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the interconnect structure 510 after the interconnect structure 510 is deposited.

[0132] like Figure 7C As shown, metal lines 504a-504d and connection pad structures 508 of second metallization layer 504 are formed over interconnect structure 510 in the interconnect structure of semiconductor device 500. Metal lines 504a-504d and connection pad structures 508 may be formed such that metal lines 504a-504d and connection pad structures 508 extend in the semiconductor device 500 along the x-direction.

[0133] The metal lines 504a-504d and the connection pad structure 508 of the second metallization layer 504 can be formed in recesses in a dielectric layer (not shown) of the interconnect structure above the interconnect structure 510. The deposition tool 102 can be used using PVD technology, ALD technology, CVD technology, oxidation technology, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit the dielectric layer. In some embodiments, after depositing the material of the dielectric layer, a planarization tool 110 may be used to planarize the dielectric layer.

[0134] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer to form a recess. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer based on the pattern to form a recess in the dielectric layer. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technology). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric layer based on the pattern.

[0135] The deposition tool 102 and / or the plating tool 112 may be used to utilize CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1The another deposition technique and / or another suitable deposition operation deposits the metal lines 504a-504d and the connecting pad structure 508 of the second metallization layer 504 in the recess. In some embodiments, a seed layer is deposited first, and the metal lines 504a-504d and the connecting pad structure 508 of the second metallization layer 504 are deposited on the seed layer. In some embodiments, after the metal lines 504a-504d and the connecting pad structure 508 of the second metallization layer 504 are deposited, a planarization tool 110 may be used to planarize the metal lines 504a-504d and the connecting pad structure 508 of the second metallization layer 504.

[0136] Metal line 504b may be formed such that metal line 504a includes segments 514a-514e. In addition, metal line 504b (e.g., a write bit line metallization layer of memory structure 400) may be formed such that metal line 504a is physically and / or electrically coupled to interconnect structure 510a. Connecting pad structure 508 may be formed such that connecting pad structure 508 is physically and / or electrically coupled to interconnect structure 510b.

[0137] like Fig.7D As shown, interconnect structure 512 is formed on second metallization layer 504. For example, interconnect structures 512a and 512b may be formed on connection pad structure 508 of second metallization layer 504. Interconnect structure 512 may be formed such that interconnect structure 512 extends in the semiconductor device 500 along the z-direction.

[0138] The interconnect structure 512 may be formed in a recess in a dielectric layer (not shown) above the second metallization layer 504 in the interconnect structure of the semiconductor device 500. The deposition tool 102 may be used to utilize PVD technology, ALD technology, CVD technology, oxidation technology, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit the dielectric layer. In some embodiments, after depositing the material of the dielectric layer, a planarization tool 110 may be used to planarize the dielectric layer.

[0139] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer to form a recess. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer based on the pattern to form a recess in the dielectric layer. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technology). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric layer based on the pattern.

[0140] The deposition tool 102 and / or the plating tool 112 may be used to utilize CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1 Another deposition technique and / or another suitable deposition operation deposits the interconnect structure 512 in the recess. In some embodiments, a seed layer is deposited first, and the interconnect structure 512 is deposited on the seed layer. In some embodiments, the planarization tool 110 can be used to planarize the metal line interconnect structure 512 after the interconnect structure 512 is deposited.

[0141] like Fig. 7E As shown, metal lines 506a-506d of third metallization layer 506 are formed over interconnect structure 512 in the interconnect structure of semiconductor device 500. Metal lines 506a-506d of third metallization layer 506 may be formed such that metal lines 506a-506d of third metallization layer 506 extend in the semiconductor device 500 along the x-direction.

[0142] The metal lines 506a-506d of the third metallization layer 506 may be formed in recesses in a dielectric layer (not shown) of an interconnect structure above the interconnect structure 512. The deposition tool 102 may be used using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and Figure 1 Another type of deposition operation technique and / or another suitable deposition technique may be used to deposit the dielectric layer. In some embodiments, after depositing the material of the dielectric layer, a planarization tool 110 may be used to planarize the dielectric layer.

[0143] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer to form a recess. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer based on the pattern to form a recess in the dielectric layer. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technology). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric layer based on the pattern.

[0144] The deposition tool 102 and / or the plating tool 112 may be used to utilize CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1 Another deposition technique and / or another suitable deposition operation described herein deposits metal lines 506a-506d of the third metallization layer 506 in the recesses. In some embodiments, a seed layer is deposited first, and the metal lines 506a-506d of the third metallization layer 506 are deposited on the seed layer. In some embodiments, after depositing the metal lines 506a-506d of the third metallization layer 506, a planarization tool 110 may be used to planarize the metal lines 506a-506d of the third metallization layer 506.

[0145] Metal line 506b may be formed such that metal line 506a is formed over connection pad structure 508. Furthermore, metal line 506b (eg, read bit line metallization layer) may be formed such that metal line 506a is physically and / or electrically coupled to interconnect structures 512a and 512b.

[0146] As mentioned above, Figure 7A-7E These are examples only. Other examples may differ Figure 7A-7E Different from what is described in .

[0147] Figure 8 8 is a flow chart of an example process 800 associated with forming a semiconductor device including a memory structure described herein. In some embodiments, one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102-114) are used to perform Figure 8 One or more process boxes.

[0148] like Figure 8As shown, process 800 may include forming a doped region in a substrate of a semiconductor device (block 810). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to form a doped region (eg, well region 406) in substrate 402 of semiconductor device 500.

[0149] like Figure 8 As further shown, process 800 may include forming a first gate structure of a first transistor of the memory structure above the doped region (block 820). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to form a first gate structure (e.g., first floating gate structure 432a) of a first transistor (e.g., first storage transistor structure 440a) of memory structure 400 above the doped region.

[0150] like Figure 8 As further shown, process 800 may include forming a second gate structure of a second transistor of the memory structure above the doped region (block 830). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to form a second gate structure (e.g., second floating gate structure 432b) of a second transistor (e.g., second storage transistor structure 440b) of memory structure 400 above the doped region.

[0151] like Figure 8 As further shown, process 800 may include forming a first source / drain region adjacent to the first gate structure in the doped region (block 840). For example, one or more of semiconductor processing tools 102-114 may be used to form a first source / drain region (e.g., storage source / drain region 438a) adjacent to the first gate structure in the doped region, as described herein.

[0152] like Figure 8 As further shown, process 800 may include forming a second source / drain region adjacent to the second gate structure in the doped region (block 850). For example, one or more of semiconductor processing tools 102-114 may be used to form a second source / drain region (e.g., storage source / drain region 438b) adjacent to the second gate structure in the doped region, as described herein.

[0153] like Figure 8 As further shown, the process 800 may include forming a first metallization layer (over the first source / drain region and the second source / drain region) (block 860). For example, as described herein, one or more of the semiconductor processing tools 102-114 may be used to form the first metallization layer (e.g., one or more of the metal lines 502a-502d of the first metallization layer 502) over the first source / drain region and the second source / drain region.

[0154] like Figure 8 As further shown, process 800 may include forming a write bit line metallization layer coupled to the first metallization layer over the first source / drain region (block 870). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to form a write bit line metallization layer (e.g., one or more of metal lines 504a-504d of second metallization layer 504) over the first source / drain region coupled to the first metallization layer.

[0155] like Figure 8 As further shown, process 800 may include forming a read bit line metallization layer coupled to the first metallization layer over the second source / drain region and over the write bit line metallization layer (block 880). For example, as described herein, one or more of semiconductor processing tools 102-114 may be used to form a read bit line metallization layer (e.g., one or more of metal lines 506a-506d of third metallization layer 506) coupled to the first metallization layer over the second source / drain region and over the write bit line metallization layer.

[0156] Process 800 may include other implementations, such as any single implementation or any combination of implementations described below and / or implementations related to one or more other processes described elsewhere herein.

[0157] In a first embodiment, forming a first metallization layer includes forming a first metal line (e.g., metal line 502a) of the first metallization layer above a first source / drain region, and forming a second metal line (e.g., metal line 502b) of the first metallization layer above a second source / drain region, wherein the step of forming a write bit line metallization layer includes forming a write bit line metallization layer coupled to the first metal line, and wherein the step of forming a read bit line metallization layer includes forming a read bit line metallization layer coupled to the second metal line.

[0158] In a second embodiment, either alone or in combination with the first embodiment, process 800 includes forming one or more first interconnect structures (e.g., interconnect structure 510a) above a first metal line, establishing one or more second interconnect structures (e.g., interconnect structure 510b) above a second metal line, and forming a connecting pad structure 508 above the one or more second interconnect line structures, wherein forming a write bit line metallization layer includes forming a write bit line metallization layer above the one or more first interconnect line structures, and wherein forming a read bit line metallization layer includes forming a read bit line metallization layer above the connecting pad structure 508.

[0159] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, process 800 includes forming one or more third interconnect structures (e.g., interconnect structure 512a, interconnect structure 512b) above the connecting pad structure 508, wherein forming a read bit line metallization layer includes forming a read bit line metallization layer above the one or more third interconnect structures.

[0160] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, forming a read bit line metallization layer includes forming the read bit line metallization layer to a thickness (e.g., dimension D8) greater than a thickness (e.g., dimension D7) of the write bit line metallization layer.

[0161] although Figure 8 An example block diagram of process 800 is shown, but in some implementations, process 800 includes Figure 8 The blocks shown may be additional blocks, fewer blocks, different blocks, or blocks in a different arrangement. Additionally or alternatively, two or more blocks of process 800 may be executed in parallel.

[0162] In this way, the semiconductor device includes a non-volatile memory structure such as an MTP memory cell. The layout of the metallization layer of the semiconductor device coupled to the non-volatile memory structure is configured to achieve a low electromigration probability in the non-volatile memory structure, particularly under operating temperature parameters associated with harsh applications such as automotive and / or industrial. The non-volatile memory structure is electrically coupled to a first metallization layer (e.g., an M1 layer). The first metallization layer electrically couples the non-volatile memory structure to a second metallization layer (e.g., an M2 layer), which is configured as a write bit line of the non-volatile memory structure. The first metallization layer electrically couples the non-volatile memory structure to a third metallization layer (e.g., an M3 layer) above the second metallization layer. The third metallization layer is configured as a read bit line of the non-volatile memory structure. The larger top-view width of the third metallization layer compared to the second metallization layer enables it to better handle a cell read current of the non-volatile memory structure (greater than a cell write current of the non-volatile memory structure). Specifically, since the heat dissipation in the third metallization layer is greater than that in the second metallization layer, the larger top-view width of the third metallization layer enables it to withstand electromigration at a larger operating current.

[0163] As described in more detail above, some implementations of the present invention provide a semiconductor device. The semiconductor device includes a memory structure. The semiconductor device includes a first metallization layer coupled to the memory structure. The semiconductor device includes a second metallization layer located above the first metallization layer, which is coupled to the memory structure through the first metallization layer, wherein the second metallization layer is a write bit line metallization layer of the memory structure. The semiconductor device includes a third metallization layer located above the second metallization layer, which is coupled to the memory structure through the first metallization layer, wherein the third metallization layer is a read bit line of the memory structure.

[0164] In some embodiments, the second metallization layer is coupled to a first source / drain region of a first storage transistor structure of the memory structure; and wherein the third metallization layer is coupled to a second source / drain region of a second storage transistor structure of the memory structure.

[0165] In some embodiments, the top-view width of the third metallization layer is greater than the top-view width of the second metallization layer.

[0166] In some embodiments, the top view width of the third metallization layer is in a range from about 0.25 microns to about 0.65 microns.

[0167] In some embodiments, a top-view distance between the first metal line of the third metallization layer and the second metal line of the third metallization layer is in a range from about 0.25 microns to about 0.5 microns.

[0168] In some embodiments, a first top-view distance between the first metal line of the third metallization layer and the second metal line of the third metallization layer is greater than a second top-view distance between the third metal line of the second metallization layer and the fourth metal line of the second metallization layer.

[0169] As described in more detail above, some implementations of the present invention provide a semiconductor device. The semiconductor device includes a memory structure. The semiconductor device includes a first metallization layer coupled to the memory structure. The semiconductor device includes a second metallization layer located above the first metallization layer, the second metallization layer includes a first metal line and a connection pad structure, the first metal line is configured as a write bit line metallization layer of the memory structure. The first metal line is coupled to the first metallization layer through one or more first interconnect structures, the connection pad is spaced apart from the first metal line, and the connection pad is coupled to the first metallization layer through one or more second interconnect structures. The semiconductor device includes a third metallization layer located above the second metallization layer, the third metallization layer includes a second metal line configured as a read bit line of the memory structure, wherein the second metal line is coupled to the first metallization layer through the connection pad structure.

[0170] In some embodiments, the second metal line is coupled to the first metallization layer through one or more second interconnect structures and through one or more third interconnect structures, the one or more third interconnect structures being located between the connection pad structure and the second metal line.

[0171] In some embodiments, the number of the one or more third interconnect structures is greater than the number of the one or more second interconnect structures.

[0172] In some embodiments, the first metal line includes: a first segment adjacent to a first end of a connecting pad structure in a top view of the semiconductor device; a second segment adjacent to a second end of the connecting pad structure opposite to the first end in a top view of the semiconductor device; and a third segment adjacent to a side surface of the connecting pad structure in a top view of the semiconductor device, wherein the first segment, the second segment, and the third segment are substantially parallel in a top view of the semiconductor device, and wherein one or more first interconnect structures are coupled to the third segment.

[0173] In some embodiments, the third segment is offset from the first segment and the second segment in a top view of the semiconductor device; and wherein the second metal line overlaps the first segment and the second segment in a top view of the semiconductor device.

[0174] In some embodiments, the portion of the third segment coupled to the one or more first interconnect structures extends laterally outward from the second metal line.

[0175] In some embodiments, the first metal line includes: a fourth segment located between the first segment and the third segment; and a fifth segment located between the second segment and the third segment, wherein the second metal line overlaps the fourth segment and the fifth segment.

[0176] In some embodiments, the fourth segment and the fifth segment are substantially parallel in a top view of the semiconductor device; and wherein the first segment, the second segment, and the third segment are substantially perpendicular to the fourth segment and the fifth segment in a top view of the semiconductor device.

[0177] In some embodiments, the top-view width of the third metallization layer is greater than the top-view width of the second metallization layer; and wherein the first top-view distance between the first metal line of the third metallization layer and the second metal line of the third metallization layer is greater than the top-view distance between the first metal line of the second metallization layer and the second metal line of the second metallization layer.

[0178] As described in more detail above, some implementations of the present invention provide a method of forming a semiconductor device. The method includes forming a doped region in a substrate of a semiconductor device. The method includes forming a first gate structure of a first transistor of a memory structure above the doped region. The method includes forming a second gate structure of a second transistor of the memory structure above the doped region. The method includes forming a first source / drain region adjacent to the first gate structure in the doped region. The method includes forming a second source / drain region adjacent to the second gate structure in the doped region. The method includes forming a first metallization layer above the first source / drain region and the second source / drain region. The method includes forming a write bit line metallization layer coupled to the first metallization layer above the first source / drain region. The method includes forming a read bit line metallization layer coupled to the first metallization layer above the second source / drain region and above the write bit line metallization layer.

[0179] In some embodiments, forming a first metallization layer includes: forming a first metal line of the first metallization layer above a first source / drain region; and forming a second metal line of the first metallization layer above a second source / drain region; wherein forming a write bit line metallization layer includes: forming a write bit line metallization layer coupled to the first metal line; and wherein forming a read bit line metallization layer includes: forming a read bit line metallization layer coupled to the second metal line.

[0180] In some embodiments, the method also includes: forming one or more first interconnect structures above the first metal line; forming one or more second interconnect structures above the second metal line; and forming a connecting pad structure above the one or more second interconnect structures, wherein forming a write bit line metallization layer includes: forming a write bit line metallization layer above the one or more first interconnect structures, and wherein forming a read bit line metallization layer includes: forming a read bit line metallization layer above the connecting pad structure.

[0181] In some embodiments, the method further includes forming one or more third interconnect structures over the connection pad structure, wherein forming a read bit line metallization layer includes forming a read bit line metallization layer over the one or more third interconnect structures.

[0182] In some embodiments, forming the read bit line metallization layer includes forming the read bit line metallization layer to a thickness greater than a thickness of the write bit line metallization layer.

[0183] As used herein, "satisfying a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, a value less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc., depending on the context.

[0184] The terms "approximately" and "substantially" may mean that the value of a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that according to the present disclosure, the terms "approximately" and "substantially" may refer to a percentage of the value of a given quantity.

[0185] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: Memory structure; a first metallization layer coupled to the memory structure; a second metallization layer, located above the first metallization layer and coupled to the memory structure through the first metallization layer; Wherein, the second metallization layer is a write bit line metallization layer of the memory structure; and A third metallization layer is located above the second metallization layer and is coupled to the memory structure through the first metallization layer. The third metallization layer is a read bit line of the memory structure.

2. The semiconductor device according to claim 1, wherein the second metallization layer is coupled to a first source / drain region of a first storage transistor structure of the memory structure; as well as The third metallization layer is coupled to a second source / drain region of a second storage transistor structure of the memory structure.

3. The semiconductor device according to claim 1, wherein The top-view width of the third metallization layer is greater than the top-view width of the second metallization layer.

4. The semiconductor device according to claim 1, wherein: A first top-view distance between the first metal line of the third metallization layer and the second metal line of the third metallization layer is greater than a second top-view distance between the third metal line of the second metallization layer and the fourth metal line of the second metallization layer.

5. A semiconductor device comprising: Memory structure; a first metallization layer coupled to the memory structure; A second metallization layer is located above the first metallization layer, and the second metallization layer includes: A first metal line configured as a write bit line metallization layer of the memory structure, coupled to the first metallization layer through one or more first interconnect structures; and a connection pad structure, spaced apart from the first metal line and coupled to the first metallization layer through one or more second interconnect structures; and A third metallization layer is located above the second metallization layer, and the third metallization layer includes: a second metal line configured as a read bit line metallization layer of the memory structure, Wherein, the second metal line is coupled to the first metallization layer through the connecting pad structure.

6. The semiconductor device according to claim 5, wherein: The second metal line is coupled to the first metallization layer through the one or more second interconnect structures and through one or more third interconnect structures, the one or more third interconnect structures being located between the connection pad structure and the second metal line.

7. The semiconductor device according to claim 5, wherein: The first metal wire comprises: a first section adjacent to a first end of the connection pad structure in a top view of the semiconductor device; a second section adjacent to a second end of the connection pad structure opposite to the first end in a top view of the semiconductor device; and a third section, adjacent to a side surface of the connection pad structure in a top view of the semiconductor device, wherein the first section, the second section and the third section are substantially parallel in a top view of the semiconductor device, and Wherein, the one or more first interconnect structures are coupled to the third segment.

8. The semiconductor device according to claim 7, wherein: In a top view of the semiconductor device, the third section is offset from the first section and the second section; as well as Wherein, in a top view of the semiconductor device, the second metal line overlaps with the first section and the second section.

9. The semiconductor device according to claim 7, wherein: The first metal wire comprises: a fourth section located between the first section and the third section; and a fifth section, located between the second section and the third section, The second metal line overlaps with the fourth section and the fifth section.

10. A method of forming a semiconductor device, comprising: forming a doped region in a substrate of a semiconductor device; forming a first gate structure of a first transistor structure of a memory structure above the doped region; forming a second gate structure of a second transistor structure of the memory structure above the doped region; forming a first source / drain region in the doped region adjacent to the first gate structure; forming a second source / drain region in the doped region adjacent to the second gate structure; forming a first metallization layer over the first source / drain region and the second source / drain region; forming a write bit line metallization layer coupled to the first metallization layer over the first source / drain region; as well as A read bit line metallization layer coupled to the first metallization layer is formed over the second source / drain region and over the write bit line metallization layer.

Images