Package and method of forming same

Abstract

The package includes an interposer; a photonic interconnect structure connected to the interposer, where the photonic interconnect structure includes: a photonic component; a waveguide optically coupled to the photonic component; and an electron die electrically coupled to the photonic component; and a die electrically connected to the interposer, where the die is electrically coupled to the photonic interconnect structure through the interposer. Embodiments of the present disclosure also provide a method of forming a package.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to packages and methods of forming the same. Background Art

[0002] Optical signal transmission and processing are often combined with electrical signal transmission and processing to provide mature applications. For example, optical fibers can be used for long-distance signal transmission, and electrical signals can be used for short-distance signal transmission and processing and control. Accordingly, a device integrating long-distance optical components and short-distance electrical components is formed to convert between optical signals and electrical signals and process optical signals and electrical signals. Therefore, a package can include both optical (photonic) components and electronic devices. Summary of the invention

[0003] Some embodiments of the present disclosure provide a package comprising: an interposer; a photonic interconnect structure connected to the interposer, wherein the photonic interconnect structure comprises: a plurality of photonic components; a plurality of waveguides optically coupled to the plurality of photonic components; and electronic dies electrically coupled to the plurality of photonic components; and a plurality of dies electrically connected to the interposer, wherein the dies of the plurality of dies are electrically coupled to the photonic interconnect structure through the interposer.

[0004] Other embodiments of the present disclosure provide a package comprising: a photonic structure connected to an interconnect structure, wherein the photonic structure comprises a first device region, a second device region and a waveguide, wherein the first device region comprises a first photonic component, wherein the second device region comprises a second photonic component, wherein the first device region is optically coupled to the second device region via the waveguide; a first packaging component connected to the interconnect structure, wherein the first packaging component is electrically coupled to the first device region; and a second packaging component connected to the interconnect structure, wherein the second packaging component is electrically coupled to the second device region.

[0005] Another embodiment of the present disclosure provides a method for forming a package, the method comprising: forming a photonic interconnect structure, forming the photonic interconnect structure comprising: forming a plurality of first waveguides; forming a plurality of photonic components above the plurality of first waveguides; forming an interconnect structure above the plurality of photonic components; and bonding an electronic die to the interconnect structure; bonding the photonic interconnect structure to an intermediate layer; and bonding a plurality of semiconductor die to the intermediate layer, wherein the plurality of semiconductor die are electrically connected to the photonic interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 , Figure 2 and Figure 3 Intermediate steps in forming a photonic interconnect structure are shown according to some embodiments.

[0008] Figure 4A and Figure 4B A photonic interconnect structure according to some embodiments is shown.

[0009] Figure 5 An interposer according to some embodiments is shown.

[0010] Figure 6 A cross-sectional view of a photonic package is shown in accordance with some embodiments.

[0011] Figure 7 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0012] Figure 8 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0013] Fig. 9 A plan view of a photonic system according to some embodiments is shown.

[0014] Fig.10 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0015] Fig.11A and Fig. 11B A package assembly according to some embodiments is shown.

[0016] Fig.12 , Fig.13 , Fig.14 and Fig.15 Intermediate steps in forming a photonic interconnect structure are shown according to some embodiments.

[0017] Fig.16 A photonic interconnect structure according to some embodiments is shown.

[0018] Fig.17 A cross-sectional view of a photonic package is shown in accordance with some embodiments.

[0019] Fig.18 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0020] Fig.19 A plan view of a photonic system according to some embodiments is shown.

[0021] Fig. 20 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0022] Fig.21A cross-sectional view of a photonic package is shown in accordance with some embodiments.

[0023] Fig. 22 A cross-sectional view of a photonic package is shown in accordance with some embodiments.

[0024] Fig.23 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0025] Fig.24 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0026] Fig.25 A photonic interconnect structure according to some embodiments is shown.

[0027] Fig.26 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0028] Fig. 27 A plan view of a photonic system according to some embodiments is shown. DETAILED DESCRIPTION

[0029] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0030] In addition, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, arrows are used throughout the figures to indicate the path of light (e.g., optical signals and / or optical power). It should be understood that for clarity, the transmission of light is described along a path in one direction indicated by the arrow, but in some cases, light may also be transmitted in the opposite direction along the path.

[0031] Various photonic structures, such as interposers, packages, and systems and methods of forming them are described herein. A single photonic structure may include multiple device regions for optical signal communication and processing. In this way, the device regions of a single photonic structure may facilitate optical communication between multiple components of a package. In some embodiments, within a package, electrical signals may be used for some short-distance communications, and optical signals may be used for some long-distance communications.

[0032] The embodiments discussed herein are intended to provide examples so that the subject matter of the present disclosure can be made or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0033] Figures 1 to 4B The photonic interconnect structure 100 (see FIG. Figure 4A and Figure 4B ). The photonic interconnect structure 100 includes a photonic component 18 and / or a waveguide 26, which allows communication and processing of optical signals throughout the entire photonic interconnect structure 100. In some embodiments, the photonic interconnect structure 100 includes a plurality of device regions 101, each of which may be associated with other package components (e.g., a processing die, a memory die, etc.). The device regions 101 may communicate with each other using optical signals, and thus may facilitate optical communication between various package components associated with the device region 101. The device region 101 may be configured to receive, generate, modify, transmit and / or process optical signals. By forming a plurality of device regions 101 in a single photonic interconnect structure 100, manufacturing costs may be reduced, optical losses may be reduced, the efficiency of optical communication within the package may be improved, and / or the package size may be reduced. In this way, the photonic interconnect structure 100 may provide an interface for optical communication in a photonic system. In some cases, the photonic interconnect structure 100 may be viewed as a photonic integrated circuit (PIC), an optical interposer, and the like.

[0034] Go to Figure 1, at this stage, the photonic interconnect structure 100 includes a first substrate 10, a first insulating layer 12, and a photonic layer 14. In an embodiment, at the beginning of the manufacturing process of the photonic interconnect structure 100, the first substrate 10, the first insulating layer 12, and the photonic layer 14 may be collectively part of a silicon-on-insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The first substrate 10 may be a wafer, such as a silicon wafer. Other substrates, such as a silicon-on-insulator (SOI) substrate, a multilayer substrate, or a gradient substrate may also be used. In some embodiments, the semiconductor material of the first substrate 10 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. In other embodiments, the first substrate 10 may be a dielectric material such as silicon oxide, glass, ceramic, plastic, or any other suitable material that allows structural support for the devices thereon. Figure 1 As indicated, multiple device regions 101 may be formed on the same first substrate 10. Any suitable number or arrangement of device regions 101 may be formed on the first substrate 10. In some embodiments, multiple photonic interconnect structures 100 may be formed on a single first substrate 10, and then, the multiple photonic interconnect structures 100 may be subsequently singulated into individual photonic interconnect structures 100. In some cases, the first substrate 10 may be free of passive devices or active devices.

[0035] The first insulating layer 12 may be a dielectric layer that separates the first substrate 10 from the photonic layer 14 above, and in some embodiments, the first insulating layer 12 may also be part of a cladding material surrounding a subsequently fabricated photonic component 18 (described below). In embodiments, the first insulating layer 12 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, and the like. The first insulating layer 12 may be formed using techniques such as implantation (e.g., forming a buried oxide (BOX) layer) or using a suitable deposition technique such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), combinations of these, and the like. However, any suitable material and fabrication method may be used.

[0036] In some embodiments, the photon layer 14 may be a semiconductor material such as silicon, germanium, silicon germanium, combinations of these, etc. In other embodiments, the photon layer 14 may include a dielectric material such as silicon nitride, III-V semiconductor materials, lithium niobate materials, polymers, etc., or combinations thereof. The photon layer 14 may be formed using a suitable technique such as epitaxial growth, CVD, ALD, PVD, etc., or combinations thereof. Other materials or techniques are also possible.

[0037] Figure 2 The photonic component 18 is shown formed from the photonic layer 14 according to some embodiments. In some embodiments, the photonic component 18 may include such devices or components as optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers including tip waveguides with widths in the range of about 1 nm to about 200 nm, etc.), directional couplers, optical modulators (e.g., germanium modulators, Mach-Zehnder silicon-photonic switches, micro-electromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, optical-to-electrical converters (e.g., photodetectors, PN junctions, etc.), electro-optical converters, lasers (e.g., laser diodes), phase shifters, combinations of these, etc. However, the photonic component 18 may include other device structures or components in addition to these examples.

[0038] In some embodiments, the photonic component 18 can be formed by patterning the photonic layer 14 into an appropriate shape for the photonic component 18. For example, the photonic layer 14 can be patterned using one or more photolithographic masking and etching processes, however any suitable method of patterning the photonic layer 14 can be utilized. The patterning can expose portions of the first insulating layer 12. In some cases, additional processing steps can be performed to form some types of photonic components 18, such as additional implantation processes, deposition processes, and / or patterning processes. In some embodiments, one or more photonic components 18 can be formed by patterning the photonic layer 14, and then depositing another material on portions of the patterned photonic layer 14. For example, forming the photonic component 18 can include patterning the photonic layer 14 including silicon, and then epitaxially growing a germanium region on the patterned photonic layer 14, however other materials or process steps are also possible.

[0039] Still refer to Figure 2According to some embodiments, a second insulating layer 16 may be formed over the first insulating layer 12 and / or the photonic components 18. The second insulating layer 16 may be, for example, a dielectric layer that separates the individual photonic components 18 from each other and from the structures above. In addition, in some cases, the second insulating layer 16 may also serve as a cladding material that at least partially surrounds one or more photonic components 18. In some embodiments, the second insulating layer 16 may include silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, and the like, and the second insulating layer 16 may be formed using a suitable deposition technique (e.g., CVD, ALD, PVD, etc.). Other materials or deposition techniques are also possible. In some embodiments, after depositing the second insulating layer 16, a planarization process (e.g., a chemical mechanical polishing (CMP) process, a grinding process, etc.) may be performed to planarize the top surface of the second insulating layer 16. In some embodiments, the planarization process may expose the top surface of one or more photonic components 18. In such an embodiment, the top surface of the photonic component 18 and the top surface of the second insulating layer 16 may be flush or coplanar (within the process variation range). In some embodiments, after the planarization process is performed, one or more photonic components 18 still remain covered by the second insulating layer 16. Each device region 101 may include similar photonic components 18 or different photonic components 18.

[0040] Figure 3 An interconnect structure 20 is shown formed over the photonic component 18 in accordance with some embodiments. In some embodiments, the interconnect structure 20 includes a dielectric layer 22 (not separately shown) having conductive features 24 and waveguides 26 formed therein. The conductive features 24 allow electrical communication within the photonic interconnect structure 100, and the waveguides 26 allow optical communication within the photonic interconnect structure 100.

[0041] The conductive features 24 may include conductive wires, conductive vias, conductive pads, metallization patterns, redistribution layers, etc. that provide electrical interconnection and electrical routing within the photonic interconnect structure 100. In some cases, the conductive features 24 may be electrically connected to one or more photonic components 18. In some embodiments, the interconnect structure 20 may also include a conductive pad 28 located at a top surface of the interconnect structure 20. The conductive pad 28 may be a conductive pad, an under-bump metallization (UBM), etc. A conductive connector 30 may be formed on the conductive pad 28, which will be described in more detail below.

[0042] In some embodiments, the interconnect structure 20 is formed of alternating layers of dielectric material (e.g., dielectric layer 22) and conductive material (e.g., conductive component 24) and / or waveguide material (e.g., waveguide 26). The conductive component 24 may be formed using any suitable process, such as deposition, damascene, dual damascene, etc. In a particular embodiment, the interconnect structure 20 may have multiple layers of conductive components 24, but the exact number of conductive component 24 layers may depend on the design of the photonic interconnect structure 100. The dielectric layer 22 may be, for example, an insulating layer and / or a passivation layer, and may include silicon oxide, silicon nitride, a polymer, etc., or a combination thereof. The conductive component 24 may include, for example, a metal or metal alloy, such as copper, silver, gold, tungsten, cobalt, ruthenium, aluminum, alloys thereof, combinations thereof, etc. Other materials are also possible.

[0043] In some embodiments, conductive pad 28 is formed in a topmost dielectric layer 22 of dielectric layers 22. In some embodiments, conductive pad 28 may include a via portion (not shown) that physically and electrically contacts underlying conductive feature 24. Conductive pad 28 may include one or more layers of conductive material, such as the conductive materials described above for conductive feature 24. In some embodiments, conductive pad 28 is a UBM, which may include a portion located on and extending along a major surface of topmost dielectric layer 22. Other types of conductive pads 28 are also possible.

[0044] As mentioned above, the interconnect structure 20 may include one or more layers of waveguides 26 within the dielectric layer 22. In some embodiments, photonic components may also be formed in the interconnect structure 20, which may be similar to the photonic components 18 described previously. In some cases, the waveguides 26 may be optically coupled to each other and / or to one or more photonic components 18. In some embodiments, the waveguides 26 may be formed by depositing a waveguide material on the dielectric layer 22 during the manufacture of the interconnect structure 20. The waveguide material may be a dielectric material (such as silicon nitride, silicon oxide, silicon oxynitride, polymer, combinations of these, etc.) or a semiconductor material (such as silicon, germanium, etc.). The waveguide material may be deposited using a suitable technique, such as ALD, PVD, etc. The waveguide material may then be patterned using suitable photolithography and etching techniques to form a layer of waveguide 26. Another layer of dielectric layer 22 may then be deposited on the waveguide 26. In a particular embodiment, the interconnect structure 20 may have multiple layers of waveguides 26, but the exact number of layers of waveguides 26 may depend on the design of the photonic interconnect structure 100.

[0045] Still refer to Figure 3According to some embodiments, the conductive connector 30 can be formed on the conductive pad 28. The conductive connector 30 can be, for example, a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 30 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 30 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connector 30 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and the metal capping layer may be formed by a plating process. In other embodiments, the conductive connector 30 is omitted, and the conductive pad 28 is a bonding pad for metal-to-metal bonding with an external component.

[0046] The photonic interconnect structure 100 may have any suitable size and any suitable number and / or arrangement of device regions 101. As another example, according to some embodiments, Figure 4A shows a cross-sectional view of a photonic interconnect structure 100, and Figure 4B 1 shows a plan view of the photonic interconnect structure 100. In addition to the number and arrangement of device regions 101, FIG. 4A to FIG. 4B The photonic interconnect structure 100 may be similar to Figure 3 In some cases, the photonic interconnect structure 100 may be Figure 3 Considered as Figure 4A An enlarged view of the photonic interconnect structure 100 is shown in FIG. In some embodiments, the photonic interconnect structure 100 may have a length in a range of about 3,000 μm to about 300,000 μm and may have a width in a range of about 500 μm to about 100,000 μm, although other dimensions are possible.

[0047] Figure 5 A cross-sectional view of an interposer 150 according to some embodiments is shown. According to some embodiments, the interposer 150 includes a substrate 152, an interconnect structure 160 on the substrate 152, and through-vias 154. The substrate 152 may be a semiconductor substrate (e.g., a silicon wafer) or another type of substrate, such as the substrate previously described for the first substrate 10.

[0048] The interconnect structure 160 includes one or more layers of conductive features 164 formed in one or more dielectric layers 162 (not separately shown). The conductive features 164 may include conductive lines, conductive vias, conductive pads, etc., and may be formed using any suitable technique, such as damascene, dual damascene, etc. For example, the conductive features 164 may be formed using techniques similar to those previously described for the conductive features 24. In other embodiments, the interconnect structure 160 includes one or more waveguides formed in the dielectric layer 162.

[0049] The through-hole 154 of the interposer 150 extends through the substrate 152 and is electrically connected to the interconnect structure 160. The through-hole 154 may be formed, for example, by forming an opening extending through the substrate 152 and one or more dielectric layers 162 to expose the surface of the conductive component 164. The opening may be formed using acceptable photolithography and etching techniques, such as by forming and patterning a photoresist, and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process. Then, a conductive material may be formed in the opening to form the through-hole 154. In some embodiments, a liner (not shown) may be deposited in the opening before forming the conductive material. The conductive material may include, for example, a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, and the like. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the surface of the interposer 150 (e.g., substrate 152) so that the through-hole 154 and the surface of the interposer 150 are flush. In other embodiments, the through-hole 154 passes completely through the interposer 150. Other materials or technologies are also possible. In other embodiments, the through-hole 154 is omitted.

[0050] exist Figure 6 In some embodiments, the photonic interconnect structure 100 is connected to the interposer 150 to form the photonic package 200. Other packaging components (e.g., Figures 9 and 10The photonic interconnect structure 100 may also be connected to the interposer 150, as will be described in more detail below. In some embodiments, the conductive connector 30 of the photonic interconnect structure 100 may be placed on a corresponding conductive pad (not shown separately) of the interposer 150. The conductive pad may be formed in or on the top dielectric layer 162 of the interposer 150. For example, the conductive pad may be similar to the conductive pad 28 described for the photonic interconnect structure 100, but other conductive pads are also possible. A reflow process may then be performed to bond the conductive connector 30 to the interposer 150. In this way, the photonic interconnect structure 100 is physically and electrically connected to the interposer 150, and the interposer 150 may provide electrical interconnection between the photonic interconnect structure 100 and other packaged components. In some embodiments, the interposer 150 may also provide electrical interconnection between the device regions 101 of the photonic interconnect structure 100. In some embodiments, a bottom filler 165 may be deposited between the photonic interconnect structure 100 and the interposer 150. In some embodiments, the sidewalls of the photonic interconnect structure 100 are offset from the sidewalls of the interposer 150 , such as Figure 6 In other embodiments, the sidewalls of the photonic interconnect structure 100 and the interposer 150 may be substantially coplanar.

[0051] Further in Figure 6 In some embodiments, a conductive pad 222 and / or a conductive connector 224 may be formed on the interposer 150. The conductive pad 222 may be formed on the substrate 152 of the interposer 150, and the conductive pad 222 may be electrically connected to the through-hole 154. The conductive pad 222 may be similar to the conductive pad 28 described previously, however other types, materials, or formation processes of the conductive pad 222 are also possible. According to some embodiments, a conductive connector 224 may then be formed on the conductive pad 222. The conductive connector 224 may be similar to the conductive connector 30 described previously, however other conductive connectors 224 are also possible. In other embodiments, a second interconnect structure (not shown) is formed on the substrate 152 opposite to the interconnect structure 160, and a conductive connector 224 is formed on the second interconnect structure.

[0052] Figure 7 The photon package 200 is shown connected to a packaging substrate 252 to form a photon system 250 according to some embodiments. The packaging substrate 252 may include conductive pads, conductive wiring, and / or other conductive components that provide interconnection and electrical wiring. In some embodiments, the packaging substrate 252 may include an interposer, a semiconductor substrate (e.g., a wafer), a redistribution structure, an interconnect substrate, a core substrate, a printed circuit board (PCB), etc. In some embodiments, the packaging substrate 252 includes active devices and / or passive devices. In other embodiments, the packaging substrate 252 does not contain active devices and / or passive devices.

[0053] In some embodiments, the conductive connectors 224 of the photon package 200 are placed on corresponding conductive pads (not separately shown) of the packaging substrate 252, and then a reflow process is performed to bond the photon package 200 to the packaging substrate 252. In this way, the photon package 200 can be physically and electrically connected to the packaging substrate 252. In other embodiments, the photon package 200 can be bonded to the packaging substrate 252 using dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). In some embodiments, an underfill 253 can be deposited between the photon package 200 and the packaging substrate 252.

[0054] Figure 8 A photonic system 250 with a fiber coupler 254 is shown in accordance with some embodiments. Figure 8 The photonic system 250 is similar to Figure 7 The optical system 250 of the present invention is different in that the optical fiber coupler 254 is attached to the device area 101' of the photonic package 200. The optical fiber coupler 254 can facilitate communication between the optical system 250 and the optical fiber 256. In this way, the optical fiber coupler 254 can facilitate optical communication between the optical system 250 and an external optical system, package or component. The optical fiber 256 may include one or more optical fibers, which may be an array, etc. The optical fiber coupler 254 may be a fiber array unit (FAU) or the like, which is configured to couple an optical signal from the photonic package 200 into the optical fiber 256 and / or couple an optical signal from the optical fiber 256 into the photonic package 200. For example, the optical fiber coupler 254 may be optically coupled to the waveguide 26 within the device area 101'. Accordingly, the device area 101' may be configured to optically communicate with the optical fiber coupler 254. For example, the fiber coupler 254 may be coupled to the waveguide 26 through the first substrate 10, and a reflector, a grating coupler, a lens, etc. may be used to couple the optical signal to the waveguide 26. In some embodiments, the photonic system 250 receives optical power provided by the optical fiber 256 through the fiber coupler 254. In other embodiments, the fiber coupler 254 is not present, or a plurality of fiber couplers 254 may be used.

[0055] Fig. 9 A plan view of a photonic system 250 is shown in accordance with some embodiments. Fig. 9 The photonic system 250 may be similar to Figure 8 The photonic system 250, and Fig. 9 Indicates something like Figure 8 A cross-section of a cross-sectional view. Fig.10 Shows something like Figures 8 to 9 A cross-sectional view of the photon system 250 of the photon system 250 , Fig. 9 Indicates something like Fig.10 The photonic system 250 includes a photonic package 200 connected to a packaging substrate 252. The photonic package 200 includes a photonic interconnect structure 100 connected to an interposer 150, a packaging component 260, and a device 270. Figures 9 and 10 The photon system 250 shown in FIG. 2 is intended as an illustrative example, and other structures having other configurations, arrangements, sizes, or components are possible. For clarity, Fig. 9 Some components are not shown, such as the conductive features 164 of the interposer 150 , some waveguides 26 of the photonic interconnect structure 100 , and the like.

[0056] Package assembly 260 and / or device 270 may include, for example, a chip, a die, a system-on-chip (SoC) device, a system-on-integrated circuit (SoIC) device, a package, etc., or a combination thereof. In some embodiments, package assembly 260 and / or device 270 include a logic die, a memory die, an input-output (I / O) die, an integrated passive device (IPD), etc., or a combination thereof. For example, package assembly 260 and / or device 270 may include a logic die, such as a central processing unit (xPU or CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, an application-specific integrated circuit (ASIC) die, etc. Package assembly 260 and / or device 270 may include a memory die, such as a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a high-performance memory (HBM) die, etc. In some embodiments, the package components 260 and / or the devices 270 are connected to the interposer 150 via conductive connectors, which in some cases can be similar to the conductive connectors 30 of the photonic interconnect structure 100. For example, the conductive connectors can include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), etc. In other embodiments, different numbers or other types of package components 260 and / or devices 270 can be connected to the interposer 150.

[0057] In some embodiments, packaging assembly 260 may be part of an I / O interface between optical and electrical signals within photonic package 200. As an illustrative example, Fig.11A and Fig. 11B 2 shows a cross-sectional view and a plan view of a package assembly 260 according to some embodiments. Figures 9 and 10 and FIG. 11A to FIG. 11BIn the illustrated embodiment, package assembly 260 is a structure including one or more dies 266 connected to active interposer 262. In some cases, package assembly 260 may be considered a system-on-chip (SoC) device or a system-on-integrated circuit (SoIC) device. In other embodiments, package assembly 260 may have a different configuration, may include another number of dies 266, or may be another type of die, chip, package, etc.

[0058] Still refer to FIG. 11A to FIG. 11B , the active interposer 262 may include a substrate 263 and an interconnect structure 264 formed on one side of the substrate 263. The substrate 263 may be similar to the substrate previously described for the first substrate 10, such as a silicon wafer, etc. In some embodiments, an integrated circuit (not shown separately) may be formed in the substrate 263 using suitable techniques. For example, the integrated circuit may include a controller, a driver, a transimpedance amplifier, a transistor, other active devices, passive devices, etc., or a combination thereof. In some embodiments, the integrated circuit may be configured to interface with the photonic interconnect structure 100. For example, the integrated circuit may be configured to control the operation of the photonic component 18 to process an electrical signal corresponding to an optical signal received from the photonic interconnect structure 100, etc. In some embodiments, the active interposer 262 includes circuitry for processing electrical signals received from the photonic interconnect structure 100, such as for processing electrical signals received from the photonic component 18 including a photodetector. In some embodiments, the active interposer 262 may control the high-frequency signal transmission of the photonic component 18 according to an electrical signal (digital or analog) received from another device or die (e.g., a die 266 described below). In some embodiments, the active interposer 262 can provide a serializer / deserializer (SerDes) function. In this way, in some cases, the active interposer 262 can be considered an electronic integrated circuit (EIC) die. The active interposer 262 is electrically connected to the photonic interconnect structure 100 (and any corresponding device 270) through the interposer 150.

[0059] In some embodiments, the active interposer 262 includes a through hole extending through the substrate 263, which can be electrically connected to the interconnect structure 264. The interconnect structure 264 can include, for example, a wire, a conductive via, and / or a conductive pad formed in a dielectric layer to provide electrical interconnection. In some cases, the interconnect structure 264 can be similar to the interconnect structure 160 of the interposer 150, and similar materials or techniques can be used to form the interconnect structure 264. In some embodiments, another interconnect structure can be formed on the substrate 263 opposite to the interconnect structure 264, and the through hole can also be electrically connected to the other interconnect structure. A conductive connector 265 can be formed on the active interposer 262, and the conductive connector 265 can be similar to the conductive connector 30 described previously.

[0060] In some embodiments, one or more dies 266 may be connected to the interconnect structure 264 of the active interposer 262. The die 266 may include one or more processing devices, such as a central processing unit (CPU or xPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a high performance computing (HPC) die, a logic die, a die similar to the dies previously mentioned above, etc., or a combination thereof. The die 266 may include one or more memory devices, which may be volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), high bandwidth memory (HBM), another type of memory, etc.

[0061] In some embodiments, die 266 may include a bonding pad formed in the bonding layer, and die 266 is bonded to active interposer 262 by dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). In some embodiments, the bonding layer of die 266 is bonded to the bonding layer (e.g., the topmost dielectric layer) of interconnect structure 264 using a dielectric-to-dielectric bonding process, and the bonding pad of die 266 is bonded to the corresponding conductive pad of interconnect structure 264 using a metal-to-metal bonding process. In some embodiments, the bonding process may be initiated by activating the bonding surfaces of the bonding layers of die 266 and interconnect structure 264, which may facilitate bonding of the bonding surfaces. Activating the bonding surfaces may include, for example, dry processing, wet processing, plasma processing, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, and the like. For embodiments using wet processing, for example, an RCA cleaning process may be used. In other embodiments, the activation process may include other types of processing. After the activation process, the die 266 is aligned with the interconnect structure 264 and the die 266 is placed in physical contact with the interconnect structure 264. The die 266 and the active interposer 262 are then subjected to heat treatment and contact pressure to bond the bonding layer by dielectric-to-dielectric bonding, and the bonding pads of the die 266 are bonded to the conductive pads of the interconnect structure 264 by metal-to-metal bonding. In some embodiments, the bonding structure is then baked, annealed, pressed, or otherwise treated to strengthen or complete the bonding. This is just an example, and other bonding processes are also possible. In other embodiments, the die 266 may include conductive connectors (e.g., solder bumps, etc.), and these conductive connectors may be used to bond the die 266 to the active interposer 262.

[0062] In some embodiments, the package assembly 260 has a plurality of device regions 261, each of which may be associated with a corresponding device region 101 of the photonic interconnect structure 100. For example, FIG. 11A to FIG. 11BThe package assembly 260 shown in has two device areas 261, however another number of device areas 261 is also possible. In some embodiments, each device area 261 includes a portion of an active interposer 262 and a die 266. In this way, the combination of the device area 261 and the device area 101 can provide optical signal processing, interfaces and / or communications for the photonic system 250. In some embodiments, the device area 261 and / or the device area 101 can each have one or more associated devices 270. For example, the device 270 can be a memory die, such as an HBM die, etc., however other devices 270 are also possible. Other associations, arrangements or configurations are also possible.

[0063] In this manner, the photonic interconnect structure 100, the package assembly 260, and the device 270 of the photonic package 200 are electrically connected via the conductive features 164 within the interposer 150. The conductive features 164 can use electrical signals to ensure relatively short-distance communications within the photonic package 200. In some embodiments, the waveguide 26 within the photonic interconnect structure 100 is utilized to transmit optical signals within the photonic package 200, such as optical signals transmitted between device regions 101. In this manner, the waveguide 26 can be used to provide relatively long-distance communications within the photonic package 200 using optical signals. As an example, the die 266 of the first package assembly 260 can transmit electrical signals to the associated active interposer 262, which then transmits the corresponding electrical signals to the photonic assembly 18 of the first device region 101 of the photonic interconnect structure 100 to generate optical signals. The optical signal is transmitted to the second device area 101 in the photonic interconnect structure 100 through the waveguide 26, and in the second device area 101, other photonic components 18 in the second device area 101 can receive the optical signal. The photonic component 18 of the second device area 101 sends the corresponding electrical signal to the corresponding second package component 260. The active interposer 262 of the second package component 260 receives the electrical signal and transmits the corresponding electrical signal to the die 266 of the second package component 260. This is just an example, and other processes are also possible. In this way, by using the transmission of electrical signals through the interposer 150 over a short distance and the transmission of optical signals through the photonic interconnect structure 100 over a long distance, the efficiency, speed and / or bandwidth of the photonic package 200 (or the photonic system 250) can be improved, and the manufacturing cost can be reduced.

[0064] Figures 12 to 15 3 shows an intermediate step in forming a photonic interconnect structure 300 according to some embodiments. The photonic interconnect structure 300 is similar to the previously described photonic interconnect structure 100, except that the photonic interconnect structure 300 includes an electronic die 310 (see Fig.13). In some embodiments, the electronic die 310 can provide functionality similar to that previously described for the active interposer 262. In this way, the photonic interconnect structure 300 can provide both optical signal communication and optical signal processing, which can improve efficiency and reduce manufacturing costs. Some components or processing steps of the photonic interconnect structure 300 can be similar to those previously described for the photonic interconnect structure 100. Accordingly, some similar components can have similar reference numbers, and some similar details may not be repeated. In some embodiments, the photonic interconnect structure 300 includes a plurality of device regions 301, which can be associated with other packaging components or dies of the photonic package, similar to the device region 101 previously described.

[0065] Fig.12 Shows a similar Figure 3 The structure of the photonic interconnect structure 100 shown in FIG. 1 is different in that there is no conductive connection member 30. For example, Fig.12 The structure shown includes an optical interposer 50 formed over a first substrate 10. The optical interposer 50 includes, for example, a photonic component 18 and an interconnect structure 20 formed over the photonic component 18, the interconnect structure 20 including a conductive feature 24 and a waveguide 26 formed in a dielectric layer 22. In other embodiments, the waveguide 26 is not formed in the interconnect structure 20. The optical interposer 50 may be formed using materials or techniques similar to those previously described for the photonic interconnect structure 100. Fig.12 The structure shown, such as for Figures 1 to 3 In some embodiments, the conductive pad 28 may be a bonding pad suitable for metal-to-metal bonding, and may include a corresponding suitable material, such as copper, a copper alloy, etc. In some embodiments, the topmost dielectric layer 22 may include a material suitable for dielectric-to-dielectric bonding, such as silicon oxide, etc., and the topmost dielectric layer 22 may be regarded as a "bonding layer". A planarization process (e.g., a CMP process or a grinding process) may be performed so that the conductive pad 28 and the topmost dielectric layer 22 have a flush or coplanar surface.

[0066] exist Fig.13In some embodiments, the electronic die 310 is bonded to the interconnect structure 20. In some cases, the electronic die may be considered an electronic integrated circuit (EIC) die, etc. In some embodiments, the electronic die 310 may include a device region corresponding to the device region of the underlying structure and corresponding to the device region 301 of the final photonic interconnect structure 300. In some embodiments, the electronic die 310 may include a bonding pad 312 formed in a bonding layer, and the electronic die 310 may be bonded to the interconnect structure 20 by dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.), which will be described in more detail below.

[0067] After bonding, the electronic die 310 may be electrically connected to the photonic assembly 18 through the interconnect structure 20. The electronic die 310 may include an integrated circuit for interfacing with the photonic assembly 18, such as a circuit for controlling the operation of the photonic assembly 18. For example, the electronic die 310 may include a controller, a driver, a transimpedance amplifier, etc., or a combination thereof. The electronic die 310 may include, for example, a chip, a die, a system-on-chip (SoC) device, a system-on-integrated circuit (SoIC) device, a package, etc., or a combination thereof. The electronic die 310 may include one or more processing devices, such as a central processing unit (CPU or "xPU"), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a high-performance computing (HPC) die, a logic die, etc., or a combination thereof. The electronic die 310 may include one or more memory devices, which may be volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), high bandwidth memory (HBM), other types of memory, etc. In some embodiments, the electronic die 310 includes circuits for processing electrical signals received from the photonic component 18, such as for processing electrical signals received from the photonic component 18 including a photodetector. In some embodiments, the electronic die 310 can control the high-frequency signal transmission of the photonic component 18 based on an electrical signal (digital or analog) received from another device or die. In some embodiments, the electronic die 310 can provide a serializer / deserializer (SerDes) function. In some embodiments, the electronic die 310 can be used as part of an I / O interface between optical signals and electrical signals within the photonic interconnect structure 300. In some cases, the photonic interconnect structure 300 described herein can be viewed as a system-on-chip (SoC) device, a system-on-integrated circuit (SoIC) device, an "optical engine", "optical die", "optical structure", etc.

[0068] In some embodiments, a bonding layer of the electronic die 310 is bonded to the topmost dielectric layer 22 (e.g., "bonding layer") of the interconnect structure 20 using a dielectric-to-dielectric bonding process, and a bonding pad 312 of the electronic die 310 is bonded to a corresponding conductive pad 28 of the interconnect structure 20 using a metal-to-metal bonding process. In some embodiments, the bonding process can be initiated by activating a bonding surface of the bonding layer, which can facilitate bonding of the bonding surfaces. Activating the bonding surface can include, for example, dry processing, wet processing, plasma processing, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, and the like. For embodiments using wet processing, for example, an RCA cleaning process can be used. In other embodiments, the activation process can include other types of processing.

[0069] After the activation process, the interconnect structure 20 and the electronic die 310 can be cleaned using, for example, a chemical rinse, and then the electronic die 310 is aligned with the interconnect structure 20 and placed in physical contact with the interconnect structure 20. The bonding layers can then be bonded together by dielectric-to-dielectric bonding using heat treatment and contact pressure, and the bonding pads 312 are bonded to the conductive pads 28 by metal-to-metal bonding. In some embodiments, the bonded structure is then baked, annealed, pressed, or otherwise treated to strengthen or complete the bond. This is just an example, and other bonding processes are also possible. In some embodiments, a planarization process is performed to remove portions of the electronic die 310. In some embodiments, a support structure (not shown) is attached to the electronic die 310 to provide mechanical support for the photonic interconnect structure 300.

[0070] exist Fig.14 In some embodiments, the first substrate 10 is removed and an optical interconnect structure 320 is formed on the optical interposer 50. In some embodiments, the first substrate 10 is removed using a planarization process, such as using a CMP process, a grinding process, one or more etching processes, a combination of these processes, and the like. In other embodiments, the first insulating layer 12 is also removed. According to some embodiments, the optical interconnect structure 320 includes a waveguide 324 formed in one or more dielectric layers 322 (not shown separately). The waveguide 324 can be similar to the waveguide 26 described previously. For example, in some embodiments, the waveguide 324 can include a silicon nitride waveguide, a coupler, and the like. In some cases, one or more waveguides 324 can be optically coupled to each other and / or optically coupled to one or more photonic components 18. In this way, the optical interconnect structure 320 can provide optical communication and optical interconnection within the photonic interconnect structure 300. In other embodiments, conductive components are also formed in the optical interconnect structure 320.

[0071] In some embodiments, the waveguide 324 may be formed using materials or techniques similar to those used to form the waveguide 26. For example, the waveguide 324 may be formed by depositing a material for the waveguide 324 on the dielectric layer 322, and then patterning the material using suitable photolithography and etching techniques. The material for the waveguide 324 may be a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, a polymer, a combination of these, or the like. Another dielectric layer 322 may then be deposited on the waveguide 324. The dielectric layer 322 may include, for example, silicon oxide, spin-on glass, or the like. Other materials are also possible. In certain embodiments, the optical interconnect structure 320 may have a multilayer waveguide 324, but the exact number of layers of the waveguide 324 and / or the dielectric layer 322 may depend on the design of the photonic interconnect structure 300.

[0072] According to some embodiments, Fig.15 In the embodiment of the present invention, a through hole 326 is formed that penetrates the optical interconnect structure 320 and the second insulating layer 16. The through hole 326 can physically contact and electrically contact the conductive component 24 of the interconnect structure 20. In some embodiments, the through hole 326 can extend into one or more dielectric layers 22. The through hole 326 can be formed, for example, by forming an opening extending through the dielectric layer 322, the second insulating layer 16 and / or one or more dielectric layers 22 to expose the surface of the conductive component 24. The opening can be formed using acceptable photolithography and etching techniques, such as by forming and patterning a photoresist, and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process. A conductive material can then be formed in the opening to form the through hole 326. In some embodiments, a liner (not shown) can be deposited in the opening before the conductive material is formed. The conductive material may include, for example, a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, and the like. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the surface of the optical interconnect structure 320 (e.g., the dielectric layer 322) so that the via 326 is flush with the surface of the optical interconnect structure 320. Other materials or techniques are also possible. In other embodiments, the via 326 is omitted.

[0073] Still refer to Fig.15 According to some embodiments, a passivation layer 327 may be formed over the optical interconnect structure 320. The passivation layer 327 may include, for example, a polymer such as PBO, polyimide, BCB, etc.; a nitride such as silicon nitride, etc.; an oxide such as silicon oxide, PSG, BSG, BPSG, etc.; a sealant, a molding compound, etc.; etc., or a combination thereof. The passivation layer 327 may be formed by, for example, spin coating, lamination, CVD, PVD, ALD, etc. In some embodiments, photonic components such as waveguides, etc. may also be formed in the passivation layer 327.

[0074] Then, under-bump metallization (UBM) 329 may be formed within passivation layer 327 to make physical and electrical contact with via 326. In other embodiments, UBM 329 is formed before forming passivation layer 327. In such an embodiment, an opening is formed in passivation layer 327 that may expose UBM 329. In some embodiments, UBM 329 may be formed by forming an opening in passivation layer 327 using acceptable photolithography and etching techniques, such as by forming and patterning a photoresist, and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process. Then, one or more conductive materials may be deposited in the opening to form UBM 329. In other embodiments, UBM 329 has a bump portion that is located on the main surface of passivation layer 327 and extends along the main surface of passivation layer 327. In other embodiments, passivation layer 327 and / or UBM 329 are not formed. According to some embodiments, conductive connectors 328 may then be formed on UBM 329. Conductive connectors 328 may be similar to previously described conductive connectors 30 or 265. For example, in some embodiments, conductive connectors 328 may be solder bumps or the like.

[0075] The photonic interconnect structure 300 can have any suitable size and any suitable number and / or arrangement of device regions 301. As another example, Fig.16 3 shows a cross-sectional view of a photonic interconnect structure 300 according to some embodiments. In addition to the number and arrangement of device regions 301, Fig.16 The photonic interconnect structure 300 may be similar to Fig.15 In some cases, the photonic interconnect structure 300 may be Fig.16 Considered to be Fig.15 In some embodiments, the photonic interconnect structure 300 may have a length in a range of about 3000 μm to about 300,000 μm, or may have a width in a range of about 500 μm to about 100,000 μm, although other dimensions are possible.

[0076] exist Fig.17 In some embodiments, the photonic interconnect structure 300 is connected to the interposer 150 to form a photonic package 350. The photonic package 350 may be similar to Figure 6 The photonic package 200 of FIG. 1 is shown in FIG. 1 , except that the photonic interconnect structure 300 is attached to the interposer 150 and the die 266 can be directly connected to the interposer 150 as described in more detail below. The interposer 150 can be similar to the one previously described for FIG. Figure 5For example, the interposer 150 may include the conductive component 164. Other packaging components (e.g., Figures 9 and 10 The die 266 or device 270) is connected to the interposer 150, as described in more detail below. Fig.17 As shown, a fiber coupler 254 and / or an optical fiber 256 may be attached to the device region 301 ′ of the photonic package 350 to facilitate external optical communications.

[0077] In some embodiments, the conductive connectors 328 of the photonic interconnect structure 300 may be placed on corresponding conductive pads (not separately shown) of the interposer 150. A reflow process may then be performed to bond the conductive connectors 328 to the interposer 150. In this manner, the photonic interconnect structure 300 is physically and electrically connected to the interposer 150, and the interposer 150 may provide electrical interconnection between the photonic interconnect structure 300 and other package components. In some embodiments, the interposer 150 may also provide electrical interconnection between the device regions 301 of the photonic interconnect structure 300. In some embodiments, an underfill 165 may be deposited between the photonic interconnect structure 300 and the interposer 150. In some embodiments, the sidewalls of the photonic interconnect structure 300 and the interposer 150 may be substantially coplanar, such as Fig.17 In other embodiments, the sidewalls of the photonic interconnect structure 300 deviate from the sidewalls of the interposer 150. Fig.17 In the embodiment, conductive pads 222 and / or conductive connectors 224 may be formed on the interposer 150 , and the conductive pads 222 and / or conductive connectors 224 may be similar to the conductive pads and / or conductive connectors described previously.

[0078] Fig.18 2 shows the connection of the photonic package 350 to the packaging substrate 252 to form the photonic system 370 according to some embodiments. The packaging substrate 252 can be connected to the photonic system 370 described previously. Figure 7 In some embodiments, an underfill 253 may be deposited between the photonic package 350 and the packaging substrate 252 .

[0079] Fig.19 A plan view of a photonic system 370 is shown in accordance with some embodiments. Fig.19 The photonic system 370 may be similar to Fig.18 The photonic system 370, and Fig.19 Indicates something like Fig.18 A cross-section of a cross-sectional view. Fig. 20 Shows something like Figure 18 to Figure 19 A cross-sectional view of a photon system 370 of a photon system, and Fig.19 Indicates something like Fig. 20The photonic system 370 includes a photonic package 350 connected to a packaging substrate 252. The photonic package 350 includes a photonic interconnect structure 300 connected to an interposer 150, a die 266, and a device 270. Figure 19 to Figure 20 The photon system 370 shown in FIG. 1 is intended as an illustrative example, and other structures having other configurations, arrangements, sizes, or components are possible. For clarity, Fig.19 Some components are not shown, such as the conductive features 164 of the interposer 150 , some waveguides 26 of the photonic interconnect structure 300 , and the like.

[0080] The die 266 and the device 270 can be similar to the die and devices previously described for the photonic system 250. For example, in some embodiments, the device 270 can be an HBM die and the die 266 can be an xPU die, however other devices, die, or combinations thereof are also possible. In some embodiments, the die 266 and / or the device 270 are connected to the interposer 150 via a conductive connector, which can be similar to the conductive connectors previously described. In other embodiments, different numbers or other types of die 266 and / or devices 270 can be connected to the interposer 150. In other embodiments, the photonic system 370 can include only one of the die 266 or the device 270.

[0081] The photonic interconnect structure 300, the die 266, and the device 270 of the photonic package 350 are electrically connected through the conductive features 164 in the interposer 150. The conductive features 164 can ensure relatively short-distance communication within the photonic package 350 using electrical signals. For example, the related die 266, the device 270, and the device area 301 can be electrically connected through the interposer 150. In some embodiments, the waveguides 26 and / or 324 in the photonic interconnect structure 300 are utilized to transmit optical signals within the photonic package 350, such as optical signals transmitted between the device areas 301. In this way, the waveguides 26 / 324 can be used to provide relatively long-distance communication within the photonic package 350 using optical signals. In this way, by using the transmission of electrical signals over a short distance through the interposer 150 and the transmission of optical signals over a long distance through the photonic interconnect structure 300, the efficiency, speed, and / or bandwidth of the photonic package 350 (or the photonic system 370) can be improved, and the manufacturing cost can be reduced.

[0082] Fig.21 4 shows a photonic package 400 according to some embodiments. The photonic package 400 may be similar to the previous Figure 6 The photonic package 200 described above differs in that the photonic interconnect structure 100 is connected to the interposer 150 using dielectric-to-dielectric bonding and metal-to-metal bonding. The photonic interconnect structure 100 is similar to Figure 6The photonic interconnect structure 100 is different in that the conductive pad 28 may be a bonding pad suitable for metal-to-metal bonding. The interposer 150 is similar to Figure 6 The interposer 150 is similar to the interposer 150, except that the interposer 150 includes a bonding pad 153 formed in the topmost dielectric layer 162. The conductive pad 28 may be bonded to the bonding pad 153 using metal-to-metal bonding, such as previously described for Fig.13 The bonding layer of dielectric layer 22 may be bonded to the bonding layer (eg, the topmost layer) of dielectric layer 162 using dielectric-to-dielectric bonding, such as described previously for Fig.13 The photonic package 400 may be connected to the packaging substrate 252 to form a photonic system.

[0083] Fig. 22 4 shows a photonic package 450 according to some embodiments. The photonic package 450 may be similar to the previous embodiments for Fig.17 The photonic package 350 is described in detail except that the photonic interconnect structure 300 is connected to the interposer 150 using dielectric-to-dielectric bonding and metal-to-metal bonding. The photonic interconnect structure 300 is similar to Fig.17 The photonic interconnect structure 300 is similar to the photonic interconnect structure 300, except that the conductive pad 329 can be a bonding pad suitable for metal-to-metal bonding, and the passivation layer 327 can be a bonding layer suitable for dielectric-to-dielectric bonding. Fig. 22 For example, the interposer 150 includes a bonding pad 153 formed in the topmost dielectric layer 162. The conductive pad 329 may be bonded to the bonding pad 153 using metal-to-metal bonding, such as previously described for Fig.13 The passivation layer 327 may be bonded to a bonding layer (eg, a topmost layer) of the dielectric layer 162 using a dielectric-to-dielectric bond, such as described previously for Fig.13 In this way, using metal-to-metal bonding and dielectric-to-dielectric bonding instead of using conductive connectors can reduce package size, improve electrical connections, and improve device efficiency. As with other photonic packages described herein, photonic package 450 can be connected to packaging substrate 252 to form a photonic system.

[0084] Fig.23 2 shows a photonic system 500 according to some embodiments. The photonic system 500 is similar to the Fig.10The photonic system 250 is described except that a redistribution interposer 510 is used instead of the interposer 150. For example, the photonic system 500 includes a photonic package 502, which includes a photonic interconnect structure 100 connected to the redistribution interposer 510, a packaging component 260, and a device 270. The photonic package 502 can be connected to the packaging substrate 252 using conductive connectors 224 and the like to form the photonic system 500.

[0085] The redistribution interposer 510 may be, for example, an organic interposer, a redistribution structure, etc. The redistribution interposer 510 may include a plurality of redistribution layers 512 formed in a plurality of dielectric layers 514 (not shown separately). The redistribution layer 512 may include conductive lines, conductive vias, conductive pads, etc. The redistribution layer 512 may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. In some embodiments, the dielectric layer 514 may include a polymer, such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB)-based polymer, etc. In other embodiments, the dielectric layer 514 may include other suitable dielectric materials, such as silicon oxide, etc. The redistribution layer 512 may be formed using any suitable process, such as deposition, plating, inlay, dual inlay, etc. In some embodiments, the redistribution interposer 510 is substantially free of active devices and passive devices. In other embodiments, the redistribution interposer 510 includes a waveguide formed in the dielectric layer 514. In some cases, using redistribution interposer 510 may reduce manufacturing costs and package size.

[0086] Fig.24 2 shows a photonic system 550 according to some embodiments. The photonic system 550 is similar to the Fig. 20 The photonic system 370 is described, except that a redistribution interposer 510 is used instead of the interposer 150. For example, the photonic system 550 includes a photonic package 552, which includes the photonic interconnect structure 300, the die 266, and the device 270 connected to the redistribution interposer 510. The redistribution interposer 510 can be similar to the previously described Fig.23 Redistribution interposer 510 is depicted. Photonic package 552 may be connected to packaging substrate 252 using conductive connectors 224 or the like to form photonic system 550.

[0087] Fig.25A cross-sectional view of a photonic interconnect structure 600 according to some embodiments is shown. Some components of the photonic interconnect structure 600 can be similar to components of the previously described photonic interconnect structure 100 and / or photonic interconnect structure 300. For example, in some embodiments, the photonic interconnect structure 600 includes an interconnect structure 620 formed above a photonic component 618 in a dielectric layer 626. The photonic component 618 can be similar to the previously described photonic component 18, and the dielectric layer 626 can be similar to the previously described second insulating layer 16. The interconnect structure 620 can be similar to the previously described interconnect structure 20, and can include a conductive feature 624 electrically connected to the photonic component 618. An optical interconnect structure 670 can be formed above the photonic component 618, the optical interconnect structure 670 including a waveguide 626 formed in a dielectric layer 673, and the optical interconnect structure 670, the waveguide 626, and the dielectric layer 673 can be similar to the optical interconnect structure 320, the waveguide 324, and the dielectric layer 322 of the photonic interconnect structure 300. A via 676 may be formed through the optical interconnect structure 670 , the via 676 being electrically connected to the conductive feature 624 .

[0088] In some embodiments, the electronic die 610 is bonded to the interconnect structure 620. The electronic die 610 can be similar to the electronic die 310 described previously and can provide similar functionality. A through-hole 616 can extend through the electronic die 610, and in some cases, the through-hole 616 can be electrically connected to the conductive feature 624. The electronic die 610 can be bonded to the interconnect structure 620 by metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the photonic interconnect structure 600 includes a device region 601. In this manner, the photonic interconnect structure 600 can be similar to the photonic interconnect structure 300, and the photonic interconnect structure 600 can be formed using similar techniques.

[0089] Fig.26 A photonic system 700 is shown in accordance with some embodiments. Fig.26 The photonic system 700 is similar to Fig.24 The photonic system 550 of the present invention is different in that the local interconnect 702 is formed in the redistribution interposer 510, and the photonic interconnect structure 600 is formed within the redistribution interposer 510. In some embodiments, the photonic package 710 may include the redistribution interposer 510, the local interconnect 702 located within the redistribution interposer 510, the photonic interconnect structure 600 located within the redistribution interposer 510, the die 266 connected to the redistribution interposer 510, and the device 270 connected to the redistribution interposer 510. The photonic package 710 may be connected to the package substrate 252 through the conductive connector 224 or the like.

[0090] The local interconnect 702 may be, for example, a chip, a chip module, a local silicon interconnect, an interconnect structure, etc., which provides additional electrical interconnection within the redistribution interposer 510. For example, the local interconnect 702 may provide electrical connections between adjacent components (such as the die 266, the device 270, etc.). The local interconnect 702 may include conductive features (e.g., wires, vias, pads, etc.) formed in a dielectric layer. The conductive features may be formed using suitable techniques, such as inlays, dual inlays, etc. For example, in some cases, the local interconnect 702 may include an interconnect structure located on a substrate, which may have a through-substrate via (TSV) therein, however other local interconnects 702 are also possible. In some cases, the conductive features of the local interconnect 702 may have a smaller line width and / or pitch than the redistribution layer 512 of the redistribution interposer 510, which may allow for a greater density of electrical wiring. The local interconnect 702 may or may not include passive devices or active devices. Fig.26 The local interconnects 702 shown in FIG. 7 are illustrative examples, and other local interconnects 702 or configurations thereof are possible.

[0091] The photonic interconnect structure 600 is formed within the redistribution interposer 510 to provide electrical and optical communications within the photonic system 700. In some embodiments, one or more dies 266, devices 270, etc. may be connected to the photonic interconnect structure 600 via conductive connectors or metal-to-metal bonding. In some cases, the die 266 and / or the device 270 may be connected to the associated device region 601 of the photonic interconnect structure 600. The photonic interconnect structure 600, the die 266, and the device 270 of the photonic package 710 are electrically connected through the redistribution layer 512 within the redistribution interposer 510 and / or through the local interconnect 702. In some embodiments, a waveguide 626 within the photonic interconnect structure 600 is utilized to transmit optical signals within the photonic system 700, such as optical signals transmitted between the device regions 601. For example, the waveguide 626 may be used to provide relatively long-distance communication within the photonic package 710 using optical signals. In this manner, by using electrical signals transmitted over short distances through redistribution interposer 510 and local interconnects 702 and optical signals transmitted over long distances through photonic interconnect structure 600 , the efficiency, speed, and / or bandwidth of photonic system 700 may be improved and manufacturing costs may be reduced.

[0092] In some embodiments, the local interconnects 702 and the photonic interconnect structure 600 may be placed on a carrier substrate (not shown), and then the redistribution interposer 510 may be formed around the local interconnects 702 and the photonic interconnect structure 600. In other embodiments, the redistribution interposer 510 may be formed first, and then the local interconnects 702 and the photonic interconnect structure 600 may be placed in openings formed in the redistribution interposer 510. In some embodiments, the top surfaces of the local interconnects 702, the photonic interconnect structure 600, and / or the redistribution interposer 510 may be substantially flush or coplanar.

[0093] Fig. 27 A plan view of a photonic system 700 is shown in accordance with some embodiments. Fig. 27 The photonic system 700 may be similar to Fig.26 The photonic system 700, and Fig. 27 Indicates something like Fig.26 2. The photonic system 700 includes a photonic package 710 connected to the package substrate 252. The photonic package 710 includes a photonic interconnect structure 600 and a local interconnect 702 located within the redistribution interposer 510, as well as a die 266 and a device 270 connected to the redistribution interposer 510. In some embodiments, the fiber coupler 254 and / or the optical fiber 256 can be optically coupled to the photonic interconnect structure 600. Fig. 27 The photonic system 700 shown in FIG. 7 is intended as an illustrative example, and other structures having other configurations, arrangements, sizes, or components are possible. For clarity, Fig. 27 Some parts are not shown.

[0094] Embodiments of the present disclosure have some advantageous features. By using electrical signals transmitted over short distances and optical signals transmitted over long distances, the efficiency, speed and / or bandwidth of devices, packages or structures can be improved. Photonic interconnect structures described herein can be used to ensure optical communication within a package. A single photonic structure can include multiple device regions, which can replace multiple photonic dies. Forming multiple device regions within a single structure can reduce manufacturing costs, reduce package size, and ensure optical communication between each die or device of a package. This can allow more dies or devices to be optically connected within a single package. In some cases, some photonic interconnect structures described herein can be considered as "monolithic" structures. The embodiments described herein can promote electrical and optical communication within a package, which can improve performance and efficiency.

[0095] In an embodiment of the present disclosure, a package includes an interposer; a photonic interconnect structure connected to the interposer, wherein the photonic interconnect structure includes: a photonic component; a waveguide optically coupled to the photonic component; and an electronic tube core electrically coupled to the photonic component; and a tube core electrically connected to the interposer, wherein the tube core is electrically coupled to the photonic interconnect structure through the interposer. In an embodiment, the photonic interconnect structure is connected to the interposer through a solder bump. In an embodiment, the photonic interconnect structure is connected to the interposer through a dielectric-to-dielectric bond and a metal-to-metal bond. In an embodiment, the waveguide is a silicon nitride waveguide. In an embodiment, the interposer includes a conductive redistribution layer in a polymer dielectric layer. In an embodiment, the package includes an optical fiber array unit attached to the electronic tube core, wherein the optical fiber array unit is optically coupled to the waveguide. In an embodiment, the tube cores are electrically coupled to corresponding separate device areas of the photonic interconnect structure, respectively. In an embodiment, the device areas of the photonic interconnect structure include corresponding areas of the electronic tube core and corresponding groups of photonic element components, respectively.

[0096] In an embodiment of the present disclosure, a package includes: an interposer; a photonic interconnect structure connected to the interposer, wherein the photonic interconnect structure includes: a plurality of photonic components; a plurality of waveguides optically coupled to the plurality of photonic components; and an electronic die electrically coupled to the plurality of photonic components; and a plurality of dies electrically connected to the interposer, wherein the dies of the plurality of dies are electrically coupled to the photonic interconnect structure through the interposer. In an embodiment, the photonic interconnect structure is connected to the interposer through solder bumps. In an embodiment, the photonic interconnect structure is connected to the interposer through dielectric-to-dielectric bonding and metal-to-metal bonding. In an embodiment, the plurality of waveguides are silicon nitride waveguides. In an embodiment, the interposer includes a plurality of conductive redistribution layers located in a plurality of polymer dielectric layers. In an embodiment, the package further includes an optical fiber array unit attached to the electronic die, wherein the optical fiber array unit is optically coupled to the plurality of waveguides. In an embodiment, the dies of the plurality of dies are electrically coupled to respective individual device regions of the photonic interconnect structure, respectively. In an embodiment, the device regions of the photonic interconnect structure include respective regions of the electronic die and respective groups of photonic components of the plurality of photonic components, respectively.

[0097] In an embodiment of the present disclosure, a package includes a photonic structure connected to an interconnect structure, wherein the photonic structure includes a first device region, a second device region, and a waveguide, wherein the first device region includes a first photonic component, wherein the second device region includes a second photonic component, wherein the first device region is optically coupled to the second device region through the waveguide; a first package component connected to the interconnect structure, wherein the first package component is electrically coupled to the first device region; and a second package component connected to the interconnect structure, wherein the second package component is electrically coupled to the second device region. In an embodiment, the first package component includes a first integrated circuit die and a second integrated circuit die bonded to an active interposer. In an embodiment, the first integrated circuit die is electrically coupled to the first device region of the photonic structure, and the second integrated circuit die is electrically coupled to the third device region of the photonic structure. In an embodiment, the first package component is a first semiconductor die, and the second package component is a second semiconductor die. In an embodiment, the photonic structure includes a glass substrate. In an embodiment, the first photonic component and the second photonic component are formed on a substrate, wherein the first device region and the second device region respectively include different portions of the substrate, wherein the substrate does not contain passive devices and active devices. In an embodiment, the substrate is a glass substrate. In an embodiment, the photonic structure includes an electronic die, wherein a first portion of the electronic die within a first device region is electrically coupled to a first photonic component, and a second portion of the electronic die within a second device region is electrically coupled to a second photonic component. In an embodiment, a first packaging component is electrically coupled to the first photonic component, and a second packaging component is electrically coupled to the second photonic component.

[0098] In an embodiment of the present disclosure, a method of forming a package includes: forming a photonic interconnect structure, forming the photonic interconnect structure includes: forming a plurality of first waveguides; forming a plurality of photonic components above the plurality of first waveguides; forming an interconnect structure above the plurality of photonic components; and bonding an electronic die to the interconnect structure; bonding the photonic interconnect structure to an interposer; and bonding a plurality of semiconductor dies to the interposer, wherein the plurality of semiconductor dies are electrically connected to the photonic interconnect structure. In an embodiment, the method of forming a package also includes forming a plurality of second waveguides within the interconnect structure. In an embodiment, bonding the photonic interconnect structure includes performing a fusion bonding process. In an embodiment, the method of forming a package also includes bonding the interposer to a package substrate.

[0099] In an embodiment of the present disclosure, a method includes forming a photonic interconnect structure, forming the photonic interconnect structure includes: forming a first waveguide; forming a photonic component above the first waveguide; forming an interconnect structure above the photonic component; and bonding an electronic die to the interconnect structure; bonding the photonic interconnect structure to an interposer; and bonding a semiconductor die to the interposer, wherein the semiconductor die is electrically connected to the photonic interconnect structure. In an embodiment, the method includes forming a second waveguide within the interconnect structure. In an embodiment, bonding the photonic interconnect structure includes performing a fusion bonding process. In an embodiment, the method includes bonding the interposer to a packaging substrate.

[0100] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A package comprising: Intermediary layer; A photonic interconnect structure connected to the interposer, wherein the photonic interconnect structure comprises: multiple photonic components; a plurality of waveguides optically coupled to the plurality of photonic components; and an electronic die electrically coupled to the plurality of photonic components; and A plurality of dies are electrically connected to the interposer, wherein the dies of the plurality of dies are electrically coupled to the photonic interconnect structure through the interposer.

2. The package according to claim 1, wherein: The photonic interconnect structure is connected to the interposer via solder bumps.

3. The package according to claim 1, wherein: The photonic interconnect structure is connected to the interposer through dielectric-to-dielectric bonding and metal-to-metal bonding.

4. The package according to claim 1, wherein: The plurality of waveguides are silicon nitride waveguides.

5. The package according to claim 1, wherein: The interposer includes a plurality of conductive redistribution layers disposed within a plurality of polymer dielectric layers.

6. The package of claim 1 further comprising a fiber array unit attached to the electronic die, wherein: The optical fiber array unit is optically coupled to the plurality of waveguides.

7. The package according to claim 1, wherein: The dies of the plurality of dies are respectively electrically coupled to corresponding individual device regions of the photonic interconnect structure.

8. The package according to claim 7, wherein: The device regions of the photonic interconnect structure include corresponding regions of the electronic die and corresponding groups of photonic components of the plurality of photonic components, respectively.

9. A package comprising: a photonic structure connected to the interconnect structure, wherein the photonic structure comprises a first device region, a second device region, and a waveguide, wherein the first device region comprises a first photonic component, wherein the second device region comprises a second photonic component, wherein the first device region is optically coupled to the second device region through the waveguide; a first package component connected to the interconnect structure, wherein the first package component is electrically coupled to the first device region; and A second package component is connected to the interconnect structure, wherein the second package component is electrically coupled to the second device region.

10. A method of forming a package, comprising: Forming a photonic interconnect structure, the forming of the photonic interconnect structure comprising: forming a plurality of first waveguides; forming a plurality of photonic components above the plurality of first waveguides; forming an interconnect structure over the plurality of photonic components; and bonding an electronic die to the interconnect structure; bonding the photonic interconnect structure to an interposer; and A plurality of semiconductor dies are bonded to the interposer, wherein the plurality of semiconductor dies are electrically connected to the photonic interconnect structure.

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