A novel method for preparing a power device and a power device

Abstract

The present application discloses a method for preparing a novel power device and a power device, which relates to the technical field of power semiconductor devices and can solve the problem of excessive stress of Vds under fast shutdown of SGT MOSFET devices, thereby improving the stability of the device. The method comprises: forming an epitaxial layer on a first surface of a first substrate; forming a plurality of polysilicon on the epitaxial layer, the polysilicon comprising a first polysilicon and a second polysilicon, the first polysilicon and the second polysilicon being arranged alternately; connecting each of the first polysilicon to a first electrode, connecting each of the second polysilicon to a second electrode, to obtain a target structure; connecting the first electrode to the gate of the device structure, and connecting the second electrode to the source of the device structure.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a preparation method of a novel power device and a power device. Background Art

[0002] Shielded Gate Trench (SGT) MOSFET device is an innovative trench power MOSFET with low on-resistance, low switching loss, and superior frequency characteristics. It can be used in core power key components such as mobile phone fast charging, motor drive and power management system. In addition, with the rise of electric vehicles, the demand for medium and low voltage MOSFET is increasing. SGT MOSFET helps improve system efficiency and power density in motor control and power battery systems.

[0003] In SGT MOSFET, by connecting the shield electrode to the source electrode, this design achieves the function of shielding the gate and drift region, thereby reducing the Miller capacitance and gate charge of the device and accelerating the switching speed of the device. However, this also causes the device to have excessive Vds stress under fast shutdown, resulting in the risk of device breakdown, damage or even burning. Summary of the invention

[0004] The present application provides a novel method for preparing a power device and a power device, which can solve the problem of excessive Vds stress during fast shutdown of an SGT MOSFET device, thereby improving the stability of the device.

[0005] In order to achieve the above purpose, this application adopts the following technical solutions:

[0006] In a first aspect of the embodiments of the present application, a method for preparing a novel power device is provided, the method comprising:

[0007] forming an epitaxial layer on a first surface of a first substrate;

[0008] forming a plurality of polysilicon layers on the epitaxial layer, wherein the polysilicon layers include first polysilicon and second polysilicon layers, and the first polysilicon layers and the second polysilicon layers are arranged alternately;

[0009] Connecting each of the first polysilicon to a first electrode, and connecting each of the second polysilicon to a second electrode, to obtain a target structure;

[0010] The first electrode is connected to a gate of the device structure, and the second electrode is connected to a source of the device structure.

[0011] As a possible implementation manner, the forming a plurality of polysilicon layers on the epitaxial layer includes:

[0012] Depositing a polysilicon layer on the epitaxial layer;

[0013] The polysilicon layer is etched to form the first polysilicon and the second polysilicon.

[0014] As a possible implementation manner, the step of connecting each first polysilicon to the first electrode includes:

[0015] forming a first passivation layer on the first polysilicon and the second polysilicon;

[0016] After forming a plurality of etching holes in the first passivation layer, forming a first electrode and a second electrode on the first passivation layer, the etching holes including a first etching hole and a second etching hole;

[0017] The first electrode is connected to the first polysilicon through a first etched hole.

[0018] As a possible implementation manner, the step of connecting each second polysilicon to the second electrode includes:

[0019] The second electrode is connected to the second polysilicon through a second etched hole.

[0020] As a possible implementation manner, before connecting the first electrode to the gate of the device structure, the method further includes:

[0021] forming a gate and the source on the first surface of the second substrate;

[0022] A drain is formed on the second surface of the second substrate.

[0023] As a possible implementation manner, forming the gate and the source on the first surface of the second substrate includes:

[0024] After etching a plurality of second grooves on the first surface of the second substrate, a second grooved surface is obtained;

[0025] After oxidizing the second groove-shaped surface to form an oxide layer, second polysilicon is filled in the second groove to obtain a substrate structure;

[0026] The gate and the source are formed on the substrate structure.

[0027] As a possible implementation manner, forming the gate and the source on the substrate structure includes:

[0028] After etching the first surface of the substrate structure along each second groove position, an isolation layer is formed at the groove position to obtain an isolation surface;

[0029] After forming a gate oxide layer on the isolation surface, filling gate polysilicon at the trench position on the gate oxide layer;

[0030] The source is formed in the second substrate below the gate oxide layer.

[0031] As a possible implementation manner, forming the source electrode in the second substrate under the gate oxide layer includes:

[0032] A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.

[0033] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.

[0034] In a second aspect of the embodiment of the present application, a power device is provided, the power device comprising: a target structure and a device structure; the target structure comprises:

[0035] a first substrate;

[0036] an epitaxial layer, located on the first surface of the first substrate;

[0037] A plurality of polysilicon layers, located on the epitaxial layer, the polysilicon layers comprising first polysilicon and second polysilicon layers, wherein the first polysilicon layers and the second polysilicon layers are arranged alternately;

[0038] A first electrode and a second electrode are located on the polysilicon, the first polysilicon is connected to the first electrode, and the second polysilicon is connected to the second electrode;

[0039] The first electrode is also connected to the gate of the device structure, and the second electrode is also connected to the source of the device structure.

[0040] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0041] The method for preparing a novel power device provided in an embodiment of the present application comprises forming an epitaxial layer on a first surface of a first substrate; forming a plurality of polysilicon layers on the epitaxial layer, wherein the polysilicon layers include a first polysilicon layer and a second polysilicon layer, and the first polysilicon layers and the second polysilicon layers are arranged alternately; connecting each of the first polysilicon layers to a first electrode, and connecting each of the second polysilicon layers to a second electrode; connecting the first electrode to a gate electrode of a device structure, and connecting the second electrode to a source electrode of the device structure, so that the input capacitance of the device can be increased, thereby solving the problem of excessive stress of Vds under fast shutdown of an SGT MOSFET device, and further improving the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A flow chart of a method for preparing a novel power device provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of a longitudinal section of a device structure provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of a longitudinal section of a target structure provided in an embodiment of the present application.

[0045] Reference numerals:

[0046] 1- oxide layer, 2- third polysilicon, 3- isolation layer, 4- gate polysilicon, 5- second passivation layer, 6- gate oxide layer, 7- source, 8- metal electrode, 9- drain, 10- first substrate, 11- epitaxial layer, 12- first polysilicon, 13- first passivation layer, 14- first electrode, 15- second polysilicon. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0050] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0051] The present application provides a method for preparing a novel power device, such as Figure 1 As shown, the method comprises the following steps:

[0052] Step 101, forming an epitaxial layer on a first surface of a first substrate;

[0053] Step 102, forming a plurality of polysilicon layers on the epitaxial layer, wherein the polysilicon layers include first polysilicon layers and second polysilicon layers, and the first polysilicon layers and the second polysilicon layers are arranged alternately;

[0054] Step 103, connecting each of the first polysilicon to a first electrode, and connecting each of the second polysilicon to a second electrode, to obtain a target structure;

[0055] Step 104: Connect the first electrode to the gate of the device structure, and connect the second electrode to the source of the device structure.

[0056] The substrate is used as a carrier of the power device and mainly plays a supporting role. The substrate can be made of silicon, germanium or germanium silicon. In this embodiment, the substrate is preferably made of silicon, which is the most common, cheap and stable semiconductor material.

[0057] The substrate has a first surface and a second surface opposite to each other, wherein the first surface can be understood as the front side of the substrate, and the second surface can be understood as the back side of the substrate. The gate region and the source electrode of the device structure are formed on the first surface. The drain electrode of the device structure is formed on the second surface of the substrate.

[0058] Optionally, the step 102 of forming a plurality of polysilicon layers on the epitaxial layer includes:

[0059] A polysilicon layer is deposited on the epitaxial layer, and the polysilicon layer is etched to form a plurality of polysilicon layers.

[0060] Optionally, the step 103 of connecting each of the first polysilicon to the first electrode includes:

[0061] A first passivation layer is formed on the polysilicon, and after a plurality of etching holes are formed in the first passivation layer, a first electrode and a second electrode are formed on the first passivation layer, wherein the etching holes include a first etching hole and a second etching hole, and the first electrode is connected to the first polysilicon through the first etching hole.

[0062] Similarly, the above step 103 of connecting each of the second polysilicon to the second electrode includes: the second electrode is connected to the second polysilicon through a second etched hole.

[0063] The target structure can be prepared through the above steps 101 to 103. The process for preparing the target structure in the present application is simple and can be prepared through the existing preparation process of power devices.

[0064] It should be noted that the target structure can also be connected to the gate and source of other power devices accordingly, and can also increase the input capacitance of other power devices, thereby reducing the Vds stress of other power devices under fast shutdown.

[0065] Optionally, before connecting the first electrode to the gate of the device structure, the method further includes: forming a gate and the source on the first surface of the second substrate, and forming a drain on the second surface of the second substrate.

[0066] Specifically, the forming of the gate and the source on the first surface of the second substrate includes: etching a plurality of second grooves on the first surface of the second substrate to obtain a second grooved surface;

[0067] After oxidizing the second groove-shaped surface to form an oxide layer, second polysilicon is filled in the second groove to obtain a substrate structure;

[0068] The gate and the source are formed on the substrate structure.

[0069] Furthermore, the forming of the gate and the source on the substrate structure comprises:

[0070] After etching the first surface of the substrate structure along each second groove position, an isolation layer is formed at the groove position to obtain an isolation surface;

[0071] After forming a gate oxide layer on the isolation surface, filling gate polysilicon at the trench position on the gate oxide layer;

[0072] The source is formed in the second substrate below the gate oxide layer.

[0073] Wherein, the forming of the source electrode in the second substrate under the gate oxide layer comprises:

[0074] A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.

[0075] The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0076] In addition, after forming the source electrode in the first substrate under the gate oxide layer, the method further includes:

[0077] After forming a second passivation layer on the gate oxide layer, a plurality of second etching holes are formed in the second passivation layer to obtain a hole etching surface, wherein the second etching holes are etched into the source electrode;

[0078] A metal electrode is formed on the hole etching surface, and the metal electrode is connected to the source electrode through the second etching hole.

[0079] The method for preparing a novel power device provided in an embodiment of the present application comprises forming an epitaxial layer on a first surface of a first substrate; forming a plurality of polysilicon layers on the epitaxial layer, wherein the polysilicon layers include a first polysilicon layer and a second polysilicon layer, and the first polysilicon layers and the second polysilicon layers are arranged alternately; connecting each of the first polysilicon layers to a first electrode, and connecting each of the second polysilicon layers to a second electrode; connecting the first electrode to a gate electrode of a device structure, and connecting the second electrode to a source electrode of the device structure, so that the input capacitance of the device can be increased, thereby solving the problem of excessive stress of Vds under fast shutdown of an SGT MOSFET device, and further improving the stability of the device.

[0080] The present application also provides a power device, which includes: a target structure and a device structure, such as Figure 2 The schematic diagram of the device structure is shown in Figure 3 Shown is a schematic diagram of the target structure.

[0081] The target structure includes:

[0082] A first substrate 10;

[0083] An epitaxial layer 11, located on a first surface of the first substrate 10;

[0084] A plurality of polysilicon layers, located on the epitaxial layer, the polysilicon layers include a first polysilicon layer 12 and a second polysilicon layer 15, and the first polysilicon layer 12 and the second polysilicon layer 15 are arranged alternately;

[0085] The first electrode 14 and the second electrode are located on the polysilicon, the first polysilicon 12 is connected to the first electrode, and the second polysilicon 15 is connected to the second electrode;

[0086] The first electrode 14 is also connected to the gate of the device structure, and the second electrode is also connected to the source 7 of the device structure.

[0087] Optionally, the multiple polysilicon layers are formed by etching a polysilicon layer.

[0088] Optionally, the target structure also includes:

[0089] A first passivation layer 13, wherein the first passivation layer 13 is formed on the polysilicon, and the first passivation layer 13 comprises a plurality of etching holes, wherein the etching holes comprise a first etching hole and a second etching hole;

[0090] The first electrode 14 and the second electrode are located on the first passivation layer 13 . The first electrode 14 is connected to the first polysilicon 12 through the first etching hole, and the second electrode is connected to the second polysilicon 15 through the second etching hole.

[0091] It should be noted that Figure 3 is a longitudinal cross-sectional view of the target structure at the position of the first electrode 14, Figure 3 The example of connecting the first electrode 14 to the first polysilicon 12 is used for illustration. The method of connecting the second electrode to the second polysilicon 15 can be referred to Figure 3 .

[0092] Optionally, the device structure includes:

[0093] A gate and a source 7, formed on the first surface of the second substrate;

[0094] The drain electrode 9 is formed on the second surface of the second substrate.

[0095] Optionally, the device structure further includes:

[0096] a second grooved surface, wherein the second grooved surface is a surface formed by etching a plurality of second grooves on the first surface of the second substrate;

[0097] A substrate structure, wherein the substrate structure is obtained by oxidizing the second groove-shaped surface to form an oxide layer 1, and then filling the second groove with third polysilicon 2;

[0098] The gate and the source 7 are formed on the substrate structure.

[0099] Optionally, the device structure further includes:

[0100] An isolation surface, wherein the isolation surface is a surface after the first surface of the substrate structure is etched along each second groove position and an isolation layer 3 is formed at the groove position;

[0101] A gate polysilicon 4, wherein the gate polysilicon 4 is located at a groove position on a gate oxide layer 6, and the gate oxide layer 6 is formed on the isolation surface;

[0102] A source electrode 7, wherein the source electrode 7 is formed in the second substrate below the gate oxide layer 6;

[0103] Optionally, the device structure further includes:

[0104] A second passivation layer 5 is located on the gate oxide layer 6, and the second passivation layer 5 includes a plurality of second etching holes, each of which is etched into the source electrode 7;

[0105] The metal electrode 8 is located on the second passivation layer 5 , and the metal electrode 8 is connected to the source electrode 7 through the second etched hole.

[0106] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0107] Regarding the specific limitations of the power device, reference may be made to the limitations of the method for preparing the power device in the embodiments of the present application, and no further details will be given here.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0109] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.

Claims

1. A method for preparing a novel power device, characterized in that: The method comprises: forming an epitaxial layer on a first surface of a first substrate; forming a plurality of polysilicon layers on the epitaxial layer, wherein the polysilicon layers include first polysilicon and second polysilicon layers, and the first polysilicon layers and the second polysilicon layers are arranged alternately; Connecting each of the first polysilicon to a first electrode, and connecting each of the second polysilicon to a second electrode, to obtain a target structure; The first electrode is connected to a gate of a pre-fabricated SGTMOSFET device structure, and the second electrode is connected to a source of the device structure.

2. The method according to claim 1, characterized in that The forming of a plurality of polysilicon layers on the epitaxial layer comprises: Depositing a polysilicon layer on the epitaxial layer; The polysilicon layer is etched to form the first polysilicon and the second polysilicon.

3. The method according to claim 1, characterized in that The step of connecting each of the first polysilicon to the first electrode comprises: forming a first passivation layer on the first polysilicon and the second polysilicon; After forming a plurality of etching holes in the first passivation layer, forming a first electrode and a second electrode on the first passivation layer, the etching holes including a first etching hole and a second etching hole; The first electrode is connected to the first polysilicon through the first etched hole.

4. The method according to claim 3, characterized in that The step of connecting each of the second polysilicon layers to the second electrode comprises: The second electrode is connected to the second polysilicon through the second etched hole.

5. The method according to claim 1, characterized in that Before connecting the first electrode to the gate of the pre-fabricated device structure, the method further includes: forming the gate and the source on the first surface of the second substrate; A drain is formed on the second surface of the second substrate.

6. The method according to claim 5, characterized in that The forming of the gate and the source on the first surface of the second substrate comprises: After etching a plurality of second grooves on the first surface of the second substrate, a second grooved surface is obtained; After oxidizing the second groove-shaped surface to form an oxide layer, filling the second groove with second polysilicon to obtain a substrate structure; The gate and the source are formed on the substrate structure.

7. The method according to claim 6, characterized in that The step of forming the gate and the source on the substrate structure comprises: After etching the first surface of the substrate structure along each second groove position, an isolation layer is formed at the groove position to obtain an isolation surface; After forming a gate oxide layer on the isolation surface, filling gate polysilicon at the trench position on the gate oxide layer; The source is formed in the second substrate below the gate oxide layer.

8. The method according to claim 7, characterized in that The forming of the source electrode in the second substrate under the gate oxide layer comprises: A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.

9. The method according to claim 8, characterized in that The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.

10. A power device, characterized in that: The power device comprises: a target structure and a device structure of SGTMOSFET; The target structure includes: a first substrate; an epitaxial layer, located on the first surface of the first substrate; A plurality of polysilicon layers, located on the epitaxial layer, the polysilicon layers comprising first polysilicon and second polysilicon layers, wherein the first polysilicon layers and the second polysilicon layers are arranged alternately; A first electrode and a second electrode are located on the polysilicon, the first polysilicon is connected to the first electrode, and the second polysilicon is connected to the second electrode; The first electrode is also connected to the gate of the device structure, and the second electrode is also connected to the source of the device structure.

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