Preparation method of semiconductor device

Abstract

The invention discloses a preparation method of a semiconductor device, and the method comprises the steps: providing an epitaxial wafer which comprises a semiconductor substrate and an epitaxial layer located on the upper surface of the semiconductor substrate; forming a first mask layer with a first through hole on the upper surface of the epitaxial layer; forming an (i + 1) th mask layer with an (i + 1) th through hole on the surface of the ith mask layer with the ith through hole; etching the epitaxial layer based on the (i + 1) th through hole, and forming an ith-level groove in the upper surface of the epitaxial layer so as to sequentially form a first-level groove to an Mth-level groove of an M-level groove structure in the upper surface of the epitaxial layer; before the ith-level groove is formed, the (i + 1) th mask layer covers the top of the ith mask layer and covers the side wall and the bottom of the ith through hole; the apertures of the first through hole to the (M + 1) th through hole are sequentially reduced; and forming a self-aligned ion implantation window based on at least one of the first mask layer to the (M + 1) th mask layer, performing self-aligned ion implantation, and forming an ion implantation region in the surface of the M-level groove structure.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device preparation, and in particular to a method for preparing a semiconductor device. Background Art

[0002] With the development of science and technology, planar semiconductor devices have reached the point where the size of device cells can be reduced but the on-resistance cannot be reduced. The main reason is that due to the limitation of the resistance of the neck region of JFET (Junction Field-Effect Transistor), even with a smaller lithography size, the on-resistance per unit area is difficult to reduce to 2mΩ·cm 2 .

[0003] Compared with planar semiconductor devices, trench semiconductor devices can change the conductive channel from horizontal to vertical through the trench structure, eliminating the JFET neck resistance, greatly increasing the cell density, and improving the current handling capability of the semiconductor device.

[0004] In trench semiconductor devices, it is necessary to prepare a multi-level trench structure in order to achieve a greater ion implantation depth in the epitaxial layer. In the existing preparation method, when ion implantation is performed in the multi-level trench structure, it is necessary to remove the mask layer for preparing the multi-level trench structure and then prepare a new mask layer for ion implantation in the multi-level trench structure. Summary of the invention

[0005] In view of the above problems, the present application provides a method for preparing a semiconductor device, and the specific scheme is as follows:

[0006] A method for preparing a semiconductor device, comprising:

[0007] Providing an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on an upper surface of the semiconductor substrate;

[0008] forming a first mask layer having a first through hole on the upper surface of the epitaxial layer;

[0009] forming an (i+1)th mask layer having an (i+1)th through hole on a surface of the (i)th mask layer having an (i)th through hole;

[0010] The epitaxial layer is etched based on the i+1th through hole to form an i-th level groove in the upper surface of the epitaxial layer, so as to sequentially form the 1st level groove to the M-level groove structure in the upper surface of the epitaxial layer; wherein M is a positive integer greater than 1; before forming the i-th level groove, the i+1th mask layer covers the top of the i-th mask layer and covers the sidewall and bottom of the i-th through hole, and i is a positive integer not greater than M; the apertures of the 1st through hole to the M+1th through hole are sequentially reduced, and the widths of the 1st level groove to the M-th level groove are sequentially reduced;

[0011] A self-aligned ion implantation window is formed based on at least one of the first mask layer to the M+1th mask layer, and self-aligned ion implantation is performed to form an ion implantation region in the surface of the M-level trench structure.

[0012] Optionally, in the above preparation method, after the Mth level trench structure is formed in the upper surface of the epitaxial layer based on the M+1th through hole, the top of the 2nd mask layer to the M+1th mask layer is flush with the upper surface of the 1st mask layer; in the 1st level trench to the M-1th level trench, the side wall of the ath level trench is covered with the a+2th mask layer, and a is a positive integer not greater than M-1.

[0013] Optionally, in the above preparation method, the i-th mask layer and the i+1-th mask layer have a wet etching selectivity ratio;

[0014] The method of forming an ion implantation region in a surface of an M-level trench structure comprises:

[0015] Based on the wet etching selection ratio, the jth mask layer is removed, and other mask layers are retained to expose the area around the opening of the j-1th level trench; j is a positive integer greater than 1 and not greater than M+1;

[0016] Self-aligned ion implantation is performed using the gap between the j-1th mask layer and the j+1th mask layer as a self-aligned ion implantation window to form ion implantation regions in the sidewall surface of the j-1th level groove and in the bottom surface of the Mth level groove.

[0017] Optionally, in the above-mentioned preparation method, the epitaxial layer and the ion implantation region have different doping types to form a junction controlled diode;

[0018] After forming a plurality of ion implantation regions in the surface of the M-th level trench structure, the method further comprises:

[0019] Retaining the first mask layer with the first through hole, and after removing other mask layers, forming an ohmic contact layer in the M-level trench structure, the ohmic contact layer covering the surface of the M-level trench structure and the upper surface of the epitaxial layer exposed by the first through hole, so as to form a plurality of junction-controlled diodes based on the M-level trench structure;

[0020] The M-level trench structure is filled with a dielectric material.

[0021] Optionally, in the above preparation method, the i-th mask layer and the (i+1)-th mask layer have a wet etching selectivity ratio of not less than 100.

[0022] Optionally, in the above preparation method, the first mask layer and the second mask layer have a wet etching selectivity ratio; the second mask layer to the M+1th mask layer are film layers of the same material;

[0023] The method of forming an ion implantation region in a surface of an M-level trench structure comprises:

[0024] Based on the wet etching selection ratio, removing the second mask layer to the M+1th mask layer;

[0025] The first through hole in the first mask layer is used as a self-aligned ion implantation window to perform self-aligned ion implantation on the M-level trench structure to form an integrated ion implantation area in the surface of the M-level trench structure and around the opening of the first-level trench.

[0026] Optionally, in the above-mentioned preparation method, the epitaxial layer and the ion implantation region have different doping types to form a junction controlled diode;

[0027] After forming a plurality of ion implantation regions, the method further comprises:

[0028] After removing the first mask layer, a dielectric material is filled in the M-level trench structure;

[0029] forming a first electrode and a second electrode; wherein the first electrode covers the upper surface of the epitaxial layer, and the second electrode covers the lower surface of the semiconductor substrate;

[0030] A junction-controlled diode is formed between the integrated ion implantation region and the epitaxial layer.

[0031] Optionally, in the above preparation method, the thicknesses of the second mask layer to the (M+1)th mask layer are all smaller than the thickness of the first mask layer.

[0032] Optionally, in the above preparation method, the thicknesses of the second mask layer to the M+1th mask layer are all the same.

[0033] Optionally, in the above preparation method, the epitaxial layer is an N-type doped silicon carbide layer;

[0034] Ion implantation is performed on the surface of the M-level trench structure based on P-type ions.

[0035] By means of the above technical scheme, the present application provides a method for preparing a semiconductor device, which can form an M-level trench structure having a 1st-level trench to an M-level trench in the upper surface of the epitaxial layer based on the 1st mask layer to the M+1th mask layer. The 1st mask layer to the M+1th mask layer have a 1st through hole to an M+1th through hole in sequence, and the apertures of the 1st through hole to the M+1th through hole decrease in sequence. Before forming the i-level trench, the i+1th mask layer covers the top of the i-th mask layer, and covers the sidewalls and bottom of the i-th through hole. In this way, based on etching the epitaxial layer by the i+1th through hole, the i-level trench of the M-level trench structure can be formed in the upper surface of the epitaxial layer, so as to form an M-level trench structure having a 1st-level trench to an M-level trench in the surface of the epitaxial layer.

[0036] In addition, since the preparation method can form the next mask layer after forming the corresponding first-level groove according to the through hole in the previous mask layer, the surface of each level of groove can be covered with a corresponding mask layer respectively. Therefore, when at least two mask layers have a wet etching selectivity, a self-aligned ion implantation window can be directly formed using at least one of the 1st mask layer to the M+1th mask layer, and self-aligned ion implantation can be performed based on the self-aligned ion implantation window, so that an ion implantation area can be formed on the surface of the M-level groove structure, and there is no need to separately prepare a mask layer for ion implantation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0038] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0039] Figure 1 It is a schematic diagram of the ion implantation principle based on a single-stage trench;

[0040] Figure 2 It is a schematic diagram of the ion implantation principle based on multi-level trenches;

[0041] Figure 3-Figure 8 A device structure diagram at different process steps in a method for preparing a semiconductor device;

[0042] Figure 9-Figure 25 A device structure diagram of different process steps of a semiconductor manufacturing method provided in an embodiment of the present application.

[0043] Reference numerals:

[0044] 10-photoresist layer; 11-ion implantation area; 12-multi-level trench; 13-single-level trench; 14-mask layer; 15-epitaxial layer; 16-semiconductor substrate; 17-drift layer; 18-epitaxial wafer; 19-self-aligned ion implantation window; 20-ohmic contact layer; 21-dielectric material; 22-first electrode; 23-second electrode; EL 1 -1st mask layer; EL2 -Second mask layer; EL 3 -3rd mask layer; EL 4 - 4th mask layer; Via 1 -Through hole 1; Via 2 - Second through hole; Via 3 -Third through hole; Via 4 - 4th through hole; GR 1 -1st level groove; GR 2 -Second level groove; GR 3 - Level 3 grooves. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0046] Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0047] Wide bandgap semiconductors such as SiC have excellent material properties such as wide bandgap width, high critical breakdown electric field, high electron saturation drift velocity and high thermal conductivity, so they have broad application prospects in high-voltage, high-frequency and high-temperature power electronic devices. SiC MOSFET devices have the advantages of high breakdown voltage, low specific on-resistance, high switching speed and low switching loss. After years of research in the industry, modern technological advances have reached the point where the size of the MOS cell can be reduced but the on-resistance cannot be reduced. The main reason is that due to the limitation of the resistance of the JFET neck region, even with a smaller lithography size, the on-resistance per unit area is difficult to reduce to 2mΩ·cm 2 The trench structure can effectively solve this problem. It changes the conductive channel from horizontal to vertical. Compared with the ordinary structure, it eliminates the JFET neck resistance, greatly increases the cell density, and improves the current handling capacity of the power semiconductor.

[0048] However, trench SiC MOSFET devices still have problems in actual process manufacturing and application: the high electric field in the SiC drift region leads to a high electric field on the gate oxide layer. This problem is exacerbated at the trench corners, causing the gate oxide layer to quickly break down under high drain voltages. Due to the limited depth of P-type ion implantation in wide bandgap semiconductors such as SiC, many targeted trench gate protection structures and surge protection designs are difficult to implement in terms of process.

[0049] The problem of limited P-type implantation depth and difficulty in diffusion of doping elements in wide bandgap semiconductors such as SiC can be solved by using a multi-level trench plus ion implantation method. In this way, a deeper P-type ion implantation area can be formed in the SiC material without the need for high-energy and high-dose ion implantation, so as to form a P+ doping masking layer or junction-controlled diode in the SiC material.

[0050] refer to Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the ion implantation principle based on a single-stage trench. Figure 2 Schematic diagram of the ion implantation principle based on multi-level trenches.

[0051] like Figure 1 As shown, when it is necessary to form an integrated continuous ion implantation region 11 in the surface of the single-stage trench 13, as the trench depth in the epitaxial layer 15 increases, ion implantation in the single-stage trench 13 will cause discontinuity in the ion implantation region 11 at the trench sidewall and bottom.

[0052] like Figure 2 As shown, when it is necessary to form an integrated and continuous ion implantation region 11 on the surface of the multi-level groove 12 , based on the step structure of the multi-level groove 12 , an integrated and continuous ion implantation region 11 with good morphology can be formed on the surface of the multi-level groove 12 .

[0053] In addition, while it is not easy for a single-level groove 13 to form multiple separated ion implantation regions 11 on the groove surface, the multi-level groove 12 can be based on the step structure between each level of the groove, which facilitates the accurate formation of multiple separated ion implantation regions 11 on the surface of at least two levels of the multi-level groove 12.

[0054] To form a Figure 2 The multi-level grooves 12 of the integrated continuous ion implantation region are conventionally prepared by the following process: Figure 3-Figure 8 shown.

[0055] refer to Figure 3-Figure 8 , Figure 3-Figure 8 The device structure diagram of a semiconductor device manufacturing method at different process steps is shown in FIG. 1 . The manufacturing method includes: Figure 3As shown, based on a mask layer 14, a multi-level trench 12 is formed after multiple etchings. Since the mask layer 14 has an etching window with the same width as the opening of the top first-level trench of the multi-level trench 12, the mask layer 14 covers the epitaxial layer 15 around the opening of the top first-level trench. Figure 4 As shown, the mask layer 14 used to form the multi-level trenches 13 on the surface of the epitaxial layer 15 is peeled off. Figure 5 As shown in FIG. 1 , a mask material is filled in the multi-level trench 12, and the mask material also covers the upper surface of the epitaxial layer 15. Then, a patterned photoresist layer 10 is formed on the surface of the epitaxial material through a photolithography process. Figure 6 As shown, the mask material is etched based on the photoresist layer 10 to remove the mask material in the multi-level grooves 12, and the epitaxial material on the upper surface of the epitaxial layer 15 is retained to form another mask layer 14 with an injection window, and then the photoresist layer 10 is removed. The width of the injection window is greater than the opening width of the uppermost first-level groove, so that when ion implantation is performed based on the other mask layer 14 with the injection window, a layer as shown in FIG. Figure 2 The ion implantation region 11 is shown as an integrated and continuous region.

[0056] As described above, in the conventional preparation method, when forming an integrated continuous ion implantation area 11 in the multi-level groove 12, it is necessary to peel off the original mask layer 14 used for etching to form the multi-level groove, and prepare a new mask layer 14 for ion implantation separately. Figure 3 The structure shown in FIG. 1 is subjected to ion implantation, and the formed ion implantation region 11 is as shown in FIG. Figure 7 As shown, due to the obstruction of the mask layer 14 originally used for etching the multi-level grooves 12, ion implantation cannot be completed in the sidewall of the topmost groove, so that the ion implantation area 11 in the semiconductor device cannot be grounded through the metal layer above the epitaxial layer 15, posing a risk of leakage.

[0057] In addition, although Figure 3-Figure 6 The process flow shown can form Figure 2 The ion implantation region 11 is continuous and integrated. Figure 8 As shown, since the process of forming a new mask layer 14 requires filling the multi-level trench 12 with mask material, as shown in FIG. Figure 8 As shown, when the mask material in the multi-level groove 12 is removed by etching based on the photoresist layer 10, the mask material is likely to remain at the groove corner position at the bottom of each level of the groove, affecting the ion implantation depth and dose. The ion implantation area 11 is a P-type implantation area, and when used as a P+ doping masking layer, it will affect the P-type masking effect to deviate from the design value.

[0058] Based on the above description, it can be seen that due to the limited depth of P-type ion implantation in SiC materials, on the one hand, many targeted trench gate protection structures and surge protection designs are difficult to implement from a process perspective, and on the other hand, it is difficult to prepare super junction devices. Although the multi-level trench structure can solve the problem of limited P-type implantation depth in SiC materials, and lower implantation energy can be used to achieve deeper P-type ion implantation, after preparing the multi-level trenches, the mask pattern for ion implantation needs to be re-prepared. The preparation of the new mask pattern requires the addition of a photolithography process, which increases the complexity of the preparation process, and there is a problem of residual mask material at the groove corner at the bottom of the trench.

[0059] Moreover, there is currently no mature preparation process for forming multiple separate ion implantation areas 11 in local areas of multi-level grooves. When designing semiconductor devices, if selective ion implantation is required on the steps of multi-level grooves 12 to achieve a special ion implantation area 11 design, the current process is difficult to achieve.

[0060] In view of this, an embodiment of the present application provides a method for preparing a semiconductor device, comprising:

[0061] Providing an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on an upper surface of the semiconductor substrate;

[0062] forming a first mask layer having a first through hole on the upper surface of the epitaxial layer;

[0063] forming an (i+1)th mask layer having an (i+1)th through hole on a surface of the (i)th mask layer having an (i)th through hole;

[0064] The epitaxial layer is etched based on the i+1th through hole to form an i-th level groove in the upper surface of the epitaxial layer, so as to form the 1st level groove to the M-level groove structure in the upper surface of the epitaxial layer; wherein M is a positive integer greater than 1; before forming the i-th level groove, the i+1th mask layer covers the top of the i-th mask layer and covers the sidewall and bottom of the i-th through hole, and i is a positive integer not greater than M; the apertures of the 1st through hole to the M+1th through hole decrease successively, and the widths of the 1st level groove to the M-th level groove decrease successively;

[0065] A self-aligned ion implantation window is formed based on at least one of the first mask layer to the M+1th mask layer, and self-aligned ion implantation is performed to form an ion implantation region in the surface of the M-level trench structure.

[0066] The preparation method can form an M-level trench structure having a 1st-level trench to an M-level trench in the upper surface of the epitaxial layer based on the 1st mask layer to the M+1th mask layer. The 1st mask layer to the M+1th mask layer have a 1st through hole to an M+1th through hole in sequence, and the apertures of the 1st through hole to the M+1th through hole decrease in sequence. Before forming the i-level trench, the i+1th mask layer covers the top of the i-th mask layer and covers the sidewall and bottom of the i-th through hole. In this way, based on the i+1th through hole, the epitaxial layer is etched, and the i-level trench of the M-level trench structure can be formed in the upper surface of the epitaxial layer, so as to form an M-level trench structure having a 1st-level trench to an M-level trench in the surface of the epitaxial layer.

[0067] In addition, since the preparation method can form the next mask layer after forming the corresponding first-level groove according to the through hole in the previous mask layer, the surface of each level of groove can be covered with a corresponding mask layer respectively. Therefore, when at least two mask layers have a wet etching selectivity, a self-aligned ion implantation window can be directly formed using at least one of the 1st mask layer to the M+1th mask layer, and self-aligned ion implantation can be performed based on the self-aligned ion implantation window, so that an ion implantation area can be formed on the surface of the M-level groove structure, and there is no need to separately prepare a mask layer for ion implantation.

[0068] In the embodiments of the present application, the preparation method of the semiconductor device is described by taking the P-type ion implantation in the SiC epitaxial layer as an example. It is easy to know that the epitaxial layer in the semiconductor device is not limited to SiC material, but can also be an epitaxial layer of other materials, such as multi-level trench ion implantation of a larger depth such as Si epitaxial layer, GaN epitaxial layer and GaAs epitaxial layer; ion implantation is not limited to P-type implantation, but can be P-type implantation or N-type implantation.

[0069] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0070] refer to Figure 9-Figure 25 , Figure 9-Figure 25 A device structure diagram of a semiconductor manufacturing method in different process steps provided in an embodiment of the present application, the manufacturing method includes:

[0071] Step S11: Fig. 9 As shown, an epitaxial wafer 18 is provided, and the epitaxial wafer 18 includes a semiconductor substrate 16 and an epitaxial layer 15 located on the upper surface of the semiconductor substrate 16 .

[0072] Optionally, in order to optimize the performance of the semiconductor device, a drift layer 17 may be first formed on the surface of the semiconductor substrate 16 , and then the epitaxial layer 15 may be formed on the surface of the drift layer 17 .

[0073] In other embodiments, the epitaxial layer 15 may be directly formed on the upper surface of the semiconductor substrate 16 .

[0074] Step S12: Figure 10-12 As shown, a first through hole Via is formed on the upper surface of the epitaxial layer 15. 1 The first mask layer EL 1 .

[0075] In step S12, the Fig.10 As shown, a first mask layer EL is first formed on the surface of the epitaxial layer 15 to cover the entire surface. 1 , and then Fig.11 As shown, the first mask layer EL is formed by photolithography. 1 A patterned photoresist layer 10 is formed on the surface of Fig.12 As shown, based on the patterned photoresist layer 10, the first mask layer EL 1 Etching is performed to form a first mask layer EL 1 The first through hole Via is formed in 1 .

[0076] Step S13: In the case of having the i-th through hole Via i The i-th mask layer EL i The surface is formed with the i+1th through hole Via i+1 The i+1th mask layer EL i+1 .

[0077] If i=1, Fig.13 As shown, in the case of the first through hole Via 1 The first mask layer EL 1 A second through hole Via is formed on the surface 2 The second mask layer EL 2 .

[0078] Step S14: Figure 14-Figure 18 As shown, based on the i+1th through hole Via i+1 The epitaxial layer 15 is etched to form an i-th level trench GR in the upper surface of the epitaxial layer 15. i , so as to form the first-level trench to the M-th-level trench of the M-level trench structure in the upper surface of the epitaxial layer 15.

[0079] Wherein, M is a positive integer greater than 1; forming the i-th level groove GR i Before, the i+1th mask layer EL i+1 Covering the i-th mask layer EL i The top of the via hole Via i The side wall and bottom of the through hole Via 1 To the M+1th viaM+1 The apertures of the first-level grooves GR 1 To the Mth level groove GR M The width decreases successively.

[0080] In step S14, Fig.13 As shown, in forming the first-level trench GR 1 Before, the second mask layer EL 2 Covering the first mask layer EL 1 The top of the first through hole 1 side walls and bottom.

[0081] When i=1, Fig.14 As shown, based on the second through hole Via 2 The epitaxial layer 15 is etched to form a first-level trench GR of an M-level trench structure in the upper surface of the epitaxial layer 15. 1 .

[0082] When i=2, Fig.15 As shown, the first-level trench GR is formed 1 After that, in the second through hole 2 The second mask layer EL 2 A third through hole Via is formed on the surface 3 The third mask layer EL 3 . For example Fig.16 As shown, based on the third through hole Via 3 The epitaxial layer 15 is etched to form a second-level trench GR of an M-level trench structure in the upper surface of the epitaxial layer 15. 2 .

[0083] When i=3, Fig.17 As shown, the second-level trench GR is formed 2 After that, in the third through hole 3 The third mask layer EL 3 A fourth through hole Via is formed on the surface 3 The fourth mask layer EL 4 . For example Fig.18 As shown, based on the 4th through hole Via 4 The epitaxial layer 15 is etched to form a third-level trench GR of an M-level trench structure in the upper surface of the epitaxial layer 15. 3 .

[0084] Based on the above description, it can be known that the preparation method provided in the embodiment of the present application can prepare an M-level trench structure based on an M+1 mask layer. In the embodiment of the present application, M=3 is used as an example for illustration. It should be noted that it is not limited to M=3, and M can be any positive integer greater than 1, such as M can be 2, or 4, or 5, and any positive integer greater than 1.

[0085] Among the first-level trenches to the M-1-level trenches, the sidewalls of the a-th-level trenches are covered with the a+2-th mask layer, where a is a positive integer not greater than M-1. Fig.18 As shown, when a=1, the first-level slot GR 1 The sidewalls are covered with a third mask layer EL 3 ; When a=2, the second level slot GR 2 The sidewalls are covered with a fourth mask layer EL 4 .

[0086] like Fig.14 , Fig.16 and Fig.18 As shown, based on the i+1th through hole Via i+1 The epitaxial layer 15 is etched to form an i-th level trench GR in the upper surface of the epitaxial layer 15. i When the i-th through hole Via is removed synchronously i The outer (i+1) mask layer EL i+1 and the i-th through hole Via i The bottom i+1 mask layer EL i+1 , retain the i-th via i The i+1th mask layer EL on the side wall i+1 Based on this, the epitaxial layer 15 is further etched to form the i-th level trench GR i .

[0087] i=1, such as Fig.14 As shown, based on the second through hole Via 2 The epitaxial layer 15 is etched to form a first-level trench GR in the upper surface of the epitaxial layer 15. 1 When the first through hole Via is removed 1 External second mask layer EL 2 and the first through hole Via 1 The second mask layer EL at the bottom 2 , keep the first via 1 The second mask layer EL on the side wall 2 Based on this, the epitaxial layer 15 is further etched to form a first-level trench GR 1 .

[0088] i=2, such as Fig.16 As shown, based on the third through hole Via 3 The epitaxial layer 15 is etched to form a second-level trench GR in the upper surface of the epitaxial layer 15. 2 When the second through hole Via is removed 2 External third mask layer EL 3 and the second through hole Via 2The third mask layer EL at the bottom 3 , keep the second through hole Via 2 The third mask layer EL on the side wall 3 Based on this, the epitaxial layer 15 is further etched to form a second-level trench GR 2 .

[0089] i=3, such as Fig.18 As shown, based on the 4th through-hole Via 4 The epitaxial layer 15 is etched to form a third-level trench GR in the upper surface of the epitaxial layer 15. 3 When the third through hole Via is removed 3 External 4th mask layer EL 4 And the third via 3 The fourth mask layer EL at the bottom 4 , keep the third via 3 The fourth mask layer EL on the sidewall 4 Based on this, the epitaxial layer 15 is further etched to form a third-level trench GR 3 .

[0090] Step S15: Figure 19-21 As shown, based on the first mask layer EL 1 To the M+1th mask layer EL M+1 A self-aligned ion implantation window 19 is formed in at least one of the grooves, and self-aligned ion implantation is performed to form an ion implantation region 11 in the surface of the M-level trench structure.

[0091] In step S15, Fig.19 As shown, by removing the third mask layer EL 3 , using the second mask layer EL 2 and the fourth mask layer EL 4 A self-aligned ion implantation window 19 is formed, and the self-aligned ion implantation window 19 exposes the first-level trench GR 1 The bottom of Fig. 20 As shown, the second-level trench GR is implanted through the self-aligned ion implantation window 19. 2 Ion implantation is performed in the sidewall surface of the ion implantation region 11, and ion implantation can also be performed in the third-level trench GR simultaneously. 3 Ions are implanted into the bottom surface of the ion implantation region 11. After the ion implantation is completed, the first mask layer EL is retained. 1 , remove the second mask layer EL 2 and the fourth mask layer EL 4 .

[0092] Based on the above description, it can be known that the preparation method provided in the embodiment of the present application can be based on the first mask layer EL 1To the M+1th mask layer EL M+1 A first-level trench GR is formed in the upper surface of the epitaxial layer 15. 1 To the Mth level groove GR M The first mask layer EL 1 To the M+1th mask layer EL M+1 There are first through holes Via 1 To the M+1th via M+1 , No. 1 through hole Via 1 To the M+1th via M+1 The apertures of the holes decrease successively, forming the i-th level groove GR i Before, the i+1th mask layer EL i+1 Covering the i-th mask layer EL i The top of the via hole Via i Thus, based on the i+1th through hole Via i+1 The epitaxial layer 15 is etched to form an i-th level trench GR of an M-level trench structure in the upper surface of the epitaxial layer 15. i , so as to form a first-level trench GR in the surface of the epitaxial layer 15 1 To the Mth level groove GR M M-level groove structure.

[0093] In addition, since the preparation method can form the next mask layer after forming the corresponding first-level groove according to the through hole in the previous mask layer, the surface of each level of the groove can be covered by a corresponding mask layer respectively. Therefore, when at least two mask layers have a wet etching selectivity ratio, the first mask layer EL can be directly used. 1 To the M+1th mask layer EL M+1 At least one of the self-aligned ion implantation windows 19 is formed, and self-aligned ion implantation can be performed based on the self-aligned ion implantation window 19, so that an ion implantation region 11 can be formed in the surface of the M-level trench structure without separately preparing a mask layer for ion implantation.

[0094] Since the first via 1 To the M+1th via M+1 The apertures of the first-level grooves GR are gradually reduced. 1 To the Mth level groove GR M The width of the grooves decreases successively, so that a step is formed between two adjacent grooves, and the bottom of the previous groove is the opening top area of ​​the adjacent next groove.

[0095] In the embodiments of the present application, Fig.18 As shown, based on the M+1th through hole Via M+1After the M-th level trench structure is formed in the upper surface of the epitaxial layer 15, the second mask layer EL 2 To the M+1th mask layer EL M+1 The top of the first mask layer EL 1 The upper surface of the first groove GR is flush; 1 To the M-1th level groove GR M-1 In the a-level groove GR a The sidewalls are covered with the a+2 mask layer EL a+2 , a is a positive integer not greater than M-1. If M=3, the first-level groove GR 1 To the 2nd level groove GR M-1 In the first level groove GR 1 The sidewalls are covered with a third mask layer EL 3 , 2nd level groove GR 2 The sidewalls are covered with a fourth mask layer EL 4 .

[0096] In the present application embodiment, Fig.18 As shown, based on the first mask layer EL 1 To the M+1th mask layer EL M+1 , first-level trenches GR are sequentially formed in the upper surface of the epitaxial layer 15 1 To the Mth level groove GR M Then, the second mask layer EL 2 To the M+1th mask layer EL M+1 Retained in the thickness direction of the epitaxial layer 15 ( Fig.18 The vertical direction of each mask layer can make each mask layer have a width direction of each level of trench ( Fig.18 In the horizontal direction) stacked in sequence, so that when the second mask layer EL is removed 2 To the M+1th mask layer EL M+1 After one or more of the steps, a set area of ​​the M-level trench structure may be exposed for ion implantation.

[0097] Therefore, in the embodiment of the present application, not only the first mask layer EL 1 To the M+1th mask layer EL M+1 Prepare M-level trench structure and selectively remove the second mask layer EL 2 To the M+1th mask layer EL M+1 One or more of them reuse at least one mask layer to form a self-aligned ion implantation window 19 to selectively implant ions in a set area of ​​the M-level trench structure, and controllably implant ions into the set area of ​​the M-level trench structure.

[0098] In one implementation of the embodiment of the present application, the i-th mask layer EL iand the i+1th mask layer EL i+1 It has a wet etching selectivity ratio, that is, any two adjacent mask layers have a wet etching selectivity ratio. Fig.18 After the device structure is formed, the second mask layer EL can be selectively removed by utilizing the wet etching selectivity between adjacent mask layers. 2 To the M+1th mask layer EL M+1 One or more of the above are used to select the area within the M-level trench structure where ion implantation is required.

[0099] If the i-th mask layer EL i and the i+1th mask layer EL i+1 With a wet etching selectivity ratio, in the preparation method provided in the embodiment of the present application, in one embodiment, a method for forming an ion implantation region 11 in the surface of the M-level trench structure comprises: based on the wet etching selectivity ratio, removing the j-th mask layer EL j , retain other mask layers to expose the j-1th level trench GR j-1 The area around the opening; j is a positive integer greater than 1 and not greater than M+1; the j-1th mask layer EL j-1 and the j+1th mask layer EL j+1 The gap between them is a self-aligned ion implantation window 19, and self-aligned ion implantation is performed in the j-1st level trench GR j-1 The sidewall surface and the M-th level trench GR M Ion implantation regions 11 are respectively formed in the bottom surface of the M-level trench structure, so that a plurality of separated ion implantation regions 11 can be formed in the surface of the M-level trench structure.

[0100] If j=3, then Fig.19 As shown, based on the wet etching selection ratio, the third mask layer EL is removed. 3 , retain other mask layers to expose the second-level trench GR 2 The area around the opening (this area is the first-level groove GR 1 The bottom area of ​​the second mask layer EL 2 With the 4th mask layer EL 4 The gap between the two is a self-aligned ion implantation window 19. After the self-aligned ion implantation, Fig. 20 As shown, in the second-stage groove GR 2 The sidewall surface of the third-level trench GR 3 Ion implantation regions 11 are formed in the bottom surfaces of the electrodes.

[0101] Taking M=3 as an example, when the i-th mask layer EL i and the i+1th mask layer EL i+1 When the wet etching selectivity is j=2, the first-level trench GR can be exposed.1 The area around the opening can be 1 The ion implantation region 11 is formed in the side wall; if j=3, the second-level trench GR can be exposed. 2 The area around the opening can be 2 An ion implantation region 11 is formed in the side wall; if j=4, the third-level trench GR can be exposed. 3 The area around the opening can be 3 An ion implantation region 11 is formed in the side wall.

[0102] Therefore, if the i-th mask layer EL i and the i+1th mask layer EL i+1 With wet etching selectivity, in the embodiment of the present application, Fig.18 Based on the device structure shown, the second mask layer EL can be removed based on the needs. 2 To the M+1th mask layer EL M+1 One or more of them can accurately identify the area in the M-level trench structure where ion implantation is required.

[0103] In the embodiment of the present application, the doping types of the epitaxial layer 15 and the ion implantation region 11 may be different, so that a junction-controlled diode may be formed. At this time, after forming a plurality of ion implantation regions 11 on the surface of the M-th level trench structure, the preparation method may also be as follows: Fig. 22 As shown, it also includes: retaining the first mask layer EL having the first through hole 1 After removing other mask layers, an ohmic contact layer 20 is formed in the M-level trench structure, and the ohmic contact layer 20 covers the surface of the M-level trench structure and the first through hole Via 1 The exposed upper surface of the epitaxial layer 15 is used to form a plurality of junction-controlled diodes based on an M-level trench structure; and a dielectric material 21 is filled in the M-level trench structure.

[0104] exist Fig. 22 In the manner shown, since a plurality of separated ion implantation regions 11 are formed in the surface of the M-th level trench structure, a plurality of PN structures can be formed in the epitaxial layer 15 to form a plurality of junction-controlled diodes. This manner can be used to form a trench junction-controlled diode structure between two trench gates of a trench gate MOS. The trench junction-controlled diode structure is as follows: Fig. 22 The junction controlled diode with multiple interconnections shown can be used to optimize the device performance of trench MOS.

[0105] In order to effectively remove the mask layer based on the wet etching selectivity, the i-th mask layer EL i and the i+1th mask layer EL i+1 The wet etching selectivity ratio is not less than 100.

[0106] When two adjacent mask layers have a wet etching selectivity ratio of not less than 100, the mask layers can be effectively removed based on the larger wet etching selectivity ratio between the adjacent mask layers to prevent mask material residue.

[0107] In one implementation of the embodiment of the present application, a first mask layer EL may also be provided. 1 With the second mask layer EL 2 With wet etching selectivity; the second mask layer EL 2 To the M+1th mask layer EL M+1 The same material film layer, that is, the second mask layer EL 2 To the M+1th mask layer EL M+1 The wet etching rate is the same, and there is no wet etching selectivity. In this method, Fig.18 After forming the M-level trench structure, the method of forming the ion implantation region 11 in the surface of the M-level trench structure includes:

[0108] First, if Fig.23 As shown, based on the wet etching selection ratio, the second mask layer EL is removed. 2 To the M+1th mask layer EL M+1 . Since the second mask layer EL 2 To the M+1th mask layer EL M+1 The second mask layer EL is the same material layer. 2 To the M+1th mask layer EL M+1 Can be removed simultaneously. 1 With the second mask layer EL 2 The wet etching selectivity ratio can be used to simultaneously remove the second mask layer EL. 2 To the M+1th mask layer EL M+1 When the first mask layer EL is retained 1 Optionally, as mentioned above, the wet etching selectivity ratio is not less than 100.

[0109] Then, if Fig.24 As shown, the first mask layer EL 1 The first via in 1 To self-align the ion implantation window 19, self-aligned ion implantation is performed to implant ions into the M-level trench structure to form an integrated ion implantation region 11 within the surface of the M-level trench structure and around the opening of the first-level trench.

[0110] exist Fig.23 and Fig.24 In the embodiment shown, the second mask layer EL 2 To the M+1th mask layer EL M+1 The same material film layer can be used together with the first mask layer EL1 It has a wet etching selectivity ratio, and the second mask layer EL can be removed simultaneously based on the wet etching selectivity ratio. 2 To the M+1th mask layer EL M+1 , and retain the first mask layer EL 1 , with the first mask layer EL 1 The first via in 1 For the self-aligned ion implantation window 19, an integrated and continuous ion implantation region 11 can be formed in the surface of the M-level groove structure. In this way, ions can be implanted on the sidewalls and bottom of each level of the groove to form an integrated and continuous ion implantation region 11, and the top of the ion implantation region 11 is located at the first through hole Via 1 The surface of the exposed epitaxial layer 15 is inside.

[0111] In the embodiments of the present application, it is not limited to Fig.23 and Fig.24 The method shown in the figure forms an integrated continuous ion implantation region 11. In the above embodiment, if the i-th mask layer EL i and the i+1th mask layer EL i+1 With wet etching selectivity, the second mask layer EL can also be removed by multiple etchings 2 To the M+1th mask layer EL M+1 Ion implantation is then performed to form an integrated and continuous ion implantation region 11 in the M-level trench structure.

[0112] In the embodiment of the present application, if a continuous ion implantation region 11 is formed in the surface of the M-level trench structure, a junction-controlled diode can be formed based on the continuous ion implantation region 11. At this time, the epitaxial layer 15 and the ion implantation region 11 have different doping types to form a junction-controlled diode; after forming a plurality of ion implantation regions 11, such as Fig.25 As shown, the preparation method further includes: removing the first mask layer EL 1 Afterwards, a dielectric material 21 is filled in the M-level trench structure to form a first electrode 22 and a second electrode 23 . The first electrode 22 covers the upper surface of the epitaxial layer 15 , and the second electrode 23 covers the lower surface of the semiconductor substrate 16 . A junction-controlled diode is formed between the integrated ion implantation region 11 and the epitaxial layer 15 .

[0113] exist Fig.25 The method shown can form an integrated continuous ion implantation region 11 on the surface of the M-level trench structure, thereby forming an integrated junction-controlled diode in the M-level trench structure to optimize the performance of semiconductor devices. This method can be used to prepare superjunction or semi-superjunction devices.

[0114] Optionally, the epitaxial layer 15 is an N-type doped silicon carbide layer, and ion implantation is performed on the surface of the M-level trench structure based on P-type ions. This method can achieve P-type ion implantation at a greater depth in the silicon carbide material.

[0115] In the embodiments of this application, Figure 13 to Figure 14 The process shown, Figure 15 to Figure 16 The process shown, Figure 17 to Figure 18 In the process shown in the figure, when forming each level of trench, it is necessary to etch and remove the first mask layer EL. 1 Other mask layers on the surface so that each mask layer and the first mask layer EL 1 The multiple etching processes will affect the first mask layer EL 1 To avoid the loss of the thickness of the first mask layer EL 1 Over-etching problem occurs, set the second mask layer EL 2 To the M+1th mask layer EL M+1 The thickness of the first mask layer EL 1 Thickness.

[0116] In one implementation of the embodiment of the present application, a second mask layer EL may be provided. 2 To the M+1th mask layer EL M+1 The thickness of the second mask layer EL is the same, which is convenient for 2 To the M+1th mask layer EL M+1 Process preparation.

[0117] The M-level groove structure has M-level steps. The area around the opening of the i-th level groove is the i-th level step. Fig.18 As shown, when M=3, the first-level groove GR 1 The opening of the i+1 epitaxial layer EL is surrounded by the first step, the opening of the second-level trench is surrounded by the second step, and the opening of the third-level trench is surrounded by the third step. i+1 The i-th level trench of the M-level trench structure can be formed. Fig.18 As shown, the second epitaxial layer EL 2 The first-level trench of the M-level trench structure can be formed, and the third epitaxial layer EL 3 The second-level trench of the M-level trench structure can be formed, and the fourth epitaxial layer EL 4 A third-level trench of the M-level trench structure may be formed.

[0118] If the second mask layer EL 2 To the M+1th mask layer EL M+1 The thickness is the same, such as Fig.18 As shown, the steps of each level in the M-level trench structure can have the same width.

[0119] In the embodiment of the present application, a second mask layer EL may also be provided. 2 To the M+1th mask layer EL M+1 At least two of the thicknesses of the layers are different, so that at least two steps of different widths can be formed in the M-level trench structure. In this way, when the second mask layer EL is selectively removed, 2 To the M+1th mask layer EL M+1 When one or more of the above are used to form multiple separated ion implantation regions 11 in the M-level trench structure, ion implantation can be performed on step surfaces of different widths to form ion implantation regions 11 of desired widths, so that the lateral width of the ion implantation region 11 can be flexibly controlled, thereby better optimizing device performance. 2 To the M+1th mask layer EL M+1 The thickness of at least two of them is different. If an integrated continuous ion implantation region 11 is formed in the M-level trench structure, the lateral width of the ion implantation region 11 corresponding to each step position can be controlled by setting the thickness of each mask layer, so that the integrated continuous ion implantation region 11 has a variety of lateral widths in each step area. This method can achieve differentiated design of the lateral width of the ion implantation region 11 at different steps by adjusting the relative thickness of each mask layer, thereby optimizing device performance.

[0120] If the second mask layer EL 2 To the M+1th mask layer EL M+1 The thickness of at least two of them is different. Further, a second mask layer EL may be provided. 2 To the M+1th mask layer EL M+1 At this time, the widths of the first to Mth steps increase successively, so that the width of the step is positively correlated with the depth of the step. The greater the step depth, the greater the step width, which facilitates ion implantation on the surface of the step with a greater depth, so as to ensure the implantation effect of the ion implantation area 11 in the side wall of the groove with a greater depth.

[0121] Each mask layer can be prepared by a plasma enhanced chemical vapor deposition (PECVD) process. The deposition thickness of the mask layer can range from 150°C to 350°C.

[0122] In the embodiment of the present application, the first mask layer EL 1 The thickness of the second mask layer EL can range from 2 μm to 5 μm. 2 To the M+1th mask layer EL M+1 In the embodiment, each mask layer includes a first mask layer EL covering the first mask layer EL before etching. 1The first film layer portion and the second film layer portion located in the previous level through hole. The thickness of the first film layer portion can range from 200nm to 1200nm, and the thickness of the second film layer portion can range from 100nm to 400nm. 2 To the M+1th mask layer EL M+1 Since the second film layer is partially located in the surface of the through hole, the deposition depth is large, and the first film layer is directly deposited on the first mask layer EL. 1 , so the thickness of the first film layer portion is greater than the thickness of the second film layer portion.

[0123] It can be seen from the above description that the preparation method provided in the embodiment of the present application can prepare an M-level trench structure in the epitaxial layer 15 based on an M+1 mask layer. The material of the mask layer can be any one of silicon oxide, silicon nitride and polysilicon, and the mask layers of different materials have a larger wet etching selectivity ratio. If the wet etching selectivity ratio of silicon nitride to silicon oxide is greater than 100, the wet etching selectivity ratio of silicon nitride to polysilicon is greater than 100. The material of each mask layer can be set according to demand, and the material of the mask layer is not limited to silicon oxide, silicon nitride and polysilicon, etc., and can also be other inorganic materials. The embodiment of the present application does not limit the material of the mask layer.

[0124] The materials of each mask layer can be set to be different, so that each mask layer can have a different wet etching speed, and there is a wet etching selectivity ratio between any two mask layers, so that a self-aligned ion implantation window 19 can be formed using the mask layer based on the wet etching selectivity ratio.

[0125] The i-th mask layer EL can also be set i The first material, the i+1th mask layer EL i+1 The first material and the second material have a wet etching selectivity ratio. 1 To the M+1th mask layer EL M+1 In the embodiment, an alternating stacking structure of a first material mask layer and a second material mask layer can be formed, and any two adjacent mask layers have a wet etching selectivity ratio, so that a self-aligned ion implantation window 19 can be formed using the mask layer based on the wet etching selectivity ratio.

[0126] You can also set the first mask layer EL 1 To the M+1th mask layer EL M+1 At least two of the films are made of different materials, so that the at least two films have a wet etching selectivity ratio, so as to form a self-aligned ion implantation window 19 by using a mask layer based on the wet etching selectivity ratio.

[0127] In the embodiment of the present application, the self-aligned ion implantation window 19 can be formed by using a mask layer for preparing an M-level trench structure, and then the second mask layer EL can be removed. 2 To the M+1th mask layer EL M+1 After at least one of the above is formed, the other mask layers are retained to form a self-aligned ion implantation window 19. Based on the self-aligned ion implantation window 19, ion implantation is directly performed, which greatly simplifies the process flow of ion implantation after multi-level groove etching, and does not require thin film deposition and photolithography patterning again. The preparation process is simple and the manufacturing cost is low. At the same time, it can also avoid the problem of mask material residue caused by unclean etching of the groove corner position when the mask material is deposited again in the multi-level groove.

[0128] As mentioned above, in the embodiment of the present application, a junction-controlled diode can be further formed based on the ion implantation region 11 in the M-level trench structure. The conduction voltage drop of the junction-controlled diode is smaller than the body diode of the device, thereby shielding the conduction of the body diode. The junction-controlled diode is a unipolar device and does not have a minority carrier storage effect, which can significantly reduce the switching loss of the semiconductor device.

[0129] In the implementation of the present application, if an integrated and continuous ion implantation area 11 is formed in the M-level trench structure, the ion implantation area 11 is not limited to forming a junction-controlled diode located between two trench gates. The M-level trench structure can also be used to form a trench gate of a semiconductor device. The integrated and continuous ion implantation area 11 can also serve as an electric field shielding layer under the surface of the gate dielectric layer of the trench gate to improve the device's withstand voltage and prevent the gate dielectric layer from being broken down at each level of the trench corner.

[0130] Optionally, in an embodiment of the present application, the epitaxial wafer 18 can be a wide bandgap semiconductor material such as silicon carbide, and the injected ions can be P-type ions. The preparation method provided in the embodiment of the present application can solve the problem of limited injection depth of P-type ions and difficulty in diffusion of P-type ions in wide bandgap semiconductor materials through a multi-stage trench combined with ion implantation method, and deeper P-type ion doping can be achieved in wide bandgap semiconductor materials without the need for high-energy and high-dose ion implantation areas.

[0131] In the embodiment of the present application, the multi-layer mask layer can sequentially form a sidewall stacking structure stacked in the horizontal direction on the sidewalls of each level of through hole, such as Fig.18 As shown, the second mask layer EL 2 Can form a cover first through hole Via 1 The sidewall of the third mask layer EL 3 Can form a cover second through hole Via 2 The sidewall, the 4th mask layer EL 4 Can form a cover third via 3 The sidewall of the second mask layer EL 2 To the 4th mask layer EL4 A sidewall stacking structure with transverse stacking is formed. The preparation method can save multiple photolithography processes and simplify the preparation process of multi-level grooves. At the same time, the width of each step can be controlled by controlling the thickness of the sidewall, so that the minimum line width of the multi-level steps is not limited by the photolithography accuracy, and the lateral width of the ion implantation area 11 corresponding to each step can also be controlled.

[0132] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0133] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0134] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0135] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0136] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on an upper surface of the semiconductor substrate; forming a first mask layer having a first through hole on the upper surface of the epitaxial layer; forming an (i+1)th mask layer having an (i+1)th through hole on a surface of the (i)th mask layer having an (i)th through hole; The epitaxial layer is etched based on the i+1th through hole to form an i-th level groove in the upper surface of the epitaxial layer, so as to sequentially form the 1st level groove to the M-level groove structure in the upper surface of the epitaxial layer; wherein M is a positive integer greater than 1; before forming the i-th level groove, the i+1th mask layer covers the top of the i-th mask layer and covers the sidewall and bottom of the i-th through hole, and i is a positive integer not greater than M; the apertures of the 1st through hole to the M+1th through hole decrease sequentially, and the widths of the 1st level groove to the M-th level groove decrease sequentially; A self-aligned ion implantation window is formed based on at least one of the first mask layer to the M+1th mask layer, and self-aligned ion implantation is performed to form an ion implantation region in the surface of the M-level trench structure.

2. The preparation method according to claim 1, characterized in that: After the Mth-level groove structure is formed in the upper surface of the epitaxial layer based on the M+1th through hole, the top of the 2nd mask layer to the M+1th mask layer is flush with the upper surface of the 1st mask layer; in the 1st-level groove to the M-1th-level groove, the side wall of the ath-level groove is covered with the a+2th mask layer, where a is a positive integer not greater than M-1.

3. The preparation method according to claim 2, characterized in that: The i-th mask layer and the i+1-th mask layer have a wet etching selectivity ratio; The method for forming the ion implantation region in the surface of the M-level trench structure comprises: Based on the wet etching selection ratio, the jth mask layer is removed, and other mask layers are retained to expose the area around the opening of the j-1th level trench; j is a positive integer greater than 1 and not greater than M+1; Self-aligned ion implantation is performed using the gap between the j-1th mask layer and the j+1th mask layer as the self-aligned ion implantation window to form ion implantation regions in the sidewall surface of the j-1th level groove and in the bottom surface of the Mth level groove.

4. The preparation method according to claim 3, characterized in that: The epitaxial layer and the ion implantation region have different doping types to form a junction controlled diode; After forming a plurality of ion implantation regions in the surface of the M-th level trench structure, the method further comprises: Retaining the first mask layer having the first through hole, and after removing other mask layers, forming an ohmic contact layer in the M-level trench structure, wherein the ohmic contact layer covers the surface of the M-level trench structure and the upper surface of the epitaxial layer exposed by the first through hole, so as to form a plurality of junction-controlled diodes based on the M-level trench structure; The M-level trench structure is filled with a dielectric material.

5. The preparation method according to claim 2, characterized in that: The i-th mask layer and the (i+1)-th mask layer have a wet etching selectivity ratio of not less than 100.

6. The preparation method according to claim 2, characterized in that: The first mask layer and the second mask layer have a wet etching selectivity ratio; the second mask layer to the M+1th mask layer are film layers of the same material; The method for forming the ion implantation region in the surface of the M-level trench structure comprises: Based on the wet etching selection ratio, removing the second mask layer to the M+1th mask layer; The first through hole in the first mask layer is used as the self-aligned ion implantation window to perform self-aligned ion implantation to implant ions into the M-level groove structure to form an integrated ion implantation region within the surface of the M-level groove structure and around the opening of the first-level groove.

7. The preparation method according to claim 6, characterized in that: The epitaxial layer and the ion implantation region have different doping types to form a junction controlled diode; After forming the plurality of ion implantation regions, the method further comprises: After removing the first mask layer, filling the M-level trench structure with a dielectric material; forming a first electrode and a second electrode; wherein the first electrode covers the upper surface of the epitaxial layer, and the second electrode covers the lower surface of the semiconductor substrate; Wherein, a junction-controlled diode is formed between the integrated ion implantation region and the epitaxial layer.

8. The preparation method according to claim 1, characterized in that: The thicknesses of the second mask layer to the M+1th mask layer are all smaller than the thickness of the first mask layer.

9. The preparation method according to claim 1, characterized in that: The thicknesses of the second mask layer to the M+1th mask layer are all the same.

10. The preparation method according to any one of claims 1 to 9, characterized in that: The epitaxial layer is an N-type doped silicon carbide layer; Ion implantation is performed on the surface of the M-level trench structure based on P-type ions.

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