Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate; forming a charge storage layer on the substrate; forming a gate structure on the charge storage layer; forming a source and a drain in the substrate on both sides of the gate structure; and performing hot carrier injection on the charge storage layer to allow electrons or holes to enter the charge storage layer. The formation method provided by this invention allows the carrier transport channel to be located away from the substrate surface, reducing the influence of the substrate interface on the channel carriers, improving the channel carrier mobility, and enhancing the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. In order to adapt to the smaller feature size, the channel length of semiconductor devices is also continuously shortened.

[0003] The semiconductor structure includes a substrate, a gate structure on the substrate, and source / drain doped layers located on both sides of the gate structure within the substrate. As the channel length continues to shorten, the gate dielectric layer of the gate structure is easily broken down, and semiconductor devices are prone to leakage and other problems.

[0004] Therefore, the performance of current semiconductor structures still needs improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can improve carrier migration efficiency, reduce device leakage current, and improve the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a charge storage layer on the substrate; forming a gate structure on the charge storage layer; forming a source and a drain in the substrate on both sides of the gate structure; and performing hot carrier injection on the charge storage layer to allow electrons or holes to enter the charge storage layer.

[0007] Optionally, the material of the charge storage layer includes silicon nitride or nitrogen-doped silicon carbide.

[0008] Optionally, the method for performing hot carrier injection on the charge storage layer includes: applying different voltages to the gate structure, the source, the drain, and the substrate to form an electric field force, wherein the electric field force causes electrons or holes to enter the charge storage layer.

[0009] Optionally, the substrate is a P-type substrate, and the charge storage layer is subjected to hot carrier injection treatment to allow electrons to enter the charge storage layer.

[0010] A first voltage is applied to the gate structure, the first voltage being equal to a positive power supply voltage that is a first preset multiple; a second voltage is applied to the drain, the second voltage being equal to a positive power supply voltage that is a second preset multiple.

[0011] Optionally, the substrate is an N-type substrate, and the charge storage layer is subjected to hot carrier injection treatment to allow holes to enter the charge storage layer.

[0012] A first voltage is applied to the gate structure, the first voltage being equal to a negative power supply voltage of a first preset multiple; a second voltage is applied to the drain, the second voltage being equal to a negative power supply voltage of a second preset multiple.

[0013] The value of the first preset multiple is 1 to 1.5, and the value of the second preset multiple is 1.1 to 1.5.

[0014] Optionally, the gate structure includes a gate dielectric layer located on the charge storage layer and a gate layer located on the gate dielectric layer.

[0015] Optionally, the method for forming the charge storage layer and the gate dielectric layer includes chemical vapor deposition or atomic layer deposition.

[0016] Accordingly, embodiments of the present invention also provide a semiconductor structure formed by the above-described forming method, comprising: a substrate; a charge storage layer located on the substrate, wherein the charge storage layer stores electrons or holes; a gate structure located on the charge storage layer; a source and a drain, wherein the source and the drain are respectively located in the substrate on both sides of the gate structure.

[0017] Optionally, the substrate is a P-type substrate, and the charge storage layer stores electrons.

[0018] Optionally, the substrate is an N-type substrate, and the charge storage layer stores holes.

[0019] Optionally, the material of the charge storage layer includes silicon nitride or nitrogen-doped silicon carbide.

[0020] Optionally, the gate structure includes a gate dielectric layer located on the charge storage layer and a gate layer located on the gate dielectric layer.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] The formation method provided by this technical solution forms a charge storage layer on a substrate and injects electrons or holes into the charge storage layer through hot carrier injection, depending on the type of semiconductor device. The electrons or holes in the charge storage layer electrostatically repel the channel carriers in the substrate. By utilizing electrostatic repulsion, the carrier transport channels are moved away from the interface between the substrate and the charge storage layer, reducing the impact of the interface on the carrier transport channels and improving the carrier mobility. Furthermore, adding a charge storage layer between the gate structure and the substrate can reduce leakage current and improve the performance of the final semiconductor device.

[0023] The semiconductor structure provided by this technical solution has a charge storage layer between the substrate and the gate structure. Depending on the type of semiconductor device, the charge carriers stored in the charge storage layer are electrons or holes. The charge storage layer will generate electrostatic repulsion on the channel carriers in the substrate. By using electrostatic repulsion, the channel carriers are pushed away from the substrate surface, reducing the adverse effect of the interface between the substrate and the charge storage layer on the transport of channel carriers, improving carrier mobility, and increasing the source and drain conduction current of the device. Furthermore, the channel layer is far away from the gate structure, which is beneficial to improving the reliability of the semiconductor structure. Attached Figure Description

[0024] Figures 1 to 4 This is a schematic diagram of the semiconductor formation process in one embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of applying a voltage to a semiconductor structure in one embodiment of the present invention. Detailed Implementation

[0026] As described in the background art, with the development of semiconductor technology, the feature size of semiconductor devices continues to decrease, and the distance between the source and drain electrodes is also shortened accordingly. In addition, the thickness of the gate dielectric layer of the gate structure gradually becomes thinner, which makes the device prone to leakage current and has an adverse effect on the performance of the device.

[0027] Currently, silicon dioxide is the commonly used material for gate dielectric layers. Although silicon dioxide has good adhesion to the substrate and forms fewer interface defects, its low dielectric constant makes it prone to leakage current as the gate dielectric layer is thinned. To reduce device leakage current, high-k dielectric materials or silicon nitride are used as gate dielectric layers. However, high-k dielectric materials and silicon nitride have poor interfacial compatibility with the substrate, resulting in poor interface performance and more defects at the gate dielectric layer-substrate contact point. This affects the mobility of carriers in the channel within the substrate, and consequently, the performance of the semiconductor device.

[0028] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure and its formation method. A charge storage layer is formed on a substrate. After hot carrier injection, electrons or holes enter the charge storage layer, making it positively or negatively charged. The charge in the charge storage layer exerts an electrostatic repulsion force on the channel carriers in the substrate. Under this electrostatic repulsion, the channel carriers in the substrate move away from the substrate surface, thereby reducing the adverse effects of interface defects between the substrate and the charge storage layer on the transport of channel carriers and improving carrier mobility. Furthermore, by adding a charge storage layer and keeping the channel carriers away from the gate dielectric layer of the gate structure, the possibility of the gate dielectric layer being broken down is reduced, improving the reliability of the gate dielectric layer and the performance of the semiconductor structure.

[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 1 to 4 This is a schematic diagram of the semiconductor formation process in one embodiment of the present invention; Figure 5 This is a schematic diagram of applying a voltage to a semiconductor structure in one embodiment of the present invention.

[0031] refer to Figure 1 Substrate 100 is provided.

[0032] The substrate 100 is one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or silicon on an insulator; the substrate 100 may also be a Si substrate, a Ge substrate, a GeSi substrate, or a GaAs substrate. In this embodiment, the substrate 100 is a Si substrate.

[0033] The substrate 100 can be an N-type substrate or a P-type substrate.

[0034] In this embodiment, the semiconductor structure formed is an NMOS device, and the substrate 100 is a P-type substrate.

[0035] In other embodiments, an N-type substrate is used to form the PMOS device.

[0036] refer to Figure 2 A charge storage layer 101 is formed on the substrate 100.

[0037] In this embodiment, a charge storage layer 101 is first formed on the substrate 100, and then a gate dielectric layer is formed on the charge storage layer 101.

[0038] In this embodiment, the method for forming the charge storage layer 101 includes: forming a charge storage material layer (not shown) on the substrate 100; patterning the charge storage material layer to form the charge storage layer 101 on the substrate 100.

[0039] In this embodiment, a charge storage material layer is formed on the substrate 100 using chemical vapor deposition; in other embodiments, an atomic layer deposition method can also be used to form a charge storage material layer on the substrate 100.

[0040] In this embodiment, the charge storage layer 101 is made of silicon nitride. The reason for using silicon nitride is that, firstly, silicon nitride has a high dielectric constant of 6 to 9, making it an ideal dielectric material with excellent insulation properties. The silicon nitride layer is located between the subsequently formed gate structure and the substrate 100, which can reduce the occurrence of device leakage and improve device reliability. Secondly, silicon nitride itself has a large number of defects such as vacancies, which can serve as a charge storage medium. This is beneficial for capturing and storing charges during subsequent hot carrier injection, thereby creating an electrostatic repulsion between the charge storage layer and the carriers in the substrate.

[0041] In other embodiments, nitrogen-doped silicon carbide may also be used as the charge storage layer.

[0042] The thickness of the charge storage layer 101 is 5 angstroms to 100 angstroms. This thickness allows the charge storage layer 101 to capture enough charge to generate a strong electrostatic repulsion force on the channel carriers in the substrate 100 and to prevent the carriers captured by the charge storage layer 101 from entering the subsequently formed gate dielectric layer 102. On the other hand, the device conduction speed will not be slowed down due to the excessive thickness of the charge storage layer 101.

[0043] refer to Figure 3 A gate dielectric layer 102 is formed on the charge storage layer 101.

[0044] In this embodiment, the method for forming the gate dielectric layer 102 includes: forming a gate dielectric material layer (not shown) on the charge storage layer 101; and patterning the gate dielectric material layer to form the gate dielectric layer 102 on the charge storage layer 101.

[0045] In other embodiments, a charge storage material layer may be formed on the substrate 100, and a gate dielectric material layer may be formed on the charge storage material layer; the gate dielectric material layer and the charge storage layer may be patterned to form a charge storage layer 101 and a gate dielectric layer 102 located on the charge storage layer 101 on the substrate 100.

[0046] In this embodiment, the gate dielectric material layer is formed using chemical vapor deposition; in other embodiments, the gate dielectric material layer can also be formed using atomic layer deposition.

[0047] In this embodiment, the gate dielectric layer 102 is made of silicon dioxide. Silicon dioxide can increase the bonding force between the silicon nitride layer and the subsequently formed gate layer, and improve the performance of the interface between the silicon nitride layer and the gate layer.

[0048] Continue to refer to Figure 3 After forming the gate dielectric layer 102, a gate layer 103 is formed on the gate dielectric layer 102.

[0049] In this embodiment, the method for forming the gate layer 103 includes: forming a gate material layer (not shown) on the gate dielectric layer 102, the gate material layer also covering the surface of the substrate 100; patterning the gate material layer to form the gate layer 103 on the gate dielectric layer 102.

[0050] In this embodiment, the gate structure includes a gate dielectric layer 102 and a gate layer 103 located on the gate dielectric layer 102.

[0051] In this embodiment, the gate layer 103 is made of polycrystalline silicon.

[0052] In this embodiment, sidewalls 104 are also formed on both sides of the gate layer 103 and the gate dielectric layer 102.

[0053] The sidewall 104 is made of one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the sidewall 104 is made of silicon nitride.

[0054] refer to Figure 4 After forming the sidewall 104, the method further includes forming a source 105 and a drain 106 in the substrate 100 on both sides of the gate layer 103.

[0055] In this embodiment, the doped ions of the source 105 and drain 106 are N-type ions, such as P, As, or Sb. In other embodiments, the doped ions of the source 105 and drain 106 may also be P-type ions, depending on the type of semiconductor device.

[0056] After the source 105 and drain 106 are formed, the charge storage layer 101 is subjected to hot carrier injection, so that electrons or holes enter the charge storage layer 101 and are captured by the charge storage layer 101.

[0057] In this embodiment, an electric field is generated by applying different voltages to the gate layer 103, source 105, drain 106 and substrate 100, and the electric field performs hot carrier injection on the charge storage layer 101.

[0058] refer to Figure 5Specifically, a first voltage V is applied to the gate layer 103 of the gate structure. gs A second voltage V is applied to the drain 106. ds A voltage V is applied to the source. s and applying a voltage V to the substrate 100 sub .

[0059] In this embodiment, the voltages applied to the gate layer 103 and the drain 106 have the same polarity.

[0060] In this embodiment, taking an NMOS device as an example, the substrate 100 is a P-type substrate, and the source 105 and drain 106 are N-type doped. When an appropriate voltage is applied to the drain 106, a transverse electric field is generated in the channel region. Electrons in the substrate 100 are accelerated under the action of the transverse electric field to form high-energy charge carriers. The high-energy charge carriers collide with the silicon lattice to generate ionized electron-hole pairs. At this time, the electrons have sufficiently high energy. The voltage applied to the gate layer 103 generates a longitudinal electric field. Under the action of the longitudinal electric field, the electrons overcome the interface potential between the substrate 100 and the charge storage layer 101 and are injected into the charge storage layer 101, where they are captured by defects in the charge storage layer 101.

[0061] In this embodiment, the first voltage V gs A positive power supply voltage V equal to the first preset multiple dd The second voltage V ds A positive power supply voltage V equal to the second preset multiple dd The source 105 and the substrate 100 are grounded.

[0062] In this embodiment, the first voltage V gs Second voltage V ds All are less than the breakdown voltage of the formed semiconductor device.

[0063] In this embodiment, the power supply voltage V dd The operating voltage for the formed semiconductor device to operate.

[0064] The first preset multiple has a value of 1 to 1.5, and the second preset multiple has a value of 1.1 to 1.5. Using this voltage range can accelerate the generation of hot carriers and speed up the process of hot carrier injection, without reaching the breakdown voltage of the semiconductor device, thus avoiding damage to the semiconductor device.

[0065] In this embodiment, the first voltage V gs Equal to the power supply voltage V dd The second voltage V ds Equal to 1.1 times the power supply voltage V dd .

[0066] In this embodiment, a first voltage V is applied. gs Second voltage V ds The same time allows for sufficient electron injection, saturating the charge storage layer 101 and thus providing a stronger electrostatic repulsion effect.

[0067] In this embodiment, the charge storage layer 101 is saturated by detecting the substrate current. The substrate current will increase during the hot carrier injection process. When the detected substrate current tends to stabilize, the carrier injection of the charge storage layer 101 reaches saturation, and the voltage applied to the gate layer 103, source 105, drain 106 and substrate 100 can be stopped.

[0068] In this embodiment, in the NMOS device, the hot carrier injection process allows electrons to enter the charge storage layer 101, making the charge storage layer 101 negatively charged. The NMOS device is an N-type channel, and the channel carriers are electrons. The polarity of the charge storage layer 101 is consistent with the polarity of the channel carriers, which can generate an electrostatic repulsion effect on the channel carriers. Under the electrostatic repulsion force, the channel carriers move away from the surface of the substrate 100 and transport deep away from the surface of the substrate 100. The influence of the interface between the substrate 100 and the charge storage layer 101 is reduced, and the carrier mobility is increased, which is beneficial to improving the performance of the semiconductor device.

[0069] It should be noted that when a positive voltage is applied to the gate layer 103, electrons in the substrate 100 are affected by the longitudinal electric field and will gather near the surface of the substrate 100. The position of the channel carriers when the attraction of the gate voltage to the electrons and the repulsion of the charge in the charge storage layer 101 to the electrons reach equilibrium is the position of the channel region when the semiconductor device is turned on.

[0070] In another embodiment, in the PMOS device, the substrate 100 is an N-type substrate, and the source 105 and drain 106 are P-type doped. When an appropriate voltage is applied to the drain 106 and the gate layer 103, holes enter the charge storage layer 101, making the charge storage layer 101 positively charged, and generating an electrostatic repulsion effect on the charge carriers of the P-type channel.

[0071] In a PMOS device, the first voltage V gs The negative power supply voltage V equal to the first preset multiple dd The second voltage V ds The negative power supply voltage V equal to the second preset multiple dd The source 105 and the substrate 100 are grounded.

[0072] The value of the first preset multiple is 1 to 1.5, and the value of the second preset multiple is 1.1 to 1.5.

[0073] refer to Figure 4 Accordingly, this embodiment of the invention also provides a semiconductor structure, including: a substrate 100; a charge storage layer 101 located on the substrate 100, wherein the charge storage layer 101 stores electrons or holes; a gate structure located on the charge storage layer 101; a source 105 and a drain 106 located on both sides of the gate structure within the substrate 100.

[0074] In this embodiment, the gate structure includes a gate dielectric layer 102 located on the charge storage layer 101, and a gate layer 103 located on the gate dielectric layer 102.

[0075] In this embodiment, the substrate 100 is a P-type substrate, and the charge storage layer 101 stores electrons.

[0076] In other embodiments, the substrate 100 is an N-type substrate, and the charge storage layer 101 stores holes.

[0077] In this embodiment, the charge storage layer 101 is made of silicon nitride.

[0078] In other embodiments, nitrogen-doped silicon carbide may also be used as the charge storage layer.

[0079] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A charge storage layer is formed on the substrate; A gate structure is formed on the charge storage layer; The source and drain are formed in the substrate on both sides of the gate structure; The charge storage layer is subjected to hot carrier injection treatment to allow electrons or holes to enter the charge storage layer. When the substrate is a P-type substrate, a first voltage is applied to the gate structure, the first voltage being equal to a positive power supply voltage that is a first preset multiple; A second voltage is applied to the drain electrode, the second voltage being equal to a positive power supply voltage that is a second preset multiple, so that electrons enter the charge storage layer; Alternatively, when the substrate is an N-type substrate, a first voltage is applied to the gate structure, the first voltage being equal to a negative power supply voltage that is a first preset multiple; A second voltage is applied to the drain electrode, the second voltage being equal to a negative power supply voltage that is a second preset multiple, so that holes enter the charge storage layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The charge storage layer is made of silicon nitride or nitrogen-doped silicon carbide.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for performing hot carrier injection on the charge storage layer includes: applying different voltages to the gate structure, the source, the drain and the substrate to form an electric field force, which causes electrons or holes to enter the charge storage layer.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The value of the first preset multiple is 1 to 1.5, and the value of the second preset multiple is 1.1 to 1.

5.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer located on the charge storage layer and a gate layer located on the gate dielectric layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The methods for forming the charge storage layer and the gate dielectric layer include chemical vapor deposition or atomic layer deposition.

7. A semiconductor structure, characterized in that, include: Substrate; A charge storage layer located on the substrate, wherein electrons or holes are stored within the charge storage layer; A gate structure located on the charge storage layer; The source and drain are respectively located in the substrate on both sides of the gate structure; When the substrate is a P-type substrate, a first voltage is applied to the gate structure, the first voltage being equal to a positive power supply voltage of a first preset multiple, and a second voltage is applied to the drain, the second voltage being equal to a positive power supply voltage of a second preset multiple. Alternatively, when the substrate is an N-type substrate, a first voltage is applied to the gate structure, the first voltage being equal to a negative power supply voltage of a first preset multiple, a second voltage is applied to the drain, the second voltage being equal to a negative power supply voltage of a second preset multiple, and holes are stored in the charge storage layer.

8. The semiconductor structure as described in claim 7, characterized in that, The charge storage layer is made of silicon nitride or nitrogen-doped silicon carbide.

9. The semiconductor structure as described in claim 7, characterized in that, The gate structure includes a gate dielectric layer located on the charge storage layer and a gate layer located on the gate dielectric layer.

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