High voltage device structure

Abstract

The present invention provides a high-voltage device structure, comprising: a substrate; a gate dielectric layer, the gate dielectric layer being formed in a trench formed in the substrate; a high-voltage P-well, the high-voltage P-well being formed in the substrate; a first N-type diffusion region, the first N-type diffusion region being formed in the high-voltage P-well at a first side surface of the gate dielectric layer and partially extending below the gate dielectric layer; a second N-type diffusion region, the second N-type diffusion region being spaced apart from the first N-type diffusion region and formed in the high-voltage P-well at a second side surface of the gate dielectric layer and partially extending below the gate dielectric layer; a drain terminal being formed in a surface layer of the first N-type diffusion region; a source terminal being formed in a surface layer of the second N-type diffusion region; and a gate material layer being formed on a surface of the gate dielectric layer and comprising a first region, a second region, and a third region. The present invention solves the problem of the existing parasitic transistor being prone to premature turn-on.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a high-voltage device structure. Background Art

[0002] OLED (organic light-emitting diode) is a current injection composite luminescence type. It has attracted widespread attention due to its advantages such as high brightness, high contrast, wide viewing angle, fast response speed, low operating voltage, strong adaptability, high energy conversion efficiency and simple manufacturing process.

[0003] OLEDs are current-driven, and their current density depends on the driving voltage across the two ends. The higher the voltage, the greater the current density, so high-voltage devices with large reverse bias voltages are required. However, high-voltage devices are prone to parasitic transistors under high negative voltages, and these parasitic transistors may partially turn on prematurely.

[0004] As logic device technology nodes advance, OLED technology integrated with advanced technology nodes is under continuous development. Currently, the most advanced mass-produced technology node is a 28nm high-dielectric metal gate (28HV) technology, which leverages the high performance and low voltage of advanced nodes. 28HV MG technology requires the integration of low-voltage SRAM and high-voltage driver devices. High voltage requires a thick gate oxide layer as the gate dielectric layer, and a thick gate oxide layer can affect subsequent metal gate processes.

[0005] In order to be compatible with metal gate technology, the high voltage region (HV) will be etched back (recess) of the active area, and then a thick silicon oxide layer will be grown to make it as consistent as possible with the height of the active area to facilitate subsequent process development. Figures 1 to 3 FIG. 1 is a schematic diagram of a device structure in each step of forming a gate dielectric layer in an existing method for manufacturing a high-voltage device. The steps of forming a gate dielectric layer in the existing method for manufacturing a high-voltage device include:

[0006] like Figure 1 As shown, a substrate 100 is provided, a shallow trench isolation structure 200 is formed in the substrate 100, and the substrate 100 in the area surrounded by the shallow trench isolation structure 200 is an active area 101; a hard mask layer 300 is formed on the surface of the substrate 100, and the material of the hard mask layer 300 is silicon nitride; a photolithography process is performed to form a photoresist pattern 400, and the photoresist pattern is patterned.

[0007] like Figure 2 As shown, the substrate 100 is etched using the patterned photoresist 400 as a mask to form a trench 500 .

[0008] like Figure 3As shown, a dielectric layer 600 is filled in the trench 500 .

[0009] However, due to the large size of the high voltage device, it needs to be reduced in order to save area. During the reduction process, the thickness of the edge of the gate dielectric layer is larger than the thickness of the central area (such as Figure 3 and Figure 4 As shown in FIG, the problem of premature turn-on of the parasitic transistor is aggravated. Summary of the Invention

[0010] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a high-voltage device structure for solving the problem that the prior parasitic transistor is prone to premature turn-on.

[0011] To achieve the above-mentioned and other related objectives, the present invention provides a high-voltage device structure, comprising:

[0012] substrate,

[0013] a gate dielectric layer, wherein the gate dielectric layer is formed in a trench formed in the substrate, wherein a thickness of a middle region of the gate dielectric layer is greater than a thickness of an edge region thereof;

[0014] a high-voltage P-well formed in the substrate;

[0015] a first N-type diffusion region, wherein the first N-type diffusion region is formed in the high-voltage P-well at a first side surface of the gate dielectric layer and partially extends to below the gate dielectric layer;

[0016] a second N-type diffusion region, the second N-type diffusion region being spaced apart from the first N-type diffusion region, formed in the high-voltage P-well at the second side surface of the gate dielectric layer, and partially extending below the gate dielectric layer;

[0017] a drain terminal formed in a surface layer of the first N-type diffusion region;

[0018] a source terminal formed in a surface layer of the second N-type diffusion region;

[0019] a gate material layer formed on a surface of the gate dielectric layer, comprising a first region, a second region, and a third region, wherein the second region connects the first region and the third region, and the three regions are in an I-shape; the second region is located in a middle region of the gate dielectric layer where the thickness is greater, the length of the second region is less than the interval between the first N-type diffusion region and the second N-type diffusion region, and the width of the second region is less than the width of the source terminal or the drain terminal;

[0020] A P-type diffusion region, formed in the high-voltage P-well, in an annular shape, surrounding the first N-type diffusion region and the second N-type diffusion region;

[0021] The width of the effective area of ​​the gate material layer is the same as the width of the source end and the drain end.

[0022] Optionally, in the length direction, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is greater than a distance b1 between a second edge of the first N-type diffusion region and the P-type diffusion region, wherein the edge of the first region is the edge close to the second region.

[0023] Optionally, in the length direction, a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region is greater than a distance b2 between a second edge of the second N-type diffusion region and the P-type diffusion region, wherein the edge of the third region is an edge close to the second region side.

[0024] Optionally, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is equal to a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region.

[0025] Optionally, a distance b1 between the second edge of the first N-type diffusion region and the P-type diffusion region is equal to a distance b2 between the second edge of the second N-type diffusion region and the P-type diffusion region.

[0026] Optionally, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is 0.7 um to 1.0 um.

[0027] Optionally, a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region is 0.7 um to 1.0 um.

[0028] Optionally, in the width direction, a distance c between an edge of the second region and an edge of the source / drain terminal is greater than 1 / 20 of the width of the source / drain terminal and less than 1 / 10 of the width of the source / drain terminal.

[0029] Optionally, the structure further includes a shallow trench isolation structure, wherein the shallow trench isolation is formed between the P-type diffusion region and the first N-type diffusion region and the second N-type diffusion region, and is formed within a designated area of ​​the first N-type diffusion region and the second N-type diffusion region and is located between the source end / the drain end and the gate dielectric layer.

[0030] Optionally, the structure further includes a lead-out region formed in a surface layer of the P-type diffusion region.

[0031] Optionally, the lead-out region is a P+ lead-out region.

[0032] Optionally, the gate material layer is made of polysilicon or metal.

[0033] Optionally, the gate dielectric layer is made of silicon oxide or a material with a high dielectric constant.

[0034] Optionally, the structure further includes sidewall spacers formed on both sides of the gate material layer.

[0035] Optionally, the substrate is a P substrate.

[0036] As described above, the high-voltage device structure of the present invention removes the edge of the gate material layer of the device effective area with the same width as the source and drain, that is, forms a second area with a smaller width, so that the width of the second area is insufficient to form gate coupling, thereby reducing the control of the gate over the edge parasitic transistor, so that the parasitic transistor is not turned on prematurely. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1 to 3 It shows a cross-sectional structural schematic diagram of a conventional process for forming a gate dielectric layer.

[0038] Figure 4 Shown is an electron microscope image of the existing formed gate dielectric layer.

[0039] Figure 5 Shown is a layout diagram of the high-voltage device structure of the present invention.

[0040] Figure 6 Display as Figure 5 The schematic diagram of the cross-sectional structure of the layout shown is taken along AA'.

[0041] Figure 7 Display as Figure 5 The schematic diagram of the cross-sectional structure of the layout shown is taken along BB'.

[0042] Explanation of Figure Numbers

[0043] 10, 100: substrate; 20: gate dielectric layer; 30: high-voltage P-well; 41: first N-type diffusion region; 41a: first edge of the first N-type diffusion region; 41b: second edge of the first N-type diffusion region; 42: second N-type diffusion region; 42a: first edge of the second N-type diffusion region; 42b: second edge of the second N-type diffusion region; 51: drain terminal; 52: source terminal; 60: gate material layer; 61: first region; 62: second region; 63: third region; 70: P-type diffusion region; 71: lead-out region; 80, 200: shallow trench isolation structure; 90: sidewall; 101: active area; 300: hard mask layer; 400: photoresist; 500: trench; 600: dielectric layer DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.

[0046] like Figures 5 to 7 As shown, this embodiment provides a high-voltage device structure, which includes:

[0047] substrate 10,

[0048] a gate dielectric layer 20, wherein the gate dielectric layer 20 is formed in a trench formed in the substrate 10, wherein a thickness of a middle region of the gate dielectric layer 20 is greater than a thickness of an edge region thereof;

[0049] A high-voltage P-well 30 is formed in the substrate 10;

[0050] a first N-type diffusion region 41 formed in the high-voltage P-well 30 at a first side surface of the gate dielectric layer 20 and partially extending below the gate dielectric layer 20 ;

[0051] a second N-type diffusion region 42 , which is spaced apart from the first N-type diffusion region 41 , formed in the high-voltage P-well 30 at the second side surface of the gate dielectric layer 20 and partially extends below the gate dielectric layer 20 ;

[0052] a drain terminal 51 formed in a surface layer of the first N-type diffusion region 41;

[0053] a source terminal 52 formed in a surface layer of the second N-type diffusion region 42;

[0054] a gate material layer 60 formed on the surface of the gate dielectric layer 20 and including a first region 61, a second region 62, and a third region 63. The second region 62 connects the first region 61 and the third region 63, forming an I-shape. The second region 62 is located in a thicker middle region of the gate dielectric layer 20. The length of the second region 62 is less than the interval between the first N-type diffusion region 41 and the second N-type diffusion region 42, and the width of the second region 62 is less than the width of the source terminal 52 or the drain terminal 51.

[0055] A P-type diffusion region 70 is formed in the high-voltage P-well 30 , is annular in shape, and surrounds the first N-type diffusion region 41 and the second N-type diffusion region 42 ;

[0056] The width of the effective area of ​​the gate material layer 60 is the same as the width of the source terminal 52 and the drain terminal 51 .

[0057] In this embodiment, Figure 5 The area enclosed by the two green boxes is the P-type diffusion region 70. It should be noted that, Figure 6 and Figure 7 The gate dielectric layer 20 is thicker in the middle region and thinner in the edge region (eg Figure 3 As shown, this shape is not drawn for the convenience of drawing. Moreover, the reason why the gate dielectric layer 20 is thicker in the middle and thinner at the edge is that the substrate at the edge of the active area is affected by the shallow trench isolation structure STI and is tilted upward. Therefore, when the gate dielectric layer 20 is formed in the active area, the gate dielectric layer 20 will be thick in the middle and thin at the edge. Moreover, in this embodiment, Figure 5 The portion in the black circle is the effective area. The so-called effective area refers to the area where the gate material layer 60 overlaps with the active area. In this area, the gate plays a role in controlling the active area, and is therefore called the effective area.

[0058] Specifically, the substrate 10 is a P substrate.

[0059] Specifically, the gate dielectric layer 20 is made of silicon oxide or a material with a high dielectric constant.

[0060] Specifically, the gate material layer 60 is made of polysilicon or metal.

[0061] Specifically, in the length direction, the distance a1 between the edge of the first region 61 and the first edge 41a of the first N-type diffusion region 41 is greater than the distance b1 between the second edge 41b of the first N-type diffusion region 41 and the P-type diffusion region 70, wherein the edge of the first region 61 is the edge close to the side of the second region 62.

[0062] Specifically, in the length direction, the distance a2 between the edge of the third region 63 and the first edge 42a of the second N-type diffusion region 42 is greater than the distance b2 between the second edge 42b of the second N-type diffusion region 42 and the P-type diffusion region 70, wherein the edge of the third region 63 is the edge close to the side of the second region 62.

[0063] Specifically, the distance a1 between the edge of the first region 61 and the first edge 41 a of the first N-type diffusion region 41 is equal to the distance a2 between the edge of the third region 63 and the first edge 42 a of the second N-type diffusion region 42 .

[0064] Specifically, a distance b1 between the second edge of the first N-type diffusion region 41 and the P-type diffusion region 70 is equal to a distance b2 between the second edge of the second N-type diffusion region 42 and the P-type diffusion region 70 .

[0065] Specifically, a distance a1 between an edge of the first region 61 and a first edge 41 a of the first N-type diffusion region 41 is 0.7 um to 1.0 um.

[0066] Specifically, a distance a2 between the edge of the third region 63 and the first edge 42 a of the second N-type diffusion region 42 is 0.7 um to 1.0 um.

[0067] Specifically, in the width direction, the distance c between the edge of the second region 62 and the edge of the source terminal 52 / the drain terminal 51 is greater than 1 / 20 of the width of the source terminal 52 / the drain terminal 51 and less than 1 / 10 of the width of the source terminal 52 / the drain terminal 51.

[0068] Specifically, the structure also includes a shallow trench isolation structure 80, and the shallow trench isolation 80 is formed between the P-type diffusion region 70 and the first N-type diffusion region 41 and the second N-type diffusion region 42, and is formed in a designated area of ​​the first N-type diffusion region 41 and the second N-type diffusion region 42 and is located between the source terminal 52 / the drain terminal 51 and the gate dielectric layer 20.

[0069] Specifically, the structure further includes a lead-out region 71 , which is formed in the surface layer of the P-type diffusion region 70 .

[0070] More specifically, the lead-out region 71 is a P+ lead-out region.

[0071] Specifically, the structure further includes sidewall spacers 90 , and the sidewall spacers 90 are formed on both sides of the gate material layer 60 .

[0072] In this embodiment, the substrate 10 in each figure is also represented by P-sub, the high-voltage P well 30 is also represented by HVPW, which is the abbreviation of high voltage P type well, the first N-type diffusion region 41 and the second N-type diffusion region 42 are also represented by HVNDF, which is the abbreviation of high voltage N type diffusion, the P-type diffusion region 70 is also represented by HVPDF, which is the abbreviation of high voltage P type diffusion; and the shallow trench isolation structure is also represented by STI.

[0073] Furthermore, in this embodiment, a metal interconnection layer is formed on the substrate. Figure 6 and Figure 7 The metal interconnect layer is omitted in the figure. The metal interconnect layer will be formed on the multi-layer front metal layer pattern and the through holes connecting the front metal layer patterns of each layer. Finally, the source, drain and gate electrodes formed by the front metal layer patterning will be formed. The drain terminal will be connected to the drain electrode, the source terminal will be connected to the source electrode, the lead-out region will serve as the substrate electrode (bulk), and the gate material layer will be connected to the gate.

[0074] In summary, the high-voltage device structure of the present invention removes the edges of the gate material layer within the active device region, which is the same width as the source and drain electrodes. This creates a smaller second region, which is not wide enough to form gate coupling. This reduces the gate's control over the edge parasitic transistors, preventing premature turn-on of the parasitic transistors. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A high voltage device structure, characterized in that: The structure includes: substrate, a gate dielectric layer, wherein the gate dielectric layer is formed in a trench formed in the substrate, wherein a thickness of a middle region of the gate dielectric layer is greater than a thickness of an edge region thereof; a high-voltage P-well formed in the substrate; a first N-type diffusion region, wherein the first N-type diffusion region is formed in the high-voltage P-well at a first side surface of the gate dielectric layer and partially extends to below the gate dielectric layer; a second N-type diffusion region, the second N-type diffusion region being spaced apart from the first N-type diffusion region, formed in the high-voltage P-well at the second side surface of the gate dielectric layer, and partially extending below the gate dielectric layer; a drain terminal formed in a surface layer of the first N-type diffusion region; a source terminal formed in a surface layer of the second N-type diffusion region; a gate material layer formed on a surface of the gate dielectric layer, comprising a first region, a second region, and a third region, wherein the second region connects the first region and the third region, and the three regions are in an I-shape; the second region is located in a middle region of the gate dielectric layer where the thickness is greater, the length of the second region is less than the interval between the first N-type diffusion region and the second N-type diffusion region, and the width of the second region is less than the width of the source terminal or the drain terminal; A P-type diffusion region, formed in the high-voltage P-well, in an annular shape, surrounding the first N-type diffusion region and the second N-type diffusion region; Wherein, the width of the effective area of ​​the gate material layer is the same as the width of the source end and the drain end; In the length direction, a distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is greater than a distance b1 between a second edge of the first N-type diffusion region and the P-type diffusion region, wherein the edge of the first region is the edge close to the second region.

2. The high voltage device structure according to claim 1, characterized in that: In the length direction, the distance a2 between the edge of the third region and the first edge of the second N-type diffusion region is greater than the distance b2 between the second edge of the second N-type diffusion region and the P-type diffusion region, wherein the edge of the third region is the edge close to the second region side.

3. The high voltage device structure according to claim 2, characterized in that: A distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is equal to a distance a2 between an edge of the third region and a first edge of the second N-type diffusion region.

4. The high voltage device structure according to claim 2, characterized in that: A distance b1 between the second edge of the first N-type diffusion region and the P-type diffusion region is equal to a distance b2 between the second edge of the second N-type diffusion region and the P-type diffusion region.

5. The high voltage device structure according to claim 1, characterized in that: A distance a1 between an edge of the first region and a first edge of the first N-type diffusion region is 0.7 um to 1.0 um.

6. The high voltage device structure according to claim 2, characterized in that: A distance a2 between an edge of the third region and a first edge of the second N-type diffusion region is 0.7 um to 1.0 um.

7. The high voltage device structure according to claim 1, characterized in that: In the width direction, a distance c between an edge of the second region and an edge of the source / drain terminal is greater than 1 / 20 of the width of the source / drain terminal and less than 1 / 10 of the width of the source / drain terminal.

8. The high voltage device structure according to claim 1, characterized in that: The structure also includes a shallow trench isolation structure, which is formed between the P-type diffusion region and the first N-type diffusion region and the second N-type diffusion region, and is formed in a designated area of ​​the first N-type diffusion region and the second N-type diffusion region and is located between the source end / the drain end and the gate dielectric layer.

9. The high voltage device structure according to claim 1, characterized in that: The structure further includes a lead-out region formed in a surface layer of the P-type diffusion region.

10. The high voltage device structure according to claim 9, characterized in that: The lead-out region is a P+ lead-out region.

11. The high voltage device structure according to claim 1, characterized in that: The gate material layer is made of polysilicon or metal.

12. The high voltage device structure according to claim 1, characterized in that: The gate dielectric layer is made of silicon oxide or a high dielectric constant material.

13. The high voltage device structure according to claim 1, characterized in that: The structure further includes sidewall spacers formed on both sides of the gate material layer.

14. The high voltage device structure according to claim 1, characterized in that: The substrate is a P substrate.

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