Multi-gate device and forming method thereof

Abstract

Embodiments of the invention provide a multi-gate device and a method of forming the same. The method includes forming a first complementary field effect transistor (CFET) and a second CFET. The first CFET includes a first lower transistor and a first upper transistor overlapping the first lower transistor. The second CFET includes a second lower transistor and a second upper transistor overlapping the second lower transistor. The method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching the first gate stack between the first upper transistor and the second upper transistor, and etching the second gate stack between the second lower transistor and the second lower transistor. The first opening is filled with a dielectric material to form a dielectric region. The method further includes performing a second etch process to etch a middle portion of the dielectric region and form a second opening, and filling the second opening with a conductive material to form a via.

Description

Technical Field

[0001] Embodiments of the present application relate to multi-gate devices and methods of forming the same. Background Art

[0002] Complementary field effect transistors (CFETs) were developed to meet the increasingly stringent requirements for increasing transistor density in integrated circuits. A CFET includes a lower transistor and an upper transistor overlapping the lower transistor. The lower transistors and upper transistors of multiple CFETs can be interconnected to form a circuit. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a multi-gate device is provided, comprising: forming a first complementary field effect transistor (CFET), the first CFET comprising: a first lower transistor; and a first upper transistor overlapping the first lower transistor; forming a second CFET, the second CFET comprising: a second lower transistor; and a second upper transistor overlapping the second lower transistor; performing a first etching process to form a first opening, wherein the first etching process comprises: etching a gate stack between the first CFET and the second CFET; and etching a plurality of alternating structures vertically aligned with the gate stack; filling the first opening with a dielectric material to form a dielectric region; performing a second etching process to etch a middle portion of the dielectric region and to form a second opening; and filling the second opening with a conductive material to form a through hole.

[0004] According to another aspect of an embodiment of the present application, a multi-gate device is provided, comprising: a first complementary field effect transistor (CFET), comprising: a first lower transistor; and a first upper transistor overlapping the first lower transistor; a second CFET, comprising: a second lower transistor; and a second upper transistor overlapping the second lower transistor; a dielectric liner located in the middle between the first CFET and the second CFET, the dielectric liner comprising: an upper portion located between the first upper transistor and the second upper transistor; and a lower portion located between the first lower transistor and the second lower transistor; a through hole surrounded by the dielectric liner; a first contact plug above the through hole and connected to the through hole; and a second contact plug below the through hole and connected to the through hole.

[0005] According to another aspect of an embodiment of the present application, a multi-gate device is provided, comprising: a complementary field effect transistor (CFET), comprising: a lower transistor, the lower transistor comprising: a first gate stack; and a first gate spacer, on the sidewall of the first gate stack; and an upper transistor, overlapping with the lower transistor and comprising: a second gate stack; and a second gate spacer, on the sidewall of the second gate stack; a dielectric liner, comprising: an upper portion, contacting the first sidewall of the second gate spacer; and a lower portion, contacting the second sidewall of the first gate spacer; and a through hole, surrounded by the dielectric liner. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A perspective view of a complementary field effect transistor (CFET) and a through via is shown in accordance with some embodiments.

[0008] Figure 2-Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B and Figure 12-13 A diagram showing the formation of a CFET and a through-via in a monolithic CFET formation process according to some embodiments.

[0009] Fig.14 A through via extending laterally to the source / drain region of a CFET is shown in accordance with some embodiments.

[0010] Fig.15 , Fig.16A and Fig. 16B A view is shown of backside formation of a through via in accordance with some embodiments.

[0011] Figure 17-Figure 19 , Fig. 20A and Fig. 20B Illustrations showing formation of through vias from the front and back sides of respective wafers in accordance with some embodiments.

[0012] Figure 21-Figure 31 A diagram illustrating forming a CFET and a through-via in a parallel CFET formation process according to some embodiments.

[0013] Figure 32-Figure 39A diagram showing the formation of a CFET and a through-via in a sequential CFET formation process according to some embodiments.

[0014] Fig.40 A through-hole formed by a front-side formation process and a back-side formation process in a sequential formation process is shown in accordance with some embodiments.

[0015] Fig.41 A process flow for forming a through-via in a CFET is shown according to some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0018] A complementary field effect transistor (CFET) and a through hole for front and back side interconnection and a method for forming them are provided. According to some embodiments, a dielectric region is formed, which is sometimes referred to as a single diffusion break (SDB) region or a polycrystalline region cut on a diffusion edge. The SDB region is etched to form an opening therein, and the opening is subsequently filled to form a through hole that can be formed by metal. The through hole extends horizontally from the top surface of the top FET to the bottom level of the bottom FET, and can be used for electrical interconnection and signal interconnection between the front and back sides of the corresponding wafer. The embodiments discussed herein are intended to provide examples of the subject matter of the present disclosure that can be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of different embodiments. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0019] Figure 1 An example of a CFET 10 (including FETs (transistors) 10U and 10L) according to some embodiments is shown. Figure 1 It is a three-dimensional view, and some features of the CFET are omitted for ease of explanation. The CFET includes multiple vertically stacked FETs. For example, the CFET may include a lower nanostructure FET (transistor) 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type) opposite to the first device type. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 is used as a channel region of the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U.

[0020] The gate dielectric 88 surrounds the corresponding semiconductor nanostructure 26. The gate electrode 90 (including the lower gate electrode 90L and the upper gate electrode 90U) is formed on the gate dielectric 88. The source / drain region 62 (including the lower source / drain region 62L and the upper source / source region 62U) is disposed on opposite sides of the gate dielectric 88 and the corresponding gate electrode 90. Depending on the context, the source / drain region may be referred to as a source or a drain individually or collectively. Isolation features (not shown) may be formed to separate the desired source region in the source / drain region 62 and / or the desired gate electrode in the gate electrode 90. Figure 1 Further shown is a through-hole 84 formed inside the dielectric liner 80'. The through-hole 84 is conductive and may be formed of a metal or a metal alloy. The dielectric liner 80' may be external to the etched SDB region.

[0021] Figure 2-Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B and Figure 12-13 2 shows a cross-sectional view of an intermediate stage of forming a CFET and a through hole using an SDB process according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in process 200, as shown in FIG. Fig.41 The formation of the CFET according to these figures is referred to as a monolithic formation process because the formation of the upper FET and the lower FET can share multiple common formation processes. In the subsequent discussion, unless otherwise specified, a figure with a number followed by the letter "A" may illustrate a figure formed along the same Figure 1 A vertical cross-sectional view of a section similar to the vertical reference section A-A' in FIG. A figure followed by the letter "B" may illustrate a cross-sectional view similar to the vertical reference section A-A' in FIG. Figure 1 A cross-sectional view of a section similar to the vertical reference section BB'.

[0022] exist Figure 2 In the present invention, a wafer 2 including a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The SOI substrate may include a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. According to some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, a III-V compound semiconductor; or a combination thereof.

[0023] A multilayer stack 22 is formed over the substrate 20. Fig.41 As shown, the corresponding process is shown as process 202 in process flow 200. Multilayer stack 22 includes alternating dummy semiconductor layers 24 and semiconductor layers 26. Dummy semiconductor layers 24 include dummy semiconductor layers 24A and dummy semiconductor layers 24B. Semiconductor layer 26 includes lower semiconductor nanostructures 26L and upper semiconductor nanostructures 26U. Lower semiconductor nanostructures 26L and upper semiconductor nanostructures 26U are used to form lower FETs and upper FETs, respectively.

[0024] According to some embodiments, there is a bottom dummy semiconductor layer 24B (labeled as 24B1 for distinction) above and in physical contact with the semiconductor strip 20' as part of the substrate 20. According to alternative embodiments, the bottom dummy semiconductor layer 24B is not formed, and the semiconductor strip 20' can be in physical contact with the corresponding overlying dummy semiconductor layer 24A. Therefore, the bottom dummy semiconductor layer 24B1 is subsequently shown as a dotted line to indicate that these layers may or may not exist.

[0025] Appropriate well regions (not separately shown), such as p-well regions and n-well regions, may be formed in the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U. For example, the semiconductor nanostructures 26L and 26U may be in-situ doped (when epitaxially grown) and / or implanted to a desired conductivity type.

[0026] The dummy semiconductor layer 24A is formed of a first semiconductor material, and the dummy semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from the same group of candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etching selectivity to each other. In this way, in subsequent processes, the dummy semiconductor layer 24B can be removed at a faster rate than the dummy semiconductor layer 24A.

[0027] The semiconductor layer 26 (including the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U) is formed of one or more semiconductor materials. The semiconductor material may also be selected from the same group of candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U may be formed of the same semiconductor material, or may be composed of different semiconductor materials.

[0028] According to some embodiments, the dummy semiconductor layer 24A is formed of or includes silicon germanium, the semiconductor layer 26 is formed of silicon, and the dummy semiconductor layer 24B may be formed of germanium or silicon germanium with a higher atomic percentage of germanium than the dummy semiconductor layer 24A.

[0029] The multilayer stack 22 and substrate 20 are patterned to form semiconductor strips 28. Fig.41 As shown, the corresponding process is shown as process 204 in process flow 200. Each semiconductor strip 28 includes a semiconductor strip 20' (a portion of the original substrate 20) and a multilayer stack 22', which is the remaining portion of the multilayer stack 22. Hereinafter, the layers in the remaining portion 22' may be referred to as nanostructures. Etching may be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic. Pseudo semiconductor layer 24A and pseudo nanostructure 24B may be further collectively referred to as pseudo nanostructure 24.

[0030] The lower semiconductor nanostructure 26L will serve as the channel region of the lower nanostructure FET of the CFET. The upper semiconductor nanostructure 26U will serve as the channel region of the upper nanostructure FET of the CFET. The intermediate semiconductor nanostructure 26M is a semiconductor nanostructure 26 directly above / below (e.g., in contact with the pseudo nanostructure) the pseudo nanostructure 24B. The intermediate semiconductor nanostructure 26M can be used for isolation and may or may not be used as the channel region of the CFET. The pseudo nanostructure 24B will then be replaced by a dielectric isolation structure. The dielectric isolation structure and the intermediate semiconductor nanostructure 26M can define the boundaries of the lower nanostructure FET and the upper nanostructure FET.

[0031] Isolation regions 32 are formed above substrate 20 and between adjacent semiconductor strips 28. Fig.41 As shown, the corresponding process is shown as process 206 in process flow 200. The isolation region 32 may include a dielectric liner and a dielectric material above the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, etc., or a combination thereof. The formation of the isolation region 32 may include depositing a dielectric layer and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc. to remove excess portions of the dielectric material. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. According to some embodiments, the isolation region 32 includes silicon oxide formed by an FCVD process followed by an annealing process.

[0032] After the planarization process, the isolation region 32 is recessed. Some upper portions of the semiconductor strip 28 (including the multilayer stack 22') protrude higher than the remaining isolation region 32 to form a protruding fin 34. Fig.41 As shown, a corresponding process is also shown as process 206 in process flow 200 .

[0033] A dummy gate dielectric 36 is formed on the protruding fin 34. The dummy gate dielectric 36 may be formed or comprised of, for example, silicon oxide, silicon nitride, a combination thereof, and the like, and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 38 is formed on the dummy gate dielectric 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive, and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), and the like. One or more mask layers 40 are formed on the planarized dummy gate layer 38, and may include, for example, silicon nitride, silicon oxynitride, and the like.

[0034] Next, the mask layer 40 may be patterned by photolithography and etching processes to form a mask, and then the mask is used to etch and pattern the dummy gate layer 38, and possibly the dummy gate dielectric 36. The resulting structure is as shown in FIG. Figure 3 As shown, Figure 3 Shows Figure 2 The vertical cross section 3-3 in FIG. 3 is along the length direction of the semiconductor strip 28. The mask layer 40, the dummy gate layer 38 and the remaining portion of the dummy gate dielectric 36 form a dummy gate stack 42, as shown in FIG. Figure 3 As shown. Fig.41 As shown, a corresponding process is shown in process flow 200 as process 208 .

[0035] Then, gate spacers 44 are formed on the multilayer stack 22' and on the exposed sidewalls of the dummy gate stack 42. Fig.41 As shown, the corresponding process is shown as process 210 in process flow 200. Gate spacers 44 can be formed by conformally depositing one or more dielectric layers and then anisotropically etching the dielectric layers. Applicable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., which can be formed by deposition processes such as CVD, ALD, etc.

[0036] refer to Figure 4 , source / drain recesses 46 are formed in semiconductor strip 28. Fig.41 2 , the corresponding process is also shown as process 210 in process flow 200. Source / drain recesses 46 are formed by etching and may extend through multilayer stack 22' and into semiconductor strip 20'. The bottom surface of source / drain recesses 46 may be above, below, or flush with the top surface of isolation region 32 ( Figure 4 4. In the etching process, the gate spacers 44 and the dummy gate stack 42 mask portions of the semiconductor strips 28. The etching may include a single etching process or multiple etching processes. A timed etching process may be used to stop etching the source / drain recesses 46 when the source / drain recesses 46 reach a desired depth.

[0037] exist Figure 5 In the embodiment, an internal spacer 54 and a dielectric isolation layer 56 are formed. Fig.41 As shown, the corresponding process is shown as process 212 in process flow 200. The formation of the inner spacer 54 and the dielectric isolation layer 56 may include an etching process ( Figure 6 ).

[0038] The etching process may be isotropic and may be selective to the material of the dummy semiconductor layer 24A, so that the dummy semiconductor layer 24 is etched at a faster rate than the semiconductor nanostructures 26U and 26L. The etching process may also be selective to the material of the dummy nanostructure 24B, so that the dummy nanostructure 24B is etched at a faster rate than the dummy semiconductor layer 24A. In this way, the dummy nanostructure 24B may be completely removed while the dummy semiconductor layer 24A is laterally recessed.

[0039] According to some embodiments, wherein dummy nanostructure 24B is formed of germanium or silicon germanium having a high germanium atomic percentage, dummy semiconductor layer 24A is formed of silicon germanium having a low germanium atomic percentage, and semiconductor nanostructure 26 (including 26M, 26U, and 26L) is formed of silicon not containing germanium, the etching process may include a dry etching process with or without plasma using chlorine gas.

[0040] Since the dummy gate stack 42 is in contact with the sidewall of the semiconductor nanostructure 26 (see Figure 2 ), so the dummy gate stack 42 can support the upper semiconductor nanostructure 26U so that the upper semiconductor nanostructure 26U does not collapse when the dummy nanostructure 24B is removed. In addition, although the sidewalls of the dummy semiconductor layer 24A are shown as being straight after etching, the sidewalls may be concave or convex.

[0041] The internal spacer 54 is formed on the sidewall of the laterally recessed dummy semiconductor layer 24A, and the dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (commonly) and the lower semiconductor nanostructure 26L (commonly). In the subsequently formed source / drain region, the internal spacer 54 can act as an isolation component between the subsequently formed drain / source region and the subsequently formed gate structure. In addition, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain region by a subsequent etching process (e.g., an etching process for forming a gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (commonly) from the lower semiconductor nanostructure 26L (commonly). In addition, the intermediate semiconductor nanostructure 26M and the dielectric isolation layer 56 can define the boundary of the lower nanostructure FET and the upper nanostructure FET.

[0042] The internal spacer 54 and the dielectric isolation layer 56 can be formed by conformally depositing a dielectric insulating material in the source / drain recess 46 and between the upper and lower semiconductor nanostructures 26U and 26L, and then etching the insulating material. The insulating material can be a non-low-k dielectric material, which can be a carbon-containing dielectric material, such as silicon carbon nitride, silicon oxycarbide, silicon oxynitride, etc. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. After being etched, the insulating material has a portion remaining on the sidewall of the dummy semiconductor layer 24A (thereby forming the internal spacer 54), and has a portion remaining between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thereby forming the dielectric isolation layer 56).

[0043] refer to Figure 6 , forming a lower epitaxial source / drain region 62L. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. Fig.41 As shown, the corresponding process is shown as process 222 in process flow 200. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26L, but not the upper semiconductor nanostructure 26U. The inner spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy semiconductor layer 24A, which will be replaced with a replacement gate in a subsequent process.

[0044] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium doped with p-type dopants such as boron, indium, etc.

[0045] The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the upper semiconductor nanostructure 26U may be masked to prevent undesired epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U is removed.

[0046] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric (ILD) 68 are formed over the lower epitaxial source / drain regions 62L. Fig.41As shown, the corresponding process is shown as process 224 in process flow 200. The first CESL 66 can be formed of a dielectric material having a high etch selectivity to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD) or FCVD. Applicable dielectric materials of the first ILD 68 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0047] The formation process may include depositing a conformal CESL layer, depositing a material for the first ILD 68, followed by a planarization process, and then an etch-back process. According to some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After the recess, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0048] An upper epitaxial source / drain region 62U is then formed in the upper portion of the source / drain recess 46. Fig.41 As shown, the corresponding process is shown as process 226 in process flow 200. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U.

[0049] The conductivity type of the upper epitaxial source / drain region 62U can be opposite to the conductivity type of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped opposite to the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U can be doped in situ, and / or n-type or p-type dopants can be implanted. Adjacent upper source / drain regions 62U can remain separate or can be merged after the epitaxial process.

[0050] After forming the epitaxial source / drain regions 62U, the second CESL 70 and the second ILD 72 are formed. Fig.41As shown, each corresponding process is shown as process 228 in process flow 200. The materials and formation methods can be similar to the materials and formation methods of the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here. The formation process can include depositing layers for CESL 70 and ILD 72, and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process can remove the mask 40, or not remove the hard mask 40.

[0051] refer to Figure 7 , forming a hard mask 73 on top of the ILD 72. The formation process may include recessing the ILD 72 to form a recess, filling the recess with a dielectric material such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc. Then a planarization process is performed to remove excess portions of the dielectric material, leaving the hard mask 73.

[0052] Fig. 8A and FIG. 8B to FIG. 12 The through-holes 84 are shown formed from the front side of the corresponding wafer according to some embodiments. Fig. 8A and Figure 8B In the embodiment of the present invention, a trench 76 (also referred to as an opening) is formed between two adjacent source / drain regions 62 (including 62U and 62L). The trench 76 may alternatively be referred to as an SDB opening. Fig.41 As shown, a corresponding process is shown in process flow 200 as process 230 . Figure 8B Shows Fig. 8A 8B-8B in cross section. The trench 76 is formed by etching a portion of the dummy gate stack 42 and the lower portion of the multilayer stack 22'. Some portions of the multilayer stack 22' are active areas. The trench 76 extends into the semiconductor strip 20' and may penetrate the semiconductor strip 20'.

[0053] In order to form the groove 76, Fig. 8A and Figure 8B An etch mask 78 (which may include a patterned photoresist) is formed on the structure. The etch mask 78 is patterned and then the pattern is transferred to the underlying structure by an etching process to remove the underlying material and form the trench 76. The etching may include multiple etching processes for etching different materials.

[0054] The trench 76 is then filled with a dielectric material to form a dielectric region 80. The resulting structure is as shown in FIG. Fig. 9A and Fig. 9B As shown. The process of etching the dummy gate stack and the underlying active region and then forming the dielectric region 80 is also referred to as an SDB process. Therefore, the dielectric region 80 may also be referred to as an SDB region. Fig.41As shown, the corresponding process is shown as process 232 in process flow 200. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, boron nitride, combinations thereof, multilayers thereof, etc. The corresponding deposition process may be conformal or non-conformal, and may include CVD, ALD, PECVD, flowable chemical vapor deposition (FCVD), etc.

[0055] refer to Fig. 10A and Fig. 10B , the dielectric region 80 is etched to remove the middle portion, leaving an outer portion forming a ring, which is referred to as a dielectric liner 80'. Fig.41 As shown, the corresponding process is shown as process 234 in process flow 200. A trench 82 (also referred to as an opening) is thereby formed, and when viewed from the top, the dielectric liner 80' forms a complete ring around the trench 82. There is no break in the dielectric liner 80', so it can effectively isolate the subsequently formed through-hole 84 from the semiconductor nanostructures 26U and 26L. In order to form the trench 82, an etch mask 79 can be formed and patterned, and the etch mask is used to etch away the middle portion of the dielectric region 80.

[0056] According to some embodiments, the sidewall thickness of the dielectric liner 80' is between about 1 nm and 3 nm. It will be appreciated that the dielectric liner 80' cannot be too thick or too thin. If the thickness of the dielectric liner 80' is too small, for example less than 1 nm, there is a risk that the subsequently deposited conductive fill material may short-circuit with the gate electrode, semiconductor nanostructure, or source / drain region, or additional leakage paths may be created. If the sidewall thickness of the dielectric liner 80' is too large, for example greater than 3 nm, in subsequent processes, due to the high aspect ratio, it is difficult to fill the conductive fill material into the trench 82, and voids may be created in the resulting through-hole. The voids in the through-hole result in an unfavorable increase in the resistance of the through-hole.

[0057] exist Fig.11A and Fig. 11B In the process, a conductive filling material is deposited in the trench and then a planarization process is performed to make the top surface of the conductive filling material flush with the top surface of the mask 73 (or the dummy gate electrode 38 if present). A through hole 84 is thus formed between adjacent source / drain regions of two adjacent CFETs. Fig.41 As shown, the corresponding process is shown as process 236 in process flow 200. The conductive fill material can be formed of or include cobalt, tungsten, ruthenium, copper, molybdenum, etc. or alloys thereof. The conductive fill material can be deposited by any suitable process, such as physical vapor deposition (PVD), CVD, ALD, metal organic chemical vapor deposition, etc.

[0058] The resulting through-hole 84 may not be too wide or too narrow. If the conductive fill material is too narrow, the high aspect ratio may cause voids during deposition and cause the through-hole 84 to have too high a resistance. If the conductive fill material is too wide, it may encroach on adjacent conductive structures, such as subsequently formed gate electrodes or source / drain regions, and create a risk of short circuits or additional leakage paths. According to some embodiments, the width (from sidewall to sidewall) of the resulting through-hole 84 may be in a range between about 8 nm and 12 nm.

[0059] According to some embodiments, Fig.11A As shown, the sidewalls of dielectric liner 80' are in contact with the sidewalls of inner spacer 54 and nanostructures 26U and 26L, and may be in contact with the sidewalls of gate spacer 44. The width of the structure including dielectric liner 80' and through hole 84 may be the same as the width of dummy gate stack 42 (within process variation), or may be slightly larger than the width of dummy gate stack 42 due to consumption of gate spacer 44 in the etching process. According to these embodiments, gate spacer 44 is on the opposite side of dielectric liner 80' and in contact with dielectric liner 80'.

[0060] like Fig.11A and Fig. 11B The through hole 84 may have the shape of an elongated strip in a top view of the structure. According to some embodiments, the through hole 84 may also extend through a single or multiple multilayer stacks 22'.

[0061] It should be understood that because the dielectric liner 80' is formed by etching the dielectric region 80 (rather than by a conformal deposition process), the thickness of the dielectric liner 80' can be controlled, and different portions of the dielectric liner 80 can have different thicknesses from each other even if they are located at the same level. In addition, the thickness of the dielectric liner 80' in one cross section can be different from the thickness of the dielectric liner 80' in another cross section, even if they are measured at the same level. For example, Fig.11A The thickness T1 in may be different from Fig. 11B The thickness T2 may also be less than Fig. 11B This can minimize the difficulty of gap filling while minimizing the risk of electrical shorts and leakage.

[0062] In addition, since the dielectric liner 80' is formed by etching the dielectric region 80 instead of by a conformal deposition process, the thickness of the dielectric liner 80' at different levels may also be equal to or different from each other. Fig.11A In the embodiment, the top thickness T1, the middle thickness T1' and the bottom thickness T1" may be the same or different from each other. Fig. 11B In the embodiment, the top thickness T2, the middle thickness T2' and the bottom thickness T2'' can be the same as or different from each other.

[0063] According to an alternative embodiment, the formation of the dielectric liner 80' can be formed by a conformal deposition process (rather than by forming a COPDE region and then etching the COPDE region) to deposit a conformal dielectric liner 80' extending into the trench 76. A metal material is then deposited to fill the remaining trench 76. A planarization process is then performed to remove excess portions of the conformal dielectric liner 80' and excess portions of the metal material above the dummy gate stack 42. The resulting structure is substantially the same as Fig.12 The illustration is the same except that the conformal dielectric liner 80 ′ includes a portion directly beneath the through via 84 .

[0064] The Fig.11A and Fig. 11B The dummy gate stack 42 is shown, thereby forming a recess between the gate spacers 44 and extending to a level below the multilayer stack 22' ( Fig.11A , also refer to Figure 2 ). The sidewalls of the multilayer stack 22' are thus exposed, and the sidewalls of the nanostructures 26U and 26L and the dummy semiconductor layer 24A are exposed.

[0065] The dummy semiconductor layer 24A is then removed such that the recess extends laterally between the semiconductor nanostructures 26U and 26L. According to some embodiments, the dummy gate stack 42 and the dummy gate dielectric 36 are removed by an isotropic etching process. The dummy semiconductor layer 24A may be removed by any acceptable etching process that selectively etches the material of the dummy semiconductor layer 24 at a faster rate than the material of the semiconductor nanostructures 26, the internal spacers 54, and the isolation structures 56. The etching may be isotropic.

[0066] exist Fig.12 In the embodiment, a replacement gate stack 86 (including gate stacks 86U and 86L) is formed, which includes a gate dielectric 88 and a gate electrode 90 (also including gate electrodes 90U and 90L). Fig.41 As shown, the corresponding process is shown as process 238 in process flow 200. The gate dielectric 88 can be conformally formed on the channel region of the semiconductor nanostructure 26. Each gate dielectric 88 may include an interfacial layer (IL), which may be formed of an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, or the like, or include the above-mentioned materials. Each gate dielectric 88 may also include a high dielectric constant (high k) dielectric layer formed of a high k dielectric material having a k value greater than 3.9 and possibly greater than about 7.0. The high k dielectric material may include a metal oxide or metal nitride of a metal such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead. The formation method of the gate dielectric 88 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0067] Further references Fig.12 , the lower gate electrode 90L is formed on the gate dielectric 88. The lower gate electrode 90L is disposed between the lower semiconductor nanostructures 26L. Therefore, the lower gate electrode 90L also wraps around the lower semiconductor nanostructures 26L. The upper gate electrode 90U is formed on the gate dielectric 88. The upper gate electrode 90U is disposed between the upper semiconductor nanostructures 26U. Therefore, the upper gate electrode 90U also wraps around the upper semiconductor nanostructures 26U.

[0068] The lower gate electrode 90L and the upper gate electrode 90U may include an adhesion layer, a work function layer, a fill metal, etc. The material of the work function layer is selected based on the conductivity type of the corresponding FET. For example, for an n-type FET, an n-type work function material such as TiAl, TiAlN, etc. can be used to form the work function layer. For a p-type FET, a p-type work function material such as TiN can be used to form the work function layer. According to some embodiments, the upper gate electrode 90U can be recessed to form a recess between the opposing gate spacers 44, and then a dielectric material is filled into the recess to form a gate hard mask (not shown).

[0069] Fig.13 The formation of source / drain silicide regions 92 and source / drain contact plugs 94U are shown, which are formed on the upper source / source region 62U. A front side dielectric layer 103 is formed, which may include an etch stop layer, an interlayer dielectric (ILD), etc. Contact plugs / vias 96 and 98 are formed in the dielectric layer 103 and are electrically connected to the through hole 84, the source / drain contact plugs 94U and the gate electrode 90U. Fig.41 As shown, a corresponding process is shown in process flow 200 as process 240 .

[0070] Next, the substrate 20 is removed by, for example, etching, CMP, etc. Fig.12 ). The bottom end of the through hole 84 is exposed. According to some embodiments, Fig.13 As shown, the substrate 20 is completely removed. According to an alternative embodiment, the substrate 20 is thinned but not completely removed. Subsequently, a backside dielectric layer 105 is formed. The backside contact plug 102 is formed to penetrate the backside dielectric layer 105 and connect to the through hole 84. Fig.41 As shown, the corresponding process is shown as process 242 in process flow 200. Electrical connection to lower source / drain region 62L may be achieved through backside contact plug 104, which is formed in backside dielectric layer 105 according to some embodiments.

[0071] Thus, a lower nanostructure FET 10L and an upper nanostructure FET 10U are formed, and together they form a CFET 10. Fig.13 In the example shown, two CFETs are formed on opposite sides of a through hole 84. In a corresponding structure, the through hole 84 utilizes the space used by the SDB area to form the through hole 84. The through hole 84 can be used for front and back signal routing, power supply (VDD and / or VSS), etc. Therefore, the space used to electrically isolate adjacent CFETs is also used for signal and electrical interconnection. Since the interconnection is formed in close proximity to the CFET, the corresponding front and back interconnect lines including the through hole 84 are short and therefore have low resistance.

[0072] Fig.14 , Fig.15 , Fig.16A and Fig. 16B , Figure 17-Figure 19 , Fig. 20A and Fig. 20B , Figure 21-Figure 31 and Figure 32-Figure 39 A cross-sectional view of an intermediate stage in the formation of a CFET and a via according to an alternative embodiment of the present disclosure is shown. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components represented by the same reference numerals in the previous embodiments. Details on materials, structures, and formation processes provided in any embodiment described throughout can be applied to any other embodiment.

[0073] Fig.14 A structure according to an alternative embodiment is shown. Fig.14 The structure shown in Fig.13 The structure shown in FIG. 1 is substantially the same except that the dielectric liner 80 ′ formed using the SDB process is laterally extended to contact one or both of the source / drain regions 62U and / or to contact one or both of the source regions 62L and 62U. According to some embodiments, the dielectric liner 80 ′ may also contact the CESL 70 and 66 .

[0074] The formation process of this structure can be basically the same as that in the above-mentioned embodiment, except that Fig.14 In the process shown, the corresponding etching mask used to form the trench 76 has a larger opening, and some of the top surfaces of the gate spacers 44 are also exposed through the opening. As a result, the corresponding trench 76 is wider, and the through hole 84 can be formed wider. According to some embodiments, the width (sidewall to sidewall) of the through hole 84 is in the range between about 15nm and about 69nm. Fig.14 In some embodiments shown, the dielectric liner 80 ′ may contact the sidewalls of the vertical portions of the CESL 70 .

[0075] In the front-side discussed embodiment, the through-vias 84 are formed from the front side of each wafer. Fig.15 , Fig.16A and Fig. 16BAn embodiment is shown in which the through-holes 84 are formed from the back side of the corresponding wafer. The initial process of these embodiments is basically the same as Figures 2 to 9A and Fig. 9B , and the dielectric region 84 has been formed from the front side of the corresponding wafer, as shown Fig. 9A and Fig. 9B Next, the dummy gate stack 42 and the dummy semiconductor layer 24A are removed. Fig. 9A ), and then forming a replacement gate stack 86. The resulting structure is as shown Fig.15 In the subsequent process, Fig.15 As shown, a front side dielectric layer 103 and contact plugs 96 and 98 are formed.

[0076] Next, the substrate 20 is removed (see Fig. 9A ), and some backside components, such as dielectric layer 105 and contact plug 104 ( Fig.15 According to an alternative embodiment, contact plugs 104 may not be formed. Dielectric layer 105 is planarized from the back side of the wafer (bottom side shown) until dielectric region 80 is exposed from the back side of the respective wafer, the dielectric region 80 being substantially aligned with the dielectric region 80. Fig. 9A Same as shown.

[0077] In subsequent processes, such as Fig.15 As shown, dielectric region 80 (SDB region) is etched from the back side of the corresponding wafer, forming trench 82. Front side dielectric layer 103 and contact plug 96 are exposed to trench 82 and may serve as an etch stop layer according to some embodiments.

[0078] refer to Fig.16A , the trench 82 is filled with a dielectric material to form a through hole 84. Next, according to some embodiments, some additional dielectric layers 105 and conductive features such as conductive plugs 102 may be formed on the back side of the corresponding wafer.

[0079] Fig. 16B Shows Fig.16A It can be understood that when the groove 76 is formed from the front side of the corresponding wafer, as shown in FIG. Figure 8B As shown, the groove 76 may be tapered, with the upper portion becoming wider than the lower portion. The actual taper may be less than Figure 8B The tapered profile of the trench 76 causes the outer profiles of the dielectric region 80 and the dielectric liner 80' to also be tapered, with the upper portion gradually becoming wider than the lower portion. The final profile of the dielectric liner 80' is as shown in FIG. Fig. 16B shown.

[0080] However, the dielectric region 80 ( Fig.15 ) is etched from the back side of the corresponding wafer. Fig.15The groove 82 in the embodiment may be tapered, with the lower portion becoming wider than the corresponding upper portion. This results in the through hole 84 also being tapered, such as Fig. 16B As shown, the lower portion is increasingly wider than the corresponding upper portion. Therefore, the upper portion of the dielectric liner 80' is also increasingly thicker than the corresponding lower portion. According to some embodiments, the inner and outer sidewalls of the dielectric liner 80' are straight and slope in opposite directions.

[0081] Figure 17-Figure 19 , Fig. 20A and Fig. 20B An embodiment is shown in which through-holes 84 are formed from the front and back sides of the respective wafers. The initial process of these embodiments is substantially the same as Figures 2 to 9A and Fig. 9B The same as shown in FIG. Then, a replacement gate stack is formed to replace the dummy gate stack. The resulting structure is as shown in FIG. Fig.17 Source / drain silicide regions 92 and source / drain contact plugs 94U are also formed.

[0082] Next, further reference Fig.17 , forming an etching mask 79A, and etching from the front side of the corresponding wafer Fig. 9A The substantially same dielectric region 80 is etched to form a trench 82A in the dielectric region 80. The etch mask 79A is then removed. A dielectric liner portion 80A is thereby formed, which is a portion of the remaining dielectric region 80 surrounding the trench 82A.

[0083] Next, refer to Fig.18 , trench 82A is filled with a conductive material to form a through-hole portion 84A, which is then planarized so that its top surface is coplanar with the top surface of gate spacer 44. A dielectric layer 103 is then formed on the front side of the structure as shown. According to some embodiments, contact plugs 96 and 98 are also formed to connect to through-hole portion 84A and source / drain contact plugs 94U and gate electrode 90U.

[0084] Next, the substrate 20 and the semiconductor strips 20' are removed, and a dielectric layer 105 is formed on the back side of the corresponding wafer. Fig.19 According to some embodiments, Fig.19 As shown, substrate 20 is completely removed. According to alternative embodiments, substrate 20 is thinned but not completely removed. According to some embodiments, silicide regions and backside source / drain contact plugs 104 may be formed to connect to lower source / drain regions 62L.

[0085] Then, an etching mask 79B is formed on the back side of the corresponding wafer, and the dielectric region 80 is etched from the back side of the corresponding wafer, thereby forming a trench 82B in the dielectric region 80. Then, the etching mask 79B is removed. Thus, a dielectric liner portion 80B is formed, which is a portion of the dielectric region 80 surrounding the trench 82B.

[0086] The dielectric liner portions 80A and 80B together form a dielectric liner 80'. The material of the dielectric liner portions 80A and 80B is the remainder of the same dielectric region 80, so there is no distinguishable interface separating the dielectric liner portion 80A from the dielectric liner portion 80B. On the other hand, since the dielectric liner portions 80A and 80B are formed from the front sides of the opposite sides of the corresponding wafers by different etching processes and using different etching masks, the bonding area 81 where the dielectric liner portion 80 is bonded to the dielectric liner portion 80B can have different thicknesses. In addition, in the bonding area 81, there may be a sudden thickness change. The bonding area 81 of the dielectric liner portions 80A and 80B can therefore be distinguishable. It should be understood that the bonding area 81 shown is part of the annular bonding area.

[0087] Fig. 20A The groove 82B ( Fig.19 ) is filled to form a through-hole portion 84B. The through-hole portion 84A is joined to the through-hole portion 84B and together forms the through-hole 84. According to some embodiments, the through-hole portions 84A and 84B may be formed of the same or different conductive (metal) materials, which may be selected from metals such as Co, W, Ru, Cu, Mo, Ni and alloys thereof. The through-hole portions 84A and 84B may therefore be distinguished from each other or not. On the other hand, the joining region 81 of the through-hole portions 84A and 84B may also be found from the thickness variation from the dielectric liner portion 80A to the dielectric liner portion 80B, so that the joining region 81 between the through-hole portions 84A and 84B may be determined. In a subsequent process, a contact plug 102 may be formed to connect to the through-hole 84 from the back side. A dielectric layer 105 may also be formed, wherein the contact plug 102 is formed in the dielectric layer 105.

[0088] Fig. 20B According to some embodiments Fig. 20A It can be understood that when the groove 76 is formed from the front side of the corresponding wafer, as shown in FIG. Figure 8B As shown, the trench 76 may be tapered, with the upper portion becoming wider than the lower portion. However, for the dielectric region 80 ( Fig.15 ) is etched from the front and back sides of the corresponding wafer. Fig.17 The groove 82A in the embodiment may be tapered, with the upper portion becoming wider than the corresponding lower portion. This results in the through hole portion 84A being tapered, such as Fig. 20B As shown, the lower portion is increasingly narrower than the corresponding upper portion.

[0089] on the other hand, Fig.19 The trench 82B in the through hole 84B is formed by etching the dielectric region 80 from the back side of the corresponding wafer. Therefore, the trench 82B can be tapered, wherein the lower portion is increasingly wider than the corresponding upper portion. This results in the through hole portion 84B being tapered, such as Fig. 20B As shown, the lower portion is wider and wider than the corresponding upper portion. In addition, the dielectric liner portion 80B can also have an upper portion that is thicker and thicker than the corresponding lower portion. On the other hand, the dielectric liner portion 80A can have a smaller difference between the upper portion and the lower portion than the dielectric liner portion 80B. The upper portion and the lower portion of the dielectric liner portion 80A can also have the same thickness (within the process variation range).

[0090] According to some embodiments, the interface between the through-hole portion 84A and the dielectric liner portion 80A is straight, and the interface between the through-hole portion 84B and the dielectric liner portion 80B is also straight. There is an abrupt thickness change in the region 81. In addition, a step may be formed, which includes a sidewall of the dielectric liner portion 80A, a sidewall of the dielectric liner portion 80B, and a top surface connecting the sidewall of the dielectric liner portion 80A to the sidewall of the dielectric liner portion 80B.

[0091] It should be understood that since the dielectric liner 80' is formed by etching the dielectric region 80, the thickness of the dielectric liner 80' can be controlled, and the thickness of different portions thereof can be different from each other even if they are measured at the same level. In addition, the thickness of the dielectric liner 80' in one cross section can be different from the thickness of the dielectric liner 80' in another cross section even if they are measured at the same level. The thickness difference can be substantially the same as Fig.11A The thicknesses T1, T1' and T1" and Fig. 11B The thicknesses T2, T2' and T2" are the same and can be obtained from Fig.11A The thicknesses T1, T1' and T1" and Fig. 11B The thickness difference can be understood by referring to the discussion of thickness T2, T2' and T2" in the figure.

[0092] Figure 21 to Figure 31 A cross-sectional view of a CFET and a through-hole formation according to an alternative embodiment is shown. The corresponding formation process of the CFET is also referred to as a parallel formation process. Figure 21-25 The formation of the upper wafer 110 and the upper FET 10U in the upper wafer 110 according to some embodiments is shown. A brief formation process will be discussed below. It should be understood that some details of the various processes may be different from Figures 1 to 13 The discussion of the embodiment shown is the same as that of Figures 1 to 13 These details are implemented in the discussion of the illustrated embodiments and therefore are not discussed here.

[0093] refer to Fig.21 , forming an upper wafer 110U. A multilayer stack 22' is formed. Fig.21 The multilayer stack 22' shown may be used with Figure 3 The upper portion of the multilayer stack 22' shown is substantially identical, with the upper portion being higher than the Figure 3 Therefore, Fig.21 The formation process of the structure shown may be similar to that of reference Figure 2 and Figure 3 The discussion is essentially the same, except Figure 3 The lower portion of the multilayer stack 22' is not Fig.21 In addition, the plurality of bands (similar to Figure 2 parallel and close to each other.

[0094] Further references Fig.21 , forming a plurality of dummy gate stacks 42, each dummy gate stack 42 including a dummy gate dielectric 36, a dummy gate electrode 38, and possibly one or more mask layers 40. The plurality of dummy gate stacks 42 are also formed as a plurality of strips having a longitudinal direction perpendicular to the longitudinal direction of the multilayer stack 22'. In addition, the plurality of dummy gate stacks 42 are formed on the top surface (eg, Fig.21 as shown) and sidewalls (as Figure 2 Then, a gate spacer 44 is formed on the sidewall of the dummy gate stack 42. Fig.21 As shown, the pseudo semiconductor layer 24A and the semiconductor nanostructure 26U are respectively Figure 2 and Figure 3 The dummy semiconductor layer 24 and the semiconductor nanostructure 26U discussed are substantially the same and the details are not repeated here.

[0095] Next, if Fig. 22 As shown, the multilayer stack 22' is etched using the dummy gate stack 42 and the gate spacer 44 as an etching mask to form a recess 46. The recess 46 may extend to a level lower than the bottom of the multilayer stack 22'. An internal spacer 54 is formed by the recess 46. The formation of the internal spacer 54 may include an etching process that laterally etches the dummy semiconductor layer 24A ( Figure 6 ) to form a lateral recess, depositing a dielectric layer to fill the recess, and etching the dielectric layer to remove the portion of the dielectric layer outside the lateral recess. The portion of the dielectric layer remaining in the lateral recess forms an internal spacer 54.

[0096] refer to Fig.23, forming the upper source / drain region 62U. The formation process is substantially the same as discussed in the previous embodiment and is not repeated here. Next, CESL 70 and ILD 72 are formed to fill the remaining portion of recess 46 ( Fig. 22 ).

[0097] Fig.24 The formation of a replacement gate stack 86U is shown, which includes a gate dielectric 88 and a gate electrode 90U. The formation process may include removing the dummy gate stack 42, removing the dummy semiconductor layer 24A, and forming a gate dielectric 88 and a gate electrode 90U filling the corresponding recess. The details of the formation process are not repeated here, and can be implemented by the discussion of the previous embodiment. Thus, the upper nanostructure FET 10U is formed.

[0098] refer to Fig.25 , the gate contact plug 116 and the source / drain contact plug 118 are formed to be electrically coupled to the gate electrode 90U and the upper source / drain region 62U, respectively. A silicide region (not shown) may also be formed on the top surface of the upper source / drain region 62U. An etch stop layer 112, an ILD 114, and a bonding layer 120U are also formed. The bonding layer 120U may be formed of or include a silicon-containing dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon oxynitride, etc. A bonding pad 124U is also formed to be electrically coupled to the contact plugs 116 and 118. According to some embodiments, the top surfaces of the bonding pad 124U and the bonding layer 120U may be coplanar by a planarization process such as a CMP process or a mechanical grinding process.

[0099] Fig.26 A lower wafer 110L and the formation of lower nanostructure FETs 10L in the lower wafer 110L are shown in accordance with some embodiments. The upper nanostructure FET 10U and the lower nanostructure FET 10L have opposite conductivity types, one of which is an n-type FET and the other is a p-type FET. The formation process of the lower nanostructure FET 10L may be substantially the same as the formation process of the upper nanostructure FET 10U, wherein the materials (e.g., source / drain regions and work function layers) are selected to be appropriate for the conductivity type of the lower nanostructure FET 10L. Components in the lower wafer 110L are denoted using the same reference numerals as corresponding components in the upper wafer 110U, except that some components may be followed by the letter "L" (rather than the letter "U") to indicate that they are components in the lower wafer 110L.

[0100] Fig. 27The bonding of the upper wafer 110U to the lower wafer 110L is shown. The bonding may be performed by hybrid bonding, where the bonding pads 124U in the upper wafer 110U are bonded to the bonding pads 124L in the lower wafer 110L, and the dielectric layer 120U in the upper wafer 110U is bonded to the dielectric layer 120L in the lower wafer 110L. Thus, the upper nanostructure FET 10U is electrically connected to the lower nanostructure FET 10L.

[0101] Next, the substrate 20 in the upper wafer 110U is removed, for example, by etching. A dielectric layer 101U is then formed and planarized to form a flat top surface. The resulting structure is as shown in FIG. Fig.28 According to an alternative embodiment, the substrate 20 in the upper wafer 110U is thinned (but not completely removed) by, for example, a CMP process or a mechanical grinding process.

[0102] The gate stack 86U between two adjacent source / drain regions 62U, the gate stack 86L between two adjacent source / drain regions 62L, the nanostructures 26U and 26L, and some dielectric layers are then etched to form trenches 76 extending from the dielectric layer 101U to the semiconductor strip 20' in the lower wafer 110L. The etching includes multiple anisotropic etching processes to etch different materials.

[0103] refer to Fig.29 According to some embodiments, a dielectric liner 80' and a through hole 84 are formed. The formation process also includes filling the trench 76 with a dielectric material and performing a planarization process to form a dielectric region (SDB region). The details of the dielectric region can refer to the embodiment of the front side. The dielectric region is then etched, and then a conductive material is filled into the corresponding opening to form a through hole 84.

[0104] refer to Fig.30 , a backside dielectric layer 105U is formed, and may include an etch stop layer and an ILD. A backside contact plug 102U is formed to penetrate the backside dielectric layer 105U. The dielectric layer 105U and the contact plug 102U are referred to as backside components because they are on the backside of the upper wafer 110U.

[0105] Fig.31 The substrate 20 ( Fig.30 ), and forming a backside dielectric layer 105L and contact plugs 102L on the backside of the lower wafer 110L. According to some embodiments, as Fig.31As shown, the substrate 20 in the lower wafer 110L is completely removed. According to an alternative embodiment, the substrate 20 in the lower wafer 110L is thinned but not completely removed. The through-hole 84 electrically connects the contact plug 102U to the back contact plug 102L. The contact plugs 102U and 102L can be further connected to signal lines, power lines, etc. for electrical interconnection and signal interconnection. In the resulting structure, the lower nanostructure FET 10L and the upper nanostructure FET 10U are bonded in a face-to-face manner.

[0106] exist Fig.29 and Fig.30 In the illustrated embodiment, the through-holes 84 are formed from the back side of the upper wafer 110U. According to an alternative embodiment, the through-holes 84 may be formed from the back side of the lower wafer 110L. According to another alternative embodiment, the through-holes 84 may be formed from both the back side of the upper wafer 110U and the back side of the lower wafer 110L. Details of the resulting dielectric liner 80' and through-holes 84 may be found in the discussion of the front side embodiment, including Fig.11A , Fig. 11B , Fig. 16B and Fig. 20B Discussion.

[0107] Figure 32 to Figure 39 A cross-sectional view of a CFET and a through hole formation according to an alternative embodiment is shown. The corresponding formation process of the CFET is also referred to as a sequential formation process. In these embodiments, the lower nanostructure FET 10L is formed first, and then the upper nanostructure FET 10U is formed on the already formed lower nanostructure FET 10L. A brief formation process will be discussed below. It should be understood that the details of the multiple processes according to these embodiments may be the same as the discussion of the embodiments on the front side, or may be implemented from the discussion of the embodiments on the front side, and therefore these details may not be repeated here.

[0108] refer to Fig.32 , forming the lower wafer 110L. Fig.32 The formation process of the structure shown can be compared with that of Fig.24 The formation of the upper wafer 110U shown is substantially the same as discussed above, and the formation process is also referred to as Figure 2 and Figure 3 110L and includes a gate stack 86L including a replacement gate dielectric 88 and a replacement gate electrode 90L. The gate stack 86L extends into the space between adjacent semiconductor nanostructures 26U.

[0109] like Fig.32As shown, a bonding layer 124L is formed. According to some embodiments, the bonding layer 124L is formed by a deposition process such as CVD, ALD, PECVD, etc. A planarization process may be performed to flatten the top surface of the bonding layer 124L. The bonding layer 124L may be formed of or include a silicon-containing dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxynitride, etc.

[0110] Next, if Fig.33 As shown, a multilayer stack 22' is formed and bonded to the lower wafer 110L below through a bonding layer 124U. The bonding layer 124U may also be formed of or include a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon, silicon oxynitride, etc. The multilayer stack 22' may be bonded to the lower wafer 110L below. Fig.21 The upper portion of the multilayer stack shown is substantially identical and is higher than Figure 3 The top layer in the multilayer stack 22' may be a semiconductor nanostructure 26U, which may be formed of silicon. The bottom layer in the multilayer stack 22' may be a dummy semiconductor layer 24A, which may be formed of silicon germanium.

[0111] According to some embodiments, the formation and bonding of the bonding layer 124U and the multilayer stack 22' may include forming alternating layers of semiconductor nanostructures 26U and dummy semiconductor layers 24A on a semiconductor substrate, and depositing the bonding layer 124U on the multilayer stack 22'. The alternating layers of semiconductor nanostructures 26U and dummy semiconductor layers 24A are epitaxially grown in multiple epitaxial processes, each of which forms one of the semiconductor nanostructures 26 and dummy semiconductor layers 24A. The resulting structure is referred to as an upper wafer 110U. The upper wafer 110U is then bonded to the lower wafer 110L by bonding the bonding layer 124U to the bonding layer 124L.

[0112] According to an alternative embodiment, instead of pre-forming the upper wafer 110U and bonding the upper wafer 110U to the lower wafer 110L, a bonding layer 124U is first formed on a semiconductor layer (not shown), which may be a silicon germanium layer. The bonding layer 124U is then bonded to the bonding layer 124L in the lower wafer 110L together with the overlying semiconductor layer. The semiconductor layer is then thinned to a desired thickness to form a bottom dummy semiconductor layer 24A. Alternating layers of semiconductor nanostructures 26U and dummy semiconductor layers 24A are then epitaxially grown on the bottom dummy semiconductor layer 24A.

[0113] Further references Fig.33, forming a plurality of dummy gate stacks 42, each dummy gate stack 42 including a dummy gate dielectric 36, a dummy gate electrode 38, and possibly one or more mask layers 40. The plurality of dummy gate stacks 42 are also formed as a plurality of strips having a longitudinal direction perpendicular to the longitudinal direction of the multilayer stack 22'. In addition, the plurality of dummy gate stacks 42 are formed on the top surface (eg, Fig.33 as shown) and sidewalls (as Figure 2 Then, a gate spacer 44 is formed on the sidewall of the dummy gate stack 42.

[0114] Next, if Fig.34 As shown, the internal spacer 54, the source / drain region 62U, the CESL 70, and the ILD 72 are formed. The formation process may include anisotropically etching the multilayer stack 22' from the opening until the bonding layer 124U is exposed. Then, the internal spacer 54 is formed by laterally recessing the dummy semiconductor layer 24A to form a lateral recess and filling the lateral recess with a dielectric material. Then, the source / drain region 62U is formed, followed by the CESL 70 and the ILD 72.

[0115] refer to Fig.35 , remove Fig.34 The dummy gate stack 42 shown forms a replacement gate stack 86U and extends to the space between adjacent semiconductor nanostructures 26U. The formation of the gate stack 86U is not discussed in detail here and can be found in the discussion of the previous embodiment. The upper transistor 10U is thus formed. The lower nanostructure FET 10L and the upper nanostructure FET 10U together form the CFET 10. Throughout the description, the components above the bonding layer 124L are collectively referred to as the upper wafer 110U.

[0116] refer to Fig.36 , the gate stack 86U (including the gate electrode 90U) between two adjacent source / drain regions 62U, two adjacent gate stacks 86L (including the gate electrode 90L) between two adjacent source / drain regions 62L, and the overlying and underlying structures of the gate stacks 86U and 86L are etched to form a trench 76. The trench 76 extends from the top surface of the ILD 72 to the semiconductor strip 20' in the lower wafer 110L. The etching includes multiple anisotropic etching processes, in which the sidewalls of the upper wafer 110U and the lower wafer 110L facing the trench 76 are straight (in process variations).

[0117] Next, if Fig.37 As shown, a dielectric liner 80' and a through hole 84 are formed in the trench 76. The formation process also includes filling the dielectric material into the opening and performing a planarization process to form a dielectric region (SDB region). The dielectric region is then etched, and then a conductive material is filled into the corresponding opening to form the through hole 84.

[0118] Fig.38 The formation of an etch stop layer 112, an ILD 114, and front side contact plugs 96, 116, and 118 is shown. The front side contact plugs 96, 116, and 118 extend into the etch stop layer 112 and the ILD 114. The contact plugs 96, 116, and 118 are connected to the through via 84, the gate electrode 90U, and the source / drain region 62U, respectively. A source / drain silicide layer (not shown) may be formed on the source / drain region.

[0119] It should be understood that since the dielectric liner 80' is formed by etching the dielectric region 80, the thickness of the dielectric liner 80' can be controlled, and the thicknesses of different portions thereof may be different from each other even if they are measured at the same level. In addition, even if they are in the same cross section, the thicknesses of the dielectric liner 80' measured at different levels may be different from each other.

[0120] Next, according to some embodiments, the substrate 20 in the lower wafer 110L is removed, for example, by etching, CMP, etc. The resulting structure is as follows: Fig.39 As shown. The bottom end of the through hole 84 may be exposed. According to some embodiments, as Fig.39 As shown, the substrate 20 in the lower wafer 110L is completely removed. According to an alternative embodiment, the substrate 20 is thinned but not completely removed.

[0121] Subsequently, a backside etch stop layer 112 and a dielectric layer 105 are formed, such as Fig.39 The backside contact plug 102 may penetrate the etch stop layer 112 and the backside dielectric layer 105 and be connected to the through hole 84 .

[0122] exist Fig.36 and Fig.37 In the illustrated embodiment, the through-holes 84 are formed from the front side of the upper wafer 110U. According to an alternative embodiment, the through-holes 84 may be formed from the back side of the lower wafer 110L. According to yet another alternative embodiment, the through-holes 84 may be formed from both the front side of the upper wafer 110U and the back side of the lower wafer 110L. Details of the resulting dielectric liner 80' and through-holes 84 may be found in the discussion of the front side embodiment, including Fig.11A , Fig. 11B , Fig. 16B and Fig. 20B Discussion.

[0123] Fig.40An alternative embodiment is shown in which the through-hole 84 is formed from the front side and the back side of the respective composite wafers including the upper wafer 110U and the lower wafer 110L. Therefore, the dielectric liner 80' includes a portion 80A formed from the front side of the upper wafer 110U and a portion 80B formed from the back side of the lower wafer 110L. In addition, the through-hole 84 includes a portion 84A formed from the front side and a portion 84B formed from the back side. Fig. 20B Cross-sectional views of dielectric liner 80 ′ and details of through-hole 84 may be found in conjunction with the corresponding discussion.

[0124] Embodiments of the present disclosure have some advantageous features. The SDB region can be formed to isolate active regions, such as semiconductor fins or semiconductor nanostructures of adjacent FETs. According to some embodiments, the middle portion of the SDB region is removed using etching, and the resulting trench is filled with a metal material, while a through hole is formed inside the SDB region. The remaining portion of the SDB region surrounds the through hole and serves to isolate the through hole from the CFET. Therefore, the chip area occupied by the SDB region is well utilized.

[0125] According to some embodiments of the present disclosure, a method includes forming a first CFET, the first CFET including a first lower transistor and a first upper transistor overlapping the first lower transistor; forming a second CFET, the second CFET including a second lower transistor and a second upper transistor overlapping the second lower transistor; performing a first etching process to form a first opening, wherein the first etching process includes: etching a gate stack between the first CFET and the second CFET; and etching a plurality of alternating structures vertically aligned with the gate stack; filling the first opening with a dielectric material to form a dielectric region; performing a second etching process to etch a middle portion of the dielectric region and to form a second opening; and filling the second opening with a conductive material to form a through hole.

[0126] In one embodiment, the method further includes: forming a first contact plug above the through hole; and forming a second contact plug below the through hole, wherein the first contact plug is electrically connected to the second contact plug through the through hole. In one embodiment, at a time after the second etching process, the remaining portion of the dielectric region surrounds the second opening. In one embodiment, the first etching process is performed from the front side of the corresponding wafer including the first CFET and the second CFET. In one embodiment, the first etching process is performed from the back side of the corresponding wafer including the first CFET and the second CFET. In one embodiment, a third etching process is performed from the front side of the corresponding wafer including the first CFET and the second CFET; and a fourth etching process is performed from the back side of the corresponding wafer.

[0127] In one embodiment, the method further comprises, after the third etching process and before the fourth etching process, filling a first portion of a second opening formed by the third etching process with a first portion of a conductive material; and after the fourth etching process, filling a second portion of the second opening formed by the fourth etching process with a second portion of a conductive material. In one embodiment, the dielectric region penetrates some remaining portions of the stacked layers and contacts sidewalls of some remaining portions of the stacked layers, and wherein the stacked layers comprise: a plurality of semiconductor layers formed of a first material; and a plurality of dielectric internal spacers, wherein the plurality of semiconductor layers and the plurality of dielectric internal spacers are alternately positioned.

[0128] In one embodiment, the dielectric region includes a first sidewall that physically contacts a second sidewall of a source / drain region of one of the first lower transistor and the first upper transistor. In one embodiment, the first lower transistor and the first upper transistor are formed by a monolithic formation process. In one embodiment, the first lower transistor and the first upper transistor are formed by a process comprising the steps of: forming the first lower transistor in a first wafer; forming the first upper transistor in a second wafer; and bonding the first wafer to the second wafer, wherein a first etching process is performed after bonding. In one embodiment, the first upper transistor is formed after forming the first lower transistor, and the dielectric region is formed after forming the first upper transistor.

[0129] According to some embodiments of the present disclosure, a structure includes a first CFET, which includes a first lower transistor and a first upper transistor overlapping the first lower transistor; a second CFET, which includes a second lower transistor and a second upper transistor overlapping the second lower transistor; a dielectric liner located in the middle between the first CFET and the second CFET, the dielectric liner including an upper portion located between the first upper transistor and the second upper transistor and a lower portion located between the first lower transistor and the second lower transistor; a through hole surrounded by the dielectric liner; a first contact plug above the through hole and connected to the through hole; and a second contact plug below the through hole and connected to the through hole.

[0130] In one embodiment, the structure further comprises: a plurality of semiconductor layers; and a plurality of internal spacers separating the plurality of semiconductor layers, wherein the dielectric liner contacts a sidewall of each of the plurality of semiconductor layers and the plurality of internal spacers. In one embodiment, one of the first lower transistor and the first upper transistor comprises a source / drain region, and the source / drain region physically contacts a sidewall of the dielectric liner. In one embodiment, the dielectric liner becomes thinner from the top to the bottom of the dielectric liner. In one embodiment, in a middle portion of the dielectric liner, the thickness of the dielectric liner has an abrupt change.

[0131] According to some embodiments of the present disclosure, a structure includes a CFET, the CFET including a lower transistor, the lower transistor including a first gate stack and a first gate spacer on a sidewall of the first gate stack; and an upper transistor overlapping the lower transistor, the upper transistor including a second gate stack and a second gate spacer on a sidewall of the second gate stack; a dielectric liner including an upper portion of a first sidewall contacting the second gate spacer and a lower portion of a second sidewall contacting the first gate spacer; and a through hole surrounded by the dielectric liner. In one embodiment, the structure also includes an additional CFET, the additional CFET including an additional gate spacer, wherein the dielectric liner is further in physical contact with an additional sidewall of the additional gate spacer. In one embodiment, a middle portion of the dielectric liner has an abruptly changing thickness.

[0132] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a multi-gate device, comprising: forming a first complementary field effect transistor, the first complementary field effect transistor comprising: a first lower transistor; and a first upper transistor overlapping the first lower transistor; forming a second complementary field effect transistor, the second complementary field effect transistor comprising: a second lower transistor; and a second upper transistor overlapping the second lower transistor; Performing a first etching process to form a first opening, wherein the first etching process includes: etching a gate stack between the first complementary field effect transistor and the second complementary field effect transistor; and etching a plurality of alternating structures vertically aligned with the gate stack; filling the first opening with a dielectric material to form a dielectric region; performing a second etching process to etch a middle portion of the dielectric region and form a second opening; and The second opening is filled with a conductive material to form a through hole.

2. The method according to claim 1, further comprising: forming a first contact plug on the through hole; as well as A second contact plug is formed under the through-hole, wherein the first contact plug is electrically connected to the second contact plug through the through-hole.

3. The method according to claim 1, wherein: At a time after the second etching process, a remaining portion of the dielectric region surrounds the second opening.

4. The method according to claim 1, wherein: The first etching process comprises: performing a third etching process from a front side of a corresponding wafer including the first complementary field effect transistor and the second complementary field effect transistor; and A fourth etching process is performed from a back side of the corresponding wafer.

5. The method according to claim 1, wherein: The first lower transistor and the first upper transistor are formed by a process comprising the following steps: forming the first lower transistor in a first wafer; forming the first upper transistor in a second wafer; and The first wafer is bonded to the second wafer, wherein the first etching process is performed after the bonding.

6. A multi-gate device comprising: A first complementary field effect transistor comprising: a first lower transistor; and a first upper transistor overlapping the first lower transistor; A second complementary field effect transistor comprising: a second lower transistor; and a second upper transistor overlapping the second lower transistor; a dielectric liner located between the first complementary field effect transistor and the second complementary field effect transistor, the dielectric liner comprising: an upper portion located between the first upper transistor and the second upper transistor; and a lower portion located between the first lower transistor and the second lower transistor; a through hole surrounded by the dielectric liner; a first contact plug over and connected to the through-hole; and A second contact plug is under the through-hole and connected to the through-hole.

7. The multi-gate device according to claim 6, further comprising: a plurality of semiconductor layers; as well as A plurality of inner spacers separate the plurality of semiconductor layers, wherein the dielectric liner contacts a sidewall of each of the plurality of semiconductor layers and the plurality of inner spacers.

8. The multi-gate device according to claim 6, wherein: One of the first lower transistor and the first upper transistor includes a source / drain region, and the source / drain region physically contacts a sidewall of the dielectric liner.

9. The multi-gate device according to claim 6, wherein: The dielectric liner becomes thinner from the top to the bottom of the dielectric liner.

10. A multi-gate device comprising: Complementary field effect transistors, including: A lower transistor, the lower transistor comprising: a first gate stack; and a first gate spacer disposed on a sidewall of the first gate stack; and an upper transistor overlapping the lower transistor and comprising: a second gate stack; and A second gate spacer, located on a sidewall of the second gate stack; a dielectric liner, comprising: an upper portion contacting a first sidewall of the second gate spacer; and a lower portion contacting the second sidewall of the first gate spacer; and a through hole surrounded by the dielectric liner.

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