Miniature light-emitting diode chip, manufacturing method thereof and display device
By introducing inter-pixel trench and sidewall reflection structures into the micro-light emitting diode chip, the problems of low luminous efficiency and inter-pixel crosstalk of Micro-LED are solved, and higher luminous efficiency and better display effects are achieved.
Patent Information
- Application Number
- CN202411543927.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-07
AI Technical Summary
Micro-LED has low luminous efficiency and has inter-pixel crosstalk problems, which affects the display effect.
A miniature light emitting diode chip is designed, adopting inter-pixel trench and sidewall reflection structures, the sidewall reflection layer and the light-absorbing protection layer are laminated in sequence, the sidewall reflection layer fills part of the space inside the trench, and the light-absorbing protection layer fills the remaining space.
The luminous efficiency of the micro-light emitting diode chip is improved, the optical crosstalk between pixels is reduced, power consumption is reduced, and the display effect is improved.
Smart Images
Figure CN119403337A_ABST
Abstract
Description
[Technical field]
[0001] The present application relates to the field of semiconductor light emitting technology, and in particular to a micro light emitting diode chip and a manufacturing method thereof, and a display device. [Background technology]
[0002] With the rise of Micro-LED (Micro-Light Emitting Diode) technology, many traditional LED (Light Emitting Diode) device manufacturing processes have also been gradually introduced into the Micro-LED manufacturing process. However, due to the rapid reduction in the size of Micro-LED, crosstalk and size effects will occur between pixels, resulting in a significant decrease in luminous efficiency. In addition, the introduction of process solutions that can improve the luminous efficiency of traditional-sized LED devices into the Micro-LED manufacturing process also has great process risks or very limited improvement effects.
[0003] Therefore, how to improve the luminous efficiency of Micro-LED and improve the crosstalk between pixels is an important issue currently faced. [Summary of the invention]
[0004] The embodiments of the present application provide a micro light emitting diode chip and a manufacturing method thereof, and a display device to improve the luminous efficiency of the micro light emitting diode chip and reduce the crosstalk between pixels of the micro light emitting diode chip.
[0005] In order to solve the above problems, an embodiment of the present application provides a micro-light-emitting diode chip, which includes: a light-emitting stack having a pixel array area, the pixel array area including at least one pixel area and a pixel channel area, the pixel channel area is arranged around each pixel area in the at least one pixel area, the light-emitting stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer which are sequentially stacked; an inter-pixel groove, which is arranged in the pixel channel area, and the inter-pixel groove penetrates to the first semiconductor layer; a sidewall reflection structure, which is arranged in the pixel channel area, and the sidewall reflection structure includes a sidewall reflection layer and a light absorption protection layer which are sequentially stacked in a direction away from the first semiconductor layer, wherein the sidewall reflection layer is arranged in the inter-pixel groove and fills part of the space in the inter-pixel groove, and the light absorption protection layer is arranged on the side of the sidewall reflection layer away from the bottom wall surface of the inter-pixel groove and fills the remaining space in the inter-pixel groove.
[0006] The height of the sidewall reflective layer relative to the plane where the bottom wall surface of the inter-pixel groove is located is smaller than the height of the light-emitting layer relative to the plane where the bottom wall surface of the inter-pixel groove is located.
[0007] The micro light emitting diode chip further comprises: a sidewall passivation layer, which is arranged between the sidewall reflection structure and the sidewall of the inter-pixel groove.
[0008] Among them, the micro-light emitting diode chip also includes: a current diffusion layer and a reflective layer, which are stacked in sequence on the side of the second semiconductor layer in the pixel area away from the light emitting layer, the orthographic projection area of the reflective layer on the plane where the first semiconductor layer is located is smaller than the orthographic projection area of the current diffusion layer on the plane where the first semiconductor layer is located, and the orthographic projection area of the current diffusion layer on the plane where the first semiconductor layer is located is smaller than the orthographic projection area of the second semiconductor layer in the pixel area on the plane where the first semiconductor layer is located; a passivation layer, covering the reflective layer, the current diffusion layer and the light emitting stack, and the inter-pixel grooves penetrate the passivation layer.
[0009] Among them, the light-emitting stack also has a pixel peripheral area, the pixel peripheral area is located around the pixel array area, and the pixel peripheral area is provided with a groove, which penetrates into the first semiconductor layer; the micro light-emitting diode chip also includes: a first polarity electrode, which is arranged on the bottom wall surface of the groove, and the side wall reflective layer is conductive and electrically connected to the first polarity electrode.
[0010] Among them, the micro-light-emitting diode chip also includes a second polarity electrode, which is arranged on the side of the second semiconductor layer in the pixel area away from the light-emitting layer, and the height of the first polarity electrode relative to the plane where the bottom wall of the groove is located is equal to the height of the second polarity electrode relative to the plane where the bottom wall of the groove is located.
[0011] In order to solve the above problems, an embodiment of the present application also provides a method for manufacturing a micro-light-emitting diode chip, which comprises: providing an epitaxial stack, the epitaxial stack having a pixel array area, the pixel array area comprising at least one pixel area and a pixel channel area, the pixel channel area being arranged around each pixel area in the at least one pixel area, the epitaxial stack comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence; forming an inter-pixel groove in the pixel channel area, the inter-pixel groove extending through the first semiconductor layer; forming a sidewall reflection layer in the inter-pixel groove, the sidewall reflection layer filling part of the space in the inter-pixel groove; forming a light-absorbing protective layer in the pixel channel area, and obtaining a sidewall reflection structure comprising a sidewall reflection layer and a light-absorbing protective layer, wherein the light-absorbing protective layer is arranged on a side of the sidewall reflection layer away from the bottom wall of the inter-pixel groove, and fills the remaining space in the inter-pixel groove.
[0012] Before forming the inter-pixel groove in the pixel channel region, the method further includes: forming a current diffusion layer on a side of the second semiconductor layer in the pixel region away from the light-emitting layer, wherein the orthographic projection area of the current diffusion layer on the plane where the first semiconductor layer is located is smaller than the orthographic projection area of the second semiconductor layer in the pixel region on the plane where the first semiconductor layer is located; forming a reflective layer on a side of the current diffusion layer away from the second semiconductor layer, wherein the orthographic projection area of the reflective layer on the plane where the first semiconductor layer is located is smaller than the orthographic projection area of the current diffusion layer on the plane where the first semiconductor layer is located; forming a passivation layer, wherein the passivation layer covers the reflective layer, the current diffusion layer and the light-emitting stack; and the inter-pixel groove runs through the passivation layer.
[0013] Among them, the epitaxial stack also has a pixel peripheral area, which is located around the pixel array area; the method also includes: forming a groove in the pixel peripheral area, the groove extending through the first semiconductor layer; forming a first polarity electrode on the bottom wall of the groove; and the inter-pixel groove is connected to the groove.
[0014] In order to solve the above problems, an embodiment of the present application further provides a display device, which includes any of the above-mentioned micro-light emitting diode chips, or a micro-light emitting diode chip manufactured by any of the above-mentioned methods.
[0015] The beneficial effects of the present application are as follows: the micro-LED chip and its manufacturing method, as well as the display device provided by the present application, introduce inter-pixel grooves and sidewall reflection structures in the micro-LED chip, the inter-pixel grooves and the sidewall reflection structures are arranged in the pixel channel region, wherein the inter-pixel grooves penetrate to the first semiconductor layer, the sidewall reflection structure is arranged around the light-emitting layer in each pixel region, and includes a sidewall reflection layer and a light-absorbing protective layer stacked in sequence in a direction away from the first semiconductor layer, and the sidewall reflection layer is arranged in the inter-pixel grooves and fills part of the space in the inter-pixel grooves, and the light-absorbing protective layer is arranged on the sidewall reflection layer. The layer is on the side away from the bottom wall of the groove between pixels and fills the remaining space in the groove between pixels. Therefore, during the use of the micro-LED chip, it is ensured that the side wall reflection layer can reflect the large-angle light emitted by the light-emitting layer in the pixel area to the light-emitting side, so as to improve the luminous efficiency of the micro-LED chip, and ensure that the light-absorbing protection layer can absorb the light emitted by the light-emitting layer in the pixel area and propagated to other pixel areas around it, so as to reduce the optical crosstalk problem between pixels of the micro-LED chip, thereby reducing the power consumption of the micro-LED chip and improving the display effect of the micro-LED chip.
Brief Description of the Drawings
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 is a schematic diagram of the cross-sectional structure of a micro light emitting diode chip provided in an embodiment of the present application;
[0018] Figure 2 is a schematic diagram of a top view structure of a light-emitting stack provided in an embodiment of the present application;
[0019] Figure 3 is another cross-sectional structural schematic diagram of a micro light emitting diode chip provided in an embodiment of the present application;
[0020] Figure 4 is another cross-sectional structural schematic diagram of a micro light emitting diode chip provided in an embodiment of the present application;
[0021] Figure 5 It is a schematic flow chart of a method for manufacturing a micro light emitting diode chip provided in an embodiment of the present application;
[0022] Figure 6 is a schematic diagram of the cross-sectional structure of an epitaxial stack provided in an embodiment of the present application;
[0023] Figure 7 is a schematic diagram of a cross-sectional structure after a groove is formed according to an embodiment of the present application;
[0024] Figure 8 is a schematic diagram of a cross-sectional structure after a passivation layer is formed according to an embodiment of the present application;
[0025] Fig. 9 is a schematic diagram of a cross-sectional structure after forming an upper inter-pixel groove provided in an embodiment of the present application;
[0026] Fig.10 is a schematic diagram of a cross-sectional structure after forming inter-pixel grooves provided in an embodiment of the present application;
[0027] Fig.11 is another schematic cross-sectional structure diagram after forming inter-pixel grooves provided in an embodiment of the present application;
[0028] Fig.12 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application. [Specific implementation method]
[0029] The following is a further detailed description of the embodiments of the present application in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the embodiments of the present application, but do not limit the scope of the embodiments of the present application. Similarly, the following examples are only some embodiments of the embodiments of the present application rather than all embodiments, and all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.
[0030] When describing the structure of a component, when a layer or a region is referred to as being "on" or "above" another layer or another region, it may mean being directly above the other layer or another region, or having other layers or regions between it and the other layer or another region. Also, if the component is turned over, the layer or the region will be "under" or "below" the other layer or another region. In addition, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.
[0031] In addition, the directional terms mentioned in the embodiments of the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the embodiments of the present application, rather than to limit the embodiments of the present application. In each of the accompanying drawings, units with similar structures are represented by the same figure numbers. For clarity, the various parts in the drawings are not drawn to scale. In addition, certain related parts may not be shown in the drawings.
[0032] The following is a detailed description with reference to specific embodiments. It should be noted that the embodiments of the present application can be presented in various forms, some examples of which will be described below.
[0033] See also Figure 1 and Figure 2 , Figure 1 is a schematic cross-sectional structure diagram of a micro light emitting diode chip provided in an embodiment of the present application, Figure 2 Schematic diagram of the top view of the light-emitting stack provided in the embodiment of the present application. Figure 1 and Figure 2As shown, the micro-LED chip 10 includes a light-emitting stack 100, an inter-pixel groove 2 and a sidewall reflection structure 200, wherein the light-emitting stack 100 has a pixel array region C1, the pixel array region C1 includes at least one pixel region C11 and a pixel channel region C12, and the pixel channel region C12 is arranged around each pixel region C11 in the at least one pixel region C11. In addition, the light-emitting stack 100 includes a first semiconductor layer 101, a light-emitting layer 102 and a second semiconductor layer 103 which are sequentially stacked in the longitudinal direction Z. The inter-pixel groove 2 and the sidewall reflection structure 200 can both be arranged in the pixel channel region C11, and can both be arranged around the light-emitting layer 102 in each pixel region C11.
[0034] Specifically, the inter-pixel groove 2 may penetrate the first semiconductor layer 101, and the sidewall reflection structure 200 may include a sidewall reflection layer 201 and a light absorption protection layer 202 which are sequentially stacked in a direction away from the first semiconductor layer 101. The sidewall reflection layer 201 may be disposed in the inter-pixel groove 2 and fill a portion of the space in the inter-pixel groove 2, and the light absorption protection layer 202 may be disposed on a side of the sidewall reflection layer 201 away from the bottom wall of the inter-pixel groove 2 and fill the remaining space in the inter-pixel groove 2.
[0035] Furthermore, the side wall reflection layer 201 has a light reflection function, that is, it can reflect the light emitted by the light emitting layer 102, and the orthographic projection of the side wall reflection layer 201 on the plane where the first semiconductor layer 102 is located can surround the orthographic projection of the light emitting layer 102 in each pixel region C11 on the plane where the first semiconductor layer 102 is located. The light absorption protection layer 202 has a light absorption function, that is, it can absorb the light emitted by the light emitting layer 102, and the orthographic projection of the light absorption protection layer 202 on the plane where the first semiconductor layer 102 is located can surround the orthographic projection of the light emitting layer 102 in each pixel region C11 on the plane where the first semiconductor layer 102 is located.
[0036] Thus, during the use of the micro-LED chip 10, the light emitted by the light-emitting layer 102 in the pixel area C11 and propagated to the side wall reflection layer 201 can be reflected by the side wall reflection layer 201, and the light emitted by the light-emitting layer 102 in the pixel area C11 and propagated to the light-absorbing protective layer 202 can be absorbed by the light-absorbing layer 102. Therefore, by introducing the side wall reflection structure 200 into the micro-LED chip 10, the light-emitting efficiency of the micro-LED chip 10 can be improved, and the problem of crosstalk between pixels can be improved, thereby reducing the power consumption of the micro-LED chip 10 and improving its display effect.
[0037] In this embodiment, the material of the light absorbing protective layer 202 may include an insulating material with high absorption of visible light. In some examples, the light absorbing protective layer 202 may be a black matrix. The material of the side wall reflective layer 201 may include a metal material with high reflectivity of visible light. In some examples, the material of the side wall reflective layer 201 may be silver (Ag), or a combination of silver (Ag) and aluminum (Al), but is not limited thereto.
[0038] Specifically, the side wall reflection structure 200 may further include a side wall barrier layer (not shown), which is located between the side wall reflection layer 201 and the light absorbing protection layer 202 and is used to protect the side wall reflection layer 201 to prevent Ag migration in the side wall reflection layer 201 .
[0039] In some examples, the material of the sidewall barrier layer may include metal materials such as titanium (Ti) and / or titanium-tungsten alloy (TiW), for example, may be specifically TiW.
[0040] Furthermore, in a specific implementation, under the premise of ensuring that the sidewall barrier layer can effectively prevent the migration of Ag in the sidewall reflection layer 201, the thickness of the sidewall barrier layer should be as thin as possible to avoid the problem that the overall light absorption and light reflection performance of the sidewall reflection structure 200 is significantly deteriorated due to the poor light absorption and light reflection performance of the sidewall barrier layer.
[0041] In some embodiments, Figure 1 As shown, the micro-LED chip 10 may further include a substrate 11, which is used to support the film structure thereon. Specifically, the micro-LED chip 10 may further include a buffer layer 12, which may be disposed on one side of the substrate 11, and the light-emitting stack 100 may be disposed on the side of the buffer layer 12 away from the substrate 11. Specifically, the first semiconductor layer 101, the light-emitting layer 102, and the second semiconductor layer 103 are sequentially stacked on the side of the buffer layer 12 away from the substrate 11, and the buffer layer 12 can relieve the stress generated between the first semiconductor layer 101 and the substrate 11 due to lattice mismatch and thermal expansion coefficient mismatch.
[0042] In some examples, the substrate 11 may be a sapphire substrate, a silicon substrate or a silicon carbide substrate, etc. The material of the buffer layer 12 may include buffer materials such as silicon nitride, silicon oxide, gallium nitride or aluminum nitride. For example, the buffer layer 12 may be specifically an unintentionally doped gallium nitride (U-GaN) layer.
[0043] In the above-mentioned light-emitting stack 100, the light-emitting layer 102 may be a quantum well layer, for example, an indium gallium nitride quantum well layer, or an indium gallium nitride / gallium nitride multi-quantum well layer. The first semiconductor layer 101 and the second semiconductor layer 103 have different polarities. Specifically, the first semiconductor layer 101 may be one of an N-type semiconductor layer and a P-type semiconductor layer, and the second semiconductor layer 103 may be the other of an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor layer may be specifically an N-type gallium nitride layer or an N-type gallium arsenide layer, and the P-type semiconductor layer may be specifically a P-type gallium nitride layer or a P-type aluminum gallium nitride layer.
[0044] In some embodiments, Figure 1 and Figure 2 As shown, the pixel array region C1 may include a plurality of pixel regions C11, which may be distributed in an array. Furthermore, the pixel channel region C12 may be disposed around each pixel region C11 in the plurality of pixel regions C11 and may be in a mesh structure.
[0045] Specifically, the sidewall reflection structure 200 is located in the pixel channel region C12, and can be arranged around the top of the first semiconductor layer 101, the light emitting layer 102, and the second semiconductor layer 103 in each pixel region C11 of the plurality of pixel regions C11, so as to separate the top of the first semiconductor layer 101 in each pixel region C11 from the top of the first semiconductor layer 101 in other pixel regions C11 located around it, separate the light emitting layer 102 in each pixel region C11 from the light emitting layer 102 in other pixel regions C11 located around it, and separate the second semiconductor layer 103 in each pixel region C11 from the second semiconductor layer 103 in other pixel regions C11 located around it. In this way, it is ensured that the sidewall reflection structure 200 can have good light absorption and light reflection performance for each pixel region C11, so as to effectively improve the light emitting efficiency of each pixel region C11, and effectively improve the light crosstalk problem between adjacent pixel regions C11.
[0046] In some embodiments, Figure 1 As shown, in the above side wall reflection structure 200, the height of the side wall reflection layer 201 in the direction away from the first semiconductor layer 101 (i.e., the longitudinal direction Z) is smaller than the height of the light emitting layer 102 in the direction away from the first semiconductor layer 101. In other words, Figure 1As shown, the height of the side wall reflective layer 201 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located can be smaller than the height of the light emitting layer 102 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located. In this way, the problem of the side wall reflective layer 201 electrically connecting the second semiconductor layer 103 and the first semiconductor layer 101 in the pixel area C11 to cause a short circuit can be avoided.
[0047] In some examples, such as Figure 1 As shown, the inter-pixel groove 2 may sequentially penetrate the second semiconductor layer 103, the light-emitting layer 102 and a portion of the first semiconductor layer 101 from top to bottom. Furthermore, the height of the upper surface of the sidewall reflective layer 201 relative to the plane where the bottom wall of the inter-pixel groove 2 is located may be less than the height of the upper surface of the first semiconductor layer 101 relative to the plane where the bottom wall of the inter-pixel groove 2 is located in the pixel region C11. In this way, the risk of the conductive material in the sidewall reflective layer 201 migrating upward along the sidewall of the light-emitting layer 102 in the pixel region C11 can be reduced, thereby improving product reliability.
[0048] In some embodiments, Figure 3 As shown, the above-mentioned micro-LED chip 10 may further include a sidewall passivation layer 13, and the sidewall passivation layer 13 is arranged between the sidewall reflection structure 200 and the side wall of the inter-pixel groove 2, so that the sidewall passivation layer 13 can electrically isolate the sidewall reflection structure 200 in the inter-pixel groove 2 from the second semiconductor layer 103 and the light-emitting layer 102 in the light-emitting stack 100, thereby avoiding the sidewall reflection structure 200 being electrically connected to the second semiconductor layer 103 and the light-emitting layer 102 in the pixel area C11 to cause short circuit or leakage problems, thereby improving product reliability.
[0049] In some examples, the material of the sidewall passivation layer 13 may include insulating materials such as silicon oxide, silicon nitride and / or aluminum oxide.
[0050] Specifically, under the premise that the sidewall passivation layer 13 is disposed between the sidewall reflective structure 200 and the sidewall of the inter-pixel trench 2, as shown in FIG. Figure 3As shown, the height of the upper surface of the sidewall reflective layer 201 relative to the plane where the bottom wall of the inter-pixel groove 2 is located can be greater than or equal to the height of the upper surface of the first semiconductor layer 101 in the pixel region C11 relative to the plane where the bottom wall of the inter-pixel groove 2 is located, for example, it can be greater than or equal to the height of the upper surface of the light-emitting layer 102 relative to the plane where the bottom wall of the inter-pixel groove 2 is located. In addition, the height of the upper surface of the sidewall reflective layer 201 relative to the plane where the bottom wall of the inter-pixel groove 2 is located can be less than the height of the upper surface of the second semiconductor layer 103 relative to the plane where the bottom wall of the inter-pixel groove 2 is located, so that the light absorption protection layer 202 can be arranged at least around the top portion of the second semiconductor layer 103 in each pixel region C11. In this way, it is ensured that the light absorption protection layer 202 can effectively protect the sidewall reflective layer 201, and ensure that the light absorption protection layer 202 can reduce the risk of lateral migration of the conductive material in the sidewall reflective layer 201, thereby improving product reliability.
[0051] In some examples, such as Figure 3 As shown. The height of the upper surface of the side wall reflection layer 201 relative to the plane where the bottom wall of the inter-pixel groove 2 is located can be greater than the height of the upper surface of the light emitting layer 102 relative to the plane where the bottom wall of the inter-pixel groove 2 is located, and less than the height of the upper surface of the second semiconductor layer 103 relative to the plane where the bottom wall of the inter-pixel groove 2 is located. In this way, the reflection performance of the side wall reflection structure 200 on the large-angle light emitted by the light emitting layer 102 in the pixel area C11 can be enhanced, thereby greatly improving the luminous efficiency of the micro light emitting diode chip 10.
[0052] In the above embodiment, if Figures 1 to 3 As shown, the light emitting stack 100 may further include a pixel peripheral region C2, and the pixel peripheral region C2 is located around the pixel array region C1. Figure 1 and Figure 3 As shown, the pixel peripheral region C2 may be provided with a groove 104 , and the groove 104 penetrates the first semiconductor layer 101 .
[0053] Specifically, Figure 1 and Figure 3 As shown, the groove 104 can penetrate the second semiconductor layer 103, the light-emitting layer 102 and part of the first semiconductor layer 101 from top to bottom, and the bottom wall surface of the groove 104 and the bottom wall surface of the above-mentioned inter-pixel groove 2 can be located in the same plane, or can be basically located in the same plane.
[0054] In some embodiments, Figure 1 and Figure 3As shown, the micro-LED chip 10 may further include a first polarity electrode 300, which is disposed on the bottom wall of the groove 104 and is electrically connected to the first semiconductor layer 101. The material of the first polarity electrode 300 may include a metal material, for example, may include at least one of titanium (Ti), gold (Au), platinum (Pt), nickel (Ni) and aluminum (Al).
[0055] In some specific embodiments, Figure 4 As shown, the side wall reflective layer 201 can be conductive and can be electrically connected to the first polarity electrode 300. Specifically, the outer walls of the side wall reflective layer 201 can be connected to the side walls of the first polarity electrode 300 to achieve electrical connection between the side wall reflective layer 201 and the first polarity electrode 300. In this way, the uniformity of the current distribution inside the pixel array region C1 can be improved, and thus the display uniformity of the micro light emitting diode chip 10 can be improved.
[0056] In the above embodiment, if Figure 1 , Figure 3 and Figure 4 As shown, the micro-LED chip 10 may further include a reflective layer 500, which is disposed on a side of the second semiconductor layer 103 in the pixel region C11 away from the light-emitting layer 102. The reflective layer 500 may be made of a metal material having a high reflectivity to visible light. In some examples, the reflective layer 500 may be made of silver (Ag), or a combination of silver (Ag) and aluminum (Al), but is not limited thereto.
[0057] Specifically, during the use of the micro-LED chip 10, the light emitted by the light-emitting layer 102 in the pixel area C11 and propagated to the reflective layer 500 can be reflected by the reflective layer 500, and the reflected light will propagate outward toward the side of the light-emitting stack 100 away from the reflective layer 500 (i.e., the light-emitting side), thereby further improving the luminous efficiency of the micro-LED chip 10.
[0058] Moreover, in a specific implementation, the above-mentioned micro-light emitting diode chip 10 may further include a blocking layer (not shown in the figure), which is arranged on the side of the above-mentioned reflective layer 500 away from the second semiconductor layer 103, and can completely cover the surface of the reflective layer 500 away from the second semiconductor layer 103 (i.e., the upper surface) to prevent Ag in the above-mentioned reflective layer 500 from migrating upward, thereby improving the reliability of the product.
[0059] In some examples, the material of the barrier layer may include metal materials such as titanium (Ti) and / or titanium-tungsten alloy (TiW), for example, may be specifically TiW.
[0060] In some specific embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the orthographic projection area of the reflective layer 500 on the plane where the first semiconductor layer 101 is located can be smaller than the orthographic projection area of the second semiconductor layer 103 in the pixel area C11 on the plane where the first semiconductor layer 101 is located. In other words, the lower surface area of the reflective layer 500 can be smaller than the upper surface area of the second semiconductor layer 103 in the pixel area C11. Specifically, there can be a spacing area between the orthographic projection boundary of the reflective layer 500 on the plane where the first semiconductor layer 101 is located and the orthographic projection boundary of the second semiconductor layer 103 in the pixel area C11 on the plane where the first semiconductor layer 101 is located. In this way, the lateral migration path of Ag in the reflective layer 500 can be extended to improve the problem of reduced product reliability caused by lateral migration of Ag in the reflective layer 500.
[0061] In some embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the micro-LED chip 10 may further include a current diffusion layer 400, which is disposed on the side of the second semiconductor layer 103 in the pixel region C11 away from the light-emitting layer 102, and the reflective layer 500 may be disposed on the side of the current diffusion layer 400 away from the second semiconductor layer 103. Moreover, the current diffusion layer 400 can evenly distribute the current to the entire second semiconductor layer 103 (for example, the P-type gallium nitride layer), thereby effectively improving the light-emitting efficiency of the micro-LED chip 10.
[0062] In some specific embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the orthographic projection area of the reflective layer 500 on the plane where the first semiconductor layer 101 is located can be smaller than the orthographic projection area of the current diffusion layer 400 on the plane where the first semiconductor layer 101 is located. In other words, the lower surface area of the reflective layer 500 can be smaller than the upper surface area of the current diffusion layer 400. Specifically, there can be a spacing area between the orthographic projection boundary of the reflective layer 500 on the plane where the first semiconductor layer 101 is located and the orthographic projection boundary of the current diffusion layer 400 on the plane where the first semiconductor layer 101 is located. In this way, the lateral migration path of Ag in the reflective layer 500 can be extended to improve the problem of reduced product reliability caused by lateral migration of Ag in the reflective layer 500.
[0063] In some specific embodiments, Figure 1 , Figure 3 and Figure 4As shown, the orthographic projection area of the reflective layer 500 on the plane where the first semiconductor layer 101 is located may be smaller than the orthographic projection area of the current diffusion layer 400 on the plane where the first semiconductor layer 101 is located, and the orthographic projection area of the current diffusion layer 400 on the plane where the first semiconductor layer 101 is located may be smaller than the orthographic projection area of the second semiconductor layer 103 in the pixel region C11 on the plane where the first semiconductor layer 101 is located. In other words, the lower surface area of the reflective layer 500 may be smaller than the upper surface area of the current diffusion layer 400, and the lower surface area of the current diffusion layer 400 may be smaller than the upper surface area of the second semiconductor layer 103 in the pixel region C11. Specifically, the orthographic projection boundary of the current diffusion layer 400 on the plane where the first semiconductor layer 101 is located may be located between the orthographic projection boundary of the reflective layer 500 on the plane where the first semiconductor layer 101 is located and the orthographic projection boundary of the second semiconductor layer 103 in the pixel region C11 on the plane where the first semiconductor layer 101 is located. In this way, the lateral migration path of Ag in the reflective layer 500 can be further extended, so as to more effectively improve the problem of reduced product reliability caused by lateral migration of Ag in the reflective layer 500.
[0064] In some examples, the current diffusion layer 500 can be obtained by evaporating multiple layers of metal (e.g., titanium (Ti), aluminum (Al), gold (Au), platinum (Pt) or nickel (Ni), etc.) or semiconductor oxide (e.g., indium tin oxide (ITO) or zinc oxide (ZnO), etc.) on the surface of the second semiconductor layer 103 in the pixel region C11 facing away from the light-emitting layer 102 to form current conduction.
[0065] In some embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the micro-LED chip 10 may further include a second polarity electrode 600, which is disposed on the side of the second semiconductor layer 103 in the pixel region C11 away from the light-emitting layer 102. Furthermore, in the above embodiment in which the micro-LED chip 10 includes a reflective layer 500, the second polarity electrode 600 may be specifically disposed on the side of the reflective layer 500 away from the second semiconductor layer 103, and the barrier layer may be disposed between the second polarity electrode 600 and the reflective layer 500. Specifically, the material of the second polarity electrode 600 may include a metal material, for example, may include at least one of titanium (Ti), gold (Au), platinum (Pt), nickel (Ni) and aluminum (Al).
[0066] Furthermore, in a specific implementation, in the micro-LED chip 10, the height of the first polarity electrode 300 relative to the plane where the bottom wall of the groove 104 is located can be equal or substantially equal to the height of the second polarity electrode 600 relative to the plane where the bottom wall of the groove 104 is located. In other words, the surface of the first polarity electrode 300 facing away from the first semiconductor layer 101 and the surface of the second polarity electrode 105 facing away from the first semiconductor layer 101 can be located in the same plane, or can be located substantially in the same plane, so as to reduce the process difficulty of forming a bonding layer on the first polarity electrode 300 and the second polarity electrode 600.
[0067] In some examples, the first semiconductor layer 101 and the second semiconductor layer 103 may be an N-type semiconductor layer and a P-type semiconductor layer, respectively, and accordingly, the first polarity electrode 300 and the second polarity electrode 600 may be an N-type electrode and a P-type electrode, respectively. In other examples, the first semiconductor layer 101 and the second semiconductor layer 103 may be a P-type semiconductor layer and an N-type semiconductor layer, respectively, and accordingly, the first polarity electrode 300 and the second polarity electrode 600 may be a P-type electrode and an N-type electrode, respectively.
[0068] In the above embodiment, if Figure 1 , Figure 3 and Figure 4 As shown, the micro-LED chip 10 may further include a passivation layer 800, which may cover the first polarity electrode 300, the second polarity electrode 600, the barrier layer, the reflective layer 500, the current diffusion layer 400 and the light-emitting stack 100, and may also cover the inner wall surface of the groove 104. In this way, the passivation layer 800 can effectively prevent the corrosion of the first polarity electrode 300, the second polarity electrode 600, the barrier layer, the reflective layer 500, the current diffusion layer 400 and the light-emitting stack 100 by external water and oxygen, thereby improving product reliability.
[0069] Specifically, Figure 1 , Figure 3 and Figure 4 As shown, the micro-LED chip 10 may further include a first bonding layer 700A and a second bonding layer 700B. The first bonding layer 700A is disposed on the side of the first polarity electrode 300 away from the bottom wall of the groove 104, and the first bonding layer 700A penetrates the passivation layer 800 and is electrically connected to the first polarity electrode 300. The second bonding layer 700B is disposed on the side of the second polarity electrode 600 away from the second semiconductor layer 103, and the second bonding layer 700B penetrates the passivation layer 800 and is electrically connected to the second polarity electrode 600.
[0070] In some examples, the material of the passivation layer 800 may include insulating materials such as silicon oxide, silicon nitride and / or aluminum oxide. The material of the first bonding layer 700A and the second bonding layer 700B may include one or more metal materials such as gold (Au), tin (Sn), indium (In) and cobalt (Cn).
[0071] In some embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the side wall reflection structure 200 may penetrate the passivation layer 800. Moreover, the height of the side wall reflection structure 200 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located may be greater than the height of the second semiconductor layer 103 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located, and less than or equal to the height of the first bonding layer 700A and the second bonding layer 700B relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located. In some examples, such as Figure 1 , Figure 3 and Figure 4 As shown, the height of the sidewall reflection structure 200 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located can be greater than the height of the current diffusion layer 400 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located, and less than the height of the reflection layer 500 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located. In this way, under the premise that the height of the sidewall reflection structure 200 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located is less than or equal to the height of the first bonding layer 700A and the second bonding layer 700B relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located, by increasing the height of the sidewall reflection structure 200 relative to the plane where the bottom wall surface of the inter-pixel groove 2 is located, the overall light absorption performance of the sidewall reflection structure 200 can be improved, thereby more effectively improving the inter-pixel light crosstalk problem of the micro-LED chip 10.
[0072] In some specific embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the light absorption protection layer 202 may include a through portion 202A and a covering portion 202B which are sequentially stacked in a direction away from the first semiconductor layer 101 (i.e., direction Z in the figure). The through portion 202A may refer to a portion of the light absorption protection layer 202 that penetrates the passivation layer 800 and / or the light emitting stack 100, and the covering portion 202B may refer to the remaining portion of the light absorption protection layer 202 except the through portion 202A.
[0073] Specifically, the orthographic projection of the covering portion 202B on the plane where the first semiconductor layer 101 is located can completely cover the orthographic projection of the penetration portion 202A on the plane where the first semiconductor layer 101 is located, and the orthographic projection of the penetration portion 202A on the plane where the first semiconductor layer 101 is located can completely cover the orthographic projection of the side wall reflection layer 201 on the plane where the first semiconductor layer 101 is located. In addition, the orthographic projection area of the covering portion 202B on the plane where the first semiconductor layer 101 is located can be greater than the orthographic projection area of the penetration portion 202A on the plane where the first semiconductor layer 101 is located, the orthographic projection area of the penetration portion 202A on the plane where the first semiconductor layer 101 is located can be greater than or equal to the orthographic projection area of the side wall reflection layer 201 on the plane where the first semiconductor layer 101 is located, and the covering portion 202B can partially cover the pixel area C11. In this way, not only is it ensured that the light-absorbing protection layer 202 can more effectively block the upward or lateral migration of the conductive material in the side wall reflection layer 201, but it is also ensured that the conductive material layer 22 can absorb more light emitted by the light-emitting layer 102, so as to more effectively reduce the crosstalk between pixels of the above-mentioned micro-LED chip 10.
[0074] As can be seen from the above, the micro-LED chip provided in the embodiment of the present application, by introducing the inter-pixel groove and the sidewall reflection structure in the micro-LED chip, the inter-pixel groove and the sidewall reflection structure are arranged in the pixel channel region, wherein the inter-pixel groove penetrates to the first semiconductor layer, the sidewall reflection structure is arranged around the light-emitting layer in each pixel region, and includes a sidewall reflection layer and a light absorption protection layer stacked in sequence in a direction away from the first semiconductor layer, and the sidewall reflection layer is arranged in the inter-pixel groove and fills part of the space in the inter-pixel groove, and the light absorption protection layer is arranged in the sidewall reflection layer away from the inter-pixel groove On one side of the bottom wall of the groove, and fills the remaining space in the groove between pixels, so that during the use of the micro-light-emitting diode chip, it is ensured that the side wall reflection layer can reflect the large-angle light emitted by the light-emitting layer in the pixel area to the light-emitting side, so as to improve the luminous efficiency of the micro-light-emitting diode chip, and ensure that the light-absorbing protection layer can absorb the light emitted by the light-emitting layer in the pixel area and propagated to other pixel areas around it, so as to reduce the light crosstalk problem between pixels of the micro-light-emitting diode chip, thereby reducing the power consumption of the micro-light-emitting diode chip and improving the display effect of the micro-light-emitting diode chip.
[0075] See also Figure 5 , Figure 5 The flowchart of the method for manufacturing the micro-LED chip provided in the embodiment of the present application is also provided in Figures 1 to 4 , Figures 1 to 41 is a schematic diagram of the structure of the micro-LED chip during the preparation process provided in the embodiment of the present application. This embodiment takes the formation of the micro-LED chip 10 as an example to illustrate the preparation method. The specific process of the preparation method of the micro-LED chip 10 can be as follows:
[0076] Step S11: providing an epitaxial stack 1, wherein the epitaxial stack 1 has a pixel array region C1, wherein the pixel array region C1 includes at least one pixel region C11 and a pixel channel region C12, wherein the pixel channel region C12 is disposed around each pixel region C11 in the at least one pixel region C11, and wherein the epitaxial stack 1 includes a first semiconductor layer 101, a light emitting layer 102, and a second semiconductor layer 103 (such as Figure 6 shown).
[0077] Specifically, Figure 6 As shown, a buffer layer 12 can be formed on one side of the substrate 11, and then an epitaxial stack 1 can be formed on the side of the buffer layer 12 facing away from the substrate 11. The substrate 11 is used to support the film structure located thereon, and can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The buffer layer 12 can relieve the stress generated by the lattice mismatch and the thermal expansion coefficient mismatch between the epitaxial stack 1 and the substrate 11, and the material of the buffer layer 12 can include buffer materials such as silicon nitride, silicon oxide, gallium nitride or aluminum nitride. The above-mentioned epitaxial stack 1 can include a first semiconductor layer 101, a light-emitting layer 102, and a second semiconductor layer 103 stacked in sequence on the buffer layer 12 in a longitudinal direction Z perpendicular to the substrate 11.
[0078] In some embodiments, Figure 6 As shown, the epitaxial stack 1 may further include a pixel peripheral region C2, and the pixel peripheral region C2 is located around the pixel array region C1. Figure 7 As shown, the manufacturing method of the micro light emitting diode chip 10 may further include: forming a groove 104 in the pixel peripheral area C1 , wherein the groove 104 penetrates the first semiconductor layer 101 .
[0079] Specifically, Figure 6 and Figure 7 As shown, after obtaining the above-mentioned epitaxial stack 1, an etching process can be used to etch the epitaxial stack 1 in the pixel peripheral area C2 from top to bottom in the longitudinal direction Z perpendicular to the substrate 11 to form a groove 104 that penetrates the first semiconductor layer 101. The obtained epitaxial stack 100 with the groove 104 is the light-emitting stack 100 in the above-mentioned embodiment.
[0080] Furthermore, it should be noted that after forming the above-mentioned groove 104, Figure 7As shown, the epitaxial stack 100 forms a mesa structure corresponding to each pixel array region C1, and the cross-sectional shape of the mesa structure perpendicular to the longitudinal direction Z can be a geometric shape such as a square or a circle.
[0081] In some examples, such as Figure 7 As shown, the groove 104 may penetrate the second semiconductor layer 103 and the light emitting layer 102 in the longitudinal direction Z and extend into the first semiconductor layer 101 to achieve sufficient etching, thereby ensuring that the first semiconductor layer 101 can be exposed through the groove 104 .
[0082] Furthermore, in a specific implementation, an etching mask layer may be deposited on the surface of the epitaxial stack 1 facing away from the substrate 11, and the etching mask layer may be patterned, and then the epitaxial stack 1 may be etched according to the pattern of the etching mask layer to form the groove 104. The material of the etching mask layer may include etching-resistant materials such as photoresist, metal materials or insulating materials, and after the groove 104 is formed, the etching mask layer may be removed cleanly by chemical or physical methods to facilitate subsequent process steps.
[0083] In some embodiments, after the above step S11 and before the following step S12, the method for manufacturing the micro-LED chip 10 may further include:
[0084] Step A: forming a reflective layer 500 (eg, Figure 8 shown).
[0085] Step B: forming a passivation layer 800, the passivation layer 800 covers the reflective layer 500 and the light emitting stack 100 (eg Figure 8 shown).
[0086] Specifically, Figure 8 As shown, before the above step A, the manufacturing method of the above micro-LED chip 10 may further include: forming a current diffusion layer 400 on the side of the second semiconductor layer 103 away from the light-emitting layer 102 in the pixel area C11. Accordingly, the above step A may specifically include: forming a reflective layer 500 on the side of the current diffusion layer 400 away from the second semiconductor layer 103. In addition, the above passivation layer 800 also covers the current diffusion layer 400.
[0087] The orthographic projection area of the current diffusion layer 400 on the plane where the first semiconductor layer 101 is located may be smaller than the orthographic projection area of the second semiconductor layer 103 in the pixel region C11 on the plane where the first semiconductor layer 101 is located. The orthographic projection area of the reflective layer 500 on the plane where the first semiconductor layer 101 is located may be smaller than the orthographic projection area of the current diffusion layer 400 on the plane where the first semiconductor layer 101 is located.
[0088] Furthermore, in a specific implementation, the current diffusion layer 400 can be obtained by evaporating multiple layers of metal (e.g., titanium (Ti), aluminum (Al), gold (Au), platinum (Pt) or nickel (Ni)) or semiconductor oxide (e.g., indium tin oxide (ITO) or zinc oxide (ZnO)) on the surface of the second semiconductor layer 103 in the pixel region C11 away from the light emitting layer 102 to form current conduction. Then, after the current diffusion layer 400 is formed, a reflective metal material (e.g., Ag and Al) can be deposited on the side of the current diffusion layer 400 away from the second semiconductor layer 103 through photolithography and deposition processes to form the reflective layer 500.
[0089] In some embodiments, Figure 8 As shown, before the above step B, the method for manufacturing the micro light emitting diode chip 10 may further include: forming a second polarity electrode 600 (such as Figure 8 In addition, the passivation layer 800 also covers the second polarity electrode 600 .
[0090] Specifically, Figure 8 As shown, before forming the second polarity electrode 600, the manufacturing method of the micro-LED chip 10 may further include: forming a blocking layer (not shown in the figure) on the side of the reflective layer 400 away from the second semiconductor layer 103 (or the current diffusion layer 400). Accordingly, the forming of the second polarity electrode 600 on the side of the reflective layer 400 away from the second semiconductor layer 103 (or the current diffusion layer 400) may specifically include: forming the second polarity electrode 600 on the side of the blocking layer away from the reflective layer 500. In addition, the passivation layer 800 also covers the blocking layer.
[0091] Furthermore, in a specific implementation, after forming the reflective layer 500 , a metal material such as Ti and / or TiW may be deposited on the side of the reflective layer 400 away from the second semiconductor layer 103 (or the current diffusion layer 400 ) through a deposition process to form the barrier layer.
[0092] In some specific embodiments, Figure 8 As shown, after forming the groove 104 and before forming the passivation layer 800, the method for manufacturing the micro-LED chip 10 may further include: forming a first polarity electrode 300 on the bottom wall of the groove 104. Accordingly, the passivation layer 800 also covers the first polarity electrode 300. In addition, during specific implementation, the first polarity electrode 300 and the second polarity electrode 600 may be formed simultaneously.
[0093] Specifically, after forming the above-mentioned reflective layer 500 (or the above-mentioned barrier layer), a metal material (for example, Ti, Au, Pt, Ni and / or Al, etc.) can be deposited on the bottom wall surface of the above-mentioned groove 104 and on the side of the above-mentioned reflective layer 500 (or the above-mentioned barrier layer) away from the second semiconductor layer 103 through a deposition process to form the above-mentioned first polarity electrode 300 and the above-mentioned second polarity electrode 600.
[0094] Furthermore, after forming the first polarity electrode 300 and the second polarity electrode 600, an insulating material (such as silicon oxide, silicon nitride and / or aluminum oxide, etc.) may be deposited on the side of the epitaxial stack 100 where the groove 104 is provided by a deposition process to form the passivation layer 800. Specifically, the passivation layer 800 may cover the first polarity electrode 300, the second polarity electrode 600, the blocking layer, the reflective layer 500, the current diffusion layer 400 and the light-emitting stack 100, and may also cover the inner wall surface of the groove 104.
[0095] Step S12: forming an inter-pixel trench 2 in the pixel channel region C12, the inter-pixel trench 2 penetrating the first semiconductor layer 103 (such as Fig.10 shown).
[0096] In this embodiment, if Figure 2 As shown, the pixel array region C1 may include a plurality of pixel regions C11, which may be distributed in an array. Furthermore, the pixel channel region C12 may be disposed around each pixel region C11 in the plurality of pixel regions C11 and may be in a mesh structure.
[0097] Specifically, the above-mentioned inter-pixel groove 2 can be arranged around the top portion of the first semiconductor layer 101 and the light-emitting layer 102 and the second semiconductor layer 103 in each pixel area C11, so as to separate the top portion of the first semiconductor layer 101 in each pixel area C11 from the top portion of the first semiconductor layer 101 in other pixel areas C11 located around it, separate the light-emitting layer 102 in each pixel area C11 from the light-emitting layer 102 in other pixel areas C11 located around it, and separate the second semiconductor layer 103 in each pixel area C11 from the second semiconductor layer 103 in other pixel areas C11 located around it by the above-mentioned sidewall reflection structure 200.
[0098] In some examples, such as Fig.10As shown, after the above-mentioned passivation layer 800 is formed, an etching process can be used to etch the passivation layer 800 covering the surface of the pixel channel area C12 and the epitaxial stack 1 in the pixel channel area C12 from top to bottom in the longitudinal direction Z perpendicular to the substrate 11, so as to form an inter-pixel groove 2 that penetrates the above-mentioned passivation layer 800, the second semiconductor layer 103 and the light-emitting layer 102, and extends to the inside of the first semiconductor layer 101.
[0099] In some examples, such as Fig.10 As shown, the bottom wall surface of the inter-pixel trench 2 and the bottom wall surface of the groove 104 may be located in the same plane or substantially in the same plane.
[0100] Step S13: forming a sidewall reflective layer 201 in the inter-pixel trench 2, the sidewall reflective layer 201 filling a portion of the space in the inter-pixel trench 2 (eg, Fig.10 and Figure 1 shown).
[0101] Specifically, Fig.10 and Figure 1 As shown, after the above-mentioned inter-pixel grooves 2 are formed, a reflective metal material (such as Ag and Al) may be deposited in the above-mentioned inter-pixel grooves 2 through a deposition process to form the above-mentioned sidewall reflective layer 201 .
[0102] In some embodiments, Fig.10 and Figure 3 As shown, after forming the above-mentioned inter-pixel groove 2 and before forming the above-mentioned sidewall reflection layer 201, the manufacturing method of the above-mentioned micro-LED chip 10 may further include: forming a sidewall passivation layer 13 on the sidewall surface of the above-mentioned inter-pixel groove 2. Moreover, the above-mentioned step S13 may specifically include: forming the above-mentioned sidewall reflection layer 201 in the inter-pixel groove 2 with the above-mentioned sidewall passivation layer 13 provided on the sidewall surface, the height of the above-mentioned sidewall reflection layer 201 relative to the bottom wall surface of the inter-pixel groove 2 is less than the depth of the inter-pixel groove 2, and the above-mentioned sidewall passivation layer 13 can electrically isolate the above-mentioned sidewall reflection layer 201 from the second semiconductor layer 103 and the light-emitting layer 102 exposed on the sidewall surface of the above-mentioned inter-pixel groove 2.
[0103] Step S14: forming a light absorbing protective layer 202 in the pixel channel region C12, and obtaining a side wall reflection structure 200 including a side wall reflection layer 201 and a light absorbing protective layer 202, wherein the light absorbing protective layer 202 is arranged on a side of the side wall reflection layer 201 away from the bottom wall surface of the inter-pixel groove 2, and fills the remaining space in the inter-pixel groove 2 (such as Fig.10 and Figure 1 shown).
[0104] In some embodiments, Fig.11 and Figure 4As shown, the above-mentioned inter-pixel channel 2 can be connected to the groove 104, and the outer walls around the inner sidewall reflective layer 201 of the inter-pixel channel 2 can be connected to the side walls of the first polarity electrode 300 on the bottom wall surface of the above-mentioned groove 104, so that the electrical connection between the above-mentioned sidewall reflective layer 201 and the above-mentioned first polarity electrode 300 can be achieved.
[0105] In some embodiments, Fig.10 , Figure 1 , Figure 3 and Figure 4 As shown, after forming the above-mentioned sidewall reflection layer 201 and before forming the above-mentioned light absorbing protective layer 202, the manufacturing method of the above-mentioned micro-light emitting diode chip 10 may also include: forming a sidewall barrier layer (not shown in the figure) on the side of the above-mentioned sidewall reflection layer 201 away from the bottom wall surface of the above-mentioned inter-pixel groove 2, the sidewall barrier layer is located in the above-mentioned inter-pixel groove 2, and the height of the sidewall barrier layer relative to the bottom wall surface of the above-mentioned inter-pixel groove 2 is less than the depth of the above-mentioned inter-pixel groove 2, so as to ensure that there is still remaining space in the above-mentioned inter-pixel groove 2 to be filled by the above-mentioned light absorbing protective layer 202.
[0106] In the above embodiment, after forming the above passivation layer 800, the method for manufacturing the above micro-LED chip 10 may further include: Fig.10 As shown, a first through hole 3A and a second through hole 3B are formed, wherein the first through hole 3A penetrates through the passivation layer 800 covered on the surface of the first polarity electrode 300 to expose the first polarity electrode 300, and the second through hole 3B penetrates through the passivation layer 800 covered on the surface of the second polarity electrode 600 to expose the second polarity electrode 600; and Figure 1 , Figure 3 and Figure 4 As shown, a first bonding layer 700A is formed on the side of the first polarity electrode 300 away from the bottom wall of the groove 104, and a second bonding layer 700B is formed on the side of the second polarity electrode 600 away from the reflective layer 500, the first bonding layer 700A fills the first through hole 3A and is electrically connected to the first polarity electrode 300, and the second bonding layer 700B fills the second through hole 3B and is electrically connected to the second polarity electrode 600.
[0107] In some specific embodiments, the above step S12 may include: Fig. 9 As shown, the passivation layer 800 covering the surface of the pixel channel region C12 is etched to form an upper inter-pixel groove 20 penetrating the passivation layer 800; and Fig. 9 and Fig.10As shown, through the upper inter-pixel trench 20, part of the epitaxial stack 100 in the pixel channel region C12 is etched to form a lower inter-pixel trench connected to the upper inter-pixel trench 20, thereby obtaining the inter-pixel trench 2 including the upper inter-pixel trench 20 and the lower inter-pixel trench.
[0108] Specifically, the upper inter-pixel groove 20 may be formed simultaneously with the first through hole 3A and the second through hole 3B.
[0109] Furthermore, in a specific implementation, an etching mask layer may be deposited on the surface of the passivation layer 800 facing away from the substrate 11, and the etching mask layer may be patterned, and then the passivation layer 800 may be etched according to the pattern of the etching mask layer to form the upper inter-pixel groove 20, the first through hole 3A, and the second through hole 3B. Next, the epitaxial stack 100 exposed by the upper inter-pixel groove 20 may be etched to form the lower inter-pixel groove, thereby obtaining the inter-pixel groove 2 including the upper inter-pixel groove 20 and the lower inter-pixel groove.
[0110] In some examples, etching the epitaxial stack 100 exposed by the upper inter-pixel groove 20 to form the lower inter-pixel groove may specifically include: selectively etching the epitaxial stack 100 exposed by the upper inter-pixel groove 20 to form the lower inter-pixel groove. Specifically, the first polarity electrode 300 and the second polarity electrode 600 may be made of a metal material such as Au that is relatively resistant to etching, so that in the process of selectively etching the epitaxial stack 100 exposed by the upper inter-pixel groove 20 to form the lower inter-pixel groove, it is ensured that the first polarity electrode 300 exposed by the first through hole 3A and the second polarity electrode 600 exposed by the second through hole 3B may not be etched, or may be substantially not etched, so as to avoid damage to the first polarity electrode 300 and the second polarity electrode 600.
[0111] It should be noted that the specific structure of the micro-LED chip 10 in this embodiment can refer to the specific implementation in the above-mentioned micro-LED chip embodiment, so it will not be repeated here.
[0112] As can be seen from the above, the method for manufacturing a micro-light-emitting diode chip provided in an embodiment of the present application provides an epitaxial stack, the epitaxial stack has a pixel array area, the pixel array area includes at least one pixel area and a pixel channel area, the pixel channel area is arranged around each pixel area in the at least one pixel area, the epitaxial stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence, and then an inter-pixel groove is formed in the pixel channel area, the inter-pixel groove penetrates to the first semiconductor layer, and a sidewall reflection layer is formed in the inter-pixel groove, the sidewall reflection layer fills part of the space in the inter-pixel groove, and then a light-absorbing protective layer is formed in the pixel channel area to obtain a sidewall reflection layer and a light-absorbing protective layer. The side wall reflection structure of the light protection layer, wherein the light absorption protection layer is arranged on the side of the side wall reflection layer away from the bottom wall surface of the inter-pixel groove, and fills the remaining space in the inter-pixel groove, thereby ensuring that during the use of the micro-light-emitting diode chip, the side wall reflection layer can reflect the large-angle light emitted by the light-emitting layer in the pixel area to the light-emitting side, so as to improve the luminous efficiency of the micro-light-emitting diode chip, and ensure that the light absorption protection layer can absorb the light emitted by the light-emitting layer in the pixel area and propagated to other pixel areas around it, so as to reduce the light crosstalk problem between pixels of the micro-light-emitting diode chip, thereby reducing the power consumption of the micro-light-emitting diode chip and improving the display effect of the micro-light-emitting diode chip.
[0113] See also Fig.12 , Fig.12 is a schematic diagram of the structure of the display device provided in the embodiment of the present application. Fig.12 As shown, the display device 30 may include the micro-LED chip 31 of any of the above embodiments, or the micro-LED chip 31 manufactured by the manufacturing method of the micro-LED chip of any of the above embodiments.
[0114] Specifically, the micro-LED chip 31 may include a light-emitting stack, an inter-pixel groove, and a sidewall reflection structure. The light-emitting stack has a pixel array region, the pixel array region includes at least one pixel region and a pixel channel region, the pixel channel region is arranged around each pixel region in the at least one pixel region, and the light-emitting stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in sequence. The inter-pixel groove is arranged in the pixel channel region, and the inter-pixel groove runs through the first semiconductor layer. The sidewall reflection structure is arranged in the pixel channel region, and the sidewall reflection structure includes a sidewall reflection layer and a light absorption protection layer stacked in sequence in a direction away from the first semiconductor layer, wherein the sidewall reflection layer is arranged in the inter-pixel groove and fills part of the space in the inter-pixel groove, and the light absorption protection layer is arranged on the side of the sidewall reflection layer away from the bottom wall of the inter-pixel groove and fills the remaining space in the inter-pixel groove.
[0115] In some examples, the display device 30 can be an electronic device such as an optical projection, a vehicle-mounted head-up display (HUD), or any device with a display screen such as a smart phone, a smart watch, a laptop computer, a tablet computer, a driving recorder, a navigator, a head-mounted device, etc.
[0116] It should be noted that the display device provided in the embodiment of the present application, since it is equipped with the micro-light emitting diode chip provided in the embodiment of the present application, can achieve the beneficial effects that can be achieved by any micro-light emitting diode chip provided in the embodiment of the present application. Please see the previous embodiments for details, which will not be repeated here.
[0117] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A micro light emitting diode chip, characterized in that: include: A light emitting stack having a pixel array region, wherein the pixel array region includes at least one pixel region and a pixel channel region, wherein the pixel channel region is arranged around each pixel region in the at least one pixel region, and wherein the light emitting stack includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer which are sequentially stacked; An inter-pixel groove, provided in the pixel channel region, the inter-pixel groove penetrating into the first semiconductor layer; A sidewall reflection structure is arranged in the pixel channel area, and the sidewall reflection structure includes a sidewall reflection layer and a light absorption protection layer which are stacked in sequence in a direction away from the first semiconductor layer, wherein the sidewall reflection layer is arranged in the inter-pixel groove and fills part of the space in the inter-pixel groove, and the light absorption protection layer is arranged on a side of the sidewall reflection layer away from the bottom wall surface of the inter-pixel groove and fills the remaining space in the inter-pixel groove.
2. The micro light emitting diode chip according to claim 1, characterized in that: The height of the side wall reflection layer relative to the plane where the bottom wall surface of the inter-pixel groove is located is smaller than the height of the light emitting layer relative to the plane where the bottom wall surface of the inter-pixel groove is located.
3. The micro light emitting diode chip according to claim 1, characterized in that: The micro light emitting diode chip further comprises: The sidewall passivation layer is disposed between the sidewall reflective structure and the sidewall of the inter-pixel groove.
4. The micro-LED chip according to claim 1, further comprising: A current diffusion layer and a reflective layer are sequentially stacked on a side of the second semiconductor layer in the pixel region away from the light-emitting layer, an orthographic projection area of the reflective layer on a plane where the first semiconductor layer is located is smaller than an orthographic projection area of the current diffusion layer on a plane where the first semiconductor layer is located, and an orthographic projection area of the current diffusion layer on a plane where the first semiconductor layer is located is smaller than an orthographic projection area of the second semiconductor layer in the pixel region on a plane where the first semiconductor layer is located; A passivation layer covers the reflective layer, the current diffusion layer and the light-emitting stack, and the inter-pixel groove runs through the passivation layer.
5. The micro light emitting diode chip according to claim 1, characterized in that: The light emitting stack further comprises a pixel peripheral region, the pixel peripheral region is located at the periphery of the pixel array region, and the pixel peripheral region is provided with a groove, and the groove penetrates to the first semiconductor layer; The micro light emitting diode chip further comprises: A first polarity electrode is disposed on the bottom wall surface of the groove, and the side wall reflection layer is conductive and electrically connected to the first polarity electrode.
6. The micro light emitting diode chip according to claim 5, characterized in that: The micro-LED chip also includes a second polarity electrode, which is arranged on the side of the second semiconductor layer in the pixel area away from the light-emitting layer, and the height of the first polarity electrode relative to the plane where the bottom wall of the groove is located is equal to the height of the second polarity electrode relative to the plane where the bottom wall of the groove is located.
7. A method for manufacturing a micro light emitting diode chip, characterized in that: include: Providing an epitaxial stack, the epitaxial stack having a pixel array region, the pixel array region including at least one pixel region and a pixel channel region, the pixel channel region being arranged around each pixel region in the at least one pixel region, the epitaxial stack including a first semiconductor layer, a light emitting layer, and a second semiconductor layer which are sequentially stacked; forming an inter-pixel groove in the pixel channel region, wherein the inter-pixel groove penetrates the first semiconductor layer; forming a sidewall reflection layer in the inter-pixel groove, wherein the sidewall reflection layer fills a part of the space in the inter-pixel groove; A light absorbing protective layer is formed in the pixel channel region to obtain a side wall reflection structure including the side wall reflection layer and the light absorbing protective layer, wherein the light absorbing protective layer is arranged on a side of the side wall reflection layer away from the bottom wall surface of the inter-pixel groove and fills the remaining space in the inter-pixel groove.
8. The method according to claim 7, characterized in that: Before forming the inter-pixel grooves in the pixel channel region, the method further comprises: forming a current diffusion layer on a side of the second semiconductor layer away from the light emitting layer in the pixel region, wherein an orthographic projection area of the current diffusion layer on a plane where the first semiconductor layer is located is smaller than an orthographic projection area of the second semiconductor layer on a plane where the first semiconductor layer is located in the pixel region; forming a reflective layer on a side of the current diffusion layer away from the second semiconductor layer, wherein an orthographic projection area of the reflective layer on a plane where the first semiconductor layer is located is smaller than an orthographic projection area of the current diffusion layer on a plane where the first semiconductor layer is located; forming a passivation layer, wherein the passivation layer covers the reflective layer, the current diffusion layer and the light-emitting stack; Furthermore, the inter-pixel groove penetrates the passivation layer.
9. The manufacturing method according to claim 7, characterized in that: The epitaxial stack further comprises a pixel peripheral region, and the pixel peripheral region is located at the periphery of the pixel array region; the method further comprises: forming a groove in the peripheral area of the pixel, wherein the groove penetrates the first semiconductor layer; forming a first polarity electrode on the bottom wall surface of the groove; Furthermore, the inter-pixel trench is connected to the groove.
10. A display device, characterized in that: A micro-light emitting diode chip comprising any one of claims 1 to 6, or a micro-light emitting diode chip manufactured by the method described in any one of claims 7 to 9.